diff options
-rw-r--r-- | drivers/char/tpm/tpm.c | 52 | ||||
-rw-r--r-- | drivers/char/tpm/tpm.h | 11 | ||||
-rw-r--r-- | drivers/char/tpm/tpm_atmel.c | 21 | ||||
-rw-r--r-- | drivers/char/tpm/tpm_nsc.c | 54 |
4 files changed, 87 insertions, 51 deletions
diff --git a/drivers/char/tpm/tpm.c b/drivers/char/tpm/tpm.c index c937ea2bcdbc..7da4fe921277 100644 --- a/drivers/char/tpm/tpm.c +++ b/drivers/char/tpm/tpm.c | |||
@@ -28,19 +28,35 @@ | |||
28 | #include <linux/spinlock.h> | 28 | #include <linux/spinlock.h> |
29 | #include "tpm.h" | 29 | #include "tpm.h" |
30 | 30 | ||
31 | #define TPM_MINOR 224 /* officially assigned */ | 31 | enum tpm_const { |
32 | TPM_MINOR = 224, /* officially assigned */ | ||
33 | TPM_BUFSIZE = 2048, | ||
34 | TPM_NUM_DEVICES = 256, | ||
35 | TPM_NUM_MASK_ENTRIES = TPM_NUM_DEVICES / (8 * sizeof(int)) | ||
36 | }; | ||
32 | 37 | ||
33 | #define TPM_BUFSIZE 2048 | 38 | /* PCI configuration addresses */ |
39 | enum tpm_pci_config_addr { | ||
40 | PCI_GEN_PMCON_1 = 0xA0, | ||
41 | PCI_GEN1_DEC = 0xE4, | ||
42 | PCI_LPC_EN = 0xE6, | ||
43 | PCI_GEN2_DEC = 0xEC | ||
44 | }; | ||
45 | |||
46 | enum tpm_config { | ||
47 | TPM_LOCK_REG = 0x0D, | ||
48 | TPM_INTERUPT_REG = 0x0A, | ||
49 | TPM_BASE_ADDR_LO = 0x08, | ||
50 | TPM_BASE_ADDR_HI = 0x09, | ||
51 | TPM_UNLOCK_VALUE = 0x55, | ||
52 | TPM_LOCK_VALUE = 0xAA, | ||
53 | TPM_DISABLE_INTERUPT_VALUE = 0x00 | ||
54 | }; | ||
34 | 55 | ||
35 | /* PCI configuration addresses */ | ||
36 | #define PCI_GEN_PMCON_1 0xA0 | ||
37 | #define PCI_GEN1_DEC 0xE4 | ||
38 | #define PCI_LPC_EN 0xE6 | ||
39 | #define PCI_GEN2_DEC 0xEC | ||
40 | 56 | ||
41 | static LIST_HEAD(tpm_chip_list); | 57 | static LIST_HEAD(tpm_chip_list); |
42 | static DEFINE_SPINLOCK(driver_lock); | 58 | static DEFINE_SPINLOCK(driver_lock); |
43 | static int dev_mask[32]; | 59 | static int dev_mask[TPM_NUM_MASK_ENTRIES]; |
44 | 60 | ||
45 | static void user_reader_timeout(unsigned long ptr) | 61 | static void user_reader_timeout(unsigned long ptr) |
46 | { | 62 | { |
@@ -102,17 +118,18 @@ int tpm_lpc_bus_init(struct pci_dev *pci_dev, u16 base) | |||
102 | pci_write_config_dword(pci_dev, PCI_GEN_PMCON_1, | 118 | pci_write_config_dword(pci_dev, PCI_GEN_PMCON_1, |
103 | tmp); | 119 | tmp); |
104 | } | 120 | } |
105 | tpm_write_index(0x0D, 0x55); /* unlock 4F */ | ||
106 | tpm_write_index(0x0A, 0x00); /* int disable */ | ||
107 | tpm_write_index(0x08, base); /* base addr lo */ | ||
108 | tpm_write_index(0x09, (base & 0xFF00) >> 8); /* base addr hi */ | ||
109 | tpm_write_index(0x0D, 0xAA); /* lock 4F */ | ||
110 | break; | 121 | break; |
111 | case PCI_VENDOR_ID_AMD: | 122 | case PCI_VENDOR_ID_AMD: |
112 | /* nothing yet */ | 123 | /* nothing yet */ |
113 | break; | 124 | break; |
114 | } | 125 | } |
115 | 126 | ||
127 | tpm_write_index(TPM_LOCK_REG, TPM_UNLOCK_VALUE); | ||
128 | tpm_write_index(TPM_INTERUPT_REG, TPM_DISABLE_INTERUPT_VALUE); | ||
129 | tpm_write_index(TPM_BASE_ADDR_LO, base); | ||
130 | tpm_write_index(TPM_BASE_ADDR_HI, (base & 0xFF00) >> 8); | ||
131 | tpm_write_index(TPM_LOCK_REG, TPM_LOCK_VALUE); | ||
132 | |||
116 | return 0; | 133 | return 0; |
117 | } | 134 | } |
118 | 135 | ||
@@ -527,7 +544,7 @@ void __devexit tpm_remove(struct pci_dev *pci_dev) | |||
527 | 544 | ||
528 | pci_disable_device(pci_dev); | 545 | pci_disable_device(pci_dev); |
529 | 546 | ||
530 | dev_mask[chip->dev_num / 32] &= !(1 << (chip->dev_num % 32)); | 547 | dev_mask[chip->dev_num / TPM_NUM_MASK_ENTRIES ] &= !(1 << (chip->dev_num % TPM_NUM_MASK_ENTRIES)); |
531 | 548 | ||
532 | kfree(chip); | 549 | kfree(chip); |
533 | 550 | ||
@@ -608,10 +625,11 @@ int tpm_register_hardware(struct pci_dev *pci_dev, | |||
608 | 625 | ||
609 | chip->dev_num = -1; | 626 | chip->dev_num = -1; |
610 | 627 | ||
611 | for (i = 0; i < 32; i++) | 628 | for (i = 0; i < TPM_NUM_MASK_ENTRIES; i++) |
612 | for (j = 0; j < 8; j++) | 629 | for (j = 0; j < 8 * sizeof(int); j++) |
613 | if ((dev_mask[i] & (1 << j)) == 0) { | 630 | if ((dev_mask[i] & (1 << j)) == 0) { |
614 | chip->dev_num = i * 32 + j; | 631 | chip->dev_num = |
632 | i * TPM_NUM_MASK_ENTRIES + j; | ||
615 | dev_mask[i] |= 1 << j; | 633 | dev_mask[i] |= 1 << j; |
616 | goto dev_num_search_complete; | 634 | goto dev_num_search_complete; |
617 | } | 635 | } |
diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h index 3c4ee433ec7f..1a94a8c345e0 100644 --- a/drivers/char/tpm/tpm.h +++ b/drivers/char/tpm/tpm.h | |||
@@ -25,11 +25,16 @@ | |||
25 | #include <linux/fs.h> | 25 | #include <linux/fs.h> |
26 | #include <linux/miscdevice.h> | 26 | #include <linux/miscdevice.h> |
27 | 27 | ||
28 | #define TPM_TIMEOUT 5 /* msecs */ | 28 | enum tpm_timeout { |
29 | TPM_TIMEOUT = 5, /* msecs */ | ||
30 | }; | ||
29 | 31 | ||
30 | /* TPM addresses */ | 32 | /* TPM addresses */ |
31 | #define TPM_ADDR 0x4E | 33 | enum tpm_addr { |
32 | #define TPM_DATA 0x4F | 34 | TPM_ADDR = 0x4E, |
35 | TPM_DATA = 0x4F | ||
36 | }; | ||
37 | |||
33 | 38 | ||
34 | struct tpm_chip; | 39 | struct tpm_chip; |
35 | 40 | ||
diff --git a/drivers/char/tpm/tpm_atmel.c b/drivers/char/tpm/tpm_atmel.c index f9333e729b62..3271391892e8 100644 --- a/drivers/char/tpm/tpm_atmel.c +++ b/drivers/char/tpm/tpm_atmel.c | |||
@@ -22,17 +22,22 @@ | |||
22 | #include "tpm.h" | 22 | #include "tpm.h" |
23 | 23 | ||
24 | /* Atmel definitions */ | 24 | /* Atmel definitions */ |
25 | #define TPM_ATML_BASE 0x400 | 25 | enum tpm_atmel_addr{ |
26 | TPM_ATML_BASE = 0x400 | ||
27 | }; | ||
26 | 28 | ||
27 | /* write status bits */ | 29 | /* write status bits */ |
28 | #define ATML_STATUS_ABORT 0x01 | 30 | enum tpm_atmel_write_status { |
29 | #define ATML_STATUS_LASTBYTE 0x04 | 31 | ATML_STATUS_ABORT = 0x01, |
30 | 32 | ATML_STATUS_LASTBYTE = 0x04 | |
33 | }; | ||
31 | /* read status bits */ | 34 | /* read status bits */ |
32 | #define ATML_STATUS_BUSY 0x01 | 35 | enum tpm_atmel_read_status { |
33 | #define ATML_STATUS_DATA_AVAIL 0x02 | 36 | ATML_STATUS_BUSY = 0x01, |
34 | #define ATML_STATUS_REWRITE 0x04 | 37 | ATML_STATUS_DATA_AVAIL = 0x02, |
35 | 38 | ATML_STATUS_REWRITE = 0x04, | |
39 | ATML_STATUS_READY = 0x08 | ||
40 | }; | ||
36 | 41 | ||
37 | static int tpm_atml_recv(struct tpm_chip *chip, u8 * buf, size_t count) | 42 | static int tpm_atml_recv(struct tpm_chip *chip, u8 * buf, size_t count) |
38 | { | 43 | { |
diff --git a/drivers/char/tpm/tpm_nsc.c b/drivers/char/tpm/tpm_nsc.c index 6e5ffcacea60..24832abe0b2d 100644 --- a/drivers/char/tpm/tpm_nsc.c +++ b/drivers/char/tpm/tpm_nsc.c | |||
@@ -22,34 +22,42 @@ | |||
22 | #include "tpm.h" | 22 | #include "tpm.h" |
23 | 23 | ||
24 | /* National definitions */ | 24 | /* National definitions */ |
25 | #define TPM_NSC_BASE 0x360 | 25 | enum tpm_nsc_addr { |
26 | #define TPM_NSC_IRQ 0x07 | 26 | TPM_NSC_BASE = 0x360, |
27 | TPM_NSC_IRQ = 0x07 | ||
28 | }; | ||
27 | 29 | ||
28 | #define NSC_LDN_INDEX 0x07 | 30 | enum tpm_nsc_index { |
29 | #define NSC_SID_INDEX 0x20 | 31 | NSC_LDN_INDEX = 0x07, |
30 | #define NSC_LDC_INDEX 0x30 | 32 | NSC_SID_INDEX = 0x20, |
31 | #define NSC_DIO_INDEX 0x60 | 33 | NSC_LDC_INDEX = 0x30, |
32 | #define NSC_CIO_INDEX 0x62 | 34 | NSC_DIO_INDEX = 0x60, |
33 | #define NSC_IRQ_INDEX 0x70 | 35 | NSC_CIO_INDEX = 0x62, |
34 | #define NSC_ITS_INDEX 0x71 | 36 | NSC_IRQ_INDEX = 0x70, |
37 | NSC_ITS_INDEX = 0x71 | ||
38 | }; | ||
35 | 39 | ||
36 | #define NSC_STATUS 0x01 | 40 | enum tpm_nsc_status_loc { |
37 | #define NSC_COMMAND 0x01 | 41 | NSC_STATUS = 0x01, |
38 | #define NSC_DATA 0x00 | 42 | NSC_COMMAND = 0x01, |
43 | NSC_DATA = 0x00 | ||
44 | }; | ||
39 | 45 | ||
40 | /* status bits */ | 46 | /* status bits */ |
41 | #define NSC_STATUS_OBF 0x01 /* output buffer full */ | 47 | enum tpm_nsc_status{ |
42 | #define NSC_STATUS_IBF 0x02 /* input buffer full */ | 48 | NSC_STATUS_OBF = 0x01, /* output buffer full */ |
43 | #define NSC_STATUS_F0 0x04 /* F0 */ | 49 | NSC_STATUS_IBF = 0x02, /* input buffer full */ |
44 | #define NSC_STATUS_A2 0x08 /* A2 */ | 50 | NSC_STATUS_F0 = 0x04, /* F0 */ |
45 | #define NSC_STATUS_RDY 0x10 /* ready to receive command */ | 51 | NSC_STATUS_A2 = 0x08, /* A2 */ |
46 | #define NSC_STATUS_IBR 0x20 /* ready to receive data */ | 52 | NSC_STATUS_RDY = 0x10, /* ready to receive command */ |
47 | 53 | NSC_STATUS_IBR = 0x20 /* ready to receive data */ | |
54 | }; | ||
48 | /* command bits */ | 55 | /* command bits */ |
49 | #define NSC_COMMAND_NORMAL 0x01 /* normal mode */ | 56 | enum tpm_nsc_cmd_mode { |
50 | #define NSC_COMMAND_EOC 0x03 | 57 | NSC_COMMAND_NORMAL = 0x01, /* normal mode */ |
51 | #define NSC_COMMAND_CANCEL 0x22 | 58 | NSC_COMMAND_EOC = 0x03, |
52 | 59 | NSC_COMMAND_CANCEL = 0x22 | |
60 | }; | ||
53 | /* | 61 | /* |
54 | * Wait for a certain status to appear | 62 | * Wait for a certain status to appear |
55 | */ | 63 | */ |