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-rw-r--r--drivers/clk/samsung/clk-exynos5250.c559
1 files changed, 264 insertions, 295 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 18d0b5ebd545..25c77ab37ccf 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for Exynos5250 SoC. 10 * Common Clock Framework support for Exynos5250 SoC.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos5250.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -85,52 +86,6 @@ enum exynos5250_plls {
85}; 86};
86 87
87/* 88/*
88 * Let each supported clock get a unique id. This id is used to lookup the clock
89 * for device tree based platforms. The clocks are categorized into three
90 * sections: core, sclk gate and bus interface gate clocks.
91 *
92 * When adding a new clock to this list, it is advised to choose a clock
93 * category and add it to the end of that category. That is because the the
94 * device tree source file is referring to these ids and any change in the
95 * sequence number of existing clocks will require corresponding change in the
96 * device tree files. This limitation would go away when pre-processor support
97 * for dtc would be available.
98 */
99enum exynos5250_clks {
100 none,
101
102 /* core clocks */
103 fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
104 fout_epll, fout_vpll,
105
106 /* gate for special clocks (sclk) */
107 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
108 sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
109 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
110 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
111 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
112 div_i2s1, div_i2s2, sclk_hdmiphy,
113
114 /* gate clocks */
115 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
116 smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
117 jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
118 usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
119 sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
120 i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
121 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
122 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
123 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
124 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, mdma0,
125 smmu_mdma0,
126
127 /* mux clocks */
128 mout_hdmi = 1024,
129
130 nr_clks,
131};
132
133/*
134 * list of controller registers to be saved and restored during a 89 * list of controller registers to be saved and restored during a
135 * suspend/resume cycle. 90 * suspend/resume cycle.
136 */ 91 */
@@ -231,24 +186,24 @@ PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
231 186
232/* fixed rate clocks generated outside the soc */ 187/* fixed rate clocks generated outside the soc */
233static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 188static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
234 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 189 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
235}; 190};
236 191
237/* fixed rate clocks generated inside the soc */ 192/* fixed rate clocks generated inside the soc */
238static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 193static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
239 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 194 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
240 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 195 FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
241 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), 196 FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
242 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), 197 FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
243}; 198};
244 199
245static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 200static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
246 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 201 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
247 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 202 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
248}; 203};
249 204
250static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { 205static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
251 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 206 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
252}; 207};
253 208
254static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 209static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
@@ -262,74 +217,74 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
262 /* 217 /*
263 * CMU_CPU 218 * CMU_CPU
264 */ 219 */
265 MUX_FA(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 220 MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
266 CLK_SET_RATE_PARENT, 0, "mout_apll"), 221 CLK_SET_RATE_PARENT, 0, "mout_apll"),
267 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 222 MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
268 223
269 /* 224 /*
270 * CMU_CORE 225 * CMU_CORE
271 */ 226 */
272 MUX_A(none, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 227 MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
273 228
274 /* 229 /*
275 * CMU_TOP 230 * CMU_TOP
276 */ 231 */
277 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 232 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
278 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 233 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
279 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 234 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
280 235
281 MUX(none, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 236 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
282 MUX(none, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1), 237 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
283 MUX(none, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 238 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
284 MUX(none, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 239 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
285 MUX(none, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 240 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
286 241
287 MUX(none, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), 242 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
288 MUX(none, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), 243 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
289 MUX(none, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1), 244 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
290 245
291 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 246 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
292 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), 247 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
293 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), 248 MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
294 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), 249 MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
295 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), 250 MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
296 251
297 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 252 MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
298 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 253 MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
299 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 254 MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
300 MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 255 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
301 256
302 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 257 MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
303 258
304 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 259 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
305 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 260 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
306 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), 261 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
307 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), 262 MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
308 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), 263 MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
309 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), 264 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
310 265
311 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), 266 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
312 267
313 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), 268 MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
314 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), 269 MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
315 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), 270 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
316 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), 271 MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
317 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), 272 MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
318 273
319 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), 274 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
320 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), 275 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
321 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), 276 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
322 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), 277 MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
323 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), 278 MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
324 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 279 MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
325 280
326 /* 281 /*
327 * CMU_CDREX 282 * CMU_CDREX
328 */ 283 */
329 MUX(none, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 284 MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
330 285
331 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 286 MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
332 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 287 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
333}; 288};
334 289
335static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 290static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
@@ -343,81 +298,81 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
343 /* 298 /*
344 * CMU_CPU 299 * CMU_CPU
345 */ 300 */
346 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 301 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
347 DIV(none, "div_apll", "mout_apll", DIV_CPU0, 24, 3), 302 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
348 DIV_A(none, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), 303 DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
349 304
350 /* 305 /*
351 * CMU_TOP 306 * CMU_TOP
352 */ 307 */
353 DIV(none, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3), 308 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
354 DIV(none, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3), 309 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
355 DIV(none, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 310 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
356 DIV(none, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), 311 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
357 DIV(none, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 312 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
358 313
359 DIV(none, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), 314 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
360 315
361 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 316 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
362 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), 317 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
363 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), 318 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
364 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), 319 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
365 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), 320 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
366 321
367 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), 322 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
368 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), 323 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
369 DIV_F(none, "div_mipi1_pre", "div_mipi1", 324 DIV_F(0, "div_mipi1_pre", "div_mipi1",
370 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), 325 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
371 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), 326 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
372 DIV(sclk_pixel, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4), 327 DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
373 328
374 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), 329 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
375 330
376 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), 331 DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
377 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), 332 DIV(0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
378 333
379 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 334 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
380 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), 335 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
381 336
382 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 337 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
383 DIV_F(none, "div_mmc_pre0", "div_mmc0", 338 DIV_F(0, "div_mmc_pre0", "div_mmc0",
384 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), 339 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
385 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 340 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
386 DIV_F(none, "div_mmc_pre1", "div_mmc1", 341 DIV_F(0, "div_mmc_pre1", "div_mmc1",
387 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), 342 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
388 343
389 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 344 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
390 DIV_F(none, "div_mmc_pre2", "div_mmc2", 345 DIV_F(0, "div_mmc_pre2", "div_mmc2",
391 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), 346 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
392 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 347 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
393 DIV_F(none, "div_mmc_pre3", "div_mmc3", 348 DIV_F(0, "div_mmc_pre3", "div_mmc3",
394 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), 349 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
395 350
396 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 351 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
397 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 352 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
398 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 353 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
399 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 354 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
400 355
401 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), 356 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
402 DIV_F(none, "div_spi_pre0", "div_spi0", 357 DIV_F(0, "div_spi_pre0", "div_spi0",
403 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), 358 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
404 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), 359 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
405 DIV_F(none, "div_spi_pre1", "div_spi1", 360 DIV_F(0, "div_spi_pre1", "div_spi1",
406 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), 361 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
407 362
408 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), 363 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
409 DIV_F(none, "div_spi_pre2", "div_spi2", 364 DIV_F(0, "div_spi_pre2", "div_spi2",
410 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), 365 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
411 366
412 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 367 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
413 368
414 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), 369 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
415 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), 370 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
416 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), 371 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
417 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), 372 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
418 373
419 DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), 374 DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
420 DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), 375 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
421}; 376};
422 377
423static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 378static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
@@ -431,180 +386,194 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
431 /* 386 /*
432 * CMU_ACP 387 * CMU_ACP
433 */ 388 */
434 GATE(mdma0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), 389 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
435 GATE(g2d, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), 390 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
436 GATE(smmu_mdma0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), 391 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
437 392
438 /* 393 /*
439 * CMU_TOP 394 * CMU_TOP
440 */ 395 */
441 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer", 396 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
442 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0), 397 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
443 GATE(sclk_cam0, "sclk_cam0", "div_cam0", 398 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
444 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0), 399 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
445 GATE(sclk_cam1, "sclk_cam1", "div_cam1", 400 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
446 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0), 401 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
447 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa", 402 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
448 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0), 403 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
449 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb", 404 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
450 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0), 405 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
451 406
452 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", 407 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
453 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0), 408 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
454 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1", 409 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
455 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), 410 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_dp, "sclk_dp", "div_dp", 411 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
457 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), 412 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
458 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 413 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
459 SRC_MASK_DISP1_0, 20, 0, 0), 414 SRC_MASK_DISP1_0, 20, 0, 0),
460 415
461 GATE(sclk_audio0, "sclk_audio0", "div_audio0", 416 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
462 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), 417 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
463 418
464 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", 419 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
465 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 420 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
466 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", 421 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
467 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 422 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
468 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", 423 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
469 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 424 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
470 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", 425 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
471 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), 426 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
472 GATE(sclk_sata, "sclk_sata", "div_sata", 427 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
473 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 428 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
474 GATE(sclk_usb3, "sclk_usb3", "div_usb3", 429 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
475 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0), 430 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
476 431
477 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg", 432 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
478 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0), 433 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
479 434
480 GATE(sclk_uart0, "sclk_uart0", "div_uart0", 435 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
481 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 436 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
482 GATE(sclk_uart1, "sclk_uart1", "div_uart1", 437 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
483 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 438 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
484 GATE(sclk_uart2, "sclk_uart2", "div_uart2", 439 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
485 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 440 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
486 GATE(sclk_uart3, "sclk_uart3", "div_uart3", 441 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
487 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), 442 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
488 GATE(sclk_pwm, "sclk_pwm", "div_pwm", 443 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
489 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0), 444 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
490 445
491 GATE(sclk_audio1, "sclk_audio1", "div_audio1", 446 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
492 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 447 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
493 GATE(sclk_audio2, "sclk_audio2", "div_audio2", 448 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
494 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 449 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
495 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 450 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
496 SRC_MASK_PERIC1, 4, 0, 0), 451 SRC_MASK_PERIC1, 4, 0, 0),
497 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", 452 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
498 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0), 453 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
499 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", 454 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
500 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 455 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
501 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", 456 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
502 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), 457 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
503 458
504 GATE(gscl0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0, 0), 459 GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
505 GATE(gscl1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0, 0), 460 0),
506 GATE(gscl2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0, 0), 461 GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
507 GATE(gscl3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 0), 462 0),
508 GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), 463 GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
509 GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), 464 0),
510 GATE(smmu_gscl0, "smmu_gscl0", "mout_aclk266_gscl_sub", 465 GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
466 0),
467 GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
468 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
469 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
511 GATE_IP_GSCL, 7, 0, 0), 470 GATE_IP_GSCL, 7, 0, 0),
512 GATE(smmu_gscl1, "smmu_gscl1", "mout_aclk266_gscl_sub", 471 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
513 GATE_IP_GSCL, 8, 0, 0), 472 GATE_IP_GSCL, 8, 0, 0),
514 GATE(smmu_gscl2, "smmu_gscl2", "mout_aclk266_gscl_sub", 473 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
515 GATE_IP_GSCL, 9, 0, 0), 474 GATE_IP_GSCL, 9, 0, 0),
516 GATE(smmu_gscl3, "smmu_gscl3", "mout_aclk266_gscl_sub", 475 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
517 GATE_IP_GSCL, 10, 0, 0), 476 GATE_IP_GSCL, 10, 0, 0),
518 477
519 GATE(fimd1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, 0), 478 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
520 GATE(mie1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, 0), 479 0),
521 GATE(dsim0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, 0), 480 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
522 GATE(dp, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), 481 0),
523 GATE(mixer, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, 0), 482 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
524 GATE(hdmi, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, 0), 483 0),
525 484 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
526 GATE(mfc, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0), 485 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
527 GATE(smmu_mfcr, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, 0), 486 0),
528 GATE(smmu_mfcl, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 0), 487 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
529 488 0),
530 GATE(rotator, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0), 489
531 GATE(jpeg, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0), 490 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
532 GATE(mdma1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0), 491 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
533 GATE(smmu_rotator, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0, 0), 492 0),
534 GATE(smmu_jpeg, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0), 493 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
535 GATE(smmu_mdma1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0), 494 0),
536 495
537 GATE(pdma0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0), 496 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
538 GATE(pdma1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0), 497 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
539 GATE(sata, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0), 498 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
540 GATE(usbotg, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0), 499 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
541 GATE(mipi_hsi, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0), 500 0),
542 GATE(sdmmc0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0), 501 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
543 GATE(sdmmc1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0), 502 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
544 GATE(sdmmc2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0), 503
545 GATE(sdmmc3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0), 504 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
546 GATE(sromc, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0), 505 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
547 GATE(usb2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0), 506 GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
548 GATE(usb3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0), 507 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
549 GATE(sata_phyctrl, "sata_phyctrl", "div_aclk200", 508 GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
509 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
510 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
511 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
512 GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
513 GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
514 GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
515 GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
516 GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
550 GATE_IP_FSYS, 24, 0, 0), 517 GATE_IP_FSYS, 24, 0, 0),
551 GATE(sata_phyi2c, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0, 0), 518 GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
552 519 0),
553 GATE(uart0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0), 520
554 GATE(uart1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0), 521 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
555 GATE(uart2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0), 522 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
556 GATE(uart3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0), 523 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
557 GATE(uart4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0), 524 GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
558 GATE(i2c0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0), 525 GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
559 GATE(i2c1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0), 526 GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
560 GATE(i2c2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0), 527 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
561 GATE(i2c3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0), 528 GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
562 GATE(i2c4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0), 529 GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
563 GATE(i2c5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0), 530 GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
564 GATE(i2c6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0), 531 GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
565 GATE(i2c7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0), 532 GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
566 GATE(i2c_hdmi, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0), 533 GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
567 GATE(adc, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0), 534 GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
568 GATE(spi0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0), 535 GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
569 GATE(spi1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0), 536 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
570 GATE(spi2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0), 537 GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
571 GATE(i2s1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0), 538 GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
572 GATE(i2s2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0), 539 GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
573 GATE(pcm1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0), 540 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
574 GATE(pcm2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0), 541 GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
575 GATE(pwm, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0), 542 GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
576 GATE(spdif, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0), 543 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
577 GATE(ac97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0), 544 GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
578 GATE(hsi2c0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0), 545 GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
579 GATE(hsi2c1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0), 546 GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
580 GATE(hsi2c2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0), 547 GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
581 GATE(hsi2c3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0), 548 GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
582 549 GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
583 GATE(chipid, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0), 550
584 GATE(sysreg, "sysreg", "div_aclk66", 551 GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
552 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
585 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 553 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
586 GATE(pmu, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0), 554 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
587 GATE(cmu_top, "cmu_top", "div_aclk66", 555 0),
556 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
588 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0), 557 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
589 GATE(cmu_core, "cmu_core", "div_aclk66", 558 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
590 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0), 559 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
591 GATE(cmu_mem, "cmu_mem", "div_aclk66", 560 GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
592 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0), 561 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
593 GATE(tzpc0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0), 562 GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
594 GATE(tzpc1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0), 563 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
595 GATE(tzpc2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0), 564 GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
596 GATE(tzpc3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0), 565 GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
597 GATE(tzpc4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0), 566 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
598 GATE(tzpc5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0), 567 GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
599 GATE(tzpc6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0), 568 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
600 GATE(tzpc7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0), 569 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
601 GATE(tzpc8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0), 570 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
602 GATE(tzpc9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0), 571 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
603 GATE(hdmi_cec, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0), 572 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
604 GATE(mct, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0), 573 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
605 GATE(wdt, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), 574 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
606 GATE(rtc, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), 575 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
607 GATE(tmu, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), 576 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
608}; 577};
609 578
610static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 579static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
@@ -652,19 +621,19 @@ static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
652}; 621};
653 622
654static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 623static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
655 [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 624 [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
656 APLL_CON0, "fout_apll", NULL), 625 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
657 [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 626 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
658 MPLL_CON0, "fout_mpll", NULL), 627 MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
659 [bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, 628 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
660 BPLL_CON0, NULL), 629 BPLL_CON0, NULL),
661 [gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK, 630 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
662 GPLL_CON0, NULL), 631 GPLL_CON0, NULL),
663 [cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK, 632 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
664 CPLL_CON0, NULL), 633 CPLL_CON0, NULL),
665 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 634 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
666 EPLL_CON0, NULL), 635 EPLL_CON0, NULL),
667 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc", 636 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
668 VPLL_LOCK, VPLL_CON0, NULL), 637 VPLL_LOCK, VPLL_CON0, NULL),
669}; 638};
670 639
@@ -686,7 +655,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
686 panic("%s: unable to determine soc\n", __func__); 655 panic("%s: unable to determine soc\n", __func__);
687 } 656 }
688 657
689 samsung_clk_init(np, reg_base, nr_clks, 658 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
690 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs), 659 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
691 NULL, 0); 660 NULL, 0);
692 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, 661 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-13 03:28:07 -0400