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-rw-r--r--arch/mips/alchemy/common/dbdma.c22
-rw-r--r--arch/mips/alchemy/common/dma.c15
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h48
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000_dma.h50
-rw-r--r--drivers/mmc/host/au1xmmc.c167
-rw-r--r--drivers/mtd/nand/au1550nd.c21
-rw-r--r--drivers/net/ethernet/amd/au1000_eth.c31
-rw-r--r--drivers/spi/spi-au1550.c66
-rw-r--r--drivers/video/fbdev/au1100fb.c4
-rw-r--r--drivers/video/fbdev/au1200fb.c31
-rw-r--r--sound/soc/au1x/psc-ac97.c140
-rw-r--r--sound/soc/au1x/psc-i2s.c100
-rw-r--r--sound/soc/au1x/psc.h22
13 files changed, 340 insertions, 377 deletions
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 19d5642c16d9..745695db5ba0 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -341,7 +341,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
341 (dtp->dev_flags & DEV_FLAGS_SYNC)) 341 (dtp->dev_flags & DEV_FLAGS_SYNC))
342 i |= DDMA_CFG_SYNC; 342 i |= DDMA_CFG_SYNC;
343 cp->ddma_cfg = i; 343 cp->ddma_cfg = i;
344 au_sync(); 344 wmb(); /* drain writebuffer */
345 345
346 /* 346 /*
347 * Return a non-zero value that can be used to find the channel 347 * Return a non-zero value that can be used to find the channel
@@ -631,7 +631,7 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
631 */ 631 */
632 dma_cache_wback_inv((unsigned long)buf, nbytes); 632 dma_cache_wback_inv((unsigned long)buf, nbytes);
633 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 633 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
634 au_sync(); 634 wmb(); /* drain writebuffer */
635 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); 635 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
636 ctp->chan_ptr->ddma_dbell = 0; 636 ctp->chan_ptr->ddma_dbell = 0;
637 637
@@ -693,7 +693,7 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
693 */ 693 */
694 dma_cache_inv((unsigned long)buf, nbytes); 694 dma_cache_inv((unsigned long)buf, nbytes);
695 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 695 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
696 au_sync(); 696 wmb(); /* drain writebuffer */
697 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); 697 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
698 ctp->chan_ptr->ddma_dbell = 0; 698 ctp->chan_ptr->ddma_dbell = 0;
699 699
@@ -760,7 +760,7 @@ void au1xxx_dbdma_stop(u32 chanid)
760 760
761 cp = ctp->chan_ptr; 761 cp = ctp->chan_ptr;
762 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */ 762 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
763 au_sync(); 763 wmb(); /* drain writebuffer */
764 while (!(cp->ddma_stat & DDMA_STAT_H)) { 764 while (!(cp->ddma_stat & DDMA_STAT_H)) {
765 udelay(1); 765 udelay(1);
766 halt_timeout++; 766 halt_timeout++;
@@ -771,7 +771,7 @@ void au1xxx_dbdma_stop(u32 chanid)
771 } 771 }
772 /* clear current desc valid and doorbell */ 772 /* clear current desc valid and doorbell */
773 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); 773 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
774 au_sync(); 774 wmb(); /* drain writebuffer */
775} 775}
776EXPORT_SYMBOL(au1xxx_dbdma_stop); 776EXPORT_SYMBOL(au1xxx_dbdma_stop);
777 777
@@ -789,9 +789,9 @@ void au1xxx_dbdma_start(u32 chanid)
789 cp = ctp->chan_ptr; 789 cp = ctp->chan_ptr;
790 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); 790 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
791 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ 791 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
792 au_sync(); 792 wmb(); /* drain writebuffer */
793 cp->ddma_dbell = 0; 793 cp->ddma_dbell = 0;
794 au_sync(); 794 wmb(); /* drain writebuffer */
795} 795}
796EXPORT_SYMBOL(au1xxx_dbdma_start); 796EXPORT_SYMBOL(au1xxx_dbdma_start);
797 797
@@ -832,7 +832,7 @@ u32 au1xxx_get_dma_residue(u32 chanid)
832 832
833 /* This is only valid if the channel is stopped. */ 833 /* This is only valid if the channel is stopped. */
834 rv = cp->ddma_bytecnt; 834 rv = cp->ddma_bytecnt;
835 au_sync(); 835 wmb(); /* drain writebuffer */
836 836
837 return rv; 837 return rv;
838} 838}
@@ -868,7 +868,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
868 au1x_dma_chan_t *cp; 868 au1x_dma_chan_t *cp;
869 869
870 intstat = dbdma_gptr->ddma_intstat; 870 intstat = dbdma_gptr->ddma_intstat;
871 au_sync(); 871 wmb(); /* drain writebuffer */
872 chan_index = __ffs(intstat); 872 chan_index = __ffs(intstat);
873 873
874 ctp = chan_tab_ptr[chan_index]; 874 ctp = chan_tab_ptr[chan_index];
@@ -877,7 +877,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
877 877
878 /* Reset interrupt. */ 878 /* Reset interrupt. */
879 cp->ddma_irq = 0; 879 cp->ddma_irq = 0;
880 au_sync(); 880 wmb(); /* drain writebuffer */
881 881
882 if (ctp->chan_callback) 882 if (ctp->chan_callback)
883 ctp->chan_callback(irq, ctp->chan_callparam); 883 ctp->chan_callback(irq, ctp->chan_callparam);
@@ -1061,7 +1061,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
1061 dbdma_gptr->ddma_config = 0; 1061 dbdma_gptr->ddma_config = 0;
1062 dbdma_gptr->ddma_throttle = 0; 1062 dbdma_gptr->ddma_throttle = 0;
1063 dbdma_gptr->ddma_inten = 0xffff; 1063 dbdma_gptr->ddma_inten = 0xffff;
1064 au_sync(); 1064 wmb(); /* drain writebuffer */
1065 1065
1066 ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr); 1066 ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
1067 if (ret) 1067 if (ret)
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 9b624e2c0fcf..4fb6207b883b 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -141,17 +141,17 @@ void dump_au1000_dma_channel(unsigned int dmanr)
141 141
142 printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr); 142 printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
143 printk(KERN_INFO " mode = 0x%08x\n", 143 printk(KERN_INFO " mode = 0x%08x\n",
144 au_readl(chan->io + DMA_MODE_SET)); 144 __raw_readl(chan->io + DMA_MODE_SET));
145 printk(KERN_INFO " addr = 0x%08x\n", 145 printk(KERN_INFO " addr = 0x%08x\n",
146 au_readl(chan->io + DMA_PERIPHERAL_ADDR)); 146 __raw_readl(chan->io + DMA_PERIPHERAL_ADDR));
147 printk(KERN_INFO " start0 = 0x%08x\n", 147 printk(KERN_INFO " start0 = 0x%08x\n",
148 au_readl(chan->io + DMA_BUFFER0_START)); 148 __raw_readl(chan->io + DMA_BUFFER0_START));
149 printk(KERN_INFO " start1 = 0x%08x\n", 149 printk(KERN_INFO " start1 = 0x%08x\n",
150 au_readl(chan->io + DMA_BUFFER1_START)); 150 __raw_readl(chan->io + DMA_BUFFER1_START));
151 printk(KERN_INFO " count0 = 0x%08x\n", 151 printk(KERN_INFO " count0 = 0x%08x\n",
152 au_readl(chan->io + DMA_BUFFER0_COUNT)); 152 __raw_readl(chan->io + DMA_BUFFER0_COUNT));
153 printk(KERN_INFO " count1 = 0x%08x\n", 153 printk(KERN_INFO " count1 = 0x%08x\n",
154 au_readl(chan->io + DMA_BUFFER1_COUNT)); 154 __raw_readl(chan->io + DMA_BUFFER1_COUNT));
155} 155}
156 156
157/* 157/*
@@ -204,7 +204,8 @@ int request_au1000_dma(int dev_id, const char *dev_str,
204 } 204 }
205 205
206 /* fill it in */ 206 /* fill it in */
207 chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN; 207 chan->io = (void __iomem *)(KSEG1ADDR(AU1000_DMA_PHYS_ADDR) +
208 i * DMA_CHANNEL_LEN);
208 chan->dev_id = dev_id; 209 chan->dev_id = dev_id;
209 chan->dev_str = dev_str; 210 chan->dev_str = dev_str;
210 chan->fifo_addr = dev->fifo_addr; 211 chan->fifo_addr = dev->fifo_addr;
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index d664b11e0baf..754207071b58 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -645,54 +645,6 @@
645 645
646#include <asm/cpu.h> 646#include <asm/cpu.h>
647 647
648/* cpu pipeline flush */
649void static inline au_sync(void)
650{
651 __asm__ volatile ("sync");
652}
653
654void static inline au_sync_udelay(int us)
655{
656 __asm__ volatile ("sync");
657 udelay(us);
658}
659
660void static inline au_sync_delay(int ms)
661{
662 __asm__ volatile ("sync");
663 mdelay(ms);
664}
665
666void static inline au_writeb(u8 val, unsigned long reg)
667{
668 *(volatile u8 *)reg = val;
669}
670
671void static inline au_writew(u16 val, unsigned long reg)
672{
673 *(volatile u16 *)reg = val;
674}
675
676void static inline au_writel(u32 val, unsigned long reg)
677{
678 *(volatile u32 *)reg = val;
679}
680
681static inline u8 au_readb(unsigned long reg)
682{
683 return *(volatile u8 *)reg;
684}
685
686static inline u16 au_readw(unsigned long reg)
687{
688 return *(volatile u16 *)reg;
689}
690
691static inline u32 au_readl(unsigned long reg)
692{
693 return *(volatile u32 *)reg;
694}
695
696/* helpers to access the SYS_* registers */ 648/* helpers to access the SYS_* registers */
697static inline unsigned long alchemy_rdsys(int regofs) 649static inline unsigned long alchemy_rdsys(int regofs)
698{ 650{
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index 7cedca5a305c..0a0cd4270c6f 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -106,7 +106,7 @@ enum {
106struct dma_chan { 106struct dma_chan {
107 int dev_id; /* this channel is allocated if >= 0, */ 107 int dev_id; /* this channel is allocated if >= 0, */
108 /* free otherwise */ 108 /* free otherwise */
109 unsigned int io; 109 void __iomem *io;
110 const char *dev_str; 110 const char *dev_str;
111 int irq; 111 int irq;
112 void *irq_dev; 112 void *irq_dev;
@@ -157,7 +157,7 @@ static inline void enable_dma_buffer0(unsigned int dmanr)
157 157
158 if (!chan) 158 if (!chan)
159 return; 159 return;
160 au_writel(DMA_BE0, chan->io + DMA_MODE_SET); 160 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
161} 161}
162 162
163static inline void enable_dma_buffer1(unsigned int dmanr) 163static inline void enable_dma_buffer1(unsigned int dmanr)
@@ -166,7 +166,7 @@ static inline void enable_dma_buffer1(unsigned int dmanr)
166 166
167 if (!chan) 167 if (!chan)
168 return; 168 return;
169 au_writel(DMA_BE1, chan->io + DMA_MODE_SET); 169 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
170} 170}
171static inline void enable_dma_buffers(unsigned int dmanr) 171static inline void enable_dma_buffers(unsigned int dmanr)
172{ 172{
@@ -174,7 +174,7 @@ static inline void enable_dma_buffers(unsigned int dmanr)
174 174
175 if (!chan) 175 if (!chan)
176 return; 176 return;
177 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); 177 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
178} 178}
179 179
180static inline void start_dma(unsigned int dmanr) 180static inline void start_dma(unsigned int dmanr)
@@ -183,7 +183,7 @@ static inline void start_dma(unsigned int dmanr)
183 183
184 if (!chan) 184 if (!chan)
185 return; 185 return;
186 au_writel(DMA_GO, chan->io + DMA_MODE_SET); 186 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
187} 187}
188 188
189#define DMA_HALT_POLL 0x5000 189#define DMA_HALT_POLL 0x5000
@@ -195,11 +195,11 @@ static inline void halt_dma(unsigned int dmanr)
195 195
196 if (!chan) 196 if (!chan)
197 return; 197 return;
198 au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); 198 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
199 199
200 /* Poll the halt bit */ 200 /* Poll the halt bit */
201 for (i = 0; i < DMA_HALT_POLL; i++) 201 for (i = 0; i < DMA_HALT_POLL; i++)
202 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) 202 if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
203 break; 203 break;
204 if (i == DMA_HALT_POLL) 204 if (i == DMA_HALT_POLL)
205 printk(KERN_INFO "halt_dma: HALT poll expired!\n"); 205 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
@@ -215,7 +215,7 @@ static inline void disable_dma(unsigned int dmanr)
215 halt_dma(dmanr); 215 halt_dma(dmanr);
216 216
217 /* Now we can disable the buffers */ 217 /* Now we can disable the buffers */
218 au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); 218 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
219} 219}
220 220
221static inline int dma_halted(unsigned int dmanr) 221static inline int dma_halted(unsigned int dmanr)
@@ -224,7 +224,7 @@ static inline int dma_halted(unsigned int dmanr)
224 224
225 if (!chan) 225 if (!chan)
226 return 1; 226 return 1;
227 return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; 227 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
228} 228}
229 229
230/* Initialize a DMA channel. */ 230/* Initialize a DMA channel. */
@@ -239,14 +239,14 @@ static inline void init_dma(unsigned int dmanr)
239 disable_dma(dmanr); 239 disable_dma(dmanr);
240 240
241 /* Set device FIFO address */ 241 /* Set device FIFO address */
242 au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); 242 __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
243 243
244 mode = chan->mode | (chan->dev_id << DMA_DID_BIT); 244 mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
245 if (chan->irq) 245 if (chan->irq)
246 mode |= DMA_IE; 246 mode |= DMA_IE;
247 247
248 au_writel(~mode, chan->io + DMA_MODE_CLEAR); 248 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
249 au_writel(mode, chan->io + DMA_MODE_SET); 249 __raw_writel(mode, chan->io + DMA_MODE_SET);
250} 250}
251 251
252/* 252/*
@@ -283,7 +283,7 @@ static inline int get_dma_active_buffer(unsigned int dmanr)
283 283
284 if (!chan) 284 if (!chan)
285 return -1; 285 return -1;
286 return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; 286 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
287} 287}
288 288
289/* 289/*
@@ -304,7 +304,7 @@ static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
304 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) 304 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
305 return; 305 return;
306 306
307 au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); 307 __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
308} 308}
309 309
310/* 310/*
@@ -316,7 +316,7 @@ static inline void clear_dma_done0(unsigned int dmanr)
316 316
317 if (!chan) 317 if (!chan)
318 return; 318 return;
319 au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); 319 __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
320} 320}
321 321
322static inline void clear_dma_done1(unsigned int dmanr) 322static inline void clear_dma_done1(unsigned int dmanr)
@@ -325,7 +325,7 @@ static inline void clear_dma_done1(unsigned int dmanr)
325 325
326 if (!chan) 326 if (!chan)
327 return; 327 return;
328 au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); 328 __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
329} 329}
330 330
331/* 331/*
@@ -344,7 +344,7 @@ static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
344 344
345 if (!chan) 345 if (!chan)
346 return; 346 return;
347 au_writel(a, chan->io + DMA_BUFFER0_START); 347 __raw_writel(a, chan->io + DMA_BUFFER0_START);
348} 348}
349 349
350/* 350/*
@@ -356,7 +356,7 @@ static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
356 356
357 if (!chan) 357 if (!chan)
358 return; 358 return;
359 au_writel(a, chan->io + DMA_BUFFER1_START); 359 __raw_writel(a, chan->io + DMA_BUFFER1_START);
360} 360}
361 361
362 362
@@ -370,7 +370,7 @@ static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
370 if (!chan) 370 if (!chan)
371 return; 371 return;
372 count &= DMA_COUNT_MASK; 372 count &= DMA_COUNT_MASK;
373 au_writel(count, chan->io + DMA_BUFFER0_COUNT); 373 __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
374} 374}
375 375
376/* 376/*
@@ -383,7 +383,7 @@ static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
383 if (!chan) 383 if (!chan)
384 return; 384 return;
385 count &= DMA_COUNT_MASK; 385 count &= DMA_COUNT_MASK;
386 au_writel(count, chan->io + DMA_BUFFER1_COUNT); 386 __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
387} 387}
388 388
389/* 389/*
@@ -396,8 +396,8 @@ static inline void set_dma_count(unsigned int dmanr, unsigned int count)
396 if (!chan) 396 if (!chan)
397 return; 397 return;
398 count &= DMA_COUNT_MASK; 398 count &= DMA_COUNT_MASK;
399 au_writel(count, chan->io + DMA_BUFFER0_COUNT); 399 __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
400 au_writel(count, chan->io + DMA_BUFFER1_COUNT); 400 __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
401} 401}
402 402
403/* 403/*
@@ -410,7 +410,7 @@ static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
410 410
411 if (!chan) 411 if (!chan)
412 return 0; 412 return 0;
413 return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1); 413 return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
414} 414}
415 415
416 416
@@ -437,10 +437,10 @@ static inline int get_dma_residue(unsigned int dmanr)
437 if (!chan) 437 if (!chan)
438 return 0; 438 return 0;
439 439
440 curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 440 curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
441 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT; 441 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
442 442
443 count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK; 443 count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
444 444
445 if ((chan->mode & DMA_DW_MASK) == DMA_DW16) 445 if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
446 count <<= 1; 446 count <<= 1;
diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
index 0ea43c09803c..2988e9df85e3 100644
--- a/drivers/mmc/host/au1xmmc.c
+++ b/drivers/mmc/host/au1xmmc.c
@@ -90,7 +90,7 @@ struct au1xmmc_host {
90 struct mmc_request *mrq; 90 struct mmc_request *mrq;
91 91
92 u32 flags; 92 u32 flags;
93 u32 iobase; 93 void __iomem *iobase;
94 u32 clock; 94 u32 clock;
95 u32 bus_width; 95 u32 bus_width;
96 u32 power_mode; 96 u32 power_mode;
@@ -162,32 +162,33 @@ static inline int has_dbdma(void)
162 162
163static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) 163static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
164{ 164{
165 u32 val = au_readl(HOST_CONFIG(host)); 165 u32 val = __raw_readl(HOST_CONFIG(host));
166 val |= mask; 166 val |= mask;
167 au_writel(val, HOST_CONFIG(host)); 167 __raw_writel(val, HOST_CONFIG(host));
168 au_sync(); 168 wmb(); /* drain writebuffer */
169} 169}
170 170
171static inline void FLUSH_FIFO(struct au1xmmc_host *host) 171static inline void FLUSH_FIFO(struct au1xmmc_host *host)
172{ 172{
173 u32 val = au_readl(HOST_CONFIG2(host)); 173 u32 val = __raw_readl(HOST_CONFIG2(host));
174 174
175 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); 175 __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
176 au_sync_delay(1); 176 wmb(); /* drain writebuffer */
177 mdelay(1);
177 178
178 /* SEND_STOP will turn off clock control - this re-enables it */ 179 /* SEND_STOP will turn off clock control - this re-enables it */
179 val &= ~SD_CONFIG2_DF; 180 val &= ~SD_CONFIG2_DF;
180 181
181 au_writel(val, HOST_CONFIG2(host)); 182 __raw_writel(val, HOST_CONFIG2(host));
182 au_sync(); 183 wmb(); /* drain writebuffer */
183} 184}
184 185
185static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) 186static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
186{ 187{
187 u32 val = au_readl(HOST_CONFIG(host)); 188 u32 val = __raw_readl(HOST_CONFIG(host));
188 val &= ~mask; 189 val &= ~mask;
189 au_writel(val, HOST_CONFIG(host)); 190 __raw_writel(val, HOST_CONFIG(host));
190 au_sync(); 191 wmb(); /* drain writebuffer */
191} 192}
192 193
193static inline void SEND_STOP(struct au1xmmc_host *host) 194static inline void SEND_STOP(struct au1xmmc_host *host)
@@ -197,12 +198,13 @@ static inline void SEND_STOP(struct au1xmmc_host *host)
197 WARN_ON(host->status != HOST_S_DATA); 198 WARN_ON(host->status != HOST_S_DATA);
198 host->status = HOST_S_STOP; 199 host->status = HOST_S_STOP;
199 200
200 config2 = au_readl(HOST_CONFIG2(host)); 201 config2 = __raw_readl(HOST_CONFIG2(host));
201 au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); 202 __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
202 au_sync(); 203 wmb(); /* drain writebuffer */
203 204
204 /* Send the stop command */ 205 /* Send the stop command */
205 au_writel(STOP_CMD, HOST_CMD(host)); 206 __raw_writel(STOP_CMD, HOST_CMD(host));
207 wmb(); /* drain writebuffer */
206} 208}
207 209
208static void au1xmmc_set_power(struct au1xmmc_host *host, int state) 210static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
@@ -296,28 +298,28 @@ static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
296 } 298 }
297 } 299 }
298 300
299 au_writel(cmd->arg, HOST_CMDARG(host)); 301 __raw_writel(cmd->arg, HOST_CMDARG(host));
300 au_sync(); 302 wmb(); /* drain writebuffer */
301 303
302 if (wait) 304 if (wait)
303 IRQ_OFF(host, SD_CONFIG_CR); 305 IRQ_OFF(host, SD_CONFIG_CR);
304 306
305 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); 307 __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
306 au_sync(); 308 wmb(); /* drain writebuffer */
307 309
308 /* Wait for the command to go on the line */ 310 /* Wait for the command to go on the line */
309 while (au_readl(HOST_CMD(host)) & SD_CMD_GO) 311 while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
310 /* nop */; 312 /* nop */;
311 313
312 /* Wait for the command to come back */ 314 /* Wait for the command to come back */
313 if (wait) { 315 if (wait) {
314 u32 status = au_readl(HOST_STATUS(host)); 316 u32 status = __raw_readl(HOST_STATUS(host));
315 317
316 while (!(status & SD_STATUS_CR)) 318 while (!(status & SD_STATUS_CR))
317 status = au_readl(HOST_STATUS(host)); 319 status = __raw_readl(HOST_STATUS(host));
318 320
319 /* Clear the CR status */ 321 /* Clear the CR status */
320 au_writel(SD_STATUS_CR, HOST_STATUS(host)); 322 __raw_writel(SD_STATUS_CR, HOST_STATUS(host));
321 323
322 IRQ_ON(host, SD_CONFIG_CR); 324 IRQ_ON(host, SD_CONFIG_CR);
323 } 325 }
@@ -339,11 +341,11 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
339 data = mrq->cmd->data; 341 data = mrq->cmd->data;
340 342
341 if (status == 0) 343 if (status == 0)
342 status = au_readl(HOST_STATUS(host)); 344 status = __raw_readl(HOST_STATUS(host));
343 345
344 /* The transaction is really over when the SD_STATUS_DB bit is clear */ 346 /* The transaction is really over when the SD_STATUS_DB bit is clear */
345 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) 347 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
346 status = au_readl(HOST_STATUS(host)); 348 status = __raw_readl(HOST_STATUS(host));
347 349
348 data->error = 0; 350 data->error = 0;
349 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); 351 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
@@ -357,7 +359,7 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
357 data->error = -EILSEQ; 359 data->error = -EILSEQ;
358 360
359 /* Clear the CRC bits */ 361 /* Clear the CRC bits */
360 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); 362 __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
361 363
362 data->bytes_xfered = 0; 364 data->bytes_xfered = 0;
363 365
@@ -380,7 +382,7 @@ static void au1xmmc_tasklet_data(unsigned long param)
380{ 382{
381 struct au1xmmc_host *host = (struct au1xmmc_host *)param; 383 struct au1xmmc_host *host = (struct au1xmmc_host *)param;
382 384
383 u32 status = au_readl(HOST_STATUS(host)); 385 u32 status = __raw_readl(HOST_STATUS(host));
384 au1xmmc_data_complete(host, status); 386 au1xmmc_data_complete(host, status);
385} 387}
386 388
@@ -412,15 +414,15 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host)
412 max = AU1XMMC_MAX_TRANSFER; 414 max = AU1XMMC_MAX_TRANSFER;
413 415
414 for (count = 0; count < max; count++) { 416 for (count = 0; count < max; count++) {
415 status = au_readl(HOST_STATUS(host)); 417 status = __raw_readl(HOST_STATUS(host));
416 418
417 if (!(status & SD_STATUS_TH)) 419 if (!(status & SD_STATUS_TH))
418 break; 420 break;
419 421
420 val = *sg_ptr++; 422 val = *sg_ptr++;
421 423
422 au_writel((unsigned long)val, HOST_TXPORT(host)); 424 __raw_writel((unsigned long)val, HOST_TXPORT(host));
423 au_sync(); 425 wmb(); /* drain writebuffer */
424 } 426 }
425 427
426 host->pio.len -= count; 428 host->pio.len -= count;
@@ -472,7 +474,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host)
472 max = AU1XMMC_MAX_TRANSFER; 474 max = AU1XMMC_MAX_TRANSFER;
473 475
474 for (count = 0; count < max; count++) { 476 for (count = 0; count < max; count++) {
475 status = au_readl(HOST_STATUS(host)); 477 status = __raw_readl(HOST_STATUS(host));
476 478
477 if (!(status & SD_STATUS_NE)) 479 if (!(status & SD_STATUS_NE))
478 break; 480 break;
@@ -494,7 +496,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host)
494 break; 496 break;
495 } 497 }
496 498
497 val = au_readl(HOST_RXPORT(host)); 499 val = __raw_readl(HOST_RXPORT(host));
498 500
499 if (sg_ptr) 501 if (sg_ptr)
500 *sg_ptr++ = (unsigned char)(val & 0xFF); 502 *sg_ptr++ = (unsigned char)(val & 0xFF);
@@ -537,10 +539,10 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
537 539
538 if (cmd->flags & MMC_RSP_PRESENT) { 540 if (cmd->flags & MMC_RSP_PRESENT) {
539 if (cmd->flags & MMC_RSP_136) { 541 if (cmd->flags & MMC_RSP_136) {
540 r[0] = au_readl(host->iobase + SD_RESP3); 542 r[0] = __raw_readl(host->iobase + SD_RESP3);
541 r[1] = au_readl(host->iobase + SD_RESP2); 543 r[1] = __raw_readl(host->iobase + SD_RESP2);
542 r[2] = au_readl(host->iobase + SD_RESP1); 544 r[2] = __raw_readl(host->iobase + SD_RESP1);
543 r[3] = au_readl(host->iobase + SD_RESP0); 545 r[3] = __raw_readl(host->iobase + SD_RESP0);
544 546
545 /* The CRC is omitted from the response, so really 547 /* The CRC is omitted from the response, so really
546 * we only got 120 bytes, but the engine expects 548 * we only got 120 bytes, but the engine expects
@@ -559,7 +561,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
559 * that means that the OSR data starts at bit 31, 561 * that means that the OSR data starts at bit 31,
560 * so we can just read RESP0 and return that. 562 * so we can just read RESP0 and return that.
561 */ 563 */
562 cmd->resp[0] = au_readl(host->iobase + SD_RESP0); 564 cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
563 } 565 }
564 } 566 }
565 567
@@ -586,7 +588,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
586 u32 mask = SD_STATUS_DB | SD_STATUS_NE; 588 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
587 589
588 while((status & mask) != mask) 590 while((status & mask) != mask)
589 status = au_readl(HOST_STATUS(host)); 591 status = __raw_readl(HOST_STATUS(host));
590 } 592 }
591 593
592 au1xxx_dbdma_start(channel); 594 au1xxx_dbdma_start(channel);
@@ -606,13 +608,13 @@ static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
606 pbus /= 2; 608 pbus /= 2;
607 divisor = ((pbus / rate) / 2) - 1; 609 divisor = ((pbus / rate) / 2) - 1;
608 610
609 config = au_readl(HOST_CONFIG(host)); 611 config = __raw_readl(HOST_CONFIG(host));
610 612
611 config &= ~(SD_CONFIG_DIV); 613 config &= ~(SD_CONFIG_DIV);
612 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; 614 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
613 615
614 au_writel(config, HOST_CONFIG(host)); 616 __raw_writel(config, HOST_CONFIG(host));
615 au_sync(); 617 wmb(); /* drain writebuffer */
616} 618}
617 619
618static int au1xmmc_prepare_data(struct au1xmmc_host *host, 620static int au1xmmc_prepare_data(struct au1xmmc_host *host,
@@ -636,7 +638,7 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host,
636 if (host->dma.len == 0) 638 if (host->dma.len == 0)
637 return -ETIMEDOUT; 639 return -ETIMEDOUT;
638 640
639 au_writel(data->blksz - 1, HOST_BLKSIZE(host)); 641 __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
640 642
641 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { 643 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
642 int i; 644 int i;
@@ -723,31 +725,34 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
723static void au1xmmc_reset_controller(struct au1xmmc_host *host) 725static void au1xmmc_reset_controller(struct au1xmmc_host *host)
724{ 726{
725 /* Apply the clock */ 727 /* Apply the clock */
726 au_writel(SD_ENABLE_CE, HOST_ENABLE(host)); 728 __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
727 au_sync_delay(1); 729 wmb(); /* drain writebuffer */
730 mdelay(1);
728 731
729 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); 732 __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
730 au_sync_delay(5); 733 wmb(); /* drain writebuffer */
734 mdelay(5);
731 735
732 au_writel(~0, HOST_STATUS(host)); 736 __raw_writel(~0, HOST_STATUS(host));
733 au_sync(); 737 wmb(); /* drain writebuffer */
734 738
735 au_writel(0, HOST_BLKSIZE(host)); 739 __raw_writel(0, HOST_BLKSIZE(host));
736 au_writel(0x001fffff, HOST_TIMEOUT(host)); 740 __raw_writel(0x001fffff, HOST_TIMEOUT(host));
737 au_sync(); 741 wmb(); /* drain writebuffer */
738 742
739 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 743 __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
740 au_sync(); 744 wmb(); /* drain writebuffer */
741 745
742 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); 746 __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
743 au_sync_delay(1); 747 wmb(); /* drain writebuffer */
748 mdelay(1);
744 749
745 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); 750 __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
746 au_sync(); 751 wmb(); /* drain writebuffer */
747 752
748 /* Configure interrupts */ 753 /* Configure interrupts */
749 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); 754 __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
750 au_sync(); 755 wmb(); /* drain writebuffer */
751} 756}
752 757
753 758
@@ -767,7 +772,7 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
767 host->clock = ios->clock; 772 host->clock = ios->clock;
768 } 773 }
769 774
770 config2 = au_readl(HOST_CONFIG2(host)); 775 config2 = __raw_readl(HOST_CONFIG2(host));
771 switch (ios->bus_width) { 776 switch (ios->bus_width) {
772 case MMC_BUS_WIDTH_8: 777 case MMC_BUS_WIDTH_8:
773 config2 |= SD_CONFIG2_BB; 778 config2 |= SD_CONFIG2_BB;
@@ -780,8 +785,8 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
780 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB); 785 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
781 break; 786 break;
782 } 787 }
783 au_writel(config2, HOST_CONFIG2(host)); 788 __raw_writel(config2, HOST_CONFIG2(host));
784 au_sync(); 789 wmb(); /* drain writebuffer */
785} 790}
786 791
787#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) 792#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
@@ -793,7 +798,7 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
793 struct au1xmmc_host *host = dev_id; 798 struct au1xmmc_host *host = dev_id;
794 u32 status; 799 u32 status;
795 800
796 status = au_readl(HOST_STATUS(host)); 801 status = __raw_readl(HOST_STATUS(host));
797 802
798 if (!(status & SD_STATUS_I)) 803 if (!(status & SD_STATUS_I))
799 return IRQ_NONE; /* not ours */ 804 return IRQ_NONE; /* not ours */
@@ -839,8 +844,8 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
839 status); 844 status);
840 } 845 }
841 846
842 au_writel(status, HOST_STATUS(host)); 847 __raw_writel(status, HOST_STATUS(host));
843 au_sync(); 848 wmb(); /* drain writebuffer */
844 849
845 return IRQ_HANDLED; 850 return IRQ_HANDLED;
846} 851}
@@ -976,7 +981,7 @@ static int au1xmmc_probe(struct platform_device *pdev)
976 goto out1; 981 goto out1;
977 } 982 }
978 983
979 host->iobase = (unsigned long)ioremap(r->start, 0x3c); 984 host->iobase = ioremap(r->start, 0x3c);
980 if (!host->iobase) { 985 if (!host->iobase) {
981 dev_err(&pdev->dev, "cannot remap mmio\n"); 986 dev_err(&pdev->dev, "cannot remap mmio\n");
982 goto out2; 987 goto out2;
@@ -1075,7 +1080,7 @@ static int au1xmmc_probe(struct platform_device *pdev)
1075 1080
1076 platform_set_drvdata(pdev, host); 1081 platform_set_drvdata(pdev, host);
1077 1082
1078 pr_info(DRIVER_NAME ": MMC Controller %d set up at %8.8X" 1083 pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
1079 " (mode=%s)\n", pdev->id, host->iobase, 1084 " (mode=%s)\n", pdev->id, host->iobase,
1080 host->flags & HOST_F_DMA ? "dma" : "pio"); 1085 host->flags & HOST_F_DMA ? "dma" : "pio");
1081 1086
@@ -1087,10 +1092,10 @@ out6:
1087 led_classdev_unregister(host->platdata->led); 1092 led_classdev_unregister(host->platdata->led);
1088out5: 1093out5:
1089#endif 1094#endif
1090 au_writel(0, HOST_ENABLE(host)); 1095 __raw_writel(0, HOST_ENABLE(host));
1091 au_writel(0, HOST_CONFIG(host)); 1096 __raw_writel(0, HOST_CONFIG(host));
1092 au_writel(0, HOST_CONFIG2(host)); 1097 __raw_writel(0, HOST_CONFIG2(host));
1093 au_sync(); 1098 wmb(); /* drain writebuffer */
1094 1099
1095 if (host->flags & HOST_F_DBDMA) 1100 if (host->flags & HOST_F_DBDMA)
1096 au1xmmc_dbdma_shutdown(host); 1101 au1xmmc_dbdma_shutdown(host);
@@ -1130,10 +1135,10 @@ static int au1xmmc_remove(struct platform_device *pdev)
1130 !(host->mmc->caps & MMC_CAP_NEEDS_POLL)) 1135 !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1131 host->platdata->cd_setup(host->mmc, 0); 1136 host->platdata->cd_setup(host->mmc, 0);
1132 1137
1133 au_writel(0, HOST_ENABLE(host)); 1138 __raw_writel(0, HOST_ENABLE(host));
1134 au_writel(0, HOST_CONFIG(host)); 1139 __raw_writel(0, HOST_CONFIG(host));
1135 au_writel(0, HOST_CONFIG2(host)); 1140 __raw_writel(0, HOST_CONFIG2(host));
1136 au_sync(); 1141 wmb(); /* drain writebuffer */
1137 1142
1138 tasklet_kill(&host->data_task); 1143 tasklet_kill(&host->data_task);
1139 tasklet_kill(&host->finish_task); 1144 tasklet_kill(&host->finish_task);
@@ -1158,11 +1163,11 @@ static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1158{ 1163{
1159 struct au1xmmc_host *host = platform_get_drvdata(pdev); 1164 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1160 1165
1161 au_writel(0, HOST_CONFIG2(host)); 1166 __raw_writel(0, HOST_CONFIG2(host));
1162 au_writel(0, HOST_CONFIG(host)); 1167 __raw_writel(0, HOST_CONFIG(host));
1163 au_writel(0xffffffff, HOST_STATUS(host)); 1168 __raw_writel(0xffffffff, HOST_STATUS(host));
1164 au_writel(0, HOST_ENABLE(host)); 1169 __raw_writel(0, HOST_ENABLE(host));
1165 au_sync(); 1170 wmb(); /* drain writebuffer */
1166 1171
1167 return 0; 1172 return 0;
1168} 1173}
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 6cece6e7ee6b..77d6c17b38c2 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -41,7 +41,7 @@ static u_char au_read_byte(struct mtd_info *mtd)
41{ 41{
42 struct nand_chip *this = mtd->priv; 42 struct nand_chip *this = mtd->priv;
43 u_char ret = readb(this->IO_ADDR_R); 43 u_char ret = readb(this->IO_ADDR_R);
44 au_sync(); 44 wmb(); /* drain writebuffer */
45 return ret; 45 return ret;
46} 46}
47 47
@@ -56,7 +56,7 @@ static void au_write_byte(struct mtd_info *mtd, u_char byte)
56{ 56{
57 struct nand_chip *this = mtd->priv; 57 struct nand_chip *this = mtd->priv;
58 writeb(byte, this->IO_ADDR_W); 58 writeb(byte, this->IO_ADDR_W);
59 au_sync(); 59 wmb(); /* drain writebuffer */
60} 60}
61 61
62/** 62/**
@@ -69,7 +69,7 @@ static u_char au_read_byte16(struct mtd_info *mtd)
69{ 69{
70 struct nand_chip *this = mtd->priv; 70 struct nand_chip *this = mtd->priv;
71 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); 71 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
72 au_sync(); 72 wmb(); /* drain writebuffer */
73 return ret; 73 return ret;
74} 74}
75 75
@@ -84,7 +84,7 @@ static void au_write_byte16(struct mtd_info *mtd, u_char byte)
84{ 84{
85 struct nand_chip *this = mtd->priv; 85 struct nand_chip *this = mtd->priv;
86 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); 86 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
87 au_sync(); 87 wmb(); /* drain writebuffer */
88} 88}
89 89
90/** 90/**
@@ -97,7 +97,7 @@ static u16 au_read_word(struct mtd_info *mtd)
97{ 97{
98 struct nand_chip *this = mtd->priv; 98 struct nand_chip *this = mtd->priv;
99 u16 ret = readw(this->IO_ADDR_R); 99 u16 ret = readw(this->IO_ADDR_R);
100 au_sync(); 100 wmb(); /* drain writebuffer */
101 return ret; 101 return ret;
102} 102}
103 103
@@ -116,7 +116,7 @@ static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
116 116
117 for (i = 0; i < len; i++) { 117 for (i = 0; i < len; i++) {
118 writeb(buf[i], this->IO_ADDR_W); 118 writeb(buf[i], this->IO_ADDR_W);
119 au_sync(); 119 wmb(); /* drain writebuffer */
120 } 120 }
121} 121}
122 122
@@ -135,7 +135,7 @@ static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
135 135
136 for (i = 0; i < len; i++) { 136 for (i = 0; i < len; i++) {
137 buf[i] = readb(this->IO_ADDR_R); 137 buf[i] = readb(this->IO_ADDR_R);
138 au_sync(); 138 wmb(); /* drain writebuffer */
139 } 139 }
140} 140}
141 141
@@ -156,7 +156,7 @@ static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
156 156
157 for (i = 0; i < len; i++) { 157 for (i = 0; i < len; i++) {
158 writew(p[i], this->IO_ADDR_W); 158 writew(p[i], this->IO_ADDR_W);
159 au_sync(); 159 wmb(); /* drain writebuffer */
160 } 160 }
161 161
162} 162}
@@ -178,7 +178,7 @@ static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
178 178
179 for (i = 0; i < len; i++) { 179 for (i = 0; i < len; i++) {
180 p[i] = readw(this->IO_ADDR_R); 180 p[i] = readw(this->IO_ADDR_R);
181 au_sync(); 181 wmb(); /* drain writebuffer */
182 } 182 }
183} 183}
184 184
@@ -234,8 +234,7 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
234 234
235 this->IO_ADDR_R = this->IO_ADDR_W; 235 this->IO_ADDR_R = this->IO_ADDR_W;
236 236
237 /* Drain the writebuffer */ 237 wmb(); /* Drain the writebuffer */
238 au_sync();
239} 238}
240 239
241int au1550_device_ready(struct mtd_info *mtd) 240int au1550_device_ready(struct mtd_info *mtd)
diff --git a/drivers/net/ethernet/amd/au1000_eth.c b/drivers/net/ethernet/amd/au1000_eth.c
index ad8b058c8068..31c48a7ac2b6 100644
--- a/drivers/net/ethernet/amd/au1000_eth.c
+++ b/drivers/net/ethernet/amd/au1000_eth.c
@@ -270,10 +270,12 @@ static void au1000_enable_mac(struct net_device *dev, int force_reset)
270 270
271 if (force_reset || (!aup->mac_enabled)) { 271 if (force_reset || (!aup->mac_enabled)) {
272 writel(MAC_EN_CLOCK_ENABLE, aup->enable); 272 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
273 au_sync_delay(2); 273 wmb(); /* drain writebuffer */
274 mdelay(2);
274 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 275 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
275 | MAC_EN_CLOCK_ENABLE), aup->enable); 276 | MAC_EN_CLOCK_ENABLE), aup->enable);
276 au_sync_delay(2); 277 wmb(); /* drain writebuffer */
278 mdelay(2);
277 279
278 aup->mac_enabled = 1; 280 aup->mac_enabled = 1;
279 } 281 }
@@ -391,7 +393,8 @@ static void au1000_hard_stop(struct net_device *dev)
391 reg = readl(&aup->mac->control); 393 reg = readl(&aup->mac->control);
392 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); 394 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
393 writel(reg, &aup->mac->control); 395 writel(reg, &aup->mac->control);
394 au_sync_delay(10); 396 wmb(); /* drain writebuffer */
397 mdelay(10);
395} 398}
396 399
397static void au1000_enable_rx_tx(struct net_device *dev) 400static void au1000_enable_rx_tx(struct net_device *dev)
@@ -404,7 +407,8 @@ static void au1000_enable_rx_tx(struct net_device *dev)
404 reg = readl(&aup->mac->control); 407 reg = readl(&aup->mac->control);
405 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); 408 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
406 writel(reg, &aup->mac->control); 409 writel(reg, &aup->mac->control);
407 au_sync_delay(10); 410 wmb(); /* drain writebuffer */
411 mdelay(10);
408} 412}
409 413
410static void 414static void
@@ -454,7 +458,8 @@ au1000_adjust_link(struct net_device *dev)
454 reg |= MAC_DISABLE_RX_OWN; 458 reg |= MAC_DISABLE_RX_OWN;
455 } 459 }
456 writel(reg, &aup->mac->control); 460 writel(reg, &aup->mac->control);
457 au_sync_delay(1); 461 wmb(); /* drain writebuffer */
462 mdelay(1);
458 463
459 au1000_enable_rx_tx(dev); 464 au1000_enable_rx_tx(dev);
460 aup->old_duplex = phydev->duplex; 465 aup->old_duplex = phydev->duplex;
@@ -618,9 +623,11 @@ static void au1000_reset_mac_unlocked(struct net_device *dev)
618 au1000_hard_stop(dev); 623 au1000_hard_stop(dev);
619 624
620 writel(MAC_EN_CLOCK_ENABLE, aup->enable); 625 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
621 au_sync_delay(2); 626 wmb(); /* drain writebuffer */
627 mdelay(2);
622 writel(0, aup->enable); 628 writel(0, aup->enable);
623 au_sync_delay(2); 629 wmb(); /* drain writebuffer */
630 mdelay(2);
624 631
625 aup->tx_full = 0; 632 aup->tx_full = 0;
626 for (i = 0; i < NUM_RX_DMA; i++) { 633 for (i = 0; i < NUM_RX_DMA; i++) {
@@ -770,7 +777,7 @@ static int au1000_init(struct net_device *dev)
770 for (i = 0; i < NUM_RX_DMA; i++) 777 for (i = 0; i < NUM_RX_DMA; i++)
771 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; 778 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
772 779
773 au_sync(); 780 wmb(); /* drain writebuffer */
774 781
775 control = MAC_RX_ENABLE | MAC_TX_ENABLE; 782 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
776#ifndef CONFIG_CPU_LITTLE_ENDIAN 783#ifndef CONFIG_CPU_LITTLE_ENDIAN
@@ -787,7 +794,7 @@ static int au1000_init(struct net_device *dev)
787 794
788 writel(control, &aup->mac->control); 795 writel(control, &aup->mac->control);
789 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ 796 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
790 au_sync(); 797 wmb(); /* drain writebuffer */
791 798
792 spin_unlock_irqrestore(&aup->lock, flags); 799 spin_unlock_irqrestore(&aup->lock, flags);
793 return 0; 800 return 0;
@@ -878,7 +885,7 @@ static int au1000_rx(struct net_device *dev)
878 } 885 }
879 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); 886 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
880 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); 887 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
881 au_sync(); 888 wmb(); /* drain writebuffer */
882 889
883 /* next descriptor */ 890 /* next descriptor */
884 prxd = aup->rx_dma_ring[aup->rx_head]; 891 prxd = aup->rx_dma_ring[aup->rx_head];
@@ -926,7 +933,7 @@ static void au1000_tx_ack(struct net_device *dev)
926 au1000_update_tx_stats(dev, ptxd->status); 933 au1000_update_tx_stats(dev, ptxd->status);
927 ptxd->buff_stat &= ~TX_T_DONE; 934 ptxd->buff_stat &= ~TX_T_DONE;
928 ptxd->len = 0; 935 ptxd->len = 0;
929 au_sync(); 936 wmb(); /* drain writebuffer */
930 937
931 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); 938 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
932 ptxd = aup->tx_dma_ring[aup->tx_tail]; 939 ptxd = aup->tx_dma_ring[aup->tx_tail];
@@ -1057,7 +1064,7 @@ static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1057 ps->tx_bytes += ptxd->len; 1064 ps->tx_bytes += ptxd->len;
1058 1065
1059 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; 1066 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1060 au_sync(); 1067 wmb(); /* drain writebuffer */
1061 dev_kfree_skb(skb); 1068 dev_kfree_skb(skb);
1062 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); 1069 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1063 return NETDEV_TX_OK; 1070 return NETDEV_TX_OK;
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c
index 67375a11d4bd..ffb42f12d5a1 100644
--- a/drivers/spi/spi-au1550.c
+++ b/drivers/spi/spi-au1550.c
@@ -141,13 +141,13 @@ static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
141 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO 141 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
142 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO 142 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
143 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD; 143 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
144 au_sync(); 144 wmb(); /* drain writebuffer */
145 145
146 hw->regs->psc_spievent = 146 hw->regs->psc_spievent =
147 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO 147 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
148 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO 148 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
149 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD; 149 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
150 au_sync(); 150 wmb(); /* drain writebuffer */
151} 151}
152 152
153static void au1550_spi_reset_fifos(struct au1550_spi *hw) 153static void au1550_spi_reset_fifos(struct au1550_spi *hw)
@@ -155,10 +155,10 @@ static void au1550_spi_reset_fifos(struct au1550_spi *hw)
155 u32 pcr; 155 u32 pcr;
156 156
157 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC; 157 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
158 au_sync(); 158 wmb(); /* drain writebuffer */
159 do { 159 do {
160 pcr = hw->regs->psc_spipcr; 160 pcr = hw->regs->psc_spipcr;
161 au_sync(); 161 wmb(); /* drain writebuffer */
162 } while (pcr != 0); 162 } while (pcr != 0);
163} 163}
164 164
@@ -188,9 +188,9 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value)
188 au1550_spi_bits_handlers_set(hw, spi->bits_per_word); 188 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
189 189
190 cfg = hw->regs->psc_spicfg; 190 cfg = hw->regs->psc_spicfg;
191 au_sync(); 191 wmb(); /* drain writebuffer */
192 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; 192 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
193 au_sync(); 193 wmb(); /* drain writebuffer */
194 194
195 if (spi->mode & SPI_CPOL) 195 if (spi->mode & SPI_CPOL)
196 cfg |= PSC_SPICFG_BI; 196 cfg |= PSC_SPICFG_BI;
@@ -218,10 +218,10 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value)
218 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz); 218 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
219 219
220 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE; 220 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
221 au_sync(); 221 wmb(); /* drain writebuffer */
222 do { 222 do {
223 stat = hw->regs->psc_spistat; 223 stat = hw->regs->psc_spistat;
224 au_sync(); 224 wmb(); /* drain writebuffer */
225 } while ((stat & PSC_SPISTAT_DR) == 0); 225 } while ((stat & PSC_SPISTAT_DR) == 0);
226 226
227 if (hw->pdata->activate_cs) 227 if (hw->pdata->activate_cs)
@@ -252,9 +252,9 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
252 au1550_spi_bits_handlers_set(hw, spi->bits_per_word); 252 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
253 253
254 cfg = hw->regs->psc_spicfg; 254 cfg = hw->regs->psc_spicfg;
255 au_sync(); 255 wmb(); /* drain writebuffer */
256 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; 256 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
257 au_sync(); 257 wmb(); /* drain writebuffer */
258 258
259 if (hw->usedma && bpw <= 8) 259 if (hw->usedma && bpw <= 8)
260 cfg &= ~PSC_SPICFG_DD_DISABLE; 260 cfg &= ~PSC_SPICFG_DD_DISABLE;
@@ -268,12 +268,12 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
268 cfg |= au1550_spi_baudcfg(hw, hz); 268 cfg |= au1550_spi_baudcfg(hw, hz);
269 269
270 hw->regs->psc_spicfg = cfg; 270 hw->regs->psc_spicfg = cfg;
271 au_sync(); 271 wmb(); /* drain writebuffer */
272 272
273 if (cfg & PSC_SPICFG_DE_ENABLE) { 273 if (cfg & PSC_SPICFG_DE_ENABLE) {
274 do { 274 do {
275 stat = hw->regs->psc_spistat; 275 stat = hw->regs->psc_spistat;
276 au_sync(); 276 wmb(); /* drain writebuffer */
277 } while ((stat & PSC_SPISTAT_DR) == 0); 277 } while ((stat & PSC_SPISTAT_DR) == 0);
278 } 278 }
279 279
@@ -396,11 +396,11 @@ static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
396 396
397 /* by default enable nearly all events interrupt */ 397 /* by default enable nearly all events interrupt */
398 hw->regs->psc_spimsk = PSC_SPIMSK_SD; 398 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
399 au_sync(); 399 wmb(); /* drain writebuffer */
400 400
401 /* start the transfer */ 401 /* start the transfer */
402 hw->regs->psc_spipcr = PSC_SPIPCR_MS; 402 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
403 au_sync(); 403 wmb(); /* drain writebuffer */
404 404
405 wait_for_completion(&hw->master_done); 405 wait_for_completion(&hw->master_done);
406 406
@@ -429,7 +429,7 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
429 429
430 stat = hw->regs->psc_spistat; 430 stat = hw->regs->psc_spistat;
431 evnt = hw->regs->psc_spievent; 431 evnt = hw->regs->psc_spievent;
432 au_sync(); 432 wmb(); /* drain writebuffer */
433 if ((stat & PSC_SPISTAT_DI) == 0) { 433 if ((stat & PSC_SPISTAT_DI) == 0) {
434 dev_err(hw->dev, "Unexpected IRQ!\n"); 434 dev_err(hw->dev, "Unexpected IRQ!\n");
435 return IRQ_NONE; 435 return IRQ_NONE;
@@ -484,7 +484,7 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
484static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \ 484static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
485{ \ 485{ \
486 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \ 486 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
487 au_sync(); \ 487 wmb(); /* drain writebuffer */ \
488 if (hw->rx) { \ 488 if (hw->rx) { \
489 *(u##size *)hw->rx = (u##size)fifoword; \ 489 *(u##size *)hw->rx = (u##size)fifoword; \
490 hw->rx += (size) / 8; \ 490 hw->rx += (size) / 8; \
@@ -504,7 +504,7 @@ static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
504 if (hw->tx_count >= hw->len) \ 504 if (hw->tx_count >= hw->len) \
505 fifoword |= PSC_SPITXRX_LC; \ 505 fifoword |= PSC_SPITXRX_LC; \
506 hw->regs->psc_spitxrx = fifoword; \ 506 hw->regs->psc_spitxrx = fifoword; \
507 au_sync(); \ 507 wmb(); /* drain writebuffer */ \
508} 508}
509 509
510AU1550_SPI_RX_WORD(8,0xff) 510AU1550_SPI_RX_WORD(8,0xff)
@@ -539,18 +539,18 @@ static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
539 } 539 }
540 540
541 stat = hw->regs->psc_spistat; 541 stat = hw->regs->psc_spistat;
542 au_sync(); 542 wmb(); /* drain writebuffer */
543 if (stat & PSC_SPISTAT_TF) 543 if (stat & PSC_SPISTAT_TF)
544 break; 544 break;
545 } 545 }
546 546
547 /* enable event interrupts */ 547 /* enable event interrupts */
548 hw->regs->psc_spimsk = mask; 548 hw->regs->psc_spimsk = mask;
549 au_sync(); 549 wmb(); /* drain writebuffer */
550 550
551 /* start the transfer */ 551 /* start the transfer */
552 hw->regs->psc_spipcr = PSC_SPIPCR_MS; 552 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
553 au_sync(); 553 wmb(); /* drain writebuffer */
554 554
555 wait_for_completion(&hw->master_done); 555 wait_for_completion(&hw->master_done);
556 556
@@ -564,7 +564,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
564 564
565 stat = hw->regs->psc_spistat; 565 stat = hw->regs->psc_spistat;
566 evnt = hw->regs->psc_spievent; 566 evnt = hw->regs->psc_spievent;
567 au_sync(); 567 wmb(); /* drain writebuffer */
568 if ((stat & PSC_SPISTAT_DI) == 0) { 568 if ((stat & PSC_SPISTAT_DI) == 0) {
569 dev_err(hw->dev, "Unexpected IRQ!\n"); 569 dev_err(hw->dev, "Unexpected IRQ!\n");
570 return IRQ_NONE; 570 return IRQ_NONE;
@@ -594,7 +594,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
594 do { 594 do {
595 busy = 0; 595 busy = 0;
596 stat = hw->regs->psc_spistat; 596 stat = hw->regs->psc_spistat;
597 au_sync(); 597 wmb(); /* drain writebuffer */
598 598
599 /* 599 /*
600 * Take care to not let the Rx FIFO overflow. 600 * Take care to not let the Rx FIFO overflow.
@@ -615,7 +615,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
615 } while (busy); 615 } while (busy);
616 616
617 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR; 617 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
618 au_sync(); 618 wmb(); /* drain writebuffer */
619 619
620 /* 620 /*
621 * Restart the SPI transmission in case of a transmit underflow. 621 * Restart the SPI transmission in case of a transmit underflow.
@@ -634,9 +634,9 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
634 */ 634 */
635 if (evnt & PSC_SPIEVNT_TU) { 635 if (evnt & PSC_SPIEVNT_TU) {
636 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD; 636 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
637 au_sync(); 637 wmb(); /* drain writebuffer */
638 hw->regs->psc_spipcr = PSC_SPIPCR_MS; 638 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
639 au_sync(); 639 wmb(); /* drain writebuffer */
640 } 640 }
641 641
642 if (hw->rx_count >= hw->len) { 642 if (hw->rx_count >= hw->len) {
@@ -690,19 +690,19 @@ static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
690 690
691 /* set up the PSC for SPI mode */ 691 /* set up the PSC for SPI mode */
692 hw->regs->psc_ctrl = PSC_CTRL_DISABLE; 692 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
693 au_sync(); 693 wmb(); /* drain writebuffer */
694 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE; 694 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
695 au_sync(); 695 wmb(); /* drain writebuffer */
696 696
697 hw->regs->psc_spicfg = 0; 697 hw->regs->psc_spicfg = 0;
698 au_sync(); 698 wmb(); /* drain writebuffer */
699 699
700 hw->regs->psc_ctrl = PSC_CTRL_ENABLE; 700 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
701 au_sync(); 701 wmb(); /* drain writebuffer */
702 702
703 do { 703 do {
704 stat = hw->regs->psc_spistat; 704 stat = hw->regs->psc_spistat;
705 au_sync(); 705 wmb(); /* drain writebuffer */
706 } while ((stat & PSC_SPISTAT_SR) == 0); 706 } while ((stat & PSC_SPISTAT_SR) == 0);
707 707
708 708
@@ -717,16 +717,16 @@ static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
717#endif 717#endif
718 718
719 hw->regs->psc_spicfg = cfg; 719 hw->regs->psc_spicfg = cfg;
720 au_sync(); 720 wmb(); /* drain writebuffer */
721 721
722 au1550_spi_mask_ack_all(hw); 722 au1550_spi_mask_ack_all(hw);
723 723
724 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE; 724 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
725 au_sync(); 725 wmb(); /* drain writebuffer */
726 726
727 do { 727 do {
728 stat = hw->regs->psc_spistat; 728 stat = hw->regs->psc_spistat;
729 au_sync(); 729 wmb(); /* drain writebuffer */
730 } while ((stat & PSC_SPISTAT_DR) == 0); 730 } while ((stat & PSC_SPISTAT_DR) == 0);
731 731
732 au1550_spi_reset_fifos(hw); 732 au1550_spi_reset_fifos(hw);
diff --git a/drivers/video/fbdev/au1100fb.c b/drivers/video/fbdev/au1100fb.c
index c0832eaff4d1..c163424de223 100644
--- a/drivers/video/fbdev/au1100fb.c
+++ b/drivers/video/fbdev/au1100fb.c
@@ -113,7 +113,7 @@ static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
113 case VESA_NO_BLANKING: 113 case VESA_NO_BLANKING:
114 /* Turn on panel */ 114 /* Turn on panel */
115 fbdev->regs->lcd_control |= LCD_CONTROL_GO; 115 fbdev->regs->lcd_control |= LCD_CONTROL_GO;
116 au_sync(); 116 wmb(); /* drain writebuffer */
117 break; 117 break;
118 118
119 case VESA_VSYNC_SUSPEND: 119 case VESA_VSYNC_SUSPEND:
@@ -121,7 +121,7 @@ static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
121 case VESA_POWERDOWN: 121 case VESA_POWERDOWN:
122 /* Turn off panel */ 122 /* Turn off panel */
123 fbdev->regs->lcd_control &= ~LCD_CONTROL_GO; 123 fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
124 au_sync(); 124 wmb(); /* drain writebuffer */
125 break; 125 break;
126 default: 126 default:
127 break; 127 break;
diff --git a/drivers/video/fbdev/au1200fb.c b/drivers/video/fbdev/au1200fb.c
index 2d77334af41b..1c8e106dca00 100644
--- a/drivers/video/fbdev/au1200fb.c
+++ b/drivers/video/fbdev/au1200fb.c
@@ -764,7 +764,7 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane,
764 764
765 /* Disable the window while making changes, then restore WINEN */ 765 /* Disable the window while making changes, then restore WINEN */
766 winenable = lcd->winenable & (1 << plane); 766 winenable = lcd->winenable & (1 << plane);
767 au_sync(); 767 wmb(); /* drain writebuffer */
768 lcd->winenable &= ~(1 << plane); 768 lcd->winenable &= ~(1 << plane);
769 lcd->window[plane].winctrl0 = winctrl0; 769 lcd->window[plane].winctrl0 = winctrl0;
770 lcd->window[plane].winctrl1 = winctrl1; 770 lcd->window[plane].winctrl1 = winctrl1;
@@ -772,7 +772,7 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane,
772 lcd->window[plane].winbuf1 = fbdev->fb_phys; 772 lcd->window[plane].winbuf1 = fbdev->fb_phys;
773 lcd->window[plane].winbufctrl = 0; /* select winbuf0 */ 773 lcd->window[plane].winbufctrl = 0; /* select winbuf0 */
774 lcd->winenable |= winenable; 774 lcd->winenable |= winenable;
775 au_sync(); 775 wmb(); /* drain writebuffer */
776 776
777 return 0; 777 return 0;
778} 778}
@@ -788,22 +788,21 @@ static void au1200_setpanel(struct panel_settings *newpanel,
788 /* Make sure all windows disabled */ 788 /* Make sure all windows disabled */
789 winenable = lcd->winenable; 789 winenable = lcd->winenable;
790 lcd->winenable = 0; 790 lcd->winenable = 0;
791 au_sync(); 791 wmb(); /* drain writebuffer */
792 /* 792 /*
793 * Ensure everything is disabled before reconfiguring 793 * Ensure everything is disabled before reconfiguring
794 */ 794 */
795 if (lcd->screen & LCD_SCREEN_SEN) { 795 if (lcd->screen & LCD_SCREEN_SEN) {
796 /* Wait for vertical sync period */ 796 /* Wait for vertical sync period */
797 lcd->intstatus = LCD_INT_SS; 797 lcd->intstatus = LCD_INT_SS;
798 while ((lcd->intstatus & LCD_INT_SS) == 0) { 798 while ((lcd->intstatus & LCD_INT_SS) == 0)
799 au_sync(); 799 ;
800 }
801 800
802 lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/ 801 lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/
803 802
804 do { 803 do {
805 lcd->intstatus = lcd->intstatus; /*clear interrupts*/ 804 lcd->intstatus = lcd->intstatus; /*clear interrupts*/
806 au_sync(); 805 wmb(); /* drain writebuffer */
807 /*wait for controller to shut down*/ 806 /*wait for controller to shut down*/
808 } while ((lcd->intstatus & LCD_INT_SD) == 0); 807 } while ((lcd->intstatus & LCD_INT_SD) == 0);
809 808
@@ -847,7 +846,7 @@ static void au1200_setpanel(struct panel_settings *newpanel,
847 lcd->pwmhi = panel->mode_pwmhi; 846 lcd->pwmhi = panel->mode_pwmhi;
848 lcd->outmask = panel->mode_outmask; 847 lcd->outmask = panel->mode_outmask;
849 lcd->fifoctrl = panel->mode_fifoctrl; 848 lcd->fifoctrl = panel->mode_fifoctrl;
850 au_sync(); 849 wmb(); /* drain writebuffer */
851 850
852 /* fixme: Check window settings to make sure still valid 851 /* fixme: Check window settings to make sure still valid
853 * for new geometry */ 852 * for new geometry */
@@ -863,7 +862,7 @@ static void au1200_setpanel(struct panel_settings *newpanel,
863 * Re-enable screen now that it is configured 862 * Re-enable screen now that it is configured
864 */ 863 */
865 lcd->screen |= LCD_SCREEN_SEN; 864 lcd->screen |= LCD_SCREEN_SEN;
866 au_sync(); 865 wmb(); /* drain writebuffer */
867 866
868 /* Call init of panel */ 867 /* Call init of panel */
869 if (pd->panel_init) 868 if (pd->panel_init)
@@ -956,7 +955,7 @@ static void au1200_setmode(struct au1200fb_device *fbdev)
956 | LCD_WINCTRL2_SCY_1 955 | LCD_WINCTRL2_SCY_1
957 ) ; 956 ) ;
958 lcd->winenable |= win->w[plane].mode_winenable; 957 lcd->winenable |= win->w[plane].mode_winenable;
959 au_sync(); 958 wmb(); /* drain writebuffer */
960} 959}
961 960
962 961
@@ -1270,7 +1269,7 @@ static void set_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
1270 1269
1271 if (pdata->flags & SCREEN_MASK) 1270 if (pdata->flags & SCREEN_MASK)
1272 lcd->colorkeymsk = pdata->mask; 1271 lcd->colorkeymsk = pdata->mask;
1273 au_sync(); 1272 wmb(); /* drain writebuffer */
1274} 1273}
1275 1274
1276static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata) 1275static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
@@ -1288,7 +1287,7 @@ static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
1288 hi1 = (lcd->pwmhi >> 16) + 1; 1287 hi1 = (lcd->pwmhi >> 16) + 1;
1289 divider = (lcd->pwmdiv & 0x3FFFF) + 1; 1288 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
1290 pdata->brightness = ((hi1 << 8) / divider) - 1; 1289 pdata->brightness = ((hi1 << 8) / divider) - 1;
1291 au_sync(); 1290 wmb(); /* drain writebuffer */
1292} 1291}
1293 1292
1294static void set_window(unsigned int plane, 1293static void set_window(unsigned int plane,
@@ -1387,7 +1386,7 @@ static void set_window(unsigned int plane,
1387 val |= (pdata->enable & 1) << plane; 1386 val |= (pdata->enable & 1) << plane;
1388 lcd->winenable = val; 1387 lcd->winenable = val;
1389 } 1388 }
1390 au_sync(); 1389 wmb(); /* drain writebuffer */
1391} 1390}
1392 1391
1393static void get_window(unsigned int plane, 1392static void get_window(unsigned int plane,
@@ -1414,7 +1413,7 @@ static void get_window(unsigned int plane,
1414 pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21; 1413 pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21;
1415 1414
1416 pdata->enable = (lcd->winenable >> plane) & 1; 1415 pdata->enable = (lcd->winenable >> plane) & 1;
1417 au_sync(); 1416 wmb(); /* drain writebuffer */
1418} 1417}
1419 1418
1420static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, 1419static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
@@ -1511,7 +1510,7 @@ static irqreturn_t au1200fb_handle_irq(int irq, void* dev_id)
1511{ 1510{
1512 /* Nothing to do for now, just clear any pending interrupt */ 1511 /* Nothing to do for now, just clear any pending interrupt */
1513 lcd->intstatus = lcd->intstatus; 1512 lcd->intstatus = lcd->intstatus;
1514 au_sync(); 1513 wmb(); /* drain writebuffer */
1515 1514
1516 return IRQ_HANDLED; 1515 return IRQ_HANDLED;
1517} 1516}
@@ -1809,7 +1808,7 @@ static int au1200fb_drv_suspend(struct device *dev)
1809 au1200_setpanel(NULL, pd); 1808 au1200_setpanel(NULL, pd);
1810 1809
1811 lcd->outmask = 0; 1810 lcd->outmask = 0;
1812 au_sync(); 1811 wmb(); /* drain writebuffer */
1813 1812
1814 return 0; 1813 return 0;
1815} 1814}
diff --git a/sound/soc/au1x/psc-ac97.c b/sound/soc/au1x/psc-ac97.c
index 986dcec79fa0..84f31e1f9d24 100644
--- a/sound/soc/au1x/psc-ac97.c
+++ b/sound/soc/au1x/psc-ac97.c
@@ -79,28 +79,28 @@ static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
79 unsigned short retry, tmo; 79 unsigned short retry, tmo;
80 unsigned long data; 80 unsigned long data;
81 81
82 au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); 82 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
83 au_sync(); 83 wmb(); /* drain writebuffer */
84 84
85 retry = AC97_RW_RETRIES; 85 retry = AC97_RW_RETRIES;
86 do { 86 do {
87 mutex_lock(&pscdata->lock); 87 mutex_lock(&pscdata->lock);
88 88
89 au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), 89 __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
90 AC97_CDC(pscdata)); 90 AC97_CDC(pscdata));
91 au_sync(); 91 wmb(); /* drain writebuffer */
92 92
93 tmo = 20; 93 tmo = 20;
94 do { 94 do {
95 udelay(21); 95 udelay(21);
96 if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) 96 if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
97 break; 97 break;
98 } while (--tmo); 98 } while (--tmo);
99 99
100 data = au_readl(AC97_CDC(pscdata)); 100 data = __raw_readl(AC97_CDC(pscdata));
101 101
102 au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); 102 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
103 au_sync(); 103 wmb(); /* drain writebuffer */
104 104
105 mutex_unlock(&pscdata->lock); 105 mutex_unlock(&pscdata->lock);
106 106
@@ -119,26 +119,26 @@ static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
119 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); 119 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
120 unsigned int tmo, retry; 120 unsigned int tmo, retry;
121 121
122 au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); 122 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
123 au_sync(); 123 wmb(); /* drain writebuffer */
124 124
125 retry = AC97_RW_RETRIES; 125 retry = AC97_RW_RETRIES;
126 do { 126 do {
127 mutex_lock(&pscdata->lock); 127 mutex_lock(&pscdata->lock);
128 128
129 au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), 129 __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
130 AC97_CDC(pscdata)); 130 AC97_CDC(pscdata));
131 au_sync(); 131 wmb(); /* drain writebuffer */
132 132
133 tmo = 20; 133 tmo = 20;
134 do { 134 do {
135 udelay(21); 135 udelay(21);
136 if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) 136 if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
137 break; 137 break;
138 } while (--tmo); 138 } while (--tmo);
139 139
140 au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); 140 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
141 au_sync(); 141 wmb(); /* drain writebuffer */
142 142
143 mutex_unlock(&pscdata->lock); 143 mutex_unlock(&pscdata->lock);
144 } while (--retry && !tmo); 144 } while (--retry && !tmo);
@@ -149,11 +149,11 @@ static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
149{ 149{
150 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); 150 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
151 151
152 au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); 152 __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
153 au_sync(); 153 wmb(); /* drain writebuffer */
154 msleep(10); 154 msleep(10);
155 au_writel(0, AC97_RST(pscdata)); 155 __raw_writel(0, AC97_RST(pscdata));
156 au_sync(); 156 wmb(); /* drain writebuffer */
157} 157}
158 158
159static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) 159static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
@@ -162,25 +162,25 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
162 int i; 162 int i;
163 163
164 /* disable PSC during cold reset */ 164 /* disable PSC during cold reset */
165 au_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); 165 __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
166 au_sync(); 166 wmb(); /* drain writebuffer */
167 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata)); 167 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
168 au_sync(); 168 wmb(); /* drain writebuffer */
169 169
170 /* issue cold reset */ 170 /* issue cold reset */
171 au_writel(PSC_AC97RST_RST, AC97_RST(pscdata)); 171 __raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
172 au_sync(); 172 wmb(); /* drain writebuffer */
173 msleep(500); 173 msleep(500);
174 au_writel(0, AC97_RST(pscdata)); 174 __raw_writel(0, AC97_RST(pscdata));
175 au_sync(); 175 wmb(); /* drain writebuffer */
176 176
177 /* enable PSC */ 177 /* enable PSC */
178 au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); 178 __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
179 au_sync(); 179 wmb(); /* drain writebuffer */
180 180
181 /* wait for PSC to indicate it's ready */ 181 /* wait for PSC to indicate it's ready */
182 i = 1000; 182 i = 1000;
183 while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i)) 183 while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
184 msleep(1); 184 msleep(1);
185 185
186 if (i == 0) { 186 if (i == 0) {
@@ -189,12 +189,12 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
189 } 189 }
190 190
191 /* enable the ac97 function */ 191 /* enable the ac97 function */
192 au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); 192 __raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
193 au_sync(); 193 wmb(); /* drain writebuffer */
194 194
195 /* wait for AC97 core to become ready */ 195 /* wait for AC97 core to become ready */
196 i = 1000; 196 i = 1000;
197 while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i)) 197 while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
198 msleep(1); 198 msleep(1);
199 if (i == 0) 199 if (i == 0)
200 printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n"); 200 printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
@@ -218,8 +218,8 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
218 218
219 chans = params_channels(params); 219 chans = params_channels(params);
220 220
221 r = ro = au_readl(AC97_CFG(pscdata)); 221 r = ro = __raw_readl(AC97_CFG(pscdata));
222 stat = au_readl(AC97_STAT(pscdata)); 222 stat = __raw_readl(AC97_STAT(pscdata));
223 223
224 /* already active? */ 224 /* already active? */
225 if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) { 225 if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
@@ -252,28 +252,28 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
252 mutex_lock(&pscdata->lock); 252 mutex_lock(&pscdata->lock);
253 253
254 /* disable AC97 device controller first... */ 254 /* disable AC97 device controller first... */
255 au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); 255 __raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
256 au_sync(); 256 wmb(); /* drain writebuffer */
257 257
258 /* ...wait for it... */ 258 /* ...wait for it... */
259 t = 100; 259 t = 100;
260 while ((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t) 260 while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
261 msleep(1); 261 msleep(1);
262 262
263 if (!t) 263 if (!t)
264 printk(KERN_ERR "PSC-AC97: can't disable!\n"); 264 printk(KERN_ERR "PSC-AC97: can't disable!\n");
265 265
266 /* ...write config... */ 266 /* ...write config... */
267 au_writel(r, AC97_CFG(pscdata)); 267 __raw_writel(r, AC97_CFG(pscdata));
268 au_sync(); 268 wmb(); /* drain writebuffer */
269 269
270 /* ...enable the AC97 controller again... */ 270 /* ...enable the AC97 controller again... */
271 au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); 271 __raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
272 au_sync(); 272 wmb(); /* drain writebuffer */
273 273
274 /* ...and wait for ready bit */ 274 /* ...and wait for ready bit */
275 t = 100; 275 t = 100;
276 while ((!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t) 276 while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
277 msleep(1); 277 msleep(1);
278 278
279 if (!t) 279 if (!t)
@@ -300,21 +300,21 @@ static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
300 switch (cmd) { 300 switch (cmd) {
301 case SNDRV_PCM_TRIGGER_START: 301 case SNDRV_PCM_TRIGGER_START:
302 case SNDRV_PCM_TRIGGER_RESUME: 302 case SNDRV_PCM_TRIGGER_RESUME:
303 au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); 303 __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
304 au_sync(); 304 wmb(); /* drain writebuffer */
305 au_writel(AC97PCR_START(stype), AC97_PCR(pscdata)); 305 __raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
306 au_sync(); 306 wmb(); /* drain writebuffer */
307 break; 307 break;
308 case SNDRV_PCM_TRIGGER_STOP: 308 case SNDRV_PCM_TRIGGER_STOP:
309 case SNDRV_PCM_TRIGGER_SUSPEND: 309 case SNDRV_PCM_TRIGGER_SUSPEND:
310 au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata)); 310 __raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
311 au_sync(); 311 wmb(); /* drain writebuffer */
312 312
313 while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype)) 313 while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
314 asm volatile ("nop"); 314 asm volatile ("nop");
315 315
316 au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); 316 __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
317 au_sync(); 317 wmb(); /* drain writebuffer */
318 318
319 break; 319 break;
320 default: 320 default:
@@ -398,13 +398,13 @@ static int au1xpsc_ac97_drvprobe(struct platform_device *pdev)
398 PSC_AC97CFG_DE_ENABLE; 398 PSC_AC97CFG_DE_ENABLE;
399 399
400 /* preserve PSC clock source set up by platform */ 400 /* preserve PSC clock source set up by platform */
401 sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; 401 sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
402 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 402 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
403 au_sync(); 403 wmb(); /* drain writebuffer */
404 au_writel(0, PSC_SEL(wd)); 404 __raw_writel(0, PSC_SEL(wd));
405 au_sync(); 405 wmb(); /* drain writebuffer */
406 au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd)); 406 __raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
407 au_sync(); 407 wmb(); /* drain writebuffer */
408 408
409 /* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */ 409 /* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
410 memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template, 410 memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
@@ -433,10 +433,10 @@ static int au1xpsc_ac97_drvremove(struct platform_device *pdev)
433 snd_soc_unregister_component(&pdev->dev); 433 snd_soc_unregister_component(&pdev->dev);
434 434
435 /* disable PSC completely */ 435 /* disable PSC completely */
436 au_writel(0, AC97_CFG(wd)); 436 __raw_writel(0, AC97_CFG(wd));
437 au_sync(); 437 wmb(); /* drain writebuffer */
438 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 438 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
439 au_sync(); 439 wmb(); /* drain writebuffer */
440 440
441 au1xpsc_ac97_workdata = NULL; /* MDEV */ 441 au1xpsc_ac97_workdata = NULL; /* MDEV */
442 442
@@ -449,12 +449,12 @@ static int au1xpsc_ac97_drvsuspend(struct device *dev)
449 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); 449 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
450 450
451 /* save interesting registers and disable PSC */ 451 /* save interesting registers and disable PSC */
452 wd->pm[0] = au_readl(PSC_SEL(wd)); 452 wd->pm[0] = __raw_readl(PSC_SEL(wd));
453 453
454 au_writel(0, AC97_CFG(wd)); 454 __raw_writel(0, AC97_CFG(wd));
455 au_sync(); 455 wmb(); /* drain writebuffer */
456 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 456 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
457 au_sync(); 457 wmb(); /* drain writebuffer */
458 458
459 return 0; 459 return 0;
460} 460}
@@ -464,8 +464,8 @@ static int au1xpsc_ac97_drvresume(struct device *dev)
464 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); 464 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
465 465
466 /* restore PSC clock config */ 466 /* restore PSC clock config */
467 au_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd)); 467 __raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
468 au_sync(); 468 wmb(); /* drain writebuffer */
469 469
470 /* after this point the ac97 core will cold-reset the codec. 470 /* after this point the ac97 core will cold-reset the codec.
471 * During cold-reset the PSC is reinitialized and the last 471 * During cold-reset the PSC is reinitialized and the last
diff --git a/sound/soc/au1x/psc-i2s.c b/sound/soc/au1x/psc-i2s.c
index fe923a7bdc39..814beffc56f2 100644
--- a/sound/soc/au1x/psc-i2s.c
+++ b/sound/soc/au1x/psc-i2s.c
@@ -120,10 +120,10 @@ static int au1xpsc_i2s_hw_params(struct snd_pcm_substream *substream,
120 unsigned long stat; 120 unsigned long stat;
121 121
122 /* check if the PSC is already streaming data */ 122 /* check if the PSC is already streaming data */
123 stat = au_readl(I2S_STAT(pscdata)); 123 stat = __raw_readl(I2S_STAT(pscdata));
124 if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) { 124 if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) {
125 /* reject parameters not currently set up in hardware */ 125 /* reject parameters not currently set up in hardware */
126 cfgbits = au_readl(I2S_CFG(pscdata)); 126 cfgbits = __raw_readl(I2S_CFG(pscdata));
127 if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) || 127 if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) ||
128 (params_rate(params) != pscdata->rate)) 128 (params_rate(params) != pscdata->rate))
129 return -EINVAL; 129 return -EINVAL;
@@ -149,33 +149,33 @@ static int au1xpsc_i2s_configure(struct au1xpsc_audio_data *pscdata)
149 unsigned long tmo; 149 unsigned long tmo;
150 150
151 /* bring PSC out of sleep, and configure I2S unit */ 151 /* bring PSC out of sleep, and configure I2S unit */
152 au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); 152 __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
153 au_sync(); 153 wmb(); /* drain writebuffer */
154 154
155 tmo = 1000000; 155 tmo = 1000000;
156 while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo) 156 while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo)
157 tmo--; 157 tmo--;
158 158
159 if (!tmo) 159 if (!tmo)
160 goto psc_err; 160 goto psc_err;
161 161
162 au_writel(0, I2S_CFG(pscdata)); 162 __raw_writel(0, I2S_CFG(pscdata));
163 au_sync(); 163 wmb(); /* drain writebuffer */
164 au_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata)); 164 __raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata));
165 au_sync(); 165 wmb(); /* drain writebuffer */
166 166
167 /* wait for I2S controller to become ready */ 167 /* wait for I2S controller to become ready */
168 tmo = 1000000; 168 tmo = 1000000;
169 while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo) 169 while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo)
170 tmo--; 170 tmo--;
171 171
172 if (tmo) 172 if (tmo)
173 return 0; 173 return 0;
174 174
175psc_err: 175psc_err:
176 au_writel(0, I2S_CFG(pscdata)); 176 __raw_writel(0, I2S_CFG(pscdata));
177 au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); 177 __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
178 au_sync(); 178 wmb(); /* drain writebuffer */
179 return -ETIMEDOUT; 179 return -ETIMEDOUT;
180} 180}
181 181
@@ -187,26 +187,26 @@ static int au1xpsc_i2s_start(struct au1xpsc_audio_data *pscdata, int stype)
187 ret = 0; 187 ret = 0;
188 188
189 /* if both TX and RX are idle, configure the PSC */ 189 /* if both TX and RX are idle, configure the PSC */
190 stat = au_readl(I2S_STAT(pscdata)); 190 stat = __raw_readl(I2S_STAT(pscdata));
191 if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) { 191 if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
192 ret = au1xpsc_i2s_configure(pscdata); 192 ret = au1xpsc_i2s_configure(pscdata);
193 if (ret) 193 if (ret)
194 goto out; 194 goto out;
195 } 195 }
196 196
197 au_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata)); 197 __raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata));
198 au_sync(); 198 wmb(); /* drain writebuffer */
199 au_writel(I2SPCR_START(stype), I2S_PCR(pscdata)); 199 __raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata));
200 au_sync(); 200 wmb(); /* drain writebuffer */
201 201
202 /* wait for start confirmation */ 202 /* wait for start confirmation */
203 tmo = 1000000; 203 tmo = 1000000;
204 while (!(au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) 204 while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
205 tmo--; 205 tmo--;
206 206
207 if (!tmo) { 207 if (!tmo) {
208 au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); 208 __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
209 au_sync(); 209 wmb(); /* drain writebuffer */
210 ret = -ETIMEDOUT; 210 ret = -ETIMEDOUT;
211 } 211 }
212out: 212out:
@@ -217,21 +217,21 @@ static int au1xpsc_i2s_stop(struct au1xpsc_audio_data *pscdata, int stype)
217{ 217{
218 unsigned long tmo, stat; 218 unsigned long tmo, stat;
219 219
220 au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); 220 __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
221 au_sync(); 221 wmb(); /* drain writebuffer */
222 222
223 /* wait for stop confirmation */ 223 /* wait for stop confirmation */
224 tmo = 1000000; 224 tmo = 1000000;
225 while ((au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) 225 while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
226 tmo--; 226 tmo--;
227 227
228 /* if both TX and RX are idle, disable PSC */ 228 /* if both TX and RX are idle, disable PSC */
229 stat = au_readl(I2S_STAT(pscdata)); 229 stat = __raw_readl(I2S_STAT(pscdata));
230 if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) { 230 if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
231 au_writel(0, I2S_CFG(pscdata)); 231 __raw_writel(0, I2S_CFG(pscdata));
232 au_sync(); 232 wmb(); /* drain writebuffer */
233 au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); 233 __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
234 au_sync(); 234 wmb(); /* drain writebuffer */
235 } 235 }
236 return 0; 236 return 0;
237} 237}
@@ -332,12 +332,12 @@ static int au1xpsc_i2s_drvprobe(struct platform_device *pdev)
332 /* preserve PSC clock source set up by platform (dev.platform_data 332 /* preserve PSC clock source set up by platform (dev.platform_data
333 * is already occupied by soc layer) 333 * is already occupied by soc layer)
334 */ 334 */
335 sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; 335 sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
336 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 336 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
337 au_sync(); 337 wmb(); /* drain writebuffer */
338 au_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd)); 338 __raw_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd));
339 au_writel(0, I2S_CFG(wd)); 339 __raw_writel(0, I2S_CFG(wd));
340 au_sync(); 340 wmb(); /* drain writebuffer */
341 341
342 /* preconfigure: set max rx/tx fifo depths */ 342 /* preconfigure: set max rx/tx fifo depths */
343 wd->cfg |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8; 343 wd->cfg |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8;
@@ -364,10 +364,10 @@ static int au1xpsc_i2s_drvremove(struct platform_device *pdev)
364 364
365 snd_soc_unregister_component(&pdev->dev); 365 snd_soc_unregister_component(&pdev->dev);
366 366
367 au_writel(0, I2S_CFG(wd)); 367 __raw_writel(0, I2S_CFG(wd));
368 au_sync(); 368 wmb(); /* drain writebuffer */
369 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 369 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
370 au_sync(); 370 wmb(); /* drain writebuffer */
371 371
372 return 0; 372 return 0;
373} 373}
@@ -378,12 +378,12 @@ static int au1xpsc_i2s_drvsuspend(struct device *dev)
378 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); 378 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
379 379
380 /* save interesting register and disable PSC */ 380 /* save interesting register and disable PSC */
381 wd->pm[0] = au_readl(PSC_SEL(wd)); 381 wd->pm[0] = __raw_readl(PSC_SEL(wd));
382 382
383 au_writel(0, I2S_CFG(wd)); 383 __raw_writel(0, I2S_CFG(wd));
384 au_sync(); 384 wmb(); /* drain writebuffer */
385 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 385 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
386 au_sync(); 386 wmb(); /* drain writebuffer */
387 387
388 return 0; 388 return 0;
389} 389}
@@ -393,12 +393,12 @@ static int au1xpsc_i2s_drvresume(struct device *dev)
393 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); 393 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
394 394
395 /* select I2S mode and PSC clock */ 395 /* select I2S mode and PSC clock */
396 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 396 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
397 au_sync(); 397 wmb(); /* drain writebuffer */
398 au_writel(0, PSC_SEL(wd)); 398 __raw_writel(0, PSC_SEL(wd));
399 au_sync(); 399 wmb(); /* drain writebuffer */
400 au_writel(wd->pm[0], PSC_SEL(wd)); 400 __raw_writel(wd->pm[0], PSC_SEL(wd));
401 au_sync(); 401 wmb(); /* drain writebuffer */
402 402
403 return 0; 403 return 0;
404} 404}
diff --git a/sound/soc/au1x/psc.h b/sound/soc/au1x/psc.h
index b16b2e02e0c9..74dffeb641fa 100644
--- a/sound/soc/au1x/psc.h
+++ b/sound/soc/au1x/psc.h
@@ -27,16 +27,16 @@ struct au1xpsc_audio_data {
27}; 27};
28 28
29/* easy access macros */ 29/* easy access macros */
30#define PSC_CTRL(x) ((unsigned long)((x)->mmio) + PSC_CTRL_OFFSET) 30#define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
31#define PSC_SEL(x) ((unsigned long)((x)->mmio) + PSC_SEL_OFFSET) 31#define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
32#define I2S_STAT(x) ((unsigned long)((x)->mmio) + PSC_I2SSTAT_OFFSET) 32#define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
33#define I2S_CFG(x) ((unsigned long)((x)->mmio) + PSC_I2SCFG_OFFSET) 33#define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
34#define I2S_PCR(x) ((unsigned long)((x)->mmio) + PSC_I2SPCR_OFFSET) 34#define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
35#define AC97_CFG(x) ((unsigned long)((x)->mmio) + PSC_AC97CFG_OFFSET) 35#define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
36#define AC97_CDC(x) ((unsigned long)((x)->mmio) + PSC_AC97CDC_OFFSET) 36#define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
37#define AC97_EVNT(x) ((unsigned long)((x)->mmio) + PSC_AC97EVNT_OFFSET) 37#define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
38#define AC97_PCR(x) ((unsigned long)((x)->mmio) + PSC_AC97PCR_OFFSET) 38#define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
39#define AC97_RST(x) ((unsigned long)((x)->mmio) + PSC_AC97RST_OFFSET) 39#define AC97_RST(x) ((x)->mmio + PSC_AC97RST_OFFSET)
40#define AC97_STAT(x) ((unsigned long)((x)->mmio) + PSC_AC97STAT_OFFSET) 40#define AC97_STAT(x) ((x)->mmio + PSC_AC97STAT_OFFSET)
41 41
42#endif 42#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-31 08:17:00 -0400