25 files changed, 211 insertions, 66 deletions

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b419016a..8b4f7b7fe88b 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -9,6 +9,18 @@ Required Properties:
 - reg: physical base address of the controller and length of memory mapped
     region.
 
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+        devices in this power domain are set to oscclk before power gating
+        and restored back after powering on a domain. This is required for
+        all domains which are powered on and off and not required for unused
+        domains.
+- clock-names: The following clocks can be specified:
+        - oscclk: Oscillator clock.
+        - pclkN, clkN: Pairs of parent of input clock and input clock to the
+                devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
+                are supported currently.
+
 Node of a device using power domains must have a samsung,power-domain property
 defined with a phandle to respective power domain.
 
@@ -19,6 +31,14 @@ Example:
                 reg = <0x10023C00 0x10>;
         };
 
+        mfc_pd: power-domain@10044060 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044060 0x20>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+                        <&clock CLK_MOUT_USER_ACLK333>;
+                clock-names = "oscclk", "pclk0", "clk0";
+        };
+
 Example of the node using power domain:
 
         node {
diff --git a/MAINTAINERS b/MAINTAINERS
index c411c40d8854..e31c87474739 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1314,6 +1314,20 @@ W:	http://oss.renesas.com
 Q:      http://patchwork.kernel.org/project/linux-sh/list/
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
 S:      Supported
+F:      arch/arm/boot/dts/emev2*
+F:      arch/arm/boot/dts/r7s*
+F:      arch/arm/boot/dts/r8a*
+F:      arch/arm/boot/dts/sh*
+F:      arch/arm/configs/ape6evm_defconfig
+F:      arch/arm/configs/armadillo800eva_defconfig
+F:      arch/arm/configs/bockw_defconfig
+F:      arch/arm/configs/genmai_defconfig
+F:      arch/arm/configs/koelsch_defconfig
+F:      arch/arm/configs/kzm9g_defconfig
+F:      arch/arm/configs/lager_defconfig
+F:      arch/arm/configs/mackerel_defconfig
+F:      arch/arm/configs/marzen_defconfig
+F:      arch/arm/configs/shmobile_defconfig
 F:      arch/arm/mach-shmobile/
 F:      drivers/sh/
 
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index ecb267767cf5..e2156a583de7 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -529,8 +529,8 @@
                 serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
                         0 0 1 2
                 >;
-                tx-num-evt = <1>;
-                rx-num-evt = <1>;
+                tx-num-evt = <32>;
+                rx-num-evt = <32>;
 };
 
 &tps {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index ab9a34ce524c..80a3b215e7d6 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -560,8 +560,8 @@
                 serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
                         0 0 1 2
                 >;
-                tx-num-evt = <1>;
-                rx-num-evt = <1>;
+                tx-num-evt = <32>;
+                rx-num-evt = <32>;
 };
 
 &tscadc {
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index 8a0a72dc7dd7..a1a0cc5eb35c 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -105,10 +105,16 @@
 
 &cpsw_emac0 {
         phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "rmii";
 };
 
 &cpsw_emac1 {
         phy_id = <&davinci_mdio>, <1>;
+        phy-mode = "rmii";
+};
+
+&phy_sel {
+        rmii-clock-ext;
 };
 
 &elm {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index d6133f497207..2ebc42140ea6 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -1045,6 +1045,8 @@
                                 reg = <0x00500000 0x80000
                                        0xf803c000 0x400>;
                                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&usb>, <&udphs_clk>;
+                                clock-names = "hclk", "pclk";
                                 status = "disabled";
 
                                 ep0 {
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 4adc28039c30..83089540e324 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -240,6 +240,7 @@
                                         regulator-name = "ldo3";
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
                                         regulator-boot-on;
                                 };
 
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index c90c76de84d6..dc7a292fe939 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -673,10 +673,12 @@
 
         l3_iclk_div: l3_iclk_div {
                 #clock-cells = <0>;
-                compatible = "fixed-factor-clock";
+                compatible = "ti,divider-clock";
+                ti,max-div = <2>;
+                ti,bit-shift = <4>;
+                reg = <0x0100>;
                 clocks = <&dpll_core_h12x2_ck>;
-                clock-mult = <1>;
-                clock-div = <1>;
+                ti,index-power-of-two;
         };
 
         l4_root_clk_div: l4_root_clk_div {
@@ -684,7 +686,7 @@
                 compatible = "fixed-factor-clock";
                 clocks = <&l3_iclk_div>;
                 clock-mult = <1>;
-                clock-div = <1>;
+                clock-div = <2>;
         };
 
         video1_clk2_div: video1_clk2_div {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index fbaf426d2daa..17b22e9cc2aa 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -554,7 +554,7 @@
                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
                 clocks = <&clock CLK_PWM>;
                 clock-names = "timers";
-                #pwm-cells = <2>;
+                #pwm-cells = <3>;
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e38532271ef9..15957227ffda 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -167,7 +167,7 @@
                 compatible = "samsung,exynos5420-audss-clock";
                 reg = <0x03810000 0x0C>;
                 #clock-cells = <1>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
         };
@@ -260,6 +260,9 @@
         mfc_pd: power-domain@10044060 {
                 compatible = "samsung,exynos4210-pd";
                 reg = <0x10044060 0x20>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+                        <&clock CLK_MOUT_USER_ACLK333>;
+                clock-names = "oscclk", "pclk0", "clk0";
         };
 
         disp_pd: power-domain@100440C0 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index f38cf7c110cc..46d893fcbe85 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -173,10 +173,8 @@ static struct platform_device exynos_cpuidle = {
 
 void __init exynos_cpuidle_init(void)
 {
-        if (soc_is_exynos5440())
-                return;
-
-        platform_device_register(&exynos_cpuidle);
+        if (soc_is_exynos4210() || soc_is_exynos5250())
+                platform_device_register(&exynos_cpuidle);
 }
 
 void __init exynos_cpufreq_init(void)
@@ -297,7 +295,7 @@ static void __init exynos_dt_machine_init(void)
          * This is called from smp_prepare_cpus if we've built for SMP, but
          * we still need to set it up for PM and firmware ops if not.
          */
-        if (!IS_ENABLED(SMP))
+        if (!IS_ENABLED(CONFIG_SMP))
                 exynos_sysram_init();
 
         exynos_cpuidle_init();
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index eb91d2350f8c..e8797bb78871 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -57,8 +57,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 
         boot_reg = sysram_ns_base_addr + 0x1c;
 
-        if (!soc_is_exynos4212() && !soc_is_exynos3250())
-                boot_reg += 4*cpu;
+        /*
+         * Almost all Exynos-series of SoCs that run in secure mode don't need
+         * additional offset for every CPU, with Exynos4412 being the only
+         * exception.
+         */
+        if (soc_is_exynos4412())
+                boot_reg += 4 * cpu;
 
         __raw_writel(boot_addr, boot_reg);
         return 0;
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index fe6570ebbdde..797cb134bfff 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -17,6 +17,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/pm_domain.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
@@ -24,6 +25,8 @@
 
 #include "regs-pmu.h"
 
+#define MAX_CLK_PER_DOMAIN      4
+
 /*
  * Exynos specific wrapper around the generic power domain
  */
@@ -32,6 +35,9 @@ struct exynos_pm_domain {
         char const *name;
         bool is_off;
         struct generic_pm_domain pd;
+        struct clk *oscclk;
+        struct clk *clk[MAX_CLK_PER_DOMAIN];
+        struct clk *pclk[MAX_CLK_PER_DOMAIN];
 };
 
 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
@@ -44,6 +50,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
         pd = container_of(domain, struct exynos_pm_domain, pd);
         base = pd->base;
 
+        /* Set oscclk before powering off a domain*/
+        if (!power_on) {
+                int i;
+
+                for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                        if (IS_ERR(pd->clk[i]))
+                                break;
+                        if (clk_set_parent(pd->clk[i], pd->oscclk))
+                                pr_err("%s: error setting oscclk as parent to clock %d\n",
+                                                pd->name, i);
+                }
+        }
+
         pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
         __raw_writel(pwr, base);
 
@@ -60,6 +79,20 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
                 cpu_relax();
                 usleep_range(80, 100);
         }
+
+        /* Restore clocks after powering on a domain*/
+        if (power_on) {
+                int i;
+
+                for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                        if (IS_ERR(pd->clk[i]))
+                                break;
+                        if (clk_set_parent(pd->clk[i], pd->pclk[i]))
+                                pr_err("%s: error setting parent to clock%d\n",
+                                                pd->name, i);
+                }
+        }
+
         return 0;
 }
 
@@ -152,9 +185,11 @@ static __init int exynos4_pm_init_power_domain(void)
 
         for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
                 struct exynos_pm_domain *pd;
-                int on;
+                int on, i;
+                struct device *dev;
 
                 pdev = of_find_device_by_node(np);
+                dev = &pdev->dev;
 
                 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
                 if (!pd) {
@@ -170,6 +205,30 @@ static __init int exynos4_pm_init_power_domain(void)
                 pd->pd.power_on = exynos_pd_power_on;
                 pd->pd.of_node = np;
 
+                pd->oscclk = clk_get(dev, "oscclk");
+                if (IS_ERR(pd->oscclk))
+                        goto no_clk;
+
+                for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                        char clk_name[8];
+
+                        snprintf(clk_name, sizeof(clk_name), "clk%d", i);
+                        pd->clk[i] = clk_get(dev, clk_name);
+                        if (IS_ERR(pd->clk[i]))
+                                break;
+                        snprintf(clk_name, sizeof(clk_name), "pclk%d", i);
+                        pd->pclk[i] = clk_get(dev, clk_name);
+                        if (IS_ERR(pd->pclk[i])) {
+                                clk_put(pd->clk[i]);
+                                pd->clk[i] = ERR_PTR(-EINVAL);
+                                break;
+                        }
+                }
+
+                if (IS_ERR(pd->clk[0]))
+                        clk_put(pd->oscclk);
+
+no_clk:
                 platform_set_drvdata(pdev, pd);
 
                 on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index 4ba587da89d2..84acdfd1d715 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -67,8 +67,12 @@ static void clk_gate2_disable(struct clk_hw *hw)
 
         spin_lock_irqsave(gate->lock, flags);
 
-        if (gate->share_count && --(*gate->share_count) > 0)
-                goto out;
+        if (gate->share_count) {
+                if (WARN_ON(*gate->share_count == 0))
+                        goto out;
+                else if (--(*gate->share_count) > 0)
+                        goto out;
+        }
 
         reg = readl(gate->reg);
         reg &= ~(3 << gate->bit_idx);
@@ -78,19 +82,26 @@ out:
         spin_unlock_irqrestore(gate->lock, flags);
 }
 
-static int clk_gate2_is_enabled(struct clk_hw *hw)
+static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
 {
-        u32 reg;
-        struct clk_gate2 *gate = to_clk_gate2(hw);
+        u32 val = readl(reg);
 
-        reg = readl(gate->reg);
-
-        if (((reg >> gate->bit_idx) & 1) == 1)
+        if (((val >> bit_idx) & 1) == 1)
                 return 1;
 
         return 0;
 }
 
+static int clk_gate2_is_enabled(struct clk_hw *hw)
+{
+        struct clk_gate2 *gate = to_clk_gate2(hw);
+
+        if (gate->share_count)
+                return !!(*gate->share_count);
+        else
+                return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
+}
+
 static struct clk_ops clk_gate2_ops = {
         .enable = clk_gate2_enable,
         .disable = clk_gate2_disable,
@@ -116,6 +127,10 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
         gate->bit_idx = bit_idx;
         gate->flags = clk_gate2_flags;
         gate->lock = lock;
+
+        /* Initialize share_count per hardware state */
+        if (share_count)
+                *share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0;
         gate->share_count = share_count;
 
         init.name = name;
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 332af927f4d3..67fd26a18441 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -76,7 +76,7 @@
  * (assuming that it is counting N upwards), or -2 if the enclosing loop
  * should skip to the next iteration (again assuming N is increasing).
  */
-static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
+static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
 {
         struct dpll_data *dd;
         long fint, fint_min, fint_max;
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 04dab2fcf862..ee6c784cd6b7 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -26,11 +26,14 @@
 #define OMAP3430_EN_WDT3_SHIFT                          12
 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK            (1 << 0)
 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT           0
+#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT                4
 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK                 (0xf << 4)
 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT          3
+#define OMAP3430_EN_IVA2_DPLL_SHIFT                     0
 #define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
 #define OMAP3430_ST_IVA2_SHIFT                          0
 #define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
+#define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
 #define OMAP3430_AUTO_IVA2_DPLL_MASK                    (0x7 << 0)
 #define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
 #define OMAP3430_IVA2_CLK_SRC_WIDTH                     3
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index b2d252bf4a53..dc571f1d3b8a 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -162,7 +162,8 @@ static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 }
 #endif
 
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+        defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
 void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
 static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 592ba0a0ecf3..b6f8f348296e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -297,33 +297,6 @@ static void omap_init_audio(void)
 static inline void omap_init_audio(void) {}
 #endif
 
-#if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \
-                defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE)
-
-static struct platform_device omap_hdmi_audio = {
-        .name   = "omap-hdmi-audio",
-        .id     = -1,
-};
-
-static void __init omap_init_hdmi_audio(void)
-{
-        struct omap_hwmod *oh;
-        struct platform_device *pdev;
-
-        oh = omap_hwmod_lookup("dss_hdmi");
-        if (!oh)
-                return;
-
-        pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
-        WARN(IS_ERR(pdev),
-             "Can't build omap_device for omap-hdmi-audio-dai.\n");
-
-        platform_device_register(&omap_hdmi_audio);
-}
-#else
-static inline void omap_init_hdmi_audio(void) {}
-#endif
-
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
 #include <linux/platform_data/spi-omap2-mcspi.h>
@@ -459,7 +432,6 @@ static int __init omap2_init_devices(void)
          */
         omap_init_audio();
         omap_init_camera();
-        omap_init_hdmi_audio();
         omap_init_mbox();
         /* If dtb is there, the devices will be created dynamically */
         if (!of_have_populated_dt()) {
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index b8208b4b1bd9..f7492df1cbba 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -29,6 +29,7 @@
 #ifdef CONFIG_TIDSPBRIDGE_DVFS
 #include "omap-pm.h"
 #endif
+#include "soc.h"
 
 #include <linux/platform_data/dsp-omap.h>
 
@@ -59,6 +60,9 @@ void __init omap_dsp_reserve_sdram_memblock(void)
         phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
         phys_addr_t paddr;
 
+        if (!cpu_is_omap34xx())
+                return;
+
         if (!size)
                 return;
 
@@ -83,6 +87,9 @@ static int __init omap_dsp_init(void)
         int err = -ENOMEM;
         struct omap_dsp_platform_data *pdata = &omap_dsp_pdata;
 
+        if (!cpu_is_omap34xx())
+                return 0;
+
         pdata->phys_mempool_base = omap_dsp_get_mempool_base();
 
         if (pdata->phys_mempool_base) {
@@ -115,6 +122,9 @@ module_init(omap_dsp_init);
 
 static void __exit omap_dsp_exit(void)
 {
+        if (!cpu_is_omap34xx())
+                return;
+
         platform_device_unregister(omap_dsp_pdev);
 }
 module_exit(omap_dsp_exit);
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 2c0c2816900f..8bc13380f0a0 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1615,7 +1615,7 @@ static int gpmc_probe_dt(struct platform_device *pdev)
                 return ret;
         }
 
-        for_each_child_of_node(pdev->dev.of_node, child) {
+        for_each_available_child_of_node(pdev->dev.of_node, child) {
 
                 if (!child->name)
                         continue;
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 20b4398cec05..284324f2b98a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1268,9 +1268,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
 };
 
 /* sata */
-static struct omap_hwmod_opt_clk sata_opt_clks[] = {
-        { .role = "ref_clk", .clk = "sata_ref_clk" },
-};
 
 static struct omap_hwmod dra7xx_sata_hwmod = {
         .name           = "sata",
@@ -1278,6 +1275,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
         .clkdm_name     = "l3init_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
         .main_clk       = "func_48m_fclk",
+        .mpu_rt_idx     = 1,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@@ -1285,8 +1283,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .opt_clks       = sata_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
 };
 
 /*
@@ -1731,8 +1727,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
  *
  */
 
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
         .name   = "usb_otg_ss",
+        .sysc   = &dra7xx_usb_otg_ss_sysc,
 };
 
 /* usb_otg_ss1 */
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 106132db532b..cbefbd7cfdb5 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -35,6 +35,8 @@
 #define OMAP3430_LOGICSTATEST_MASK                      (1 << 2)
 #define OMAP3430_LASTLOGICSTATEENTERED_MASK             (1 << 2)
 #define OMAP3430_LASTPOWERSTATEENTERED_MASK             (0x3 << 0)
+#define OMAP3430_GRPSEL_MCBSP5_MASK                     (1 << 10)
+#define OMAP3430_GRPSEL_MCBSP1_MASK                     (1 << 9)
 #define OMAP3630_GRPSEL_UART4_MASK                      (1 << 18)
 #define OMAP3430_GRPSEL_GPIO6_MASK                      (1 << 17)
 #define OMAP3430_GRPSEL_GPIO5_MASK                      (1 << 16)
@@ -42,6 +44,10 @@
 #define OMAP3430_GRPSEL_GPIO3_MASK                      (1 << 14)
 #define OMAP3430_GRPSEL_GPIO2_MASK                      (1 << 13)
 #define OMAP3430_GRPSEL_UART3_MASK                      (1 << 11)
+#define OMAP3430_GRPSEL_GPT8_MASK                       (1 << 9)
+#define OMAP3430_GRPSEL_GPT7_MASK                       (1 << 8)
+#define OMAP3430_GRPSEL_GPT6_MASK                       (1 << 7)
+#define OMAP3430_GRPSEL_GPT5_MASK                       (1 << 6)
 #define OMAP3430_GRPSEL_MCBSP4_MASK                     (1 << 2)
 #define OMAP3430_GRPSEL_MCBSP3_MASK                     (1 << 1)
 #define OMAP3430_GRPSEL_MCBSP2_MASK                     (1 << 0)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7eed03fd..f74f882f7f29 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -631,7 +631,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP4, 16, 1),
         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
-        MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
+        MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
+                        SRC_TOP4, 28, 1),
 
         MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
                         SRC_TOP5, 0, 1),
@@ -684,7 +685,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP11, 12, 1),
         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
-        MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+        MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
+                        SRC_TOP11, 28, 1),
 
         MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
                         SRC_TOP12, 4, 1),
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index f71d55f5e6e5..ab51bf20a3ed 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -162,7 +162,7 @@ static void exynos4_mct_frc_start(void)
         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 }
 
-static cycle_t exynos4_frc_read(struct clocksource *cs)
+static cycle_t notrace _exynos4_frc_read(void)
 {
         unsigned int lo, hi;
         u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
@@ -176,6 +176,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
         return ((cycle_t)hi << 32) | lo;
 }
 
+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+        return _exynos4_frc_read();
+}
+
 static void exynos4_frc_resume(struct clocksource *cs)
 {
         exynos4_mct_frc_start();
@@ -192,13 +197,24 @@ struct clocksource mct_frc = {
 
 static u64 notrace exynos4_read_sched_clock(void)
 {
-        return exynos4_frc_read(&mct_frc);
+        return _exynos4_frc_read();
+}
+
+static struct delay_timer exynos4_delay_timer;
+
+static cycles_t exynos4_read_current_timer(void)
+{
+        return _exynos4_frc_read();
 }
 
 static void __init exynos4_clocksource_init(void)
 {
         exynos4_mct_frc_start();
 
+        exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
+        exynos4_delay_timer.freq = clk_rate;
+        register_current_timer_delay(&exynos4_delay_timer);
+
         if (clocksource_register_hz(&mct_frc, clk_rate))
                 panic("%s: can't register clocksource\n", mct_frc.name);
 
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 97dcb89d37d3..3fc08ff24fa9 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -203,6 +203,8 @@
 #define CLK_MOUT_G3D            641
 #define CLK_MOUT_VPLL           642
 #define CLK_MOUT_MAUDIO0        643
+#define CLK_MOUT_USER_ACLK333   644
+#define CLK_MOUT_SW_ACLK333     645
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL          768