aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index d455bcb655c2..850506061a80 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -974,8 +974,8 @@ static struct radeon_asic r600_asic = {
974 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 974 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
975 .dma = &r600_copy_dma, 975 .dma = &r600_copy_dma,
976 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 976 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
977 .copy = &r600_copy_blit, 977 .copy = &r600_copy_dma,
978 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 978 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
979 }, 979 },
980 .surface = { 980 .surface = {
981 .set_reg = r600_set_surface_reg, 981 .set_reg = r600_set_surface_reg,
@@ -1058,8 +1058,8 @@ static struct radeon_asic rs780_asic = {
1058 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1058 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1059 .dma = &r600_copy_dma, 1059 .dma = &r600_copy_dma,
1060 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1060 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1061 .copy = &r600_copy_blit, 1061 .copy = &r600_copy_dma,
1062 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1062 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1063 }, 1063 },
1064 .surface = { 1064 .surface = {
1065 .set_reg = r600_set_surface_reg, 1065 .set_reg = r600_set_surface_reg,
@@ -1142,8 +1142,8 @@ static struct radeon_asic rv770_asic = {
1142 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1142 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1143 .dma = &r600_copy_dma, 1143 .dma = &r600_copy_dma,
1144 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1144 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1145 .copy = &r600_copy_blit, 1145 .copy = &r600_copy_dma,
1146 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1146 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1147 }, 1147 },
1148 .surface = { 1148 .surface = {
1149 .set_reg = r600_set_surface_reg, 1149 .set_reg = r600_set_surface_reg,
@@ -1226,8 +1226,8 @@ static struct radeon_asic evergreen_asic = {
1226 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1226 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1227 .dma = &evergreen_copy_dma, 1227 .dma = &evergreen_copy_dma,
1228 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1228 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1229 .copy = &r600_copy_blit, 1229 .copy = &evergreen_copy_dma,
1230 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1230 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1231 }, 1231 },
1232 .surface = { 1232 .surface = {
1233 .set_reg = r600_set_surface_reg, 1233 .set_reg = r600_set_surface_reg,
@@ -1310,8 +1310,8 @@ static struct radeon_asic sumo_asic = {
1310 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1310 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1311 .dma = &evergreen_copy_dma, 1311 .dma = &evergreen_copy_dma,
1312 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1312 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1313 .copy = &r600_copy_blit, 1313 .copy = &evergreen_copy_dma,
1314 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1314 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1315 }, 1315 },
1316 .surface = { 1316 .surface = {
1317 .set_reg = r600_set_surface_reg, 1317 .set_reg = r600_set_surface_reg,
@@ -1394,8 +1394,8 @@ static struct radeon_asic btc_asic = {
1394 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1394 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1395 .dma = &evergreen_copy_dma, 1395 .dma = &evergreen_copy_dma,
1396 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1396 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1397 .copy = &r600_copy_blit, 1397 .copy = &evergreen_copy_dma,
1398 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1398 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1399 }, 1399 },
1400 .surface = { 1400 .surface = {
1401 .set_reg = r600_set_surface_reg, 1401 .set_reg = r600_set_surface_reg,
@@ -1519,8 +1519,8 @@ static struct radeon_asic cayman_asic = {
1519 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1519 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1520 .dma = &evergreen_copy_dma, 1520 .dma = &evergreen_copy_dma,
1521 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1521 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1522 .copy = &r600_copy_blit, 1522 .copy = &evergreen_copy_dma,
1523 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1523 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1524 }, 1524 },
1525 .surface = { 1525 .surface = {
1526 .set_reg = r600_set_surface_reg, 1526 .set_reg = r600_set_surface_reg,
@@ -1644,8 +1644,8 @@ static struct radeon_asic trinity_asic = {
1644 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1644 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1645 .dma = &evergreen_copy_dma, 1645 .dma = &evergreen_copy_dma,
1646 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1646 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1647 .copy = &r600_copy_blit, 1647 .copy = &evergreen_copy_dma,
1648 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1648 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1649 }, 1649 },
1650 .surface = { 1650 .surface = {
1651 .set_reg = r600_set_surface_reg, 1651 .set_reg = r600_set_surface_reg,
@@ -1769,8 +1769,8 @@ static struct radeon_asic si_asic = {
1769 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1769 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1770 .dma = &si_copy_dma, 1770 .dma = &si_copy_dma,
1771 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1771 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1772 .copy = NULL, 1772 .copy = &si_copy_dma,
1773 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1773 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1774 }, 1774 },
1775 .surface = { 1775 .surface = {
1776 .set_reg = r600_set_surface_reg, 1776 .set_reg = r600_set_surface_reg,
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 18:25:22 -0500