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-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi146
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi122
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi122
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi161
4 files changed, 534 insertions, 17 deletions
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 0bf70ee041ed..3ba2b4675f03 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -70,6 +70,29 @@
70 clocks = <&osc24M>; 70 clocks = <&osc24M>;
71 }; 71 };
72 72
73 pll4: pll4@01c20018 {
74 #clock-cells = <0>;
75 compatible = "allwinner,sun4i-pll1-clk";
76 reg = <0x01c20018 0x4>;
77 clocks = <&osc24M>;
78 };
79
80 pll5: pll5@01c20020 {
81 #clock-cells = <1>;
82 compatible = "allwinner,sun4i-pll5-clk";
83 reg = <0x01c20020 0x4>;
84 clocks = <&osc24M>;
85 clock-output-names = "pll5_ddr", "pll5_other";
86 };
87
88 pll6: pll6@01c20028 {
89 #clock-cells = <1>;
90 compatible = "allwinner,sun4i-pll6-clk";
91 reg = <0x01c20028 0x4>;
92 clocks = <&osc24M>;
93 clock-output-names = "pll6_sata", "pll6_other", "pll6";
94 };
95
73 /* dummy is 200M */ 96 /* dummy is 200M */
74 cpu: cpu@01c20054 { 97 cpu: cpu@01c20054 {
75 #clock-cells = <0>; 98 #clock-cells = <0>;
@@ -135,12 +158,11 @@
135 "apb0_ir1", "apb0_keypad"; 158 "apb0_ir1", "apb0_keypad";
136 }; 159 };
137 160
138 /* dummy is pll62 */
139 apb1_mux: apb1_mux@01c20058 { 161 apb1_mux: apb1_mux@01c20058 {
140 #clock-cells = <0>; 162 #clock-cells = <0>;
141 compatible = "allwinner,sun4i-apb1-mux-clk"; 163 compatible = "allwinner,sun4i-apb1-mux-clk";
142 reg = <0x01c20058 0x4>; 164 reg = <0x01c20058 0x4>;
143 clocks = <&osc24M>, <&dummy>, <&osc32k>; 165 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
144 }; 166 };
145 167
146 apb1: apb1@01c20058 { 168 apb1: apb1@01c20058 {
@@ -162,6 +184,126 @@
162 "apb1_uart4", "apb1_uart5", "apb1_uart6", 184 "apb1_uart4", "apb1_uart5", "apb1_uart6",
163 "apb1_uart7"; 185 "apb1_uart7";
164 }; 186 };
187
188 nand_clk: clk@01c20080 {
189 #clock-cells = <0>;
190 compatible = "allwinner,sun4i-mod0-clk";
191 reg = <0x01c20080 0x4>;
192 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
193 clock-output-names = "nand";
194 };
195
196 ms_clk: clk@01c20084 {
197 #clock-cells = <0>;
198 compatible = "allwinner,sun4i-mod0-clk";
199 reg = <0x01c20084 0x4>;
200 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
201 clock-output-names = "ms";
202 };
203
204 mmc0_clk: clk@01c20088 {
205 #clock-cells = <0>;
206 compatible = "allwinner,sun4i-mod0-clk";
207 reg = <0x01c20088 0x4>;
208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
209 clock-output-names = "mmc0";
210 };
211
212 mmc1_clk: clk@01c2008c {
213 #clock-cells = <0>;
214 compatible = "allwinner,sun4i-mod0-clk";
215 reg = <0x01c2008c 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "mmc1";
218 };
219
220 mmc2_clk: clk@01c20090 {
221 #clock-cells = <0>;
222 compatible = "allwinner,sun4i-mod0-clk";
223 reg = <0x01c20090 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "mmc2";
226 };
227
228 mmc3_clk: clk@01c20094 {
229 #clock-cells = <0>;
230 compatible = "allwinner,sun4i-mod0-clk";
231 reg = <0x01c20094 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc3";
234 };
235
236 ts_clk: clk@01c20098 {
237 #clock-cells = <0>;
238 compatible = "allwinner,sun4i-mod0-clk";
239 reg = <0x01c20098 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "ts";
242 };
243
244 ss_clk: clk@01c2009c {
245 #clock-cells = <0>;
246 compatible = "allwinner,sun4i-mod0-clk";
247 reg = <0x01c2009c 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "ss";
250 };
251
252 spi0_clk: clk@01c200a0 {
253 #clock-cells = <0>;
254 compatible = "allwinner,sun4i-mod0-clk";
255 reg = <0x01c200a0 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "spi0";
258 };
259
260 spi1_clk: clk@01c200a4 {
261 #clock-cells = <0>;
262 compatible = "allwinner,sun4i-mod0-clk";
263 reg = <0x01c200a4 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "spi1";
266 };
267
268 spi2_clk: clk@01c200a8 {
269 #clock-cells = <0>;
270 compatible = "allwinner,sun4i-mod0-clk";
271 reg = <0x01c200a8 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "spi2";
274 };
275
276 pata_clk: clk@01c200ac {
277 #clock-cells = <0>;
278 compatible = "allwinner,sun4i-mod0-clk";
279 reg = <0x01c200ac 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "pata";
282 };
283
284 ir0_clk: clk@01c200b0 {
285 #clock-cells = <0>;
286 compatible = "allwinner,sun4i-mod0-clk";
287 reg = <0x01c200b0 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "ir0";
290 };
291
292 ir1_clk: clk@01c200b4 {
293 #clock-cells = <0>;
294 compatible = "allwinner,sun4i-mod0-clk";
295 reg = <0x01c200b4 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "ir1";
298 };
299
300 spi3_clk: clk@01c200d4 {
301 #clock-cells = <0>;
302 compatible = "allwinner,sun4i-mod0-clk";
303 reg = <0x01c200d4 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "spi3";
306 };
165 }; 307 };
166 308
167 soc@01c00000 { 309 soc@01c00000 {
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index b4764be10a60..50f34fdecdae 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -67,6 +67,29 @@
67 clocks = <&osc24M>; 67 clocks = <&osc24M>;
68 }; 68 };
69 69
70 pll4: pll4@01c20018 {
71 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk";
73 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>;
75 };
76
77 pll5: pll5@01c20020 {
78 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk";
80 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other";
83 };
84
85 pll6: pll6@01c20028 {
86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk";
88 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6";
91 };
92
70 /* dummy is 200M */ 93 /* dummy is 200M */
71 cpu: cpu@01c20054 { 94 cpu: cpu@01c20054 {
72 #clock-cells = <0>; 95 #clock-cells = <0>;
@@ -127,12 +150,11 @@
127 "apb0_ir", "apb0_keypad"; 150 "apb0_ir", "apb0_keypad";
128 }; 151 };
129 152
130 /* dummy is pll62 */
131 apb1_mux: apb1_mux@01c20058 { 153 apb1_mux: apb1_mux@01c20058 {
132 #clock-cells = <0>; 154 #clock-cells = <0>;
133 compatible = "allwinner,sun4i-apb1-mux-clk"; 155 compatible = "allwinner,sun4i-apb1-mux-clk";
134 reg = <0x01c20058 0x4>; 156 reg = <0x01c20058 0x4>;
135 clocks = <&osc24M>, <&dummy>, <&osc32k>; 157 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
136 }; 158 };
137 159
138 apb1: apb1@01c20058 { 160 apb1: apb1@01c20058 {
@@ -151,6 +173,102 @@
151 "apb1_i2c2", "apb1_uart0", "apb1_uart1", 173 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
152 "apb1_uart2", "apb1_uart3"; 174 "apb1_uart2", "apb1_uart3";
153 }; 175 };
176
177 nand_clk: clk@01c20080 {
178 #clock-cells = <0>;
179 compatible = "allwinner,sun4i-mod0-clk";
180 reg = <0x01c20080 0x4>;
181 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
182 clock-output-names = "nand";
183 };
184
185 ms_clk: clk@01c20084 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-mod0-clk";
188 reg = <0x01c20084 0x4>;
189 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
190 clock-output-names = "ms";
191 };
192
193 mmc0_clk: clk@01c20088 {
194 #clock-cells = <0>;
195 compatible = "allwinner,sun4i-mod0-clk";
196 reg = <0x01c20088 0x4>;
197 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
198 clock-output-names = "mmc0";
199 };
200
201 mmc1_clk: clk@01c2008c {
202 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-mod0-clk";
204 reg = <0x01c2008c 0x4>;
205 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
206 clock-output-names = "mmc1";
207 };
208
209 mmc2_clk: clk@01c20090 {
210 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-mod0-clk";
212 reg = <0x01c20090 0x4>;
213 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
214 clock-output-names = "mmc2";
215 };
216
217 ts_clk: clk@01c20098 {
218 #clock-cells = <0>;
219 compatible = "allwinner,sun4i-mod0-clk";
220 reg = <0x01c20098 0x4>;
221 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
222 clock-output-names = "ts";
223 };
224
225 ss_clk: clk@01c2009c {
226 #clock-cells = <0>;
227 compatible = "allwinner,sun4i-mod0-clk";
228 reg = <0x01c2009c 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
230 clock-output-names = "ss";
231 };
232
233 spi0_clk: clk@01c200a0 {
234 #clock-cells = <0>;
235 compatible = "allwinner,sun4i-mod0-clk";
236 reg = <0x01c200a0 0x4>;
237 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
238 clock-output-names = "spi0";
239 };
240
241 spi1_clk: clk@01c200a4 {
242 #clock-cells = <0>;
243 compatible = "allwinner,sun4i-mod0-clk";
244 reg = <0x01c200a4 0x4>;
245 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
246 clock-output-names = "spi1";
247 };
248
249 spi2_clk: clk@01c200a8 {
250 #clock-cells = <0>;
251 compatible = "allwinner,sun4i-mod0-clk";
252 reg = <0x01c200a8 0x4>;
253 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
254 clock-output-names = "spi2";
255 };
256
257 ir0_clk: clk@01c200b0 {
258 #clock-cells = <0>;
259 compatible = "allwinner,sun4i-mod0-clk";
260 reg = <0x01c200b0 0x4>;
261 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
262 clock-output-names = "ir0";
263 };
264
265 mbus_clk: clk@01c2015c {
266 #clock-cells = <0>;
267 compatible = "allwinner,sun4i-mod0-clk";
268 reg = <0x01c2015c 0x4>;
269 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
270 clock-output-names = "mbus";
271 };
154 }; 272 };
155 273
156 soc@01c00000 { 274 soc@01c00000 {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index ce8ef2a45be0..227be94f0b9b 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -67,6 +67,29 @@
67 clocks = <&osc24M>; 67 clocks = <&osc24M>;
68 }; 68 };
69 69
70 pll4: pll4@01c20018 {
71 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk";
73 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>;
75 };
76
77 pll5: pll5@01c20020 {
78 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk";
80 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other";
83 };
84
85 pll6: pll6@01c20028 {
86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk";
88 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6";
91 };
92
70 /* dummy is 200M */ 93 /* dummy is 200M */
71 cpu: cpu@01c20054 { 94 cpu: cpu@01c20054 {
72 #clock-cells = <0>; 95 #clock-cells = <0>;
@@ -125,12 +148,11 @@
125 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; 148 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
126 }; 149 };
127 150
128 /* dummy is pll6 */
129 apb1_mux: apb1_mux@01c20058 { 151 apb1_mux: apb1_mux@01c20058 {
130 #clock-cells = <0>; 152 #clock-cells = <0>;
131 compatible = "allwinner,sun4i-apb1-mux-clk"; 153 compatible = "allwinner,sun4i-apb1-mux-clk";
132 reg = <0x01c20058 0x4>; 154 reg = <0x01c20058 0x4>;
133 clocks = <&osc24M>, <&dummy>, <&osc32k>; 155 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
134 }; 156 };
135 157
136 apb1: apb1@01c20058 { 158 apb1: apb1@01c20058 {
@@ -148,6 +170,102 @@
148 clock-output-names = "apb1_i2c0", "apb1_i2c1", 170 clock-output-names = "apb1_i2c0", "apb1_i2c1",
149 "apb1_i2c2", "apb1_uart1", "apb1_uart3"; 171 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
150 }; 172 };
173
174 nand_clk: clk@01c20080 {
175 #clock-cells = <0>;
176 compatible = "allwinner,sun4i-mod0-clk";
177 reg = <0x01c20080 0x4>;
178 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
179 clock-output-names = "nand";
180 };
181
182 ms_clk: clk@01c20084 {
183 #clock-cells = <0>;
184 compatible = "allwinner,sun4i-mod0-clk";
185 reg = <0x01c20084 0x4>;
186 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
187 clock-output-names = "ms";
188 };
189
190 mmc0_clk: clk@01c20088 {
191 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-mod0-clk";
193 reg = <0x01c20088 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "mmc0";
196 };
197
198 mmc1_clk: clk@01c2008c {
199 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-mod0-clk";
201 reg = <0x01c2008c 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "mmc1";
204 };
205
206 mmc2_clk: clk@01c20090 {
207 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk";
209 reg = <0x01c20090 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc2";
212 };
213
214 ts_clk: clk@01c20098 {
215 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk";
217 reg = <0x01c20098 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ts";
220 };
221
222 ss_clk: clk@01c2009c {
223 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk";
225 reg = <0x01c2009c 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "ss";
228 };
229
230 spi0_clk: clk@01c200a0 {
231 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk";
233 reg = <0x01c200a0 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "spi0";
236 };
237
238 spi1_clk: clk@01c200a4 {
239 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk";
241 reg = <0x01c200a4 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "spi1";
244 };
245
246 spi2_clk: clk@01c200a8 {
247 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk";
249 reg = <0x01c200a8 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "spi2";
252 };
253
254 ir0_clk: clk@01c200b0 {
255 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk";
257 reg = <0x01c200b0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ir0";
260 };
261
262 mbus_clk: clk@01c2015c {
263 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk";
265 reg = <0x01c2015c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "mbus";
268 };
151 }; 269 };
152 270
153 soc@01c00000 { 271 soc@01c00000 {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 74bf906ef786..534f1f07bdaf 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -66,23 +66,34 @@
66 clocks = <&osc24M>; 66 clocks = <&osc24M>;
67 }; 67 };
68 68
69 /* 69 pll4: pll4@01c20018 {
70 * This is a dummy clock, to be used as placeholder on
71 * other mux clocks when a specific parent clock is not
72 * yet implemented. It should be dropped when the driver
73 * is complete.
74 */
75 pll6: pll6 {
76 #clock-cells = <0>; 70 #clock-cells = <0>;
77 compatible = "fixed-clock"; 71 compatible = "allwinner,sun4i-pll1-clk";
78 clock-frequency = <0>; 72 reg = <0x01c20018 0x4>;
73 clocks = <&osc24M>;
74 };
75
76 pll5: pll5@01c20020 {
77 #clock-cells = <1>;
78 compatible = "allwinner,sun4i-pll5-clk";
79 reg = <0x01c20020 0x4>;
80 clocks = <&osc24M>;
81 clock-output-names = "pll5_ddr", "pll5_other";
82 };
83
84 pll6: pll6@01c20028 {
85 #clock-cells = <1>;
86 compatible = "allwinner,sun4i-pll6-clk";
87 reg = <0x01c20028 0x4>;
88 clocks = <&osc24M>;
89 clock-output-names = "pll6_sata", "pll6_other", "pll6";
79 }; 90 };
80 91
81 cpu: cpu@01c20054 { 92 cpu: cpu@01c20054 {
82 #clock-cells = <0>; 93 #clock-cells = <0>;
83 compatible = "allwinner,sun4i-cpu-clk"; 94 compatible = "allwinner,sun4i-cpu-clk";
84 reg = <0x01c20054 0x4>; 95 reg = <0x01c20054 0x4>;
85 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>; 96 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
86 }; 97 };
87 98
88 axi: axi@01c20054 { 99 axi: axi@01c20054 {
@@ -141,7 +152,7 @@
141 #clock-cells = <0>; 152 #clock-cells = <0>;
142 compatible = "allwinner,sun4i-apb1-mux-clk"; 153 compatible = "allwinner,sun4i-apb1-mux-clk";
143 reg = <0x01c20058 0x4>; 154 reg = <0x01c20058 0x4>;
144 clocks = <&osc24M>, <&pll6>, <&osc32k>; 155 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
145 }; 156 };
146 157
147 apb1: apb1@01c20058 { 158 apb1: apb1@01c20058 {
@@ -163,6 +174,134 @@
163 "apb1_uart2", "apb1_uart3", "apb1_uart4", 174 "apb1_uart2", "apb1_uart3", "apb1_uart4",
164 "apb1_uart5", "apb1_uart6", "apb1_uart7"; 175 "apb1_uart5", "apb1_uart6", "apb1_uart7";
165 }; 176 };
177
178 nand_clk: clk@01c20080 {
179 #clock-cells = <0>;
180 compatible = "allwinner,sun4i-mod0-clk";
181 reg = <0x01c20080 0x4>;
182 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
183 clock-output-names = "nand";
184 };
185
186 ms_clk: clk@01c20084 {
187 #clock-cells = <0>;
188 compatible = "allwinner,sun4i-mod0-clk";
189 reg = <0x01c20084 0x4>;
190 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
191 clock-output-names = "ms";
192 };
193
194 mmc0_clk: clk@01c20088 {
195 #clock-cells = <0>;
196 compatible = "allwinner,sun4i-mod0-clk";
197 reg = <0x01c20088 0x4>;
198 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
199 clock-output-names = "mmc0";
200 };
201
202 mmc1_clk: clk@01c2008c {
203 #clock-cells = <0>;
204 compatible = "allwinner,sun4i-mod0-clk";
205 reg = <0x01c2008c 0x4>;
206 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
207 clock-output-names = "mmc1";
208 };
209
210 mmc2_clk: clk@01c20090 {
211 #clock-cells = <0>;
212 compatible = "allwinner,sun4i-mod0-clk";
213 reg = <0x01c20090 0x4>;
214 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
215 clock-output-names = "mmc2";
216 };
217
218 mmc3_clk: clk@01c20094 {
219 #clock-cells = <0>;
220 compatible = "allwinner,sun4i-mod0-clk";
221 reg = <0x01c20094 0x4>;
222 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
223 clock-output-names = "mmc3";
224 };
225
226 ts_clk: clk@01c20098 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun4i-mod0-clk";
229 reg = <0x01c20098 0x4>;
230 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
231 clock-output-names = "ts";
232 };
233
234 ss_clk: clk@01c2009c {
235 #clock-cells = <0>;
236 compatible = "allwinner,sun4i-mod0-clk";
237 reg = <0x01c2009c 0x4>;
238 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
239 clock-output-names = "ss";
240 };
241
242 spi0_clk: clk@01c200a0 {
243 #clock-cells = <0>;
244 compatible = "allwinner,sun4i-mod0-clk";
245 reg = <0x01c200a0 0x4>;
246 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
247 clock-output-names = "spi0";
248 };
249
250 spi1_clk: clk@01c200a4 {
251 #clock-cells = <0>;
252 compatible = "allwinner,sun4i-mod0-clk";
253 reg = <0x01c200a4 0x4>;
254 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
255 clock-output-names = "spi1";
256 };
257
258 spi2_clk: clk@01c200a8 {
259 #clock-cells = <0>;
260 compatible = "allwinner,sun4i-mod0-clk";
261 reg = <0x01c200a8 0x4>;
262 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
263 clock-output-names = "spi2";
264 };
265
266 pata_clk: clk@01c200ac {
267 #clock-cells = <0>;
268 compatible = "allwinner,sun4i-mod0-clk";
269 reg = <0x01c200ac 0x4>;
270 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
271 clock-output-names = "pata";
272 };
273
274 ir0_clk: clk@01c200b0 {
275 #clock-cells = <0>;
276 compatible = "allwinner,sun4i-mod0-clk";
277 reg = <0x01c200b0 0x4>;
278 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
279 clock-output-names = "ir0";
280 };
281
282 ir1_clk: clk@01c200b4 {
283 #clock-cells = <0>;
284 compatible = "allwinner,sun4i-mod0-clk";
285 reg = <0x01c200b4 0x4>;
286 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
287 clock-output-names = "ir1";
288 };
289
290 spi3_clk: clk@01c200d4 {
291 #clock-cells = <0>;
292 compatible = "allwinner,sun4i-mod0-clk";
293 reg = <0x01c200d4 0x4>;
294 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
295 clock-output-names = "spi3";
296 };
297
298 mbus_clk: clk@01c2015c {
299 #clock-cells = <0>;
300 compatible = "allwinner,sun4i-mod0-clk";
301 reg = <0x01c2015c 0x4>;
302 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
303 clock-output-names = "mbus";
304 };
166 }; 305 };
167 306
168 soc@01c00000 { 307 soc@01c00000 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 09:15:54 -0500