diff options
| -rw-r--r-- | arch/arm/mach-omap2/gpmc.c | 30 |
1 files changed, 23 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 00d510858e28..212018d4e320 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
| @@ -50,6 +50,19 @@ | |||
| 50 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | 50 | #define GPMC_ECC_SIZE_CONFIG 0x1fc |
| 51 | #define GPMC_ECC1_RESULT 0x200 | 51 | #define GPMC_ECC1_RESULT 0x200 |
| 52 | 52 | ||
| 53 | /* GPMC ECC control settings */ | ||
| 54 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | ||
| 55 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | ||
| 56 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | ||
| 57 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | ||
| 58 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | ||
| 59 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | ||
| 60 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | ||
| 61 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | ||
| 62 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | ||
| 63 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | ||
| 64 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | ||
| 65 | |||
| 53 | #define GPMC_CS0_OFFSET 0x60 | 66 | #define GPMC_CS0_OFFSET 0x60 |
| 54 | #define GPMC_CS_SIZE 0x30 | 67 | #define GPMC_CS_SIZE 0x30 |
| 55 | 68 | ||
| @@ -861,8 +874,9 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) | |||
| 861 | gpmc_ecc_used = cs; | 874 | gpmc_ecc_used = cs; |
| 862 | 875 | ||
| 863 | /* clear ecc and enable bits */ | 876 | /* clear ecc and enable bits */ |
| 864 | val = ((0x00000001<<8) | 0x00000001); | 877 | gpmc_write_reg(GPMC_ECC_CONTROL, |
| 865 | gpmc_write_reg(GPMC_ECC_CONTROL, val); | 878 | GPMC_ECC_CTRL_ECCCLEAR | |
| 879 | GPMC_ECC_CTRL_ECCREG1); | ||
| 866 | 880 | ||
| 867 | /* program ecc and result sizes */ | 881 | /* program ecc and result sizes */ |
| 868 | val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); | 882 | val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); |
| @@ -870,13 +884,15 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) | |||
| 870 | 884 | ||
| 871 | switch (mode) { | 885 | switch (mode) { |
| 872 | case GPMC_ECC_READ: | 886 | case GPMC_ECC_READ: |
| 873 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); | 887 | case GPMC_ECC_WRITE: |
| 888 | gpmc_write_reg(GPMC_ECC_CONTROL, | ||
| 889 | GPMC_ECC_CTRL_ECCCLEAR | | ||
| 890 | GPMC_ECC_CTRL_ECCREG1); | ||
| 874 | break; | 891 | break; |
| 875 | case GPMC_ECC_READSYN: | 892 | case GPMC_ECC_READSYN: |
| 876 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x100); | 893 | gpmc_write_reg(GPMC_ECC_CONTROL, |
| 877 | break; | 894 | GPMC_ECC_CTRL_ECCCLEAR | |
| 878 | case GPMC_ECC_WRITE: | 895 | GPMC_ECC_CTRL_ECCDISABLE); |
| 879 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); | ||
| 880 | break; | 896 | break; |
| 881 | default: | 897 | default: |
| 882 | printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); | 898 | printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); |
