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-rw-r--r--arch/arm/mach-omap2/iommu2.c323
-rw-r--r--arch/arm/plat-omap/include/mach/iommu2.h96
2 files changed, 419 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
new file mode 100644
index 000000000000..015f22a53ead
--- /dev/null
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -0,0 +1,323 @@
1/*
2 * omap iommu: omap2/3 architecture specific functions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/device.h>
16#include <linux/jiffies.h>
17#include <linux/module.h>
18#include <linux/stringify.h>
19
20#include <mach/iommu.h>
21
22/*
23 * omap2 architecture specific register bit definitions
24 */
25#define IOMMU_ARCH_VERSION 0x00000011
26
27/* SYSCONF */
28#define MMU_SYS_IDLE_SHIFT 3
29#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
30#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
31#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
32#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
33
34#define MMU_SYS_SOFTRESET (1 << 1)
35#define MMU_SYS_AUTOIDLE 1
36
37/* SYSSTATUS */
38#define MMU_SYS_RESETDONE 1
39
40/* IRQSTATUS & IRQENABLE */
41#define MMU_IRQ_MULTIHITFAULT (1 << 4)
42#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
43#define MMU_IRQ_EMUMISS (1 << 2)
44#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
45#define MMU_IRQ_TLBMISS (1 << 0)
46#define MMU_IRQ_MASK \
47 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
48 MMU_IRQ_TRANSLATIONFAULT)
49
50/* MMU_CNTL */
51#define MMU_CNTL_SHIFT 1
52#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
53#define MMU_CNTL_EML_TLB (1 << 3)
54#define MMU_CNTL_TWL_EN (1 << 2)
55#define MMU_CNTL_MMU_EN (1 << 1)
56
57#define get_cam_va_mask(pgsz) \
58 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
59 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
60 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
61 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
62
63static int omap2_iommu_enable(struct iommu *obj)
64{
65 u32 l, pa;
66 unsigned long timeout;
67
68 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
69 return -EINVAL;
70
71 pa = virt_to_phys(obj->iopgd);
72 if (!IS_ALIGNED(pa, SZ_16K))
73 return -EINVAL;
74
75 iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
76
77 timeout = jiffies + msecs_to_jiffies(20);
78 do {
79 l = iommu_read_reg(obj, MMU_SYSSTATUS);
80 if (l & MMU_SYS_RESETDONE)
81 break;
82 } while (time_after(jiffies, timeout));
83
84 if (!(l & MMU_SYS_RESETDONE)) {
85 dev_err(obj->dev, "can't take mmu out of reset\n");
86 return -ENODEV;
87 }
88
89 l = iommu_read_reg(obj, MMU_REVISION);
90 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
91 (l >> 4) & 0xf, l & 0xf);
92
93 l = iommu_read_reg(obj, MMU_SYSCONFIG);
94 l &= ~MMU_SYS_IDLE_MASK;
95 l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
96 iommu_write_reg(obj, l, MMU_SYSCONFIG);
97
98 iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
99 iommu_write_reg(obj, pa, MMU_TTB);
100
101 l = iommu_read_reg(obj, MMU_CNTL);
102 l &= ~MMU_CNTL_MASK;
103 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
104 iommu_write_reg(obj, l, MMU_CNTL);
105
106 return 0;
107}
108
109static void omap2_iommu_disable(struct iommu *obj)
110{
111 u32 l = iommu_read_reg(obj, MMU_CNTL);
112
113 l &= ~MMU_CNTL_MASK;
114 iommu_write_reg(obj, l, MMU_CNTL);
115 iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
116
117 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
118}
119
120static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
121{
122 int i;
123 u32 stat, da;
124 const char *err_msg[] = {
125 "tlb miss",
126 "translation fault",
127 "emulation miss",
128 "table walk fault",
129 "multi hit fault",
130 };
131
132 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
133 stat &= MMU_IRQ_MASK;
134 if (!stat)
135 return 0;
136
137 da = iommu_read_reg(obj, MMU_FAULT_AD);
138 *ra = da;
139
140 dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
141
142 for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
143 if (stat & (1 << i))
144 printk("%s ", err_msg[i]);
145 }
146 printk("\n");
147
148 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
149 return stat;
150}
151
152static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
153{
154 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
155 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
156}
157
158static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr)
159{
160 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
161 iommu_write_reg(obj, cr->ram, MMU_RAM);
162}
163
164static u32 omap2_cr_to_virt(struct cr_regs *cr)
165{
166 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
167 u32 mask = get_cam_va_mask(cr->cam & page_size);
168
169 return cr->cam & mask;
170}
171
172static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
173{
174 struct cr_regs *cr;
175
176 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
177 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
178 e->da);
179 return ERR_PTR(-EINVAL);
180 }
181
182 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
183 if (!cr)
184 return ERR_PTR(-ENOMEM);
185
186 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz;
187 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
188
189 return cr;
190}
191
192static inline int omap2_cr_valid(struct cr_regs *cr)
193{
194 return cr->cam & MMU_CAM_V;
195}
196
197static u32 omap2_get_pte_attr(struct iotlb_entry *e)
198{
199 u32 attr;
200
201 attr = e->mixed << 5;
202 attr |= e->endian;
203 attr |= e->elsz >> 3;
204 attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
205
206 return attr;
207}
208
209static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
210{
211 char *p = buf;
212
213 /* FIXME: Need more detail analysis of cam/ram */
214 p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);
215
216 return p - buf;
217}
218
219#define pr_reg(name) \
220 p += sprintf(p, "%20s: %08x\n", \
221 __stringify(name), iommu_read_reg(obj, MMU_##name));
222
223static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
224{
225 char *p = buf;
226
227 pr_reg(REVISION);
228 pr_reg(SYSCONFIG);
229 pr_reg(SYSSTATUS);
230 pr_reg(IRQSTATUS);
231 pr_reg(IRQENABLE);
232 pr_reg(WALKING_ST);
233 pr_reg(CNTL);
234 pr_reg(FAULT_AD);
235 pr_reg(TTB);
236 pr_reg(LOCK);
237 pr_reg(LD_TLB);
238 pr_reg(CAM);
239 pr_reg(RAM);
240 pr_reg(GFLUSH);
241 pr_reg(FLUSH_ENTRY);
242 pr_reg(READ_CAM);
243 pr_reg(READ_RAM);
244 pr_reg(EMU_FAULT_AD);
245
246 return p - buf;
247}
248
249static void omap2_iommu_save_ctx(struct iommu *obj)
250{
251 int i;
252 u32 *p = obj->ctx;
253
254 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
255 p[i] = iommu_read_reg(obj, i * sizeof(u32));
256 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
257 }
258
259 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
260}
261
262static void omap2_iommu_restore_ctx(struct iommu *obj)
263{
264 int i;
265 u32 *p = obj->ctx;
266
267 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
268 iommu_write_reg(obj, p[i], i * sizeof(u32));
269 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
270 }
271
272 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
273}
274
275static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
276{
277 e->da = cr->cam & MMU_CAM_VATAG_MASK;
278 e->pa = cr->ram & MMU_RAM_PADDR_MASK;
279 e->valid = cr->cam & MMU_CAM_V;
280 e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
281 e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
282 e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
283 e->mixed = cr->ram & MMU_RAM_MIXED;
284}
285
286static const struct iommu_functions omap2_iommu_ops = {
287 .version = IOMMU_ARCH_VERSION,
288
289 .enable = omap2_iommu_enable,
290 .disable = omap2_iommu_disable,
291 .fault_isr = omap2_iommu_fault_isr,
292
293 .tlb_read_cr = omap2_tlb_read_cr,
294 .tlb_load_cr = omap2_tlb_load_cr,
295
296 .cr_to_e = omap2_cr_to_e,
297 .cr_to_virt = omap2_cr_to_virt,
298 .alloc_cr = omap2_alloc_cr,
299 .cr_valid = omap2_cr_valid,
300 .dump_cr = omap2_dump_cr,
301
302 .get_pte_attr = omap2_get_pte_attr,
303
304 .save_ctx = omap2_iommu_save_ctx,
305 .restore_ctx = omap2_iommu_restore_ctx,
306 .dump_ctx = omap2_iommu_dump_ctx,
307};
308
309static int __init omap2_iommu_init(void)
310{
311 return install_iommu_arch(&omap2_iommu_ops);
312}
313module_init(omap2_iommu_init);
314
315static void __exit omap2_iommu_exit(void)
316{
317 uninstall_iommu_arch(&omap2_iommu_ops);
318}
319module_exit(omap2_iommu_exit);
320
321MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
322MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
323MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h
new file mode 100644
index 000000000000..10ad05f410e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iommu2.h
@@ -0,0 +1,96 @@
1/*
2 * omap iommu: omap2 architecture specific definitions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MACH_IOMMU2_H
14#define __MACH_IOMMU2_H
15
16#include <linux/io.h>
17
18/*
19 * MMU Register offsets
20 */
21#define MMU_REVISION 0x00
22#define MMU_SYSCONFIG 0x10
23#define MMU_SYSSTATUS 0x14
24#define MMU_IRQSTATUS 0x18
25#define MMU_IRQENABLE 0x1c
26#define MMU_WALKING_ST 0x40
27#define MMU_CNTL 0x44
28#define MMU_FAULT_AD 0x48
29#define MMU_TTB 0x4c
30#define MMU_LOCK 0x50
31#define MMU_LD_TLB 0x54
32#define MMU_CAM 0x58
33#define MMU_RAM 0x5c
34#define MMU_GFLUSH 0x60
35#define MMU_FLUSH_ENTRY 0x64
36#define MMU_READ_CAM 0x68
37#define MMU_READ_RAM 0x6c
38#define MMU_EMU_FAULT_AD 0x70
39
40#define MMU_REG_SIZE 256
41
42/*
43 * MMU Register bit definitions
44 */
45#define MMU_LOCK_BASE_SHIFT 10
46#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
47#define MMU_LOCK_BASE(x) \
48 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
49
50#define MMU_LOCK_VICT_SHIFT 4
51#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
52#define MMU_LOCK_VICT(x) \
53 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
54
55#define MMU_CAM_VATAG_SHIFT 12
56#define MMU_CAM_VATAG_MASK \
57 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
58#define MMU_CAM_P (1 << 3)
59#define MMU_CAM_V (1 << 2)
60#define MMU_CAM_PGSZ_MASK 3
61#define MMU_CAM_PGSZ_1M (0 << 0)
62#define MMU_CAM_PGSZ_64K (1 << 0)
63#define MMU_CAM_PGSZ_4K (2 << 0)
64#define MMU_CAM_PGSZ_16M (3 << 0)
65
66#define MMU_RAM_PADDR_SHIFT 12
67#define MMU_RAM_PADDR_MASK \
68 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
69#define MMU_RAM_ENDIAN_SHIFT 9
70#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
71#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
72#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
73#define MMU_RAM_ELSZ_SHIFT 7
74#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
75#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
76#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
77#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
78#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
79#define MMU_RAM_MIXED_SHIFT 6
80#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
81#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
82
83/*
84 * register accessors
85 */
86static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
87{
88 return __raw_readl(obj->regbase + offs);
89}
90
91static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
92{
93 __raw_writel(val, obj->regbase + offs);
94}
95
96#endif /* __MACH_IOMMU2_H */
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