aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--Documentation/devicetree/bindings/ata/sata_highbank.txt6
-rw-r--r--drivers/ata/sata_highbank.c13
2 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
index c84833e13363..aa83407cb7a4 100644
--- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -23,6 +23,10 @@ Optional properties:
23- calxeda,tx-atten : a u32 array that contains TX attenuation override 23- calxeda,tx-atten : a u32 array that contains TX attenuation override
24 codes, one per port. The upper 3 bytes are always 24 codes, one per port. The upper 3 bytes are always
25 0 and thus ignored. 25 0 and thus ignored.
26- calxeda,pre-clocks : a u32 that indicates the number of additional clock
27 cycles to transmit before sending an SGPIO pattern
28- calxeda,post-clocks: a u32 that indicates the number of additional clock
29 cycles to transmit after sending an SGPIO pattern
26 30
27Example: 31Example:
28 sata@ffe08000 { 32 sata@ffe08000 {
@@ -35,4 +39,6 @@ Example:
35 calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; 39 calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
36 calxeda,led-order = <4 0 1 2 3>; 40 calxeda,led-order = <4 0 1 2 3>;
37 calxeda,tx-atten = <0xff 22 0xff 0xff 23>; 41 calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
42 calxeda,pre-clocks = <10>;
43 calxeda,post-clocks = <0>;
38 }; 44 };
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index ba43c7217545..0849672218c9 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -84,6 +84,9 @@ static DEFINE_SPINLOCK(sgpio_lock);
84 84
85struct ecx_plat_data { 85struct ecx_plat_data {
86 u32 n_ports; 86 u32 n_ports;
87 /* number of extra clocks that the SGPIO PIC controller expects */
88 u32 pre_clocks;
89 u32 post_clocks;
87 unsigned sgpio_gpio[SGPIO_PINS]; 90 unsigned sgpio_gpio[SGPIO_PINS];
88 u32 sgpio_pattern; 91 u32 sgpio_pattern;
89 u32 port_to_sgpio[SGPIO_PORTS]; 92 u32 port_to_sgpio[SGPIO_PORTS];
@@ -160,6 +163,9 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
160 spin_lock_irqsave(&sgpio_lock, flags); 163 spin_lock_irqsave(&sgpio_lock, flags);
161 ecx_parse_sgpio(pdata, ap->port_no, state); 164 ecx_parse_sgpio(pdata, ap->port_no, state);
162 sgpio_out = pdata->sgpio_pattern; 165 sgpio_out = pdata->sgpio_pattern;
166 for (i = 0; i < pdata->pre_clocks; i++)
167 ecx_led_cycle_clock(pdata);
168
163 gpio_set_value(pdata->sgpio_gpio[SLOAD], 1); 169 gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
164 ecx_led_cycle_clock(pdata); 170 ecx_led_cycle_clock(pdata);
165 gpio_set_value(pdata->sgpio_gpio[SLOAD], 0); 171 gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
@@ -172,6 +178,8 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
172 sgpio_out >>= 1; 178 sgpio_out >>= 1;
173 ecx_led_cycle_clock(pdata); 179 ecx_led_cycle_clock(pdata);
174 } 180 }
181 for (i = 0; i < pdata->post_clocks; i++)
182 ecx_led_cycle_clock(pdata);
175 183
176 /* save off new led state for port/slot */ 184 /* save off new led state for port/slot */
177 emp->led_state = state; 185 emp->led_state = state;
@@ -206,6 +214,11 @@ static void highbank_set_em_messages(struct device *dev,
206 of_property_read_u32_array(np, "calxeda,led-order", 214 of_property_read_u32_array(np, "calxeda,led-order",
207 pdata->port_to_sgpio, 215 pdata->port_to_sgpio,
208 pdata->n_ports); 216 pdata->n_ports);
217 if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
218 pdata->pre_clocks = 0;
219 if (of_property_read_u32(np, "calxeda,post-clocks",
220 &pdata->post_clocks))
221 pdata->post_clocks = 0;
209 222
210 /* store em_loc */ 223 /* store em_loc */
211 hpriv->em_loc = 0; 224 hpriv->em_loc = 0;