diff options
-rw-r--r-- | drivers/clk/tegra/clk-periph-gate.c | 22 | ||||
-rw-r--r-- | drivers/clk/tegra/clk-periph.c | 40 | ||||
-rw-r--r-- | drivers/clk/tegra/clk.h | 1 | ||||
-rw-r--r-- | include/linux/clk/tegra.h | 7 |
4 files changed, 0 insertions, 70 deletions
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index f38f33e3c65d..507015314827 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c | |||
@@ -36,8 +36,6 @@ static DEFINE_SPINLOCK(periph_ref_lock); | |||
36 | 36 | ||
37 | #define read_rst(gate) \ | 37 | #define read_rst(gate) \ |
38 | readl_relaxed(gate->clk_base + (gate->regs->rst_reg)) | 38 | readl_relaxed(gate->clk_base + (gate->regs->rst_reg)) |
39 | #define write_rst_set(val, gate) \ | ||
40 | writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg)) | ||
41 | #define write_rst_clr(val, gate) \ | 39 | #define write_rst_clr(val, gate) \ |
42 | writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) | 40 | writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) |
43 | 41 | ||
@@ -123,26 +121,6 @@ static void clk_periph_disable(struct clk_hw *hw) | |||
123 | spin_unlock_irqrestore(&periph_ref_lock, flags); | 121 | spin_unlock_irqrestore(&periph_ref_lock, flags); |
124 | } | 122 | } |
125 | 123 | ||
126 | void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert) | ||
127 | { | ||
128 | if (gate->flags & TEGRA_PERIPH_NO_RESET) | ||
129 | return; | ||
130 | |||
131 | if (assert) { | ||
132 | /* | ||
133 | * If peripheral is in the APB bus then read the APB bus to | ||
134 | * flush the write operation in apb bus. This will avoid the | ||
135 | * peripheral access after disabling clock | ||
136 | */ | ||
137 | if (gate->flags & TEGRA_PERIPH_ON_APB) | ||
138 | tegra_read_chipid(); | ||
139 | |||
140 | write_rst_set(periph_clk_to_bit(gate), gate); | ||
141 | } else { | ||
142 | write_rst_clr(periph_clk_to_bit(gate), gate); | ||
143 | } | ||
144 | } | ||
145 | |||
146 | const struct clk_ops tegra_clk_periph_gate_ops = { | 124 | const struct clk_ops tegra_clk_periph_gate_ops = { |
147 | .is_enabled = clk_periph_is_enabled, | 125 | .is_enabled = clk_periph_is_enabled, |
148 | .enable = clk_periph_enable, | 126 | .enable = clk_periph_enable, |
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index d62b396863c1..c534043c0481 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c | |||
@@ -111,46 +111,6 @@ static void clk_periph_disable(struct clk_hw *hw) | |||
111 | gate_ops->disable(gate_hw); | 111 | gate_ops->disable(gate_hw); |
112 | } | 112 | } |
113 | 113 | ||
114 | void tegra_periph_reset_deassert(struct clk *c) | ||
115 | { | ||
116 | struct clk_hw *hw = __clk_get_hw(c); | ||
117 | struct tegra_clk_periph *periph = to_clk_periph(hw); | ||
118 | struct tegra_clk_periph_gate *gate; | ||
119 | |||
120 | if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) { | ||
121 | gate = to_clk_periph_gate(hw); | ||
122 | if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) { | ||
123 | WARN_ON(1); | ||
124 | return; | ||
125 | } | ||
126 | } else { | ||
127 | gate = &periph->gate; | ||
128 | } | ||
129 | |||
130 | tegra_periph_reset(gate, 0); | ||
131 | } | ||
132 | EXPORT_SYMBOL(tegra_periph_reset_deassert); | ||
133 | |||
134 | void tegra_periph_reset_assert(struct clk *c) | ||
135 | { | ||
136 | struct clk_hw *hw = __clk_get_hw(c); | ||
137 | struct tegra_clk_periph *periph = to_clk_periph(hw); | ||
138 | struct tegra_clk_periph_gate *gate; | ||
139 | |||
140 | if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) { | ||
141 | gate = to_clk_periph_gate(hw); | ||
142 | if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) { | ||
143 | WARN_ON(1); | ||
144 | return; | ||
145 | } | ||
146 | } else { | ||
147 | gate = &periph->gate; | ||
148 | } | ||
149 | |||
150 | tegra_periph_reset(gate, 1); | ||
151 | } | ||
152 | EXPORT_SYMBOL(tegra_periph_reset_assert); | ||
153 | |||
154 | const struct clk_ops tegra_clk_periph_ops = { | 114 | const struct clk_ops tegra_clk_periph_ops = { |
155 | .get_parent = clk_periph_get_parent, | 115 | .get_parent = clk_periph_get_parent, |
156 | .set_parent = clk_periph_set_parent, | 116 | .set_parent = clk_periph_set_parent, |
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 07c62f997371..16ec8d6bb87f 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h | |||
@@ -393,7 +393,6 @@ struct tegra_clk_periph_gate { | |||
393 | #define TEGRA_PERIPH_NO_DIV BIT(4) | 393 | #define TEGRA_PERIPH_NO_DIV BIT(4) |
394 | #define TEGRA_PERIPH_NO_GATE BIT(5) | 394 | #define TEGRA_PERIPH_NO_GATE BIT(5) |
395 | 395 | ||
396 | void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); | ||
397 | extern const struct clk_ops tegra_clk_periph_gate_ops; | 396 | extern const struct clk_ops tegra_clk_periph_gate_ops; |
398 | struct clk *tegra_clk_register_periph_gate(const char *name, | 397 | struct clk *tegra_clk_register_periph_gate(const char *name, |
399 | const char *parent_name, u8 gate_flags, void __iomem *clk_base, | 398 | const char *parent_name, u8 gate_flags, void __iomem *clk_base, |
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 23a0ceee831f..3ca9fca827a2 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h | |||
@@ -120,13 +120,6 @@ static inline void tegra_cpu_clock_resume(void) | |||
120 | } | 120 | } |
121 | #endif | 121 | #endif |
122 | 122 | ||
123 | #ifdef CONFIG_ARCH_TEGRA | ||
124 | void tegra_periph_reset_deassert(struct clk *c); | ||
125 | void tegra_periph_reset_assert(struct clk *c); | ||
126 | #else | ||
127 | static inline void tegra_periph_reset_deassert(struct clk *c) {} | ||
128 | static inline void tegra_periph_reset_assert(struct clk *c) {} | ||
129 | #endif | ||
130 | void tegra_clocks_apply_init_table(void); | 123 | void tegra_clocks_apply_init_table(void); |
131 | 124 | ||
132 | #endif /* __LINUX_CLK_TEGRA_H_ */ | 125 | #endif /* __LINUX_CLK_TEGRA_H_ */ |