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-rw-r--r--arch/arm/mach-rockchip/rockchip.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index d360ec044b66..b6cf3b449428 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -30,11 +30,30 @@
30#include "pm.h" 30#include "pm.h"
31 31
32#define RK3288_GRF_SOC_CON0 0x244 32#define RK3288_GRF_SOC_CON0 0x244
33#define RK3288_TIMER6_7_PHYS 0xff810000
33 34
34static void __init rockchip_timer_init(void) 35static void __init rockchip_timer_init(void)
35{ 36{
36 if (of_machine_is_compatible("rockchip,rk3288")) { 37 if (of_machine_is_compatible("rockchip,rk3288")) {
37 struct regmap *grf; 38 struct regmap *grf;
39 void __iomem *reg_base;
40
41 /*
42 * Most/all uboot versions for rk3288 don't enable timer7
43 * which is needed for the architected timer to work.
44 * So make sure it is running during early boot.
45 */
46 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
47 if (reg_base) {
48 writel(0, reg_base + 0x30);
49 writel(0xffffffff, reg_base + 0x20);
50 writel(0xffffffff, reg_base + 0x24);
51 writel(1, reg_base + 0x30);
52 dsb();
53 iounmap(reg_base);
54 } else {
55 pr_err("rockchip: could not map timer7 registers\n");
56 }
38 57
39 /* 58 /*
40 * Disable auto jtag/sdmmc switching that causes issues 59 * Disable auto jtag/sdmmc switching that causes issues