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-rw-r--r--drivers/net/wireless/b43/phy_ht.c119
-rw-r--r--drivers/net/wireless/b43/phy_ht.h6
-rw-r--r--drivers/net/wireless/b43/phy_lp.c4
-rw-r--r--drivers/net/wireless/b43/phy_n.c649
-rw-r--r--drivers/net/wireless/b43/phy_n.h146
-rw-r--r--drivers/net/wireless/b43/radio_2059.c39
-rw-r--r--drivers/net/wireless/b43/radio_2059.h14
-rw-r--r--drivers/net/wireless/b43/tables_nphy.c97
-rw-r--r--drivers/net/wireless/b43/tables_nphy.h29
9 files changed, 661 insertions, 442 deletions
diff --git a/drivers/net/wireless/b43/phy_ht.c b/drivers/net/wireless/b43/phy_ht.c
index 83239fd87040..5d6833f18498 100644
--- a/drivers/net/wireless/b43/phy_ht.c
+++ b/drivers/net/wireless/b43/phy_ht.c
@@ -30,6 +30,17 @@
30#include "radio_2059.h" 30#include "radio_2059.h"
31#include "main.h" 31#include "main.h"
32 32
33/* Force values to keep compatibility with wl */
34enum ht_rssi_type {
35 HT_RSSI_W1 = 0,
36 HT_RSSI_W2 = 1,
37 HT_RSSI_NB = 2,
38 HT_RSSI_IQ = 3,
39 HT_RSSI_TSSI_2G = 4,
40 HT_RSSI_TSSI_5G = 5,
41 HT_RSSI_TBD = 6,
42};
43
33/************************************************** 44/**************************************************
34 * Radio 2059. 45 * Radio 2059.
35 **************************************************/ 46 **************************************************/
@@ -37,8 +48,9 @@
37static void b43_radio_2059_channel_setup(struct b43_wldev *dev, 48static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
38 const struct b43_phy_ht_channeltab_e_radio2059 *e) 49 const struct b43_phy_ht_channeltab_e_radio2059 *e)
39{ 50{
40 u8 i; 51 static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
41 u16 routing; 52 u16 r;
53 int core;
42 54
43 b43_radio_write(dev, 0x16, e->radio_syn16); 55 b43_radio_write(dev, 0x16, e->radio_syn16);
44 b43_radio_write(dev, 0x17, e->radio_syn17); 56 b43_radio_write(dev, 0x17, e->radio_syn17);
@@ -53,25 +65,17 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
53 b43_radio_write(dev, 0x41, e->radio_syn41); 65 b43_radio_write(dev, 0x41, e->radio_syn41);
54 b43_radio_write(dev, 0x43, e->radio_syn43); 66 b43_radio_write(dev, 0x43, e->radio_syn43);
55 b43_radio_write(dev, 0x47, e->radio_syn47); 67 b43_radio_write(dev, 0x47, e->radio_syn47);
56 b43_radio_write(dev, 0x4a, e->radio_syn4a); 68
57 b43_radio_write(dev, 0x58, e->radio_syn58); 69 for (core = 0; core < 3; core++) {
58 b43_radio_write(dev, 0x5a, e->radio_syn5a); 70 r = routing[core];
59 b43_radio_write(dev, 0x6a, e->radio_syn6a); 71 b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a);
60 b43_radio_write(dev, 0x6d, e->radio_syn6d); 72 b43_radio_write(dev, r | 0x58, e->radio_rxtx58);
61 b43_radio_write(dev, 0x6e, e->radio_syn6e); 73 b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a);
62 b43_radio_write(dev, 0x92, e->radio_syn92); 74 b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a);
63 b43_radio_write(dev, 0x98, e->radio_syn98); 75 b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d);
64 76 b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e);
65 for (i = 0; i < 2; i++) { 77 b43_radio_write(dev, r | 0x92, e->radio_rxtx92);
66 routing = i ? R2059_RXRX1 : R2059_TXRX0; 78 b43_radio_write(dev, r | 0x98, e->radio_rxtx98);
67 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
68 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
69 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
70 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
71 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
72 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
73 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
74 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
75 } 79 }
76 80
77 udelay(50); 81 udelay(50);
@@ -87,7 +91,7 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
87 91
88static void b43_radio_2059_init(struct b43_wldev *dev) 92static void b43_radio_2059_init(struct b43_wldev *dev)
89{ 93{
90 const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 }; 94 const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
91 const u16 radio_values[3][2] = { 95 const u16 radio_values[3][2] = {
92 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 }, 96 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
93 }; 97 };
@@ -106,17 +110,17 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
106 b43_radio_mask(dev, 0xc0, ~0x0080); 110 b43_radio_mask(dev, 0xc0, ~0x0080);
107 111
108 if (1) { /* FIXME */ 112 if (1) { /* FIXME */
109 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1); 113 b43_radio_set(dev, R2059_C3 | 0x4, 0x1);
110 udelay(10); 114 udelay(10);
111 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1); 115 b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
112 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2); 116 b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);
113 117
114 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2); 118 b43_radio_set(dev, R2059_C3 | 0x4, 0x2);
115 udelay(100); 119 udelay(100);
116 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2); 120 b43_radio_mask(dev, R2059_C3 | 0x4, ~0x2);
117 121
118 for (i = 0; i < 10000; i++) { 122 for (i = 0; i < 10000; i++) {
119 if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) { 123 if (b43_radio_read(dev, R2059_C3 | 0x145) & 1) {
120 i = 0; 124 i = 0;
121 break; 125 break;
122 } 126 }
@@ -125,7 +129,7 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
125 if (i) 129 if (i)
126 b43err(dev->wl, "radio 0x945 timeout\n"); 130 b43err(dev->wl, "radio 0x945 timeout\n");
127 131
128 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1); 132 b43_radio_mask(dev, R2059_C3 | 0x4, ~0x1);
129 b43_radio_set(dev, 0xa, 0x60); 133 b43_radio_set(dev, 0xa, 0x60);
130 134
131 for (i = 0; i < 3; i++) { 135 for (i = 0; i < 3; i++) {
@@ -390,14 +394,14 @@ static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
390 **************************************************/ 394 **************************************************/
391 395
392static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel, 396static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
393 u8 rssi_type) 397 enum ht_rssi_type rssi_type)
394{ 398{
395 static const u16 ctl_regs[3][2] = { 399 static const u16 ctl_regs[3][2] = {
396 { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, }, 400 { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
397 { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, }, 401 { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
398 { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, }, 402 { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
399 }; 403 };
400 static const u16 radio_r[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1, }; 404 static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, };
401 int core; 405 int core;
402 406
403 if (core_sel == 0) { 407 if (core_sel == 0) {
@@ -411,13 +415,13 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
411 continue; 415 continue;
412 416
413 switch (rssi_type) { 417 switch (rssi_type) {
414 case 4: 418 case HT_RSSI_TSSI_2G:
415 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8); 419 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
416 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10); 420 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
417 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9); 421 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
418 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10); 422 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
419 423
420 b43_radio_set(dev, R2059_RXRX1 | 0xbf, 0x1); 424 b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);
421 b43_radio_write(dev, radio_r[core] | 0x159, 425 b43_radio_write(dev, radio_r[core] | 0x159,
422 0x11); 426 0x11);
423 break; 427 break;
@@ -429,8 +433,8 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
429 } 433 }
430} 434}
431 435
432static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, 436static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, enum ht_rssi_type type,
433 u8 nsamp) 437 s32 *buf, u8 nsamp)
434{ 438{
435 u16 phy_regs_values[12]; 439 u16 phy_regs_values[12];
436 static const u16 phy_regs_to_save[] = { 440 static const u16 phy_regs_to_save[] = {
@@ -504,15 +508,17 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
504 static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1, 508 static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
505 B43_PHY_HT_TXPCTL_CMD_C2, 509 B43_PHY_HT_TXPCTL_CMD_C2,
506 B43_PHY_HT_TXPCTL_CMD_C3 }; 510 B43_PHY_HT_TXPCTL_CMD_C3 };
511 static const u16 status_regs[3] = { B43_PHY_HT_TX_PCTL_STATUS_C1,
512 B43_PHY_HT_TX_PCTL_STATUS_C2,
513 B43_PHY_HT_TX_PCTL_STATUS_C3 };
507 int i; 514 int i;
508 515
509 if (!enable) { 516 if (!enable) {
510 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) { 517 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
511 /* We disable enabled TX pwr ctl, save it's state */ 518 /* We disable enabled TX pwr ctl, save it's state */
512 /* 519 for (i = 0; i < 3; i++)
513 * TODO: find the registers. On N-PHY they were 0x1ed 520 phy_ht->tx_pwr_idx[i] =
514 * and 0x1ee, we need 3 such a registers for HT-PHY 521 b43_phy_read(dev, status_regs[i]);
515 */
516 } 522 }
517 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits); 523 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
518 } else { 524 } else {
@@ -536,13 +542,25 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
536static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev) 542static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
537{ 543{
538 struct b43_phy_ht *phy_ht = dev->phy.ht; 544 struct b43_phy_ht *phy_ht = dev->phy.ht;
545 static const u16 base[] = { 0x840, 0x860, 0x880 };
546 u16 save_regs[3][3];
539 s32 rssi_buf[6]; 547 s32 rssi_buf[6];
548 int core;
549
550 for (core = 0; core < 3; core++) {
551 save_regs[core][1] = b43_phy_read(dev, base[core] + 6);
552 save_regs[core][2] = b43_phy_read(dev, base[core] + 7);
553 save_regs[core][0] = b43_phy_read(dev, base[core] + 0);
540 554
541 /* TODO */ 555 b43_phy_write(dev, base[core] + 6, 0);
556 b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */
557 b43_phy_set(dev, base[core] + 0, 0x0400);
558 b43_phy_set(dev, base[core] + 0, 0x1000);
559 }
542 560
543 b43_phy_ht_tx_tone(dev); 561 b43_phy_ht_tx_tone(dev);
544 udelay(20); 562 udelay(20);
545 b43_phy_ht_poll_rssi(dev, 4, rssi_buf, 1); 563 b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1);
546 b43_phy_ht_stop_playback(dev); 564 b43_phy_ht_stop_playback(dev);
547 b43_phy_ht_reset_cca(dev); 565 b43_phy_ht_reset_cca(dev);
548 566
@@ -550,7 +568,23 @@ static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
550 phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff; 568 phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
551 phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff; 569 phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
552 570
553 /* TODO */ 571 for (core = 0; core < 3; core++) {
572 b43_phy_write(dev, base[core] + 0, save_regs[core][0]);
573 b43_phy_write(dev, base[core] + 6, save_regs[core][1]);
574 b43_phy_write(dev, base[core] + 7, save_regs[core][2]);
575 }
576}
577
578static void b43_phy_ht_tssi_setup(struct b43_wldev *dev)
579{
580 static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
581 int core;
582
583 /* 0x159 is probably TX_SSI_MUX or TSSIG (by comparing to N-PHY) */
584 for (core = 0; core < 3; core++) {
585 b43_radio_set(dev, 0x8bf, 0x1);
586 b43_radio_write(dev, routing[core] | 0x0159, 0x0011);
587 }
554} 588}
555 589
556static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev) 590static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
@@ -946,6 +980,7 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
946 b43_phy_ht_tx_power_ctl(dev, false); 980 b43_phy_ht_tx_power_ctl(dev, false);
947 b43_phy_ht_tx_power_ctl_idle_tssi(dev); 981 b43_phy_ht_tx_power_ctl_idle_tssi(dev);
948 b43_phy_ht_tx_power_ctl_setup(dev); 982 b43_phy_ht_tx_power_ctl_setup(dev);
983 b43_phy_ht_tssi_setup(dev);
949 b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl); 984 b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
950 985
951 return 0; 986 return 0;
diff --git a/drivers/net/wireless/b43/phy_ht.h b/drivers/net/wireless/b43/phy_ht.h
index 9b2408efb224..6cae370d1018 100644
--- a/drivers/net/wireless/b43/phy_ht.h
+++ b/drivers/net/wireless/b43/phy_ht.h
@@ -23,6 +23,9 @@
23#define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */ 23#define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */
24#define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */ 24#define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */
25#define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */ 25#define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */
26#define B43_PHY_HT_EST_PWR_C1 0x118
27#define B43_PHY_HT_EST_PWR_C2 0x119
28#define B43_PHY_HT_EST_PWR_C3 0x11A
26#define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */ 29#define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */
27#define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */ 30#define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */
28#define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */ 31#define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */
@@ -53,6 +56,8 @@
53#define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0 56#define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0
54#define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */ 57#define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */
55#define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8 58#define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8
59#define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED
60#define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE
56#define B43_PHY_HT_TXPCTL_CMD_C2 0x222 61#define B43_PHY_HT_TXPCTL_CMD_C2 0x222
57#define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F 62#define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F
58#define B43_PHY_HT_RSSI_C1 0x219 63#define B43_PHY_HT_RSSI_C1 0x219
@@ -97,6 +102,7 @@
97#define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */ 102#define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */
98#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF 103#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF
99#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0 104#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0
105#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169)
100 106
101#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) 107#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)
102 108
diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c
index 5ed352ddae9e..92190dacf689 100644
--- a/drivers/net/wireless/b43/phy_lp.c
+++ b/drivers/net/wireless/b43/phy_lp.c
@@ -281,8 +281,8 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
281 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A); 281 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
282 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00); 282 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
283 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ || 283 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
284 (dev->dev->board_type == 0x048A) || ((dev->phy.rev == 0) && 284 (dev->dev->board_type == SSB_BOARD_BU4312) ||
285 (sprom->boardflags_lo & B43_BFL_FEM))) { 285 (dev->phy.rev == 0 && (sprom->boardflags_lo & B43_BFL_FEM))) {
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001); 286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400); 287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001); 288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 7ed39e9daa7f..7c970d3ae358 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -69,14 +69,27 @@ enum b43_nphy_rf_sequence {
69 B43_RFSEQ_UPDATE_GAINU, 69 B43_RFSEQ_UPDATE_GAINU,
70}; 70};
71 71
72enum b43_nphy_rssi_type { 72enum n_intc_override {
73 B43_NPHY_RSSI_X = 0, 73 N_INTC_OVERRIDE_OFF = 0,
74 B43_NPHY_RSSI_Y, 74 N_INTC_OVERRIDE_TRSW = 1,
75 B43_NPHY_RSSI_Z, 75 N_INTC_OVERRIDE_PA = 2,
76 B43_NPHY_RSSI_PWRDET, 76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 B43_NPHY_RSSI_TSSI_I, 77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78 B43_NPHY_RSSI_TSSI_Q, 78};
79 B43_NPHY_RSSI_TBD, 79
80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
88};
89
90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
80}; 93};
81 94
82static inline bool b43_nphy_ipa(struct b43_wldev *dev) 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
@@ -94,7 +107,7 @@ static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
94} 107}
95 108
96/************************************************** 109/**************************************************
97 * RF (just without b43_nphy_rf_control_intc_override) 110 * RF (just without b43_nphy_rf_ctl_intc_override)
98 **************************************************/ 111 **************************************************/
99 112
100/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
@@ -128,9 +141,9 @@ ok:
128} 141}
129 142
130/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */ 143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
131static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field, 144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
132 u16 value, u8 core, bool off, 145 u16 value, u8 core, bool off,
133 u8 override) 146 u8 override)
134{ 147{
135 const struct nphy_rf_control_override_rev7 *e; 148 const struct nphy_rf_control_override_rev7 *e;
136 u16 en_addrs[3][2] = { 149 u16 en_addrs[3][2] = {
@@ -168,8 +181,8 @@ static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
168} 181}
169 182
170/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ 183/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
171static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 184static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
172 u16 value, u8 core, bool off) 185 u16 value, u8 core, bool off)
173{ 186{
174 int i; 187 int i;
175 u8 index = fls(field); 188 u8 index = fls(field);
@@ -244,14 +257,14 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
244} 257}
245 258
246/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ 259/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
247static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, 260static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
248 u16 value, u8 core) 261 enum n_intc_override intc_override,
262 u16 value, u8 core)
249{ 263{
250 u8 i, j; 264 u8 i, j;
251 u16 reg, tmp, val; 265 u16 reg, tmp, val;
252 266
253 B43_WARN_ON(dev->phy.rev < 3); 267 B43_WARN_ON(dev->phy.rev < 3);
254 B43_WARN_ON(field > 4);
255 268
256 for (i = 0; i < 2; i++) { 269 for (i = 0; i < 2; i++) {
257 if ((core == 1 && i == 1) || (core == 2 && !i)) 270 if ((core == 1 && i == 1) || (core == 2 && !i))
@@ -261,12 +274,12 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
261 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 274 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
262 b43_phy_set(dev, reg, 0x400); 275 b43_phy_set(dev, reg, 0x400);
263 276
264 switch (field) { 277 switch (intc_override) {
265 case 0: 278 case N_INTC_OVERRIDE_OFF:
266 b43_phy_write(dev, reg, 0); 279 b43_phy_write(dev, reg, 0);
267 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 280 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
268 break; 281 break;
269 case 1: 282 case N_INTC_OVERRIDE_TRSW:
270 if (!i) { 283 if (!i) {
271 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, 284 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
272 0xFC3F, (value << 6)); 285 0xFC3F, (value << 6));
@@ -307,7 +320,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
307 0xFFFE); 320 0xFFFE);
308 } 321 }
309 break; 322 break;
310 case 2: 323 case N_INTC_OVERRIDE_PA:
311 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 324 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
312 tmp = 0x0020; 325 tmp = 0x0020;
313 val = value << 5; 326 val = value << 5;
@@ -317,7 +330,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
317 } 330 }
318 b43_phy_maskset(dev, reg, ~tmp, val); 331 b43_phy_maskset(dev, reg, ~tmp, val);
319 break; 332 break;
320 case 3: 333 case N_INTC_OVERRIDE_EXT_LNA_PU:
321 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 334 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
322 tmp = 0x0001; 335 tmp = 0x0001;
323 val = value; 336 val = value;
@@ -327,7 +340,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
327 } 340 }
328 b43_phy_maskset(dev, reg, ~tmp, val); 341 b43_phy_maskset(dev, reg, ~tmp, val);
329 break; 342 break;
330 case 4: 343 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
331 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 344 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
332 tmp = 0x0002; 345 tmp = 0x0002;
333 val = value << 1; 346 val = value << 1;
@@ -1011,7 +1024,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
1011 1024
1012 if (sprom->revision < 4) 1025 if (sprom->revision < 4)
1013 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM 1026 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1014 && dev->dev->board_type == 0x46D 1027 && dev->dev->board_type == SSB_BOARD_CB2_4321
1015 && dev->dev->board_rev >= 0x41); 1028 && dev->dev->board_rev >= 0x41);
1016 else 1029 else
1017 workaround = 1030 workaround =
@@ -1207,8 +1220,9 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1207 1220
1208/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ 1221/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1209static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, 1222static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1210 s8 offset, u8 core, u8 rail, 1223 s8 offset, u8 core,
1211 enum b43_nphy_rssi_type type) 1224 enum n_rail_type rail,
1225 enum n_rssi_type rssi_type)
1212{ 1226{
1213 u16 tmp; 1227 u16 tmp;
1214 bool core1or5 = (core == 1) || (core == 5); 1228 bool core1or5 = (core == 1) || (core == 5);
@@ -1217,63 +1231,74 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1217 offset = clamp_val(offset, -32, 31); 1231 offset = clamp_val(offset, -32, 31);
1218 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); 1232 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1219 1233
1220 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) 1234 switch (rssi_type) {
1221 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); 1235 case N_RSSI_NB:
1222 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) 1236 if (core1or5 && rail == N_RAIL_I)
1223 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); 1237 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1224 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) 1238 if (core1or5 && rail == N_RAIL_Q)
1225 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); 1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1226 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) 1240 if (core2or5 && rail == N_RAIL_I)
1227 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); 1241 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1228 1242 if (core2or5 && rail == N_RAIL_Q)
1229 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) 1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1230 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); 1244 break;
1231 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) 1245 case N_RSSI_W1:
1232 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); 1246 if (core1or5 && rail == N_RAIL_I)
1233 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) 1247 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1234 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); 1248 if (core1or5 && rail == N_RAIL_Q)
1235 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) 1249 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1236 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); 1250 if (core2or5 && rail == N_RAIL_I)
1237 1251 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1238 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) 1252 if (core2or5 && rail == N_RAIL_Q)
1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); 1253 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1240 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) 1254 break;
1241 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); 1255 case N_RSSI_W2:
1242 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) 1256 if (core1or5 && rail == N_RAIL_I)
1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); 1257 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1244 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) 1258 if (core1or5 && rail == N_RAIL_Q)
1245 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); 1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1246 1260 if (core2or5 && rail == N_RAIL_I)
1247 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) 1261 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1248 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); 1262 if (core2or5 && rail == N_RAIL_Q)
1249 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) 1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1250 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); 1264 break;
1251 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) 1265 case N_RSSI_TBD:
1252 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); 1266 if (core1or5 && rail == N_RAIL_I)
1253 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) 1267 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1254 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); 1268 if (core1or5 && rail == N_RAIL_Q)
1255 1269 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1256 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) 1270 if (core2or5 && rail == N_RAIL_I)
1257 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); 1271 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1258 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) 1272 if (core2or5 && rail == N_RAIL_Q)
1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); 1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1260 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) 1274 break;
1261 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); 1275 case N_RSSI_IQ:
1262 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) 1276 if (core1or5 && rail == N_RAIL_I)
1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); 1277 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1264 1278 if (core1or5 && rail == N_RAIL_Q)
1265 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I)) 1279 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1266 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); 1280 if (core2or5 && rail == N_RAIL_I)
1267 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I)) 1281 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1268 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); 1282 if (core2or5 && rail == N_RAIL_Q)
1269 1283 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1270 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q)) 1284 break;
1271 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); 1285 case N_RSSI_TSSI_2G:
1272 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q)) 1286 if (core1or5)
1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); 1287 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1288 if (core2or5)
1289 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1290 break;
1291 case N_RSSI_TSSI_5G:
1292 if (core1or5)
1293 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1294 if (core2or5)
1295 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1296 break;
1297 }
1274} 1298}
1275 1299
1276static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1300static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1301 enum n_rssi_type rssi_type)
1277{ 1302{
1278 u8 i; 1303 u8 i;
1279 u16 reg, val; 1304 u16 reg, val;
@@ -1296,7 +1321,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1296 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; 1321 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1297 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); 1322 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1298 1323
1299 if (type < 3) { 1324 if (rssi_type == N_RSSI_W1 ||
1325 rssi_type == N_RSSI_W2 ||
1326 rssi_type == N_RSSI_NB) {
1300 reg = (i == 0) ? 1327 reg = (i == 0) ?
1301 B43_NPHY_AFECTL_C1 : 1328 B43_NPHY_AFECTL_C1 :
1302 B43_NPHY_AFECTL_C2; 1329 B43_NPHY_AFECTL_C2;
@@ -1307,9 +1334,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1307 B43_NPHY_RFCTL_LUT_TRSW_UP2; 1334 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1308 b43_phy_maskset(dev, reg, 0xFFC3, 0); 1335 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1309 1336
1310 if (type == 0) 1337 if (rssi_type == N_RSSI_W1)
1311 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; 1338 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1312 else if (type == 1) 1339 else if (rssi_type == N_RSSI_W2)
1313 val = 16; 1340 val = 16;
1314 else 1341 else
1315 val = 32; 1342 val = 32;
@@ -1320,9 +1347,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1320 B43_NPHY_TXF_40CO_B32S1; 1347 B43_NPHY_TXF_40CO_B32S1;
1321 b43_phy_set(dev, reg, 0x0020); 1348 b43_phy_set(dev, reg, 0x0020);
1322 } else { 1349 } else {
1323 if (type == 6) 1350 if (rssi_type == N_RSSI_TBD)
1324 val = 0x0100; 1351 val = 0x0100;
1325 else if (type == 3) 1352 else if (rssi_type == N_RSSI_IQ)
1326 val = 0x0200; 1353 val = 0x0200;
1327 else 1354 else
1328 val = 0x0300; 1355 val = 0x0300;
@@ -1334,7 +1361,8 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1334 b43_phy_maskset(dev, reg, 0xFCFF, val); 1361 b43_phy_maskset(dev, reg, 0xFCFF, val);
1335 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); 1362 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1336 1363
1337 if (type != 3 && type != 6) { 1364 if (rssi_type != N_RSSI_IQ &&
1365 rssi_type != N_RSSI_TBD) {
1338 enum ieee80211_band band = 1366 enum ieee80211_band band =
1339 b43_current_band(dev->wl); 1367 b43_current_band(dev->wl);
1340 1368
@@ -1344,7 +1372,7 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1344 val = 0x11; 1372 val = 0x11;
1345 reg = (i == 0) ? 0x2000 : 0x3000; 1373 reg = (i == 0) ? 0x2000 : 0x3000;
1346 reg |= B2055_PADDRV; 1374 reg |= B2055_PADDRV;
1347 b43_radio_write16(dev, reg, val); 1375 b43_radio_write(dev, reg, val);
1348 1376
1349 reg = (i == 0) ? 1377 reg = (i == 0) ?
1350 B43_NPHY_AFECTL_OVER1 : 1378 B43_NPHY_AFECTL_OVER1 :
@@ -1356,33 +1384,43 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1356 } 1384 }
1357} 1385}
1358 1386
1359static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1387static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1388 enum n_rssi_type rssi_type)
1360{ 1389{
1361 u16 val; 1390 u16 val;
1391 bool rssi_w1_w2_nb = false;
1362 1392
1363 if (type < 3) 1393 switch (rssi_type) {
1394 case N_RSSI_W1:
1395 case N_RSSI_W2:
1396 case N_RSSI_NB:
1364 val = 0; 1397 val = 0;
1365 else if (type == 6) 1398 rssi_w1_w2_nb = true;
1399 break;
1400 case N_RSSI_TBD:
1366 val = 1; 1401 val = 1;
1367 else if (type == 3) 1402 break;
1403 case N_RSSI_IQ:
1368 val = 2; 1404 val = 2;
1369 else 1405 break;
1406 default:
1370 val = 3; 1407 val = 3;
1408 }
1371 1409
1372 val = (val << 12) | (val << 14); 1410 val = (val << 12) | (val << 14);
1373 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); 1411 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1374 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); 1412 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1375 1413
1376 if (type < 3) { 1414 if (rssi_w1_w2_nb) {
1377 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, 1415 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1378 (type + 1) << 4); 1416 (rssi_type + 1) << 4);
1379 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, 1417 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1380 (type + 1) << 4); 1418 (rssi_type + 1) << 4);
1381 } 1419 }
1382 1420
1383 if (code == 0) { 1421 if (code == 0) {
1384 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); 1422 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1385 if (type < 3) { 1423 if (rssi_w1_w2_nb) {
1386 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1424 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1387 ~(B43_NPHY_RFCTL_CMD_RXEN | 1425 ~(B43_NPHY_RFCTL_CMD_RXEN |
1388 B43_NPHY_RFCTL_CMD_CORESEL)); 1426 B43_NPHY_RFCTL_CMD_CORESEL));
@@ -1398,7 +1436,7 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1398 } 1436 }
1399 } else { 1437 } else {
1400 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); 1438 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1401 if (type < 3) { 1439 if (rssi_w1_w2_nb) {
1402 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 1440 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1403 ~(B43_NPHY_RFCTL_CMD_RXEN | 1441 ~(B43_NPHY_RFCTL_CMD_RXEN |
1404 B43_NPHY_RFCTL_CMD_CORESEL), 1442 B43_NPHY_RFCTL_CMD_CORESEL),
@@ -1418,7 +1456,8 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1418} 1456}
1419 1457
1420/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ 1458/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1421static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1459static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1460 enum n_rssi_type type)
1422{ 1461{
1423 if (dev->phy.rev >= 3) 1462 if (dev->phy.rev >= 3)
1424 b43_nphy_rev3_rssi_select(dev, code, type); 1463 b43_nphy_rev3_rssi_select(dev, code, type);
@@ -1427,11 +1466,12 @@ static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1427} 1466}
1428 1467
1429/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ 1468/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1430static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) 1469static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1470 enum n_rssi_type rssi_type, u8 *buf)
1431{ 1471{
1432 int i; 1472 int i;
1433 for (i = 0; i < 2; i++) { 1473 for (i = 0; i < 2; i++) {
1434 if (type == 2) { 1474 if (rssi_type == N_RSSI_NB) {
1435 if (i == 0) { 1475 if (i == 0) {
1436 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, 1476 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1437 0xFC, buf[0]); 1477 0xFC, buf[0]);
@@ -1455,8 +1495,8 @@ static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1455} 1495}
1456 1496
1457/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ 1497/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1458static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, 1498static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1459 u8 nsamp) 1499 s32 *buf, u8 nsamp)
1460{ 1500{
1461 int i; 1501 int i;
1462 int out; 1502 int out;
@@ -1487,7 +1527,7 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1487 save_regs_phy[8] = 0; 1527 save_regs_phy[8] = 0;
1488 } 1528 }
1489 1529
1490 b43_nphy_rssi_select(dev, 5, type); 1530 b43_nphy_rssi_select(dev, 5, rssi_type);
1491 1531
1492 if (dev->phy.rev < 2) { 1532 if (dev->phy.rev < 2) {
1493 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); 1533 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
@@ -1574,7 +1614,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1574 1614
1575 u16 r; /* routing */ 1615 u16 r; /* routing */
1576 u8 rx_core_state; 1616 u8 rx_core_state;
1577 u8 core, i, j; 1617 int core, i, j, vcm;
1578 1618
1579 class = b43_nphy_classifier(dev, 0, 0); 1619 class = b43_nphy_classifier(dev, 0, 0);
1580 b43_nphy_classifier(dev, 7, 4); 1620 b43_nphy_classifier(dev, 7, 4);
@@ -1586,19 +1626,19 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1586 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++) 1626 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1587 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); 1627 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1588 1628
1589 b43_nphy_rf_control_intc_override(dev, 0, 0, 7); 1629 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1590 b43_nphy_rf_control_intc_override(dev, 1, 1, 7); 1630 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
1591 b43_nphy_rf_control_override(dev, 0x1, 0, 0, false); 1631 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1592 b43_nphy_rf_control_override(dev, 0x2, 1, 0, false); 1632 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1593 b43_nphy_rf_control_override(dev, 0x80, 1, 0, false); 1633 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1594 b43_nphy_rf_control_override(dev, 0x40, 1, 0, false); 1634 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1595 1635
1596 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1636 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1597 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false); 1637 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1598 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false); 1638 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1599 } else { 1639 } else {
1600 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false); 1640 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1601 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false); 1641 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1602 } 1642 }
1603 1643
1604 rx_core_state = b43_nphy_get_rx_core_state(dev); 1644 rx_core_state = b43_nphy_get_rx_core_state(dev);
@@ -1606,35 +1646,44 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1606 if (!(rx_core_state & (1 << core))) 1646 if (!(rx_core_state & (1 << core)))
1607 continue; 1647 continue;
1608 r = core ? B2056_RX1 : B2056_RX0; 1648 r = core ? B2056_RX1 : B2056_RX0;
1609 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, 2); 1649 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1610 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, 2); 1650 N_RSSI_NB);
1611 for (i = 0; i < 8; i++) { 1651 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1652 N_RSSI_NB);
1653
1654 /* Grab RSSI results for every possible VCM */
1655 for (vcm = 0; vcm < 8; vcm++) {
1612 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3, 1656 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1613 i << 2); 1657 vcm << 2);
1614 b43_nphy_poll_rssi(dev, 2, results[i], 8); 1658 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
1615 } 1659 }
1660
1661 /* Find out which VCM got the best results */
1616 for (i = 0; i < 4; i += 2) { 1662 for (i = 0; i < 4; i += 2) {
1617 s32 curr; 1663 s32 currd;
1618 s32 mind = 0x100000; 1664 s32 mind = 0x100000;
1619 s32 minpoll = 249; 1665 s32 minpoll = 249;
1620 u8 minvcm = 0; 1666 u8 minvcm = 0;
1621 if (2 * core != i) 1667 if (2 * core != i)
1622 continue; 1668 continue;
1623 for (j = 0; j < 8; j++) { 1669 for (vcm = 0; vcm < 8; vcm++) {
1624 curr = results[j][i] * results[j][i] + 1670 currd = results[vcm][i] * results[vcm][i] +
1625 results[j][i + 1] * results[j][i]; 1671 results[vcm][i + 1] * results[vcm][i];
1626 if (curr < mind) { 1672 if (currd < mind) {
1627 mind = curr; 1673 mind = currd;
1628 minvcm = j; 1674 minvcm = vcm;
1629 } 1675 }
1630 if (results[j][i] < minpoll) 1676 if (results[vcm][i] < minpoll)
1631 minpoll = results[j][i]; 1677 minpoll = results[vcm][i];
1632 } 1678 }
1633 vcm_final = minvcm; 1679 vcm_final = minvcm;
1634 results_min[i] = minpoll; 1680 results_min[i] = minpoll;
1635 } 1681 }
1682
1683 /* Select the best VCM */
1636 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3, 1684 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1637 vcm_final << 2); 1685 vcm_final << 2);
1686
1638 for (i = 0; i < 4; i++) { 1687 for (i = 0; i < 4; i++) {
1639 if (core != i / 2) 1688 if (core != i / 2)
1640 continue; 1689 continue;
@@ -1647,16 +1696,19 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1647 offset[i] = -32; 1696 offset[i] = -32;
1648 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1697 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1649 (i / 2 == 0) ? 1 : 2, 1698 (i / 2 == 0) ? 1 : 2,
1650 (i % 2 == 0) ? 0 : 1, 1699 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
1651 2); 1700 N_RSSI_NB);
1652 } 1701 }
1653 } 1702 }
1703
1654 for (core = 0; core < 2; core++) { 1704 for (core = 0; core < 2; core++) {
1655 if (!(rx_core_state & (1 << core))) 1705 if (!(rx_core_state & (1 << core)))
1656 continue; 1706 continue;
1657 for (i = 0; i < 2; i++) { 1707 for (i = 0; i < 2; i++) {
1658 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, i); 1708 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1659 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, i); 1709 N_RAIL_I, i);
1710 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1711 N_RAIL_Q, i);
1660 b43_nphy_poll_rssi(dev, i, poll_results, 8); 1712 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1661 for (j = 0; j < 4; j++) { 1713 for (j = 0; j < 4; j++) {
1662 if (j / 2 == core) { 1714 if (j / 2 == core) {
@@ -1696,8 +1748,13 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1696 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 1748 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1697 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 1749 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1698 } 1750 }
1699 rssical_radio_regs[0] = b43_radio_read(dev, 0x602B); 1751 if (dev->phy.rev >= 7) {
1700 rssical_radio_regs[0] = b43_radio_read(dev, 0x702B); 1752 } else {
1753 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1754 B2056_RX_RSSI_MISC);
1755 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1756 B2056_RX_RSSI_MISC);
1757 }
1701 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); 1758 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1702 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); 1759 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1703 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); 1760 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
@@ -1723,9 +1780,9 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1723} 1780}
1724 1781
1725/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ 1782/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1726static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) 1783static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
1727{ 1784{
1728 int i, j; 1785 int i, j, vcm;
1729 u8 state[4]; 1786 u8 state[4];
1730 u8 code, val; 1787 u8 code, val;
1731 u16 class, override; 1788 u16 class, override;
@@ -1743,10 +1800,10 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1743 s32 results[4][4] = { }; 1800 s32 results[4][4] = { };
1744 s32 miniq[4][2] = { }; 1801 s32 miniq[4][2] = { };
1745 1802
1746 if (type == 2) { 1803 if (type == N_RSSI_NB) {
1747 code = 0; 1804 code = 0;
1748 val = 6; 1805 val = 6;
1749 } else if (type < 2) { 1806 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
1750 code = 25; 1807 code = 25;
1751 val = 4; 1808 val = 4;
1752 } else { 1809 } else {
@@ -1765,63 +1822,63 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1765 override = 0x110; 1822 override = 0x110;
1766 1823
1767 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 1824 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1768 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); 1825 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
1769 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); 1826 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1770 b43_radio_write16(dev, B2055_C1_PD_RXTX, val); 1827 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
1771 1828
1772 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 1829 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1773 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); 1830 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
1774 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); 1831 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1775 b43_radio_write16(dev, B2055_C2_PD_RXTX, val); 1832 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
1776 1833
1777 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; 1834 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1778 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; 1835 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1779 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); 1836 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1780 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); 1837 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1781 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; 1838 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1782 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; 1839 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
1783 1840
1784 b43_nphy_rssi_select(dev, 5, type); 1841 b43_nphy_rssi_select(dev, 5, type);
1785 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); 1842 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1786 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); 1843 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
1787 1844
1788 for (i = 0; i < 4; i++) { 1845 for (vcm = 0; vcm < 4; vcm++) {
1789 u8 tmp[4]; 1846 u8 tmp[4];
1790 for (j = 0; j < 4; j++) 1847 for (j = 0; j < 4; j++)
1791 tmp[j] = i; 1848 tmp[j] = vcm;
1792 if (type != 1) 1849 if (type != N_RSSI_W2)
1793 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); 1850 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1794 b43_nphy_poll_rssi(dev, type, results[i], 8); 1851 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
1795 if (type < 2) 1852 if (type == N_RSSI_W1 || type == N_RSSI_W2)
1796 for (j = 0; j < 2; j++) 1853 for (j = 0; j < 2; j++)
1797 miniq[i][j] = min(results[i][2 * j], 1854 miniq[vcm][j] = min(results[vcm][2 * j],
1798 results[i][2 * j + 1]); 1855 results[vcm][2 * j + 1]);
1799 } 1856 }
1800 1857
1801 for (i = 0; i < 4; i++) { 1858 for (i = 0; i < 4; i++) {
1802 s32 mind = 0x100000; 1859 s32 mind = 0x100000;
1803 u8 minvcm = 0; 1860 u8 minvcm = 0;
1804 s32 minpoll = 249; 1861 s32 minpoll = 249;
1805 s32 curr; 1862 s32 currd;
1806 for (j = 0; j < 4; j++) { 1863 for (vcm = 0; vcm < 4; vcm++) {
1807 if (type == 2) 1864 if (type == N_RSSI_NB)
1808 curr = abs(results[j][i]); 1865 currd = abs(results[vcm][i] - code * 8);
1809 else 1866 else
1810 curr = abs(miniq[j][i / 2] - code * 8); 1867 currd = abs(miniq[vcm][i / 2] - code * 8);
1811 1868
1812 if (curr < mind) { 1869 if (currd < mind) {
1813 mind = curr; 1870 mind = currd;
1814 minvcm = j; 1871 minvcm = vcm;
1815 } 1872 }
1816 1873
1817 if (results[j][i] < minpoll) 1874 if (results[vcm][i] < minpoll)
1818 minpoll = results[j][i]; 1875 minpoll = results[vcm][i];
1819 } 1876 }
1820 results_min[i] = minpoll; 1877 results_min[i] = minpoll;
1821 vcm_final[i] = minvcm; 1878 vcm_final[i] = minvcm;
1822 } 1879 }
1823 1880
1824 if (type != 1) 1881 if (type != N_RSSI_W2)
1825 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); 1882 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1826 1883
1827 for (i = 0; i < 4; i++) { 1884 for (i = 0; i < 4; i++) {
@@ -1836,7 +1893,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1836 offset[i] = code - 32; 1893 offset[i] = code - 32;
1837 1894
1838 core = (i / 2) ? 2 : 1; 1895 core = (i / 2) ? 2 : 1;
1839 rail = (i % 2) ? 1 : 0; 1896 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
1840 1897
1841 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, 1898 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1842 type); 1899 type);
@@ -1847,37 +1904,37 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1847 1904
1848 switch (state[2]) { 1905 switch (state[2]) {
1849 case 1: 1906 case 1:
1850 b43_nphy_rssi_select(dev, 1, 2); 1907 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
1851 break; 1908 break;
1852 case 4: 1909 case 4:
1853 b43_nphy_rssi_select(dev, 1, 0); 1910 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
1854 break; 1911 break;
1855 case 2: 1912 case 2:
1856 b43_nphy_rssi_select(dev, 1, 1); 1913 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
1857 break; 1914 break;
1858 default: 1915 default:
1859 b43_nphy_rssi_select(dev, 1, 1); 1916 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
1860 break; 1917 break;
1861 } 1918 }
1862 1919
1863 switch (state[3]) { 1920 switch (state[3]) {
1864 case 1: 1921 case 1:
1865 b43_nphy_rssi_select(dev, 2, 2); 1922 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
1866 break; 1923 break;
1867 case 4: 1924 case 4:
1868 b43_nphy_rssi_select(dev, 2, 0); 1925 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
1869 break; 1926 break;
1870 default: 1927 default:
1871 b43_nphy_rssi_select(dev, 2, 1); 1928 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
1872 break; 1929 break;
1873 } 1930 }
1874 1931
1875 b43_nphy_rssi_select(dev, 0, type); 1932 b43_nphy_rssi_select(dev, 0, type);
1876 1933
1877 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); 1934 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1878 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); 1935 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1879 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); 1936 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1880 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); 1937 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1881 1938
1882 b43_nphy_classifier(dev, 7, class); 1939 b43_nphy_classifier(dev, 7, class);
1883 b43_nphy_write_clip_detection(dev, clip_state); 1940 b43_nphy_write_clip_detection(dev, clip_state);
@@ -1895,9 +1952,9 @@ static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1895 if (dev->phy.rev >= 3) { 1952 if (dev->phy.rev >= 3) {
1896 b43_nphy_rev3_rssi_cal(dev); 1953 b43_nphy_rev3_rssi_cal(dev);
1897 } else { 1954 } else {
1898 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z); 1955 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
1899 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X); 1956 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
1900 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y); 1957 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
1901 } 1958 }
1902} 1959}
1903 1960
@@ -1930,10 +1987,8 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1930 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); 1987 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1931 1988
1932 /* Set Clip 2 detect */ 1989 /* Set Clip 2 detect */
1933 b43_phy_set(dev, B43_NPHY_C1_CGAINI, 1990 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1934 B43_NPHY_C1_CGAINI_CL2DETECT); 1991 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1935 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1936 B43_NPHY_C2_CGAINI_CL2DETECT);
1937 1992
1938 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, 1993 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1939 0x17); 1994 0x17);
@@ -1967,22 +2022,22 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1967 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); 2022 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1968 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); 2023 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1969 2024
1970 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain); 2025 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
1971 b43_phy_write(dev, 0x2A7, e->init_gain); 2026 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2027
1972 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, 2028 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1973 e->rfseq_init); 2029 e->rfseq_init);
1974 2030
1975 /* TODO: check defines. Do not match variables names */ 2031 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
1976 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain); 2032 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
1977 b43_phy_write(dev, 0x2A9, e->cliphi_gain); 2033 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
1978 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain); 2034 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
1979 b43_phy_write(dev, 0x2AB, e->clipmd_gain); 2035 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
1980 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain); 2036 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
1981 b43_phy_write(dev, 0x2AD, e->cliplo_gain); 2037
1982 2038 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
1983 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin); 2039 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
1984 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl); 2040 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
1985 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1986 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); 2041 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1987 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); 2042 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1988 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 2043 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
@@ -2164,8 +2219,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2164 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); 2219 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2165 } 2220 }
2166 if (phy->rev <= 8) { 2221 if (phy->rev <= 8) {
2167 b43_phy_write(dev, 0x23F, 0x1B0); 2222 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2168 b43_phy_write(dev, 0x240, 0x1B0); 2223 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2169 } 2224 }
2170 if (phy->rev >= 8) 2225 if (phy->rev >= 8)
2171 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); 2226 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
@@ -2182,8 +2237,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2182 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, 2237 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2183 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); 2238 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2184 2239
2185 b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000); 2240 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2186 b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000); 2241 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2187 2242
2188 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154); 2243 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2189 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159); 2244 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
@@ -2260,11 +2315,11 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2260 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), 2315 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2261 rx2tx_lut_40_11n); 2316 rx2tx_lut_40_11n);
2262 } 2317 }
2263 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2); 2318 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
2264 } 2319 }
2265 b43_phy_write(dev, 0x32F, 0x3); 2320 b43_phy_write(dev, 0x32F, 0x3);
2266 if (phy->radio_rev == 4 || phy->radio_rev == 6) 2321 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2267 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0); 2322 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2268 2323
2269 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) { 2324 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2270 if (sprom->revision && 2325 if (sprom->revision &&
@@ -2450,8 +2505,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2450 u16 tmp16; 2505 u16 tmp16;
2451 u32 tmp32; 2506 u32 tmp32;
2452 2507
2453 b43_phy_write(dev, 0x23f, 0x1f8); 2508 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2454 b43_phy_write(dev, 0x240, 0x1f8); 2509 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
2455 2510
2456 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); 2511 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2457 tmp32 &= 0xffffff; 2512 tmp32 &= 0xffffff;
@@ -2464,8 +2519,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2464 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); 2519 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2465 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); 2520 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2466 2521
2467 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); 2522 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2468 b43_phy_write(dev, 0x2AE, 0x000C); 2523 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
2469 2524
2470 /* TX to RX */ 2525 /* TX to RX */
2471 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 2526 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
@@ -2490,7 +2545,7 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2490 0x2 : 0x9C40; 2545 0x2 : 0x9C40;
2491 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); 2546 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2492 2547
2493 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700); 2548 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
2494 2549
2495 if (!dev->phy.is_40mhz) { 2550 if (!dev->phy.is_40mhz) {
2496 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); 2551 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
@@ -2542,18 +2597,18 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2542 } 2597 }
2543 2598
2544 /* Dropped probably-always-true condition */ 2599 /* Dropped probably-always-true condition */
2545 b43_phy_write(dev, 0x224, 0x03eb); 2600 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2546 b43_phy_write(dev, 0x225, 0x03eb); 2601 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
2547 b43_phy_write(dev, 0x226, 0x0341); 2602 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2548 b43_phy_write(dev, 0x227, 0x0341); 2603 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2549 b43_phy_write(dev, 0x228, 0x042b); 2604 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2550 b43_phy_write(dev, 0x229, 0x042b); 2605 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2551 b43_phy_write(dev, 0x22a, 0x0381); 2606 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2552 b43_phy_write(dev, 0x22b, 0x0381); 2607 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2553 b43_phy_write(dev, 0x22c, 0x042b); 2608 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2554 b43_phy_write(dev, 0x22d, 0x042b); 2609 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2555 b43_phy_write(dev, 0x22e, 0x0381); 2610 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2556 b43_phy_write(dev, 0x22f, 0x0381); 2611 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
2557 2612
2558 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) 2613 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2559 ; /* TODO: 0x0080000000000000 HF */ 2614 ; /* TODO: 0x0080000000000000 HF */
@@ -2572,7 +2627,7 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2572 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; 2627 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2573 2628
2574 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || 2629 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2575 dev->dev->board_type == 0x8B) { 2630 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
2576 delays1[0] = 0x1; 2631 delays1[0] = 0x1;
2577 delays1[5] = 0x14; 2632 delays1[5] = 0x14;
2578 } 2633 }
@@ -3120,21 +3175,21 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3120 b43_nphy_ipa_internal_tssi_setup(dev); 3175 b43_nphy_ipa_internal_tssi_setup(dev);
3121 3176
3122 if (phy->rev >= 7) 3177 if (phy->rev >= 7)
3123 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0); 3178 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3124 else if (phy->rev >= 3) 3179 else if (phy->rev >= 3)
3125 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false); 3180 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3126 3181
3127 b43_nphy_stop_playback(dev); 3182 b43_nphy_stop_playback(dev);
3128 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false); 3183 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3129 udelay(20); 3184 udelay(20);
3130 tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1); 3185 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3131 b43_nphy_stop_playback(dev); 3186 b43_nphy_stop_playback(dev);
3132 b43_nphy_rssi_select(dev, 0, 0); 3187 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3133 3188
3134 if (phy->rev >= 7) 3189 if (phy->rev >= 7)
3135 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0); 3190 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3136 else if (phy->rev >= 3) 3191 else if (phy->rev >= 3)
3137 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true); 3192 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3138 3193
3139 if (phy->rev >= 3) { 3194 if (phy->rev >= 3) {
3140 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; 3195 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
@@ -3573,8 +3628,8 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3573 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); 3628 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3574 } 3629 }
3575 3630
3576 b43_nphy_rf_control_intc_override(dev, 2, 0, 3); 3631 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
3577 b43_nphy_rf_control_override(dev, 8, 0, 3, false); 3632 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
3578 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 3633 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3579 3634
3580 if (core == 0) { 3635 if (core == 0) {
@@ -3584,8 +3639,10 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3584 rxval = 4; 3639 rxval = 4;
3585 txval = 2; 3640 txval = 2;
3586 } 3641 }
3587 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1)); 3642 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3588 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core)); 3643 core + 1);
3644 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3645 2 - core);
3589} 3646}
3590#endif 3647#endif
3591 3648
@@ -3847,9 +3904,13 @@ static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3847 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 3904 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3848 } 3905 }
3849 3906
3850 /* TODO use some definitions */ 3907 if (dev->phy.rev >= 7) {
3851 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); 3908 } else {
3852 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); 3909 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
3910 rssical_radio_regs[0]);
3911 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
3912 rssical_radio_regs[1]);
3913 }
3853 3914
3854 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); 3915 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3855 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); 3916 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
@@ -3880,75 +3941,75 @@ static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3880 tmp = (i == 0) ? 0x2000 : 0x3000; 3941 tmp = (i == 0) ? 0x2000 : 0x3000;
3881 offset = i * 11; 3942 offset = i * 11;
3882 3943
3883 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); 3944 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
3884 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); 3945 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
3885 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); 3946 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
3886 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); 3947 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
3887 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); 3948 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
3888 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); 3949 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
3889 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); 3950 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
3890 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); 3951 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
3891 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); 3952 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
3892 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); 3953 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
3893 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); 3954 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
3894 3955
3895 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 3956 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3896 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); 3957 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3897 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 3958 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3898 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 3959 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
3899 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 3960 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
3900 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 3961 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
3901 if (nphy->ipa5g_on) { 3962 if (nphy->ipa5g_on) {
3902 b43_radio_write16(dev, tmp | B2055_PADDRV, 4); 3963 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
3903 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); 3964 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
3904 } else { 3965 } else {
3905 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 3966 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
3906 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); 3967 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
3907 } 3968 }
3908 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 3969 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
3909 } else { 3970 } else {
3910 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); 3971 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3911 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 3972 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3912 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 3973 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
3913 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 3974 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
3914 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 3975 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
3915 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); 3976 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
3916 if (nphy->ipa2g_on) { 3977 if (nphy->ipa2g_on) {
3917 b43_radio_write16(dev, tmp | B2055_PADDRV, 6); 3978 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
3918 b43_radio_write16(dev, tmp | B2055_XOCTL2, 3979 b43_radio_write(dev, tmp | B2055_XOCTL2,
3919 (dev->phy.rev < 5) ? 0x11 : 0x01); 3980 (dev->phy.rev < 5) ? 0x11 : 0x01);
3920 } else { 3981 } else {
3921 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 3982 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
3922 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 3983 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
3923 } 3984 }
3924 } 3985 }
3925 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); 3986 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
3926 b43_radio_write16(dev, tmp | B2055_XOMISC, 0); 3987 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
3927 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); 3988 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
3928 } 3989 }
3929 } else { 3990 } else {
3930 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); 3991 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
3931 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); 3992 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3932 3993
3933 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); 3994 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
3934 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); 3995 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3935 3996
3936 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); 3997 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
3937 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); 3998 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3938 3999
3939 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); 4000 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
3940 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); 4001 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3941 4002
3942 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); 4003 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
3943 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); 4004 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
3944 4005
3945 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & 4006 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3946 B43_NPHY_BANDCTL_5GHZ)) { 4007 B43_NPHY_BANDCTL_5GHZ)) {
3947 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); 4008 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
3948 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); 4009 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
3949 } else { 4010 } else {
3950 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); 4011 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
3951 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); 4012 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
3952 } 4013 }
3953 4014
3954 if (dev->phy.rev < 2) { 4015 if (dev->phy.rev < 2) {
@@ -4144,9 +4205,9 @@ static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4144 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 4205 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4145 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 4206 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4146 4207
4147 b43_nphy_rf_control_intc_override(dev, 2, 1, 3); 4208 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4148 b43_nphy_rf_control_intc_override(dev, 1, 2, 1); 4209 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4149 b43_nphy_rf_control_intc_override(dev, 1, 8, 2); 4210 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
4150 4211
4151 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 4212 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4152 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 4213 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
@@ -4679,7 +4740,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4679 4740
4680 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | 4741 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4681 (cur_lna << 2)); 4742 (cur_lna << 2));
4682 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, 4743 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
4683 false); 4744 false);
4684 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 4745 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4685 b43_nphy_stop_playback(dev); 4746 b43_nphy_stop_playback(dev);
@@ -4728,7 +4789,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4728 break; 4789 break;
4729 } 4790 }
4730 4791
4731 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); 4792 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
4732 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 4793 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4733 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 4794 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4734 4795
@@ -4797,18 +4858,6 @@ static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4797 * N-PHY init 4858 * N-PHY init
4798 **************************************************/ 4859 **************************************************/
4799 4860
4800/*
4801 * Upload the N-PHY tables.
4802 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
4803 */
4804static void b43_nphy_tables_init(struct b43_wldev *dev)
4805{
4806 if (dev->phy.rev < 3)
4807 b43_nphy_rev0_1_2_tables_init(dev);
4808 else
4809 b43_nphy_rev3plus_tables_init(dev);
4810}
4811
4812/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ 4861/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4813static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) 4862static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4814{ 4863{
@@ -4958,7 +5007,7 @@ static int b43_phy_initn(struct b43_wldev *dev)
4958 5007
4959 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || 5008 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
4960 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && 5009 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4961 dev->dev->board_type == 0x8B)) 5010 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
4962 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); 5011 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4963 else 5012 else
4964 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); 5013 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h
index 092c0140c249..9a5b6bc27d24 100644
--- a/drivers/net/wireless/b43/phy_n.h
+++ b/drivers/net/wireless/b43/phy_n.h
@@ -54,10 +54,15 @@
54#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7 54#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
55#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ 55#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
56#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */ 56#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
57#define B43_NPHY_REV3_C1_INITGAIN_A B43_PHY_N(0x020)
57#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */ 58#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
59#define B43_NPHY_REV3_C1_INITGAIN_B B43_PHY_N(0x021)
58#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */ 60#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
61#define B43_NPHY_REV3_C1_CLIP_HIGAIN_A B43_PHY_N(0x022)
59#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */ 62#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
63#define B43_NPHY_REV3_C1_CLIP_HIGAIN_B B43_PHY_N(0x023)
60#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */ 64#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */
65#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A B43_PHY_N(0x024)
61#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */ 66#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */
62#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */ 67#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
63#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */ 68#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
@@ -107,10 +112,15 @@
107#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7 112#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
108#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */ 113#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
109#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */ 114#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
115#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B B43_PHY_N(0x036)
110#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */ 116#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
117#define B43_NPHY_REV3_C1_CLIP_LOGAIN_A B43_PHY_N(0x037)
111#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */ 118#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
119#define B43_NPHY_REV3_C1_CLIP_LOGAIN_B B43_PHY_N(0x038)
112#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */ 120#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
121#define B43_NPHY_REV3_C1_CLIP2_GAIN_A B43_PHY_N(0x039)
113#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */ 122#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
123#define B43_NPHY_REV3_C1_CLIP2_GAIN_B B43_PHY_N(0x03A)
114#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */ 124#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */
115#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */ 125#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
116#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */ 126#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
@@ -706,10 +716,146 @@
706#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */ 716#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */
707#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ 717#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
708#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 718#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
719#define B43_NPHY_ED_CRSEN B43_PHY_N(0x223)
720#define B43_NPHY_ED_CRS40ASSERTTHRESH0 B43_PHY_N(0x224)
721#define B43_NPHY_ED_CRS40ASSERTTHRESH1 B43_PHY_N(0x225)
722#define B43_NPHY_ED_CRS40DEASSERTTHRESH0 B43_PHY_N(0x226)
723#define B43_NPHY_ED_CRS40DEASSERTTHRESH1 B43_PHY_N(0x227)
724#define B43_NPHY_ED_CRS20LASSERTTHRESH0 B43_PHY_N(0x228)
725#define B43_NPHY_ED_CRS20LASSERTTHRESH1 B43_PHY_N(0x229)
726#define B43_NPHY_ED_CRS20LDEASSERTTHRESH0 B43_PHY_N(0x22A)
727#define B43_NPHY_ED_CRS20LDEASSERTTHRESH1 B43_PHY_N(0x22B)
728#define B43_NPHY_ED_CRS20UASSERTTHRESH0 B43_PHY_N(0x22C)
729#define B43_NPHY_ED_CRS20UASSERTTHRESH1 B43_PHY_N(0x22D)
730#define B43_NPHY_ED_CRS20UDEASSERTTHRESH0 B43_PHY_N(0x22E)
731#define B43_NPHY_ED_CRS20UDEASSERTTHRESH1 B43_PHY_N(0x22F)
732#define B43_NPHY_ED_CRS B43_PHY_N(0x230)
733#define B43_NPHY_TIMEOUTEN B43_PHY_N(0x231)
734#define B43_NPHY_OFDMPAYDECODETIMEOUTLEN B43_PHY_N(0x232)
735#define B43_NPHY_CCKPAYDECODETIMEOUTLEN B43_PHY_N(0x233)
736#define B43_NPHY_NONPAYDECODETIMEOUTLEN B43_PHY_N(0x234)
737#define B43_NPHY_TIMEOUTSTATUS B43_PHY_N(0x235)
738#define B43_NPHY_RFCTRLCORE0GPIO0 B43_PHY_N(0x236)
739#define B43_NPHY_RFCTRLCORE0GPIO1 B43_PHY_N(0x237)
740#define B43_NPHY_RFCTRLCORE0GPIO2 B43_PHY_N(0x238)
741#define B43_NPHY_RFCTRLCORE0GPIO3 B43_PHY_N(0x239)
742#define B43_NPHY_RFCTRLCORE1GPIO0 B43_PHY_N(0x23A)
743#define B43_NPHY_RFCTRLCORE1GPIO1 B43_PHY_N(0x23B)
744#define B43_NPHY_RFCTRLCORE1GPIO2 B43_PHY_N(0x23C)
745#define B43_NPHY_RFCTRLCORE1GPIO3 B43_PHY_N(0x23D)
746#define B43_NPHY_BPHYTESTCONTROL B43_PHY_N(0x23E)
747/* REV3+ */
748#define B43_NPHY_FORCEFRONT0 B43_PHY_N(0x23F)
749#define B43_NPHY_FORCEFRONT1 B43_PHY_N(0x240)
750#define B43_NPHY_NORMVARHYSTTH B43_PHY_N(0x241)
751#define B43_NPHY_TXCCKERROR B43_PHY_N(0x242)
752#define B43_NPHY_AFESEQINITDACGAIN B43_PHY_N(0x243)
753#define B43_NPHY_TXANTSWLUT B43_PHY_N(0x244)
754#define B43_NPHY_CORECONFIG B43_PHY_N(0x245)
755#define B43_NPHY_ANTENNADIVDWELLTIME B43_PHY_N(0x246)
756#define B43_NPHY_ANTENNACCKDIVDWELLTIME B43_PHY_N(0x247)
757#define B43_NPHY_ANTENNADIVBACKOFFGAIN B43_PHY_N(0x248)
758#define B43_NPHY_ANTENNADIVMINGAIN B43_PHY_N(0x249)
759#define B43_NPHY_BRDSEL_NORMVARHYSTTH B43_PHY_N(0x24A)
760#define B43_NPHY_RXANTSWITCHCTRL B43_PHY_N(0x24B)
761#define B43_NPHY_ENERGYDROPTIMEOUTLEN2 B43_PHY_N(0x24C)
762#define B43_NPHY_ML_LOG_TXEVM0 B43_PHY_N(0x250)
763#define B43_NPHY_ML_LOG_TXEVM1 B43_PHY_N(0x251)
764#define B43_NPHY_ML_LOG_TXEVM2 B43_PHY_N(0x252)
765#define B43_NPHY_ML_LOG_TXEVM3 B43_PHY_N(0x253)
766#define B43_NPHY_ML_LOG_TXEVM4 B43_PHY_N(0x254)
767#define B43_NPHY_ML_LOG_TXEVM5 B43_PHY_N(0x255)
768#define B43_NPHY_ML_LOG_TXEVM6 B43_PHY_N(0x256)
769#define B43_NPHY_ML_LOG_TXEVM7 B43_PHY_N(0x257)
770#define B43_NPHY_ML_SCALE_TWEAK B43_PHY_N(0x258)
771#define B43_NPHY_MLUA B43_PHY_N(0x259)
772#define B43_NPHY_ZFUA B43_PHY_N(0x25A)
773#define B43_NPHY_CHANUPSYM01 B43_PHY_N(0x25B)
774#define B43_NPHY_CHANUPSYM2 B43_PHY_N(0x25C)
775#define B43_NPHY_RXSTRNFILT20NUM00 B43_PHY_N(0x25D)
776#define B43_NPHY_RXSTRNFILT20NUM01 B43_PHY_N(0x25E)
777#define B43_NPHY_RXSTRNFILT20NUM02 B43_PHY_N(0x25F)
778#define B43_NPHY_RXSTRNFILT20DEN00 B43_PHY_N(0x260)
779#define B43_NPHY_RXSTRNFILT20DEN01 B43_PHY_N(0x261)
780#define B43_NPHY_RXSTRNFILT20NUM10 B43_PHY_N(0x262)
781#define B43_NPHY_RXSTRNFILT20NUM11 B43_PHY_N(0x263)
782#define B43_NPHY_RXSTRNFILT20NUM12 B43_PHY_N(0x264)
783#define B43_NPHY_RXSTRNFILT20DEN10 B43_PHY_N(0x265)
784#define B43_NPHY_RXSTRNFILT20DEN11 B43_PHY_N(0x266)
785#define B43_NPHY_RXSTRNFILT40NUM00 B43_PHY_N(0x267)
786#define B43_NPHY_RXSTRNFILT40NUM01 B43_PHY_N(0x268)
787#define B43_NPHY_RXSTRNFILT40NUM02 B43_PHY_N(0x269)
788#define B43_NPHY_RXSTRNFILT40DEN00 B43_PHY_N(0x26A)
789#define B43_NPHY_RXSTRNFILT40DEN01 B43_PHY_N(0x26B)
790#define B43_NPHY_RXSTRNFILT40NUM10 B43_PHY_N(0x26C)
791#define B43_NPHY_RXSTRNFILT40NUM11 B43_PHY_N(0x26D)
792#define B43_NPHY_RXSTRNFILT40NUM12 B43_PHY_N(0x26E)
793#define B43_NPHY_RXSTRNFILT40DEN10 B43_PHY_N(0x26F)
794#define B43_NPHY_RXSTRNFILT40DEN11 B43_PHY_N(0x270)
795#define B43_NPHY_CRSHIGHPOWTHRESHOLD1 B43_PHY_N(0x271)
796#define B43_NPHY_CRSHIGHPOWTHRESHOLD2 B43_PHY_N(0x272)
797#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD B43_PHY_N(0x273)
798#define B43_NPHY_CRSHIGHPOWTHRESHOLD1L B43_PHY_N(0x274)
799#define B43_NPHY_CRSHIGHPOWTHRESHOLD2L B43_PHY_N(0x275)
800#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL B43_PHY_N(0x276)
801#define B43_NPHY_CRSHIGHPOWTHRESHOLD1U B43_PHY_N(0x277)
802#define B43_NPHY_CRSHIGHPOWTHRESHOLD2U B43_PHY_N(0x278)
803#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU B43_PHY_N(0x279)
804#define B43_NPHY_CRSACIDETECTTHRESH B43_PHY_N(0x27A)
805#define B43_NPHY_CRSACIDETECTTHRESHL B43_PHY_N(0x27B)
806#define B43_NPHY_CRSACIDETECTTHRESHU B43_PHY_N(0x27C)
807#define B43_NPHY_CRSMINPOWER0 B43_PHY_N(0x27D)
808#define B43_NPHY_CRSMINPOWER1 B43_PHY_N(0x27E)
809#define B43_NPHY_CRSMINPOWER2 B43_PHY_N(0x27F)
810#define B43_NPHY_CRSMINPOWERL0 B43_PHY_N(0x280)
811#define B43_NPHY_CRSMINPOWERL1 B43_PHY_N(0x281)
812#define B43_NPHY_CRSMINPOWERL2 B43_PHY_N(0x282)
813#define B43_NPHY_CRSMINPOWERU0 B43_PHY_N(0x283)
814#define B43_NPHY_CRSMINPOWERU1 B43_PHY_N(0x284)
815#define B43_NPHY_CRSMINPOWERU2 B43_PHY_N(0x285)
816#define B43_NPHY_STRPARAM B43_PHY_N(0x286)
817#define B43_NPHY_STRPARAML B43_PHY_N(0x287)
818#define B43_NPHY_STRPARAMU B43_PHY_N(0x288)
819#define B43_NPHY_BPHYCRSMINPOWER0 B43_PHY_N(0x289)
820#define B43_NPHY_BPHYCRSMINPOWER1 B43_PHY_N(0x28A)
821#define B43_NPHY_BPHYCRSMINPOWER2 B43_PHY_N(0x28B)
822#define B43_NPHY_BPHYFILTDEN0COEF B43_PHY_N(0x28C)
823#define B43_NPHY_BPHYFILTDEN1COEF B43_PHY_N(0x28D)
824#define B43_NPHY_BPHYFILTDEN2COEF B43_PHY_N(0x28E)
825#define B43_NPHY_BPHYFILTNUM0COEF B43_PHY_N(0x28F)
826#define B43_NPHY_BPHYFILTNUM1COEF B43_PHY_N(0x290)
827#define B43_NPHY_BPHYFILTNUM2COEF B43_PHY_N(0x291)
828#define B43_NPHY_BPHYFILTNUM01COEF2 B43_PHY_N(0x292)
829#define B43_NPHY_BPHYFILTBYPASS B43_PHY_N(0x293)
830#define B43_NPHY_SGILTRNOFFSET B43_PHY_N(0x294)
831#define B43_NPHY_RADAR_T2_MIN B43_PHY_N(0x295)
832#define B43_NPHY_TXPWRCTRLDAMPING B43_PHY_N(0x296)
709#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */ 833#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */
710#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */ 834#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */
835#define B43_NPHY_EPS_OVERRIDEI_0 B43_PHY_N(0x299)
836#define B43_NPHY_EPS_OVERRIDEQ_0 B43_PHY_N(0x29A)
711#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */ 837#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */
712#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */ 838#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */
839#define B43_NPHY_EPS_OVERRIDEI_1 B43_PHY_N(0x29D)
840#define B43_NPHY_EPS_OVERRIDEQ_1 B43_PHY_N(0x29E)
841#define B43_NPHY_PAPD_CAL_ADDRESS B43_PHY_N(0x29F)
842#define B43_NPHY_PAPD_CAL_YREFEPSILON B43_PHY_N(0x2A0)
843#define B43_NPHY_PAPD_CAL_SETTLE B43_PHY_N(0x2A1)
844#define B43_NPHY_PAPD_CAL_CORRELATE B43_PHY_N(0x2A2)
845#define B43_NPHY_PAPD_CAL_SHIFTS0 B43_PHY_N(0x2A3)
846#define B43_NPHY_PAPD_CAL_SHIFTS1 B43_PHY_N(0x2A4)
847#define B43_NPHY_SAMPLE_START_ADDR B43_PHY_N(0x2A5)
848#define B43_NPHY_RADAR_ADC_TO_DBM B43_PHY_N(0x2A6)
849#define B43_NPHY_REV3_C2_INITGAIN_A B43_PHY_N(0x2A7)
850#define B43_NPHY_REV3_C2_INITGAIN_B B43_PHY_N(0x2A8)
851#define B43_NPHY_REV3_C2_CLIP_HIGAIN_A B43_PHY_N(0x2A9)
852#define B43_NPHY_REV3_C2_CLIP_HIGAIN_B B43_PHY_N(0x2AA)
853#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A B43_PHY_N(0x2AB)
854#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B B43_PHY_N(0x2AC)
855#define B43_NPHY_REV3_C2_CLIP_LOGAIN_A B43_PHY_N(0x2AD)
856#define B43_NPHY_REV3_C2_CLIP_LOGAIN_B B43_PHY_N(0x2AE)
857#define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF)
858#define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0)
713 859
714#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */ 860#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */
715#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A) 861#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A)
diff --git a/drivers/net/wireless/b43/radio_2059.c b/drivers/net/wireless/b43/radio_2059.c
index d4ce8a12ff9a..38e31d857e3e 100644
--- a/drivers/net/wireless/b43/radio_2059.c
+++ b/drivers/net/wireless/b43/radio_2059.c
@@ -27,7 +27,7 @@
27 27
28#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ 28#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
29 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ 29 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
30 r20, r21, r22, r23, r24, r25, r26, r27, r28) \ 30 r20) \
31 .radio_syn16 = r00, \ 31 .radio_syn16 = r00, \
32 .radio_syn17 = r01, \ 32 .radio_syn17 = r01, \
33 .radio_syn22 = r02, \ 33 .radio_syn22 = r02, \
@@ -41,22 +41,14 @@
41 .radio_syn41 = r10, \ 41 .radio_syn41 = r10, \
42 .radio_syn43 = r11, \ 42 .radio_syn43 = r11, \
43 .radio_syn47 = r12, \ 43 .radio_syn47 = r12, \
44 .radio_syn4a = r13, \ 44 .radio_rxtx4a = r13, \
45 .radio_syn58 = r14, \ 45 .radio_rxtx58 = r14, \
46 .radio_syn5a = r15, \ 46 .radio_rxtx5a = r15, \
47 .radio_syn6a = r16, \ 47 .radio_rxtx6a = r16, \
48 .radio_syn6d = r17, \ 48 .radio_rxtx6d = r17, \
49 .radio_syn6e = r18, \ 49 .radio_rxtx6e = r18, \
50 .radio_syn92 = r19, \ 50 .radio_rxtx92 = r19, \
51 .radio_syn98 = r20, \ 51 .radio_rxtx98 = r20
52 .radio_rxtx4a = r21, \
53 .radio_rxtx58 = r22, \
54 .radio_rxtx5a = r23, \
55 .radio_rxtx6a = r24, \
56 .radio_rxtx6d = r25, \
57 .radio_rxtx6e = r26, \
58 .radio_rxtx92 = r27, \
59 .radio_rxtx98 = r28
60 52
61#define PHYREGS(r0, r1, r2, r3, r4, r5) \ 53#define PHYREGS(r0, r1, r2, r3, r4, r5) \
62 .phy_regs.bw1 = r0, \ 54 .phy_regs.bw1 = r0, \
@@ -70,91 +62,78 @@ static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radi
70 { .freq = 2412, 62 { .freq = 2412,
71 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 63 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
72 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03, 64 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
73 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
74 0x00, 0x00, 0x00, 0xf0, 0x00), 65 0x00, 0x00, 0x00, 0xf0, 0x00),
75 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), 66 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
76 }, 67 },
77 { .freq = 2417, 68 { .freq = 2417,
78 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 69 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
79 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03, 70 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
80 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
81 0x00, 0x00, 0x00, 0xf0, 0x00), 71 0x00, 0x00, 0x00, 0xf0, 0x00),
82 PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), 72 PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
83 }, 73 },
84 { .freq = 2422, 74 { .freq = 2422,
85 RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 75 RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
86 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03, 76 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
87 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
88 0x00, 0x00, 0x00, 0xf0, 0x00), 77 0x00, 0x00, 0x00, 0xf0, 0x00),
89 PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), 78 PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
90 }, 79 },
91 { .freq = 2427, 80 { .freq = 2427,
92 RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 81 RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
93 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03, 82 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
94 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
95 0x00, 0x00, 0x00, 0xf0, 0x00), 83 0x00, 0x00, 0x00, 0xf0, 0x00),
96 PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), 84 PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
97 }, 85 },
98 { .freq = 2432, 86 { .freq = 2432,
99 RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 87 RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
100 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03, 88 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
101 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
102 0x00, 0x00, 0x00, 0xf0, 0x00), 89 0x00, 0x00, 0x00, 0xf0, 0x00),
103 PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), 90 PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
104 }, 91 },
105 { .freq = 2437, 92 { .freq = 2437,
106 RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 93 RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
107 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03, 94 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
108 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
109 0x00, 0x00, 0x00, 0xf0, 0x00), 95 0x00, 0x00, 0x00, 0xf0, 0x00),
110 PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), 96 PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
111 }, 97 },
112 { .freq = 2442, 98 { .freq = 2442,
113 RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 99 RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
114 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 100 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
115 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
116 0x00, 0x00, 0x00, 0xf0, 0x00), 101 0x00, 0x00, 0x00, 0xf0, 0x00),
117 PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), 102 PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
118 }, 103 },
119 { .freq = 2447, 104 { .freq = 2447,
120 RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 105 RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
121 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 106 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
122 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
123 0x00, 0x00, 0x00, 0xf0, 0x00), 107 0x00, 0x00, 0x00, 0xf0, 0x00),
124 PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), 108 PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
125 }, 109 },
126 { .freq = 2452, 110 { .freq = 2452,
127 RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 111 RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
128 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 112 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
129 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
130 0x00, 0x00, 0x00, 0xf0, 0x00), 113 0x00, 0x00, 0x00, 0xf0, 0x00),
131 PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), 114 PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
132 }, 115 },
133 { .freq = 2457, 116 { .freq = 2457,
134 RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 117 RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
135 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03, 118 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
136 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
137 0x00, 0x00, 0x00, 0xf0, 0x00), 119 0x00, 0x00, 0x00, 0xf0, 0x00),
138 PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), 120 PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
139 }, 121 },
140 { .freq = 2462, 122 { .freq = 2462,
141 RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 123 RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
142 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03, 124 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
143 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
144 0x00, 0x00, 0x00, 0xf0, 0x00), 125 0x00, 0x00, 0x00, 0xf0, 0x00),
145 PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), 126 PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
146 }, 127 },
147 { .freq = 2467, 128 { .freq = 2467,
148 RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 129 RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3,
149 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03, 130 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
150 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
151 0x00, 0x00, 0x00, 0xf0, 0x00), 131 0x00, 0x00, 0x00, 0xf0, 0x00),
152 PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), 132 PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
153 }, 133 },
154 { .freq = 2472, 134 { .freq = 2472,
155 RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 135 RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8,
156 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03, 136 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
157 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
158 0x00, 0x00, 0x00, 0xf0, 0x00), 137 0x00, 0x00, 0x00, 0xf0, 0x00),
159 PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), 138 PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
160 }, 139 },
diff --git a/drivers/net/wireless/b43/radio_2059.h b/drivers/net/wireless/b43/radio_2059.h
index e4d69e55e9fe..40a82d7f510c 100644
--- a/drivers/net/wireless/b43/radio_2059.h
+++ b/drivers/net/wireless/b43/radio_2059.h
@@ -5,9 +5,9 @@
5 5
6#include "phy_ht.h" 6#include "phy_ht.h"
7 7
8#define R2059_SYN 0x000 8#define R2059_C1 0x000
9#define R2059_TXRX0 0x400 9#define R2059_C2 0x400
10#define R2059_RXRX1 0x800 10#define R2059_C3 0x800
11#define R2059_ALL 0xC00 11#define R2059_ALL 0xC00
12 12
13/* Values for various registers uploaded on channel switching */ 13/* Values for various registers uploaded on channel switching */
@@ -28,14 +28,6 @@ struct b43_phy_ht_channeltab_e_radio2059 {
28 u8 radio_syn41; 28 u8 radio_syn41;
29 u8 radio_syn43; 29 u8 radio_syn43;
30 u8 radio_syn47; 30 u8 radio_syn47;
31 u8 radio_syn4a;
32 u8 radio_syn58;
33 u8 radio_syn5a;
34 u8 radio_syn6a;
35 u8 radio_syn6d;
36 u8 radio_syn6e;
37 u8 radio_syn92;
38 u8 radio_syn98;
39 u8 radio_rxtx4a; 31 u8 radio_rxtx4a;
40 u8 radio_rxtx58; 32 u8 radio_rxtx58;
41 u8 radio_rxtx5a; 33 u8 radio_rxtx5a;
diff --git a/drivers/net/wireless/b43/tables_nphy.c b/drivers/net/wireless/b43/tables_nphy.c
index 110510d53958..94c755fdda14 100644
--- a/drivers/net/wireless/b43/tables_nphy.c
+++ b/drivers/net/wireless/b43/tables_nphy.c
@@ -2174,7 +2174,7 @@ static const u16 b43_ntab_loftlt1_r3[] = {
2174/* volatile tables, PHY revision >= 3 */ 2174/* volatile tables, PHY revision >= 3 */
2175 2175
2176/* indexed by antswctl2g */ 2176/* indexed by antswctl2g */
2177static const u16 b43_ntab_antswctl2g_r3[4][32] = { 2177static const u16 b43_ntab_antswctl_r3[4][32] = {
2178 { 2178 {
2179 0x0082, 0x0082, 0x0211, 0x0222, 0x0328, 2179 0x0082, 0x0082, 0x0211, 0x0222, 0x0328,
2180 0x0000, 0x0000, 0x0000, 0x0144, 0x0000, 2180 0x0000, 0x0000, 0x0000, 0x0144, 0x0000,
@@ -3095,9 +3095,55 @@ void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
3095} 3095}
3096 3096
3097#define ntab_upload(dev, offset, data) do { \ 3097#define ntab_upload(dev, offset, data) do { \
3098 b43_ntab_write_bulk(dev, offset, offset##_SIZE, data); \ 3098 b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
3099 } while (0) 3099 } while (0)
3100void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev) 3100
3101static void b43_nphy_tables_init_rev3(struct b43_wldev *dev)
3102{
3103 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3104 u8 antswlut;
3105
3106 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3107 antswlut = sprom->fem.ghz5.antswlut;
3108 else
3109 antswlut = sprom->fem.ghz2.antswlut;
3110
3111 /* Static tables */
3112 ntab_upload(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
3113 ntab_upload(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
3114 ntab_upload(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
3115 ntab_upload(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
3116 ntab_upload(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
3117 ntab_upload(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
3118 ntab_upload(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
3119 ntab_upload(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
3120 ntab_upload(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
3121 ntab_upload(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
3122 ntab_upload(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
3123 ntab_upload(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
3124 ntab_upload(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
3125 ntab_upload(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
3126 ntab_upload(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
3127 ntab_upload(dev, B43_NTAB_C0_ESTPLT_R3, b43_ntab_estimatepowerlt0_r3);
3128 ntab_upload(dev, B43_NTAB_C1_ESTPLT_R3, b43_ntab_estimatepowerlt1_r3);
3129 ntab_upload(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
3130 ntab_upload(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
3131 ntab_upload(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
3132 ntab_upload(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
3133 ntab_upload(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
3134 ntab_upload(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
3135 ntab_upload(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
3136 ntab_upload(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
3137
3138 /* Volatile tables */
3139 if (antswlut < ARRAY_SIZE(b43_ntab_antswctl_r3))
3140 ntab_upload(dev, B43_NTAB_ANT_SW_CTL_R3,
3141 b43_ntab_antswctl_r3[antswlut]);
3142 else
3143 B43_WARN_ON(1);
3144}
3145
3146static void b43_nphy_tables_init_rev0(struct b43_wldev *dev)
3101{ 3147{
3102 /* Static tables */ 3148 /* Static tables */
3103 ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct); 3149 ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
@@ -3130,48 +3176,13 @@ void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
3130 ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1); 3176 ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
3131} 3177}
3132 3178
3133#define ntab_upload_r3(dev, offset, data) do { \ 3179/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables */
3134 b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \ 3180void b43_nphy_tables_init(struct b43_wldev *dev)
3135 } while (0)
3136void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev)
3137{ 3181{
3138 struct ssb_sprom *sprom = dev->dev->bus_sprom; 3182 if (dev->phy.rev >= 3)
3139 3183 b43_nphy_tables_init_rev3(dev);
3140 /* Static tables */
3141 ntab_upload_r3(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
3142 ntab_upload_r3(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
3143 ntab_upload_r3(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
3144 ntab_upload_r3(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
3145 ntab_upload_r3(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
3146 ntab_upload_r3(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
3147 ntab_upload_r3(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
3148 ntab_upload_r3(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
3149 ntab_upload_r3(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
3150 ntab_upload_r3(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
3151 ntab_upload_r3(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
3152 ntab_upload_r3(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
3153 ntab_upload_r3(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
3154 ntab_upload_r3(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
3155 ntab_upload_r3(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
3156 ntab_upload_r3(dev, B43_NTAB_C0_ESTPLT_R3,
3157 b43_ntab_estimatepowerlt0_r3);
3158 ntab_upload_r3(dev, B43_NTAB_C1_ESTPLT_R3,
3159 b43_ntab_estimatepowerlt1_r3);
3160 ntab_upload_r3(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
3161 ntab_upload_r3(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
3162 ntab_upload_r3(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
3163 ntab_upload_r3(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
3164 ntab_upload_r3(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
3165 ntab_upload_r3(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
3166 ntab_upload_r3(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
3167 ntab_upload_r3(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
3168
3169 /* Volatile tables */
3170 if (sprom->fem.ghz2.antswlut < ARRAY_SIZE(b43_ntab_antswctl2g_r3))
3171 ntab_upload_r3(dev, B43_NTAB_ANT_SW_CTL_R3,
3172 b43_ntab_antswctl2g_r3[sprom->fem.ghz2.antswlut]);
3173 else 3184 else
3174 B43_WARN_ON(1); 3185 b43_nphy_tables_init_rev0(dev);
3175} 3186}
3176 3187
3177/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ 3188/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
diff --git a/drivers/net/wireless/b43/tables_nphy.h b/drivers/net/wireless/b43/tables_nphy.h
index c600700ceedc..9ff33adcff89 100644
--- a/drivers/net/wireless/b43/tables_nphy.h
+++ b/drivers/net/wireless/b43/tables_nphy.h
@@ -115,22 +115,22 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
115#define B43_NTAB_NOISEVAR11_SIZE 256 115#define B43_NTAB_NOISEVAR11_SIZE 256
116#define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */ 116#define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
117#define B43_NTAB_C0_ESTPLT_SIZE 64 117#define B43_NTAB_C0_ESTPLT_SIZE 64
118#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
119#define B43_NTAB_C1_ESTPLT_SIZE 64
120#define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */ 118#define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
121#define B43_NTAB_C0_ADJPLT_SIZE 128 119#define B43_NTAB_C0_ADJPLT_SIZE 128
122#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
123#define B43_NTAB_C1_ADJPLT_SIZE 128
124#define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */ 120#define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
125#define B43_NTAB_C0_GAINCTL_SIZE 128 121#define B43_NTAB_C0_GAINCTL_SIZE 128
126#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
127#define B43_NTAB_C1_GAINCTL_SIZE 128
128#define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */ 122#define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
129#define B43_NTAB_C0_IQLT_SIZE 128 123#define B43_NTAB_C0_IQLT_SIZE 128
130#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
131#define B43_NTAB_C1_IQLT_SIZE 128
132#define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */ 124#define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
133#define B43_NTAB_C0_LOFEEDTH_SIZE 128 125#define B43_NTAB_C0_LOFEEDTH_SIZE 128
126#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
127#define B43_NTAB_C1_ESTPLT_SIZE 64
128#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
129#define B43_NTAB_C1_ADJPLT_SIZE 128
130#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
131#define B43_NTAB_C1_GAINCTL_SIZE 128
132#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
133#define B43_NTAB_C1_IQLT_SIZE 128
134#define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */ 134#define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
135#define B43_NTAB_C1_LOFEEDTH_SIZE 128 135#define B43_NTAB_C1_LOFEEDTH_SIZE 128
136 136
@@ -154,15 +154,17 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
154#define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */ 154#define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */
155#define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */ 155#define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */
156#define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */ 156#define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */
157#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
158#define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */ 157#define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */
159#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
160#define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */ 158#define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */
161#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
162#define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */ 159#define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */
163#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
164#define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */ 160#define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */
161#define B43_NTAB_C0_PAPD_COMP_R3 B43_NTAB16(26, 576)
162#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
163#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
164#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
165#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
165#define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */ 166#define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */
167#define B43_NTAB_C1_PAPD_COMP_R3 B43_NTAB16(27, 576)
166 168
167#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18 169#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18
168#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18 170#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18
@@ -182,8 +184,7 @@ void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value);
182void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset, 184void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
183 unsigned int nr_elements, const void *_data); 185 unsigned int nr_elements, const void *_data);
184 186
185void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev); 187void b43_nphy_tables_init(struct b43_wldev *dev);
186void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
187 188
188const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev); 189const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev);
189 190
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 07:44:38 -0400