19 files changed, 102 insertions, 53 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 4cf678306c9c..a9338c85630f 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -209,6 +209,16 @@ static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
+static const u32 vga_control_regs[6] =
+{
+        AVIVO_D1VGA_CONTROL,
+        AVIVO_D2VGA_CONTROL,
+        EVERGREEN_D3VGA_CONTROL,
+        EVERGREEN_D4VGA_CONTROL,
+        EVERGREEN_D5VGA_CONTROL,
+        EVERGREEN_D6VGA_CONTROL,
+};
+
 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 {
         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -216,13 +226,23 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
         struct radeon_device *rdev = dev->dev_private;
         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
         BLANK_CRTC_PS_ALLOCATION args;
+        u32 vga_control = 0;
 
         memset(&args, 0, sizeof(args));
 
+        if (ASIC_IS_DCE8(rdev)) {
+                vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
+                WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
+        }
+
         args.ucCRTC = radeon_crtc->crtc_id;
         args.ucBlanking = state;
 
         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+        if (ASIC_IS_DCE8(rdev)) {
+                WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
+        }
 }
 
 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 6ffe824624fb..e6419ca7cd37 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3840,6 +3840,8 @@ static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
         if (enable)
                 WREG32(CP_ME_CNTL, 0);
         else {
+                if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
         }
@@ -4038,6 +4040,10 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
                 return r;
         }
+
+        if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 9abea87a9213..1ecb3f1070e3 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -250,7 +250,9 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev)
         u32 rb_cntl, reg_offset;
         int i;
 
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+        if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
+            (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 
         for (i = 0; i < 2; i++) {
                 if (i == 0)
@@ -381,7 +383,9 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev)
                 }
         }
 
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+        if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
+            (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4116d0279596..f2b9e21ce4da 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4348,8 +4348,8 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
         }
 
-        /* only one DAC on DCE6 */
-        if (!ASIC_IS_DCE6(rdev))
+        /* only one DAC on DCE5 */
+        if (!ASIC_IS_DCE5(rdev))
                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
 
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 647b1d0fa62c..ea932ac66fc6 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1390,7 +1390,8 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
         if (enable)
                 WREG32(CP_ME_CNTL, 0);
         else {
-                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+                if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
                 WREG32(SCRATCH_UMSK, 0);
                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
@@ -1663,6 +1664,9 @@ static int cayman_cp_resume(struct radeon_device *rdev)
                 return r;
         }
 
+        if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c
index 51424ab79432..7cf96b15377f 100644
--- a/drivers/gpu/drm/radeon/ni_dma.c
+++ b/drivers/gpu/drm/radeon/ni_dma.c
@@ -157,7 +157,9 @@ void cayman_dma_stop(struct radeon_device *rdev)
 {
         u32 rb_cntl;
 
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+        if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
+            (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 
         /* dma0 */
         rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
@@ -259,7 +261,9 @@ int cayman_dma_resume(struct radeon_device *rdev)
                 }
         }
 
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+        if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
+            (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 3dce370adc1b..56140b4e5bb2 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2254,7 +2254,8 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  */
 void r600_cp_stop(struct radeon_device *rdev)
 {
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+        if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
         WREG32(SCRATCH_UMSK, 0);
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
@@ -2612,6 +2613,10 @@ int r600_cp_resume(struct radeon_device *rdev)
                 ring->ready = false;
                 return r;
         }
+
+        if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+
         return 0;
 }
 
@@ -2895,12 +2900,6 @@ static int r600_startup(struct radeon_device *rdev)
                 return r;
         }
 
-        r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
-        if (r) {
-                dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
-                return r;
-        }
-
         /* Enable IRQ */
         if (!rdev->irq.installed) {
                 r = radeon_irq_kms_init(rdev);
@@ -2922,12 +2921,6 @@ static int r600_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
-        r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-                             DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
-        if (r)
-                return r;
-
         r = r600_cp_load_microcode(rdev);
         if (r)
                 return r;
@@ -2935,10 +2928,6 @@ static int r600_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = r600_dma_resume(rdev);
-        if (r)
-                return r;
-
         r = radeon_ib_pool_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -2997,7 +2986,6 @@ int r600_suspend(struct radeon_device *rdev)
         radeon_pm_suspend(rdev);
         r600_audio_fini(rdev);
         r600_cp_stop(rdev);
-        r600_dma_stop(rdev);
         r600_irq_suspend(rdev);
         radeon_wb_disable(rdev);
         r600_pcie_gart_disable(rdev);
@@ -3077,9 +3065,6 @@ int r600_init(struct radeon_device *rdev)
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
-        rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
-        r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
-
         rdev->ih.ring_obj = NULL;
         r600_ih_ring_init(rdev, 64 * 1024);
 
@@ -3092,7 +3077,6 @@ int r600_init(struct radeon_device *rdev)
         if (r) {
                 dev_err(rdev->dev, "disabling GPU acceleration\n");
                 r600_cp_fini(rdev);
-                r600_dma_fini(rdev);
                 r600_irq_fini(rdev);
                 radeon_wb_fini(rdev);
                 radeon_ib_pool_fini(rdev);
@@ -3109,7 +3093,6 @@ void r600_fini(struct radeon_device *rdev)
         radeon_pm_fini(rdev);
         r600_audio_fini(rdev);
         r600_cp_fini(rdev);
-        r600_dma_fini(rdev);
         r600_irq_fini(rdev);
         radeon_wb_fini(rdev);
         radeon_ib_pool_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c
index 3452c8410bd7..b2d4c91e6272 100644
--- a/drivers/gpu/drm/radeon/r600_dma.c
+++ b/drivers/gpu/drm/radeon/r600_dma.c
@@ -100,7 +100,8 @@ void r600_dma_stop(struct radeon_device *rdev)
 {
         u32 rb_cntl = RREG32(DMA_RB_CNTL);
 
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+        if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 
         rb_cntl &= ~DMA_RB_ENABLE;
         WREG32(DMA_RB_CNTL, rb_cntl);
@@ -187,7 +188,8 @@ int r600_dma_resume(struct radeon_device *rdev)
                 return r;
         }
 
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+        if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index c5519ca4bbc4..4a8ac1cd6b4c 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -867,6 +867,8 @@ struct radeon_vm {
         struct radeon_fence             *fence;
         /* last flush or NULL if we still need to flush */
         struct radeon_fence             *last_flush;
+        /* last use of vmid */
+        struct radeon_fence             *last_id_use;
 };
 
 struct radeon_vm_manager {
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index f48bd6dc10cd..30844814c25a 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -3938,6 +3938,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
         /* tell the bios not to handle mode switching */
         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
 
+        /* clear the vbios dpms state */
+        if (ASIC_IS_DCE4(rdev))
+                bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
+
         if (rdev->family >= CHIP_R600) {
                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index a8e3342fd4a9..dfb5a1db87d4 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -138,7 +138,7 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
                                 p->ring = R600_RING_TYPE_DMA_INDEX;
                         else
                                 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
-                } else if (p->rdev->family >= CHIP_R600) {
+                } else if (p->rdev->family >= CHIP_RV770) {
                         p->ring = R600_RING_TYPE_DMA_INDEX;
                 } else {
                         return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 1235a78fbba1..ec8c388eec17 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -405,6 +405,9 @@ static int radeon_pmops_runtime_suspend(struct device *dev)
         if (radeon_runtime_pm == 0)
                 return -EINVAL;
 
+        if (radeon_runtime_pm == -1 && !radeon_is_px())
+                return -EINVAL;
+
         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
         drm_kms_helper_poll_disable(drm_dev);
         vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
@@ -427,6 +430,9 @@ static int radeon_pmops_runtime_resume(struct device *dev)
         if (radeon_runtime_pm == 0)
                 return -EINVAL;
 
+        if (radeon_runtime_pm == -1 && !radeon_is_px())
+                return -EINVAL;
+
         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
         pci_set_power_state(pdev, PCI_D0);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 866744e47cfa..c37cb79a9489 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -121,7 +121,7 @@ int radeon_fence_emit(struct radeon_device *rdev,
         (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
         (*fence)->ring = ring;
         radeon_fence_ring_emit(rdev, ring, *fence);
-        trace_radeon_fence_emit(rdev->ddev, (*fence)->seq);
+        trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq);
         return 0;
 }
 
@@ -313,7 +313,7 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
                                 continue;
 
                         last_seq[i] = atomic64_read(&rdev->fence_drv[i].last_seq);
-                        trace_radeon_fence_wait_begin(rdev->ddev, target_seq[i]);
+                        trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]);
                         radeon_irq_kms_sw_irq_get(rdev, i);
                 }
 
@@ -332,7 +332,7 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
                                 continue;
 
                         radeon_irq_kms_sw_irq_put(rdev, i);
-                        trace_radeon_fence_wait_end(rdev->ddev, target_seq[i]);
+                        trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
                 }
 
                 if (unlikely(r < 0))
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 96e440061bdb..a8f9b463bf2a 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -713,7 +713,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
         unsigned i;
 
         /* check if the id is still valid */
-        if (vm->fence && vm->fence == rdev->vm_manager.active[vm->id])
+        if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
                 return NULL;
 
         /* we definately need to flush */
@@ -726,6 +726,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
                 if (fence == NULL) {
                         /* found a free one */
                         vm->id = i;
+                        trace_radeon_vm_grab_id(vm->id, ring);
                         return NULL;
                 }
 
@@ -769,6 +770,9 @@ void radeon_vm_fence(struct radeon_device *rdev,
 
         radeon_fence_unref(&vm->fence);
         vm->fence = radeon_fence_ref(fence);
+
+        radeon_fence_unref(&vm->last_id_use);
+        vm->last_id_use = radeon_fence_ref(fence);
 }
 
 /**
@@ -1303,6 +1307,8 @@ void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
 {
         vm->id = 0;
         vm->fence = NULL;
+        vm->last_flush = NULL;
+        vm->last_id_use = NULL;
         mutex_init(&vm->mutex);
         INIT_LIST_HEAD(&vm->list);
         INIT_LIST_HEAD(&vm->va);
@@ -1341,5 +1347,6 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
         }
         radeon_fence_unref(&vm->fence);
         radeon_fence_unref(&vm->last_flush);
+        radeon_fence_unref(&vm->last_id_use);
         mutex_unlock(&vm->mutex);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_trace.h b/drivers/gpu/drm/radeon/radeon_trace.h
index 0473257d4078..f749f2c3bbdb 100644
--- a/drivers/gpu/drm/radeon/radeon_trace.h
+++ b/drivers/gpu/drm/radeon/radeon_trace.h
@@ -106,42 +106,45 @@ TRACE_EVENT(radeon_vm_set_page,
 
 DECLARE_EVENT_CLASS(radeon_fence_request,
 
-            TP_PROTO(struct drm_device *dev, u32 seqno),
+            TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
 
-            TP_ARGS(dev, seqno),
+            TP_ARGS(dev, ring, seqno),
 
             TP_STRUCT__entry(
                              __field(u32, dev)
+                             __field(int, ring)
                              __field(u32, seqno)
                              ),
 
             TP_fast_assign(
                            __entry->dev = dev->primary->index;
+                           __entry->ring = ring;
                            __entry->seqno = seqno;
                            ),
 
-            TP_printk("dev=%u, seqno=%u", __entry->dev, __entry->seqno)
+            TP_printk("dev=%u, ring=%d, seqno=%u",
+                      __entry->dev, __entry->ring, __entry->seqno)
 );
 
 DEFINE_EVENT(radeon_fence_request, radeon_fence_emit,
 
-            TP_PROTO(struct drm_device *dev, u32 seqno),
+            TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
 
-            TP_ARGS(dev, seqno)
+            TP_ARGS(dev, ring, seqno)
 );
 
 DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_begin,
 
-            TP_PROTO(struct drm_device *dev, u32 seqno),
+            TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
 
-            TP_ARGS(dev, seqno)
+            TP_ARGS(dev, ring, seqno)
 );
 
 DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_end,
 
-            TP_PROTO(struct drm_device *dev, u32 seqno),
+            TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
 
-            TP_ARGS(dev, seqno)
+            TP_ARGS(dev, ring, seqno)
 );
 
 DECLARE_EVENT_CLASS(radeon_semaphore_request,
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 18e02889ec7d..6c772e58c784 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1071,7 +1071,8 @@ static void rv770_mc_program(struct radeon_device *rdev)
  */
 void r700_cp_stop(struct radeon_device *rdev)
 {
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+        if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
         WREG32(SCRATCH_UMSK, 0);
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 07ce58716e44..09ec4f6c53bb 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3249,7 +3249,8 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable)
         if (enable)
                 WREG32(CP_ME_CNTL, 0);
         else {
-                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+                if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
                 WREG32(SCRATCH_UMSK, 0);
                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
@@ -3510,6 +3511,9 @@ static int si_cp_resume(struct radeon_device *rdev)
 
         si_enable_gui_idle_interrupt(rdev, true);
 
+        if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+
         return 0;
 }
 
@@ -5678,7 +5682,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
         }
 
         if (!ASIC_IS_NODCE(rdev)) {
-                WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
+                WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
 
                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
                 WREG32(DC_HPD1_INT_CONTROL, tmp);
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 36a5da4791ce..0471501338fb 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -3590,10 +3590,9 @@ static void si_program_display_gap(struct radeon_device *rdev)
 
         /* Setting this to false forces the performance state to low if the crtcs are disabled.
          * This can be a problem on PowerXpress systems or if you want to use the card
-         * for offscreen rendering or compute if there are no crtcs enabled.  Set it to
-         * true for now so that performance scales even if the displays are off.
+         * for offscreen rendering or compute if there are no crtcs enabled.
          */
-        si_notify_smc_display_change(rdev, true /*rdev->pm.dpm.new_active_crtc_count > 0*/);
+        si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
 }
 
 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index caa3e61a38c2..9239a6d29128 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -822,7 +822,7 @@
 #       define GRPH_PFLIP_INT_MASK                      (1 << 0)
 #       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
 
-#define DACA_AUTODETECT_INT_CONTROL                     0x66c8
+#define DAC_AUTODETECT_INT_CONTROL                      0x67c8
 
 #define DC_HPD1_INT_STATUS                              0x601c
 #define DC_HPD2_INT_STATUS                              0x6028