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-rw-r--r--drivers/gpu/drm/i915/i915_irq.c71
1 files changed, 37 insertions, 34 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5c3baa0ec049..8f7baad72316 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1190,10 +1190,10 @@ static void dp_aux_irq_handler(struct drm_device *dev)
1190} 1190}
1191 1191
1192#if defined(CONFIG_DEBUG_FS) 1192#if defined(CONFIG_DEBUG_FS)
1193static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe, 1193static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1194 uint32_t crc0, uint32_t crc1, 1194 uint32_t crc0, uint32_t crc1,
1195 uint32_t crc2, uint32_t crc3, 1195 uint32_t crc2, uint32_t crc3,
1196 uint32_t crc4) 1196 uint32_t crc4)
1197{ 1197{
1198 struct drm_i915_private *dev_priv = dev->dev_private; 1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 1199 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
@@ -1227,29 +1227,37 @@ static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
1227 1227
1228 wake_up_interruptible(&pipe_crc->wq); 1228 wake_up_interruptible(&pipe_crc->wq);
1229} 1229}
1230#else
1231static inline void
1232display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1233 uint32_t crc0, uint32_t crc1,
1234 uint32_t crc2, uint32_t crc3,
1235 uint32_t crc4) {}
1236#endif
1237
1230 1238
1231static void hsw_pipe_crc_update(struct drm_device *dev, enum pipe pipe) 1239static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1232{ 1240{
1233 struct drm_i915_private *dev_priv = dev->dev_private; 1241 struct drm_i915_private *dev_priv = dev->dev_private;
1234 1242
1235 display_pipe_crc_update(dev, pipe, 1243 display_pipe_crc_irq_handler(dev, pipe,
1236 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1244 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1237 0, 0, 0, 0); 1245 0, 0, 0, 0);
1238} 1246}
1239 1247
1240static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe) 1248static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1241{ 1249{
1242 struct drm_i915_private *dev_priv = dev->dev_private; 1250 struct drm_i915_private *dev_priv = dev->dev_private;
1243 1251
1244 display_pipe_crc_update(dev, pipe, 1252 display_pipe_crc_irq_handler(dev, pipe,
1245 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1253 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1246 I915_READ(PIPE_CRC_RES_2_IVB(pipe)), 1254 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1247 I915_READ(PIPE_CRC_RES_3_IVB(pipe)), 1255 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1248 I915_READ(PIPE_CRC_RES_4_IVB(pipe)), 1256 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1249 I915_READ(PIPE_CRC_RES_5_IVB(pipe))); 1257 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1250} 1258}
1251 1259
1252static void i9xx_pipe_crc_update(struct drm_device *dev, enum pipe pipe) 1260static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1253{ 1261{
1254 struct drm_i915_private *dev_priv = dev->dev_private; 1262 struct drm_i915_private *dev_priv = dev->dev_private;
1255 uint32_t res1, res2; 1263 uint32_t res1, res2;
@@ -1264,17 +1272,12 @@ static void i9xx_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
1264 else 1272 else
1265 res2 = 0; 1273 res2 = 0;
1266 1274
1267 display_pipe_crc_update(dev, pipe, 1275 display_pipe_crc_irq_handler(dev, pipe,
1268 I915_READ(PIPE_CRC_RES_RED(pipe)), 1276 I915_READ(PIPE_CRC_RES_RED(pipe)),
1269 I915_READ(PIPE_CRC_RES_GREEN(pipe)), 1277 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1270 I915_READ(PIPE_CRC_RES_BLUE(pipe)), 1278 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1271 res1, res2); 1279 res1, res2);
1272} 1280}
1273#else
1274static inline void hsw_pipe_crc_update(struct drm_device *dev, int pipe) {}
1275static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
1276static inline void i9xx_pipe_crc_update(struct drm_device *dev, int pipe) {}
1277#endif
1278 1281
1279/* The RPS events need forcewake, so we add them to a work queue and mask their 1282/* The RPS events need forcewake, so we add them to a work queue and mask their
1280 * IMR bits until the work is done. Other interrupts can be processed without 1283 * IMR bits until the work is done. Other interrupts can be processed without
@@ -1352,7 +1355,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1352 } 1355 }
1353 1356
1354 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1357 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1355 i9xx_pipe_crc_update(dev, pipe); 1358 i9xx_pipe_crc_irq_handler(dev, pipe);
1356 } 1359 }
1357 1360
1358 /* Consume port. Then clear IIR or we'll miss events */ 1361 /* Consume port. Then clear IIR or we'll miss events */
@@ -1456,9 +1459,9 @@ static void ivb_err_int_handler(struct drm_device *dev)
1456 1459
1457 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 1460 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1458 if (IS_IVYBRIDGE(dev)) 1461 if (IS_IVYBRIDGE(dev))
1459 ivb_pipe_crc_update(dev, pipe); 1462 ivb_pipe_crc_irq_handler(dev, pipe);
1460 else 1463 else
1461 hsw_pipe_crc_update(dev, pipe); 1464 hsw_pipe_crc_irq_handler(dev, pipe);
1462 } 1465 }
1463 } 1466 }
1464 1467
@@ -1556,10 +1559,10 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1556 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); 1559 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1557 1560
1558 if (de_iir & DE_PIPEA_CRC_DONE) 1561 if (de_iir & DE_PIPEA_CRC_DONE)
1559 i9xx_pipe_crc_update(dev, PIPE_A); 1562 i9xx_pipe_crc_irq_handler(dev, PIPE_A);
1560 1563
1561 if (de_iir & DE_PIPEB_CRC_DONE) 1564 if (de_iir & DE_PIPEB_CRC_DONE)
1562 i9xx_pipe_crc_update(dev, PIPE_B); 1565 i9xx_pipe_crc_irq_handler(dev, PIPE_B);
1563 1566
1564 if (de_iir & DE_PLANEA_FLIP_DONE) { 1567 if (de_iir & DE_PLANEA_FLIP_DONE) {
1565 intel_prepare_page_flip(dev, 0); 1568 intel_prepare_page_flip(dev, 0);
@@ -2818,7 +2821,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2818 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); 2821 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2819 2822
2820 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 2823 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2821 i9xx_pipe_crc_update(dev, pipe); 2824 i9xx_pipe_crc_irq_handler(dev, pipe);
2822 } 2825 }
2823 2826
2824 iir = new_iir; 2827 iir = new_iir;
@@ -3022,7 +3025,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
3022 blc_event = true; 3025 blc_event = true;
3023 3026
3024 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3027 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3025 i9xx_pipe_crc_update(dev, pipe); 3028 i9xx_pipe_crc_irq_handler(dev, pipe);
3026 } 3029 }
3027 3030
3028 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 3031 if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -3271,7 +3274,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
3271 blc_event = true; 3274 blc_event = true;
3272 3275
3273 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3276 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3274 i9xx_pipe_crc_update(dev, pipe); 3277 i9xx_pipe_crc_irq_handler(dev, pipe);
3275 } 3278 }
3276 3279
3277 3280
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-19 01:36:11 -0400