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-rw-r--r--drivers/devfreq/exynos/exynos4_bus.c70
-rw-r--r--drivers/devfreq/exynos/exynos5_bus.c70
-rw-r--r--drivers/devfreq/exynos/exynos_ppmu.c60
-rw-r--r--drivers/devfreq/exynos/exynos_ppmu.h8
4 files changed, 72 insertions, 136 deletions
diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c
index d99ef9e80517..d257f1fcbaa9 100644
--- a/drivers/devfreq/exynos/exynos4_bus.c
+++ b/drivers/devfreq/exynos/exynos4_bus.c
@@ -75,11 +75,6 @@ struct busfreq_opp_info {
75 unsigned long volt; 75 unsigned long volt;
76}; 76};
77 77
78struct busfreq_ppmu_data {
79 struct exynos_ppmu *ppmu;
80 int ppmu_end;
81};
82
83struct busfreq_data { 78struct busfreq_data {
84 enum exynos4_busf_type type; 79 enum exynos4_busf_type type;
85 struct device *dev; 80 struct device *dev;
@@ -515,49 +510,6 @@ static int exynos4x12_set_busclk(struct busfreq_data *data,
515 return 0; 510 return 0;
516} 511}
517 512
518static void busfreq_mon_reset(struct busfreq_ppmu_data *ppmu_data)
519{
520 unsigned int i;
521
522 for (i = 0; i < ppmu_data->ppmu_end; i++) {
523 void __iomem *ppmu_base = ppmu_data->ppmu[i].hw_base;
524
525 /* Reset the performance and cycle counters */
526 exynos_ppmu_reset(ppmu_base);
527
528 /* Setup count registers to monitor read/write transactions */
529 ppmu_data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT;
530 exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3,
531 ppmu_data->ppmu[i].event[PPMU_PMNCNT3]);
532
533 exynos_ppmu_start(ppmu_base);
534 }
535}
536
537static void exynos4_read_ppmu(struct busfreq_ppmu_data *ppmu_data)
538{
539 int i, j;
540
541 for (i = 0; i < ppmu_data->ppmu_end; i++) {
542 void __iomem *ppmu_base = ppmu_data->ppmu[i].hw_base;
543
544 exynos_ppmu_stop(ppmu_base);
545
546 /* Update local data from PPMU */
547 ppmu_data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT);
548
549 for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
550 if (ppmu_data->ppmu[i].event[j] == 0)
551 ppmu_data->ppmu[i].count[j] = 0;
552 else
553 ppmu_data->ppmu[i].count[j] =
554 exynos_ppmu_read(ppmu_base, j);
555 }
556 }
557
558 busfreq_mon_reset(ppmu_data);
559}
560
561static int exynos4x12_get_intspec(unsigned long mifclk) 513static int exynos4x12_get_intspec(unsigned long mifclk)
562{ 514{
563 int i = 0; 515 int i = 0;
@@ -681,24 +633,6 @@ out:
681 return err; 633 return err;
682} 634}
683 635
684static int exynos4_get_busier_ppmu(struct busfreq_ppmu_data *ppmu_data)
685{
686 int i, j;
687 int busy = 0;
688 unsigned int temp = 0;
689
690 for (i = 0; i < ppmu_data->ppmu_end; i++) {
691 for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
692 if (ppmu_data->ppmu[i].count[j] > temp) {
693 temp = ppmu_data->ppmu[i].count[j];
694 busy = i;
695 }
696 }
697 }
698
699 return busy;
700}
701
702static int exynos4_bus_get_dev_status(struct device *dev, 636static int exynos4_bus_get_dev_status(struct device *dev,
703 struct devfreq_dev_status *stat) 637 struct devfreq_dev_status *stat)
704{ 638{
@@ -706,8 +640,8 @@ static int exynos4_bus_get_dev_status(struct device *dev,
706 struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data; 640 struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
707 int busier; 641 int busier;
708 642
709 exynos4_read_ppmu(ppmu_data); 643 exynos_read_ppmu(ppmu_data);
710 busier = exynos4_get_busier_ppmu(ppmu_data); 644 busier = exynos_get_busier_ppmu(ppmu_data);
711 stat->current_frequency = data->curr_oppinfo.rate; 645 stat->current_frequency = data->curr_oppinfo.rate;
712 646
713 /* Number of cycles spent on memory access */ 647 /* Number of cycles spent on memory access */
diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c
index b8ab32addef6..ab54a69d09b2 100644
--- a/drivers/devfreq/exynos/exynos5_bus.c
+++ b/drivers/devfreq/exynos/exynos5_bus.c
@@ -46,11 +46,6 @@ enum exynos_ppmu_list {
46 PPMU_END, 46 PPMU_END,
47}; 47};
48 48
49struct busfreq_ppmu_data {
50 struct exynos_ppmu *ppmu;
51 int ppmu_end;
52};
53
54struct busfreq_data_int { 49struct busfreq_data_int {
55 struct device *dev; 50 struct device *dev;
56 struct devfreq *devfreq; 51 struct devfreq *devfreq;
@@ -80,49 +75,6 @@ static struct int_bus_opp_table exynos5_int_opp_table[] = {
80 {0, 0, 0}, 75 {0, 0, 0},
81}; 76};
82 77
83static void busfreq_mon_reset(struct busfreq_ppmu_data *ppmu_data)
84{
85 unsigned int i;
86
87 for (i = 0; i < ppmu_data->ppmu_end; i++) {
88 void __iomem *ppmu_base = ppmu_data->ppmu[i].hw_base;
89
90 /* Reset the performance and cycle counters */
91 exynos_ppmu_reset(ppmu_base);
92
93 /* Setup count registers to monitor read/write transactions */
94 ppmu_data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT;
95 exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3,
96 ppmu_data->ppmu[i].event[PPMU_PMNCNT3]);
97
98 exynos_ppmu_start(ppmu_base);
99 }
100}
101
102static void exynos5_read_ppmu(struct busfreq_ppmu_data *ppmu_data)
103{
104 int i, j;
105
106 for (i = 0; i < ppmu_data->ppmu_end; i++) {
107 void __iomem *ppmu_base = ppmu_data->ppmu[i].hw_base;
108
109 exynos_ppmu_stop(ppmu_base);
110
111 /* Update local data from PPMU */
112 ppmu_data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT);
113
114 for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
115 if (ppmu_data->ppmu[i].event[j] == 0)
116 ppmu_data->ppmu[i].count[j] = 0;
117 else
118 ppmu_data->ppmu[i].count[j] =
119 exynos_ppmu_read(ppmu_base, j);
120 }
121 }
122
123 busfreq_mon_reset(ppmu_data);
124}
125
126static int exynos5_int_setvolt(struct busfreq_data_int *data, 78static int exynos5_int_setvolt(struct busfreq_data_int *data,
127 unsigned long volt) 79 unsigned long volt)
128{ 80{
@@ -190,24 +142,6 @@ out:
190 return err; 142 return err;
191} 143}
192 144
193static int exynos5_get_busier_dmc(struct busfreq_ppmu_data *ppmu_data)
194{
195 int i, j;
196 int busy = 0;
197 unsigned int temp = 0;
198
199 for (i = 0; i < ppmu_data->ppmu_end; i++) {
200 for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
201 if (ppmu_data->ppmu[i].count[j] > temp) {
202 temp = ppmu_data->ppmu[i].count[j];