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-rw-r--r--arch/arm/mach-exynos/Kconfig14
-rw-r--r--arch/arm/mach-exynos/Makefile7
-rw-r--r--arch/arm/mach-exynos/Makefile.boot3
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c10
-rw-r--r--arch/arm/mach-exynos/dev-drm.c29
-rw-r--r--arch/arm/mach-exynos/dma.c141
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h3
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h10
-rw-r--r--arch/arm/mach-exynos/include/mach/spi-clocks.h2
-rw-r--r--arch/arm/mach-exynos/pm.c2
-rw-r--r--arch/arm/mach-exynos/pmu.c24
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig5
-rw-r--r--arch/arm/mach-s3c24xx/Makefile1
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2416.c1
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2443.c6
-rw-r--r--arch/arm/mach-s3c24xx/common-s3c2443.c15
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2443.c16
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/dma.h4
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/map.h5
-rw-r--r--arch/arm/mach-s3c24xx/setup-spi.c39
-rw-r--r--arch/arm/plat-samsung/Kconfig2
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-pl330.h1
-rw-r--r--drivers/spi/Kconfig2
24 files changed, 292 insertions, 52 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d3e54cbe14cf..5893e2397da1 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
61 bool "SAMSUNG EXYNOS5250" 61 bool "SAMSUNG EXYNOS5250"
62 default y 62 default y
63 depends on ARCH_EXYNOS5 63 depends on ARCH_EXYNOS5
64 select SAMSUNG_DMADEV
64 help 65 help
65 Enable EXYNOS5250 SoC support 66 Enable EXYNOS5250 SoC support
66 67
@@ -70,7 +71,7 @@ config EXYNOS4_MCT
70 help 71 help
71 Use MCT (Multi Core Timer) as kernel timers 72 Use MCT (Multi Core Timer) as kernel timers
72 73
73config EXYNOS4_DEV_DMA 74config EXYNOS_DEV_DMA
74 bool 75 bool
75 help 76 help
76 Compile in amba device definitions for DMA controller 77 Compile in amba device definitions for DMA controller
@@ -80,6 +81,11 @@ config EXYNOS4_DEV_AHCI
80 help 81 help
81 Compile in platform device definitions for AHCI 82 Compile in platform device definitions for AHCI
82 83
84config EXYNOS_DEV_DRM
85 bool
86 help
87 Compile in platform device definitions for core DRM device
88
83config EXYNOS4_SETUP_FIMD0 89config EXYNOS4_SETUP_FIMD0
84 bool 90 bool
85 help 91 help
@@ -161,7 +167,7 @@ config EXYNOS4_SETUP_USB_PHY
161 help 167 help
162 Common setup code for USB PHY controller 168 Common setup code for USB PHY controller
163 169
164config EXYNOS4_SETUP_SPI 170config EXYNOS_SETUP_SPI
165 bool 171 bool
166 help 172 help
167 Common setup code for SPI GPIO configurations. 173 Common setup code for SPI GPIO configurations.
@@ -223,7 +229,7 @@ config MACH_ARMLEX4210
223 select S3C_DEV_HSMMC2 229 select S3C_DEV_HSMMC2
224 select S3C_DEV_HSMMC3 230 select S3C_DEV_HSMMC3
225 select EXYNOS4_DEV_AHCI 231 select EXYNOS4_DEV_AHCI
226 select EXYNOS4_DEV_DMA 232 select EXYNOS_DEV_DMA
227 select EXYNOS4_SETUP_SDHCI 233 select EXYNOS4_SETUP_SDHCI
228 help 234 help
229 Machine support for Samsung ARMLEX4210 based on EXYNOS4210 235 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -350,7 +356,7 @@ config MACH_SMDK4212
350 select SAMSUNG_DEV_KEYPAD 356 select SAMSUNG_DEV_KEYPAD
351 select SAMSUNG_DEV_PWM 357 select SAMSUNG_DEV_PWM
352 select EXYNOS_DEV_SYSMMU 358 select EXYNOS_DEV_SYSMMU
353 select EXYNOS4_DEV_DMA 359 select EXYNOS_DEV_DMA
354 select EXYNOS4_SETUP_I2C1 360 select EXYNOS4_SETUP_I2C1
355 select EXYNOS4_SETUP_I2C3 361 select EXYNOS4_SETUP_I2C3
356 select EXYNOS4_SETUP_I2C7 362 select EXYNOS4_SETUP_I2C7
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 272625231c73..440a637c76f1 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
50obj-y += dev-uart.o 50obj-y += dev-uart.o
51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
54obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 53obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
55obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 54obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
56obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 55obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
56obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o
57obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
57 58
58obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o 59obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
59obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 60obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
@@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
68obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 69obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
69obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 70obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
70obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o 71obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
71obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o 72obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
index b9862e22bf10..31bd181b0514 100644
--- a/arch/arm/mach-exynos/Makefile.boot
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -1,2 +1,5 @@
1 zreladdr-y += 0x40008000 1 zreladdr-y += 0x40008000
2params_phys-y := 0x40000100 2params_phys-y := 0x40000100
3
4dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
5dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 98823120570e..da397d21bbcf 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -92,6 +92,16 @@ static struct clk init_clocks_off[] = {
92 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), 92 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
93 .enable = exynos4212_clk_ip_isp1_ctrl, 93 .enable = exynos4212_clk_ip_isp1_ctrl,
94 .ctrlbit = (1 << 4), 94 .ctrlbit = (1 << 4),
95 }, {
96 .name = "flite",
97 .devname = "exynos-fimc-lite.0",
98 .enable = exynos4212_clk_ip_isp0_ctrl,
99 .ctrlbit = (1 << 4),
100 }, {
101 .name = "flite",
102 .devname = "exynos-fimc-lite.1",
103 .enable = exynos4212_clk_ip_isp0_ctrl,
104 .ctrlbit = (1 << 3),
95 } 105 }
96}; 106};
97 107
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
new file mode 100644
index 000000000000..17c9c6ecc2e0
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-drm.c
@@ -0,0 +1,29 @@
1/*
2 * linux/arch/arm/mach-exynos/dev-drm.c
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS - core DRM device
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18
19#include <plat/devs.h>
20
21static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
22
23struct platform_device exynos_device_drm = {
24 .name = "exynos-drm",
25 .dev = {
26 .dma_mask = &exynos_drm_dma_mask,
27 .coherent_dma_mask = DMA_BIT_MASK(32),
28 }
29};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 69aaa4503205..f60b66dbcf84 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = {
103 DMACH_MIPI_HSI5, 103 DMACH_MIPI_HSI5,
104}; 104};
105 105
106struct dma_pl330_platdata exynos4_pdma0_pdata; 106static u8 exynos5250_pdma0_peri[] = {
107 DMACH_PCM0_RX,
108 DMACH_PCM0_TX,
109 DMACH_PCM2_RX,
110 DMACH_PCM2_TX,
111 DMACH_SPI0_RX,
112 DMACH_SPI0_TX,
113 DMACH_SPI2_RX,
114 DMACH_SPI2_TX,
115 DMACH_I2S0S_TX,
116 DMACH_I2S0_RX,
117 DMACH_I2S0_TX,
118 DMACH_I2S2_RX,
119 DMACH_I2S2_TX,
120 DMACH_UART0_RX,
121 DMACH_UART0_TX,
122 DMACH_UART2_RX,
123 DMACH_UART2_TX,
124 DMACH_UART4_RX,
125 DMACH_UART4_TX,
126 DMACH_SLIMBUS0_RX,
127 DMACH_SLIMBUS0_TX,
128 DMACH_SLIMBUS2_RX,
129 DMACH_SLIMBUS2_TX,
130 DMACH_SLIMBUS4_RX,
131 DMACH_SLIMBUS4_TX,
132 DMACH_AC97_MICIN,
133 DMACH_AC97_PCMIN,
134 DMACH_AC97_PCMOUT,
135 DMACH_MIPI_HSI0,
136 DMACH_MIPI_HSI2,
137 DMACH_MIPI_HSI4,
138 DMACH_MIPI_HSI6,
139};
140
141static struct dma_pl330_platdata exynos_pdma0_pdata;
107 142
108static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, 143static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
109 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata); 144 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
110 145
111static u8 exynos4210_pdma1_peri[] = { 146static u8 exynos4210_pdma1_peri[] = {
112 DMACH_PCM0_RX, 147 DMACH_PCM0_RX,
@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = {
169 DMACH_MIPI_HSI7, 204 DMACH_MIPI_HSI7,
170}; 205};
171 206
172static struct dma_pl330_platdata exynos4_pdma1_pdata; 207static u8 exynos5250_pdma1_peri[] = {
208 DMACH_PCM0_RX,
209 DMACH_PCM0_TX,
210 DMACH_PCM1_RX,
211 DMACH_PCM1_TX,
212 DMACH_SPI1_RX,
213 DMACH_SPI1_TX,
214 DMACH_PWM,
215 DMACH_SPDIF,
216 DMACH_I2S0S_TX,
217 DMACH_I2S0_RX,
218 DMACH_I2S0_TX,
219 DMACH_I2S1_RX,
220 DMACH_I2S1_TX,
221 DMACH_UART0_RX,
222 DMACH_UART0_TX,
223 DMACH_UART1_RX,
224 DMACH_UART1_TX,
225 DMACH_UART3_RX,
226 DMACH_UART3_TX,
227 DMACH_SLIMBUS1_RX,
228 DMACH_SLIMBUS1_TX,
229 DMACH_SLIMBUS3_RX,
230 DMACH_SLIMBUS3_TX,
231 DMACH_SLIMBUS5_RX,
232 DMACH_SLIMBUS5_TX,
233 DMACH_SLIMBUS0AUX_RX,
234 DMACH_SLIMBUS0AUX_TX,
235 DMACH_DISP1,
236 DMACH_MIPI_HSI1,
237 DMACH_MIPI_HSI3,
238 DMACH_MIPI_HSI5,
239 DMACH_MIPI_HSI7,
240};
173 241
174static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, 242static struct dma_pl330_platdata exynos_pdma1_pdata;
175 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata); 243
244static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
245 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
176 246
177static u8 mdma_peri[] = { 247static u8 mdma_peri[] = {
178 DMACH_MTOM_0, 248 DMACH_MTOM_0,
@@ -185,46 +255,63 @@ static u8 mdma_peri[] = {
185 DMACH_MTOM_7, 255 DMACH_MTOM_7,
186}; 256};
187 257
188static struct dma_pl330_platdata exynos4_mdma1_pdata = { 258static struct dma_pl330_platdata exynos_mdma1_pdata = {
189 .nr_valid_peri = ARRAY_SIZE(mdma_peri), 259 .nr_valid_peri = ARRAY_SIZE(mdma_peri),
190 .peri_id = mdma_peri, 260 .peri_id = mdma_peri,
191}; 261};
192 262
193static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330, 263static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
194 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata); 264 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
195 265
196static int __init exynos4_dma_init(void) 266static int __init exynos_dma_init(void)
197{ 267{
198 if (of_have_populated_dt()) 268 if (of_have_populated_dt())
199 return 0; 269 return 0;
200 270
201 if (soc_is_exynos4210()) { 271 if (soc_is_exynos4210()) {
202 exynos4_pdma0_pdata.nr_valid_peri = 272 exynos_pdma0_pdata.nr_valid_peri =
203 ARRAY_SIZE(exynos4210_pdma0_peri); 273 ARRAY_SIZE(exynos4210_pdma0_peri);
204 exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri; 274 exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
205 exynos4_pdma1_pdata.nr_valid_peri = 275 exynos_pdma1_pdata.nr_valid_peri =
206 ARRAY_SIZE(exynos4210_pdma1_peri); 276 ARRAY_SIZE(exynos4210_pdma1_peri);
207 exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri; 277 exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
208 } else if (soc_is_exynos4212() || soc_is_exynos4412()) { 278 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
209 exynos4_pdma0_pdata.nr_valid_peri = 279 exynos_pdma0_pdata.nr_valid_peri =
210 ARRAY_SIZE(exynos4212_pdma0_peri); 280 ARRAY_SIZE(exynos4212_pdma0_peri);
211 exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri; 281 exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
212 exynos4_pdma1_pdata.nr_valid_peri = 282 exynos_pdma1_pdata.nr_valid_peri =
213 ARRAY_SIZE(exynos4212_pdma1_peri); 283 ARRAY_SIZE(exynos4212_pdma1_peri);
214 exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri; 284 exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
285 } else if (soc_is_exynos5250()) {
286 exynos_pdma0_pdata.nr_valid_peri =
287 ARRAY_SIZE(exynos5250_pdma0_peri);
288 exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
289 exynos_pdma1_pdata.nr_valid_peri =
290 ARRAY_SIZE(exynos5250_pdma1_peri);
291 exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
292
293 exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
294 exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
295 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
296 exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
297 exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
298 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
299 exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
300 exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
301 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
215 } 302 }
216 303
217 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); 304 dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
218 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); 305 dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
219 amba_device_register(&exynos4_pdma0_device, &iomem_resource); 306 amba_device_register(&exynos_pdma0_device, &iomem_resource);
220 307
221 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); 308 dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
222 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); 309 dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
223 amba_device_register(&exynos4_pdma1_device, &iomem_resource); 310 amba_device_register(&exynos_pdma1_device, &iomem_resource);
224 311
225 dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask); 312 dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
226 amba_device_register(&exynos4_mdma1_device, &iomem_resource); 313 amba_device_register(&exynos_mdma1_device, &iomem_resource);
227 314
228 return 0; 315 return 0;
229} 316}
230arch_initcall(exynos4_dma_init); 317arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 0e2292d04550..d30643ba2739 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -34,6 +34,9 @@
34 34
35#define EXYNOS4_PA_JPEG 0x11840000 35#define EXYNOS4_PA_JPEG 0x11840000
36 36
37/* x = 0...1 */
38#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
39
37#define EXYNOS4_PA_G2D 0x12800000 40#define EXYNOS4_PA_G2D 0x12800000
38 41
39#define EXYNOS4_PA_I2S0 0x03830000 42#define EXYNOS4_PA_I2S0 0x03830000
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4c53f38b5a9e..606b19907f99 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -177,7 +177,7 @@
177 177
178#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) 178#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
179 179
180/* Only for EXYNOS4212 */ 180/* Only for EXYNOS4x12 */
181#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) 181#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
182#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) 182#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
183#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) 183#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
@@ -218,4 +218,12 @@
218#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) 218#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
219#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) 219#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
220 220
221/* Only for EXYNOS4412 */
222#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
223#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
224#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
225#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
226#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
227#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
228
221#endif /* __ASM_ARCH_REGS_PMU_H */ 229#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
index 576efdf6d091..c71a5fba6a84 100644
--- a/arch/arm/mach-exynos/include/mach/spi-clocks.h
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -11,6 +11,6 @@
11#define __ASM_ARCH_SPI_CLKS_H __FILE__ 11#define __ASM_ARCH_SPI_CLKS_H __FILE__
12 12
13/* Must source from SCLK_SPI */ 13/* Must source from SCLK_SPI */
14#define EXYNOS4_SPI_SRCCLK_SCLK 0 14#define EXYNOS_SPI_SRCCLK_SCLK 0
15 15
16#endif /* __ASM_ARCH_SPI_CLKS_H */ 16#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 428cfeb57724..f0bb4677eb11 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void)
313 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 313 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
314 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 314 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
315 315
316 if (soc_is_exynos4212()) { 316 if (soc_is_exynos4212() || soc_is_exynos4412()) {
317 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); 317 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
318 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM | 318 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
319 S5P_USE_STANDBYWFE_ISP_ARM); 319 S5P_USE_STANDBYWFE_ISP_ARM);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bba48f5c3e8f..77c6815eebee 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
94 { PMU_TABLE_END,}, 94 { PMU_TABLE_END,},
95}; 95};
96 96
97static struct exynos4_pmu_conf exynos4212_pmu_config[] = { 97static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, 100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
202 { PMU_TABLE_END,}, 202 { PMU_TABLE_END,},
203}; 203};
204 204
205static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
206 { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
207 { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
208 { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
209 { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
210 { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
211 { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
212 { PMU_TABLE_END,},
213};
214
205void exynos4_sys_powerdown_conf(enum sys_powerdown mode) 215void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
206{ 216{
207 unsigned int i; 217 unsigned int i;
@@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
209 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++) 219 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
210 __raw_writel(exynos4_pmu_config[i].val[mode], 220 __raw_writel(exynos4_pmu_config[i].val[mode],
211 exynos4_pmu_config[i].reg); 221 exynos4_pmu_config[i].reg);
222
223 if (soc_is_exynos4412()) {
224 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
225 __raw_writel(exynos4412_pmu_config[i].val[mode],
226 exynos4412_pmu_config[i].reg);
227 }
212} 228}
213 229
214static int __init exynos4_pmu_init(void) 230static int __init exynos4_pmu_init(void)
@@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void)
218 if (soc_is_exynos4210()) { 234 if (soc_is_exynos4210()) {
219 exynos4_pmu_config = exynos4210_pmu_config; 235 exynos4_pmu_config = exynos4210_pmu_config;
220 pr_info("EXYNOS4210 PMU Initialize\n"); 236 pr_info("EXYNOS4210 PMU Initialize\n");
221 } else if (soc_is_exynos4212()) { 237 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
222 exynos4_pmu_config = exynos4212_pmu_config; 238 exynos4_pmu_config = exynos4x12_pmu_config;
223 pr_info("EXYNOS4212 PMU Initialize\n"); 239 pr_info("EXYNOS4x12 PMU Initialize\n");
224 } else { 240 } else {
225 pr_info("EXYNOS4: PMU not supported\n"); 241 pr_info("EXYNOS4: PMU not supported\n");
226 } 242 }
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index b34287ab5afd..e24961109b70 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -518,6 +518,11 @@ config S3C2443_DMA
518 help 518 help
519 Internal config node for S3C2443 DMA support 519 Internal config node for S3C2443 DMA support
520 520
521config S3C2443_SETUP_SPI
522 bool
523 help
524 Common setup code for SPI GPIO configurations
525
521endif # CPU_S3C2443 || CPU_S3C2416 526endif # CPU_S3C2443 || CPU_S3C2416
522 527
523if CPU_S3C2443 528if CPU_S3C2443
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 3518fe812d5f..d0f3a92f9e4a 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -91,5 +91,6 @@ obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o
91# device setup 91# device setup
92 92
93obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 93obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
94obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o
94obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o 95obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o
95obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o 96obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index dbc9ab4aaca2..8702ecfaab30 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
144 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), 144 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
145 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), 145 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
146 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), 146 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
147 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
147}; 148};
148 149
149void __init s3c2416_init_clocks(int xtal) 150void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index efb3ac359566..a4c5a520d994 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -179,6 +179,11 @@ static struct clk *clks[] __initdata = {
179 &clk_hsmmc, 179 &clk_hsmmc,
180}; 180};
181 181
182static struct clk_lookup s3c2443_clk_lookup[] = {
183 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
184 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
185};
186
182void __init s3c2443_init_clocks(int xtal) 187void __init s3c2443_init_clocks(int xtal)
183{ 188{
184 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); 189 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@@ -210,6 +215,7 @@ void __init s3c2443_init_clocks(int xtal)
210 215
211 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 216 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
212 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 217 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
218 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
213 219
214 s3c_pwmclk_init(); 220 s3c_pwmclk_init();
215} 221}
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 460431589f39..aeeb2be283fa 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -424,11 +424,6 @@ static struct clk init_clocks_off[] = {
424 .enable = s3c2443_clkcon_enable_p, 424 .enable = s3c2443_clkcon_enable_p,
425 .ctrlbit = S3C2443_PCLKCON_IIS, 425 .ctrlbit = S3C2443_PCLKCON_IIS,
426 }, { 426 }, {
427 .name = "hsspi",
428 .parent = &clk_p,
429 .enable = s3c2443_clkcon_enable_p,
430 .ctrlbit = S3C2443_PCLKCON_HSSPI,
431 }, {
432 .name = "adc", 427 .name = "adc",
433 .parent = &clk_p, 428 .parent = &clk_p,
434 .enable = s3c2443_clkcon_enable_p, 429 .enable = s3c2443_clkcon_enable_p,
@@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = {
562 .ctrlbit = S3C2443_HCLKCON_HSMMC, 557 .ctrlbit = S3C2443_HCLKCON_HSMMC,
563}; 558};
564 559
560static struct clk hsspi_clk = {
561 .name = "spi",
562 .devname = "s3c64xx-spi.0",
563 .parent = &clk_p,
564 .enable = s3c2443_clkcon_enable_p,
565 .ctrlbit = S3C2443_PCLKCON_HSSPI,
566};
567
565/* EPLLCON compatible enough to get on/off information */ 568/* EPLLCON compatible enough to get on/off information */
566 569
567void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) 570void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
@@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = {
612 &clk_usb_bus, 615 &clk_usb_bus,
613 &clk_armdiv, 616 &clk_armdiv,
614 &hsmmc1_clk, 617 &hsmmc1_clk,
618 &hsspi_clk,
615}; 619};
616 620
617static struct clksrc_clk *clksrcs[] __initdata = { 621static struct clksrc_clk *clksrcs[] __initdata = {
@@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
629 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 633 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
630 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), 634 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
631 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), 635 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
636 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
632}; 637};
633 638
634void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 639void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index e227c472a40a..2d94228d2866 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -55,12 +55,20 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
55 .name = "sdi", 55 .name = "sdi",
56 .channels = MAP(S3C2443_DMAREQSEL_SDI), 56 .channels = MAP(S3C2443_DMAREQSEL_SDI),
57 }, 57 },
58 [DMACH_SPI0] = { 58 [DMACH_SPI0_RX] = {
59 .name = "spi0", 59 .name = "spi0-rx",
60 .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
61 },
62 [DMACH_SPI0_TX] = {
63 .name = "spi0-tx",
60 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX), 64 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
61 }, 65 },
62 [DMACH_SPI1] = { /* only on S3C2443/S3C2450 */ 66 [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
63 .name = "spi1", 67 .name = "spi1-rx",
68 .channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
69 },
70 [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
71 .name = "spi1-tx",
64 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX), 72 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
65 }, 73 },
66 [DMACH_UART0] = { 74 [DMACH_UART0] = {
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index acbdfecd4186..454831b66037 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -47,6 +47,10 @@ enum dma_ch {
47 DMACH_UART2_SRC2, 47 DMACH_UART2_SRC2,
48 DMACH_UART3, /* s3c2443 has extra uart */ 48 DMACH_UART3, /* s3c2443 has extra uart */
49 DMACH_UART3_SRC2, 49 DMACH_UART3_SRC2,
50 DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */
51 DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */
52 DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */
53 DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */
50 DMACH_MAX, /* the end entry */ 54 DMACH_MAX, /* the end entry */
51}; 55};
52 56
diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 78ae807f1281..8ba381f2dbe1 100644
--- a/arch/arm/mach-s3c24xx/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
@@ -98,6 +98,8 @@
98 98
99/* SPI */ 99/* SPI */
100#define S3C2410_PA_SPI (0x59000000) 100#define S3C2410_PA_SPI (0x59000000)
101#define S3C2443_PA_SPI0 (0x52000000)
102#define S3C2443_PA_SPI1 S3C2410_PA_SPI
101 103
102/* SDI */ 104/* SDI */
103#define S3C2410_PA_SDI (0x5A000000) 105#define S3C2410_PA_SDI (0x5A000000)
@@ -162,4 +164,7 @@
162#define S3C_PA_WDT S3C2410_PA_WATCHDOG 164#define S3C_PA_WDT S3C2410_PA_WATCHDOG
163#define S3C_PA_NAND S3C24XX_PA_NAND 165#define S3C_PA_NAND S3C24XX_PA_NAND
164 166
167#define S3C_PA_SPI0 S3C2443_PA_SPI0
168#define S3C_PA_SPI1 S3C2443_PA_SPI1
169
165#endif /* __ASM_ARCH_MAP_H */ 170#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
new file mode 100644
index 000000000000..5712c85f39b1
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -0,0 +1,39 @@
1/*
2 * HS-SPI device setup for S3C2443/S3C2416
3 *
4 * Copyright (C) 2011 Samsung Electronics Ltd.
5 * http://www.samsung.com/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/gpio.h>
13#include <linux/platform_device.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/s3c64xx-spi.h>
17
18#include <mach/hardware.h>
19#include <mach/regs-gpio.h>
20
21#ifdef CONFIG_S3C64XX_DEV_SPI0
22struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
23 .fifo_lvl_mask = 0x7f,
24 .rx_lvl_offset = 13,
25 .tx_st_done = 21,
26 .high_speed = 1,
27};
28
29int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
30{
31 /* enable hsspi bit in misccr */
32 s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
33
34 s3c_gpio_cfgall_range(S3C2410_GPE(11), 3,
35 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
36
37 return 0;
38}
39#endif
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a0ffc77da809..77e65b483f90 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -291,7 +291,7 @@ config S3C_DMA
291config SAMSUNG_DMADEV 291config SAMSUNG_DMADEV
292 bool 292 bool
293 select DMADEVICES 293 select DMADEVICES
294 select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \ 294 select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \
295 CPU_S5P6450 || CPU_S5P6440) 295 CPU_S5P6450 || CPU_S5P6440)
296 select ARM_AMBA 296 select ARM_AMBA
297 help 297 help
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4067d1dd7f1c..61ca2f356c52 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -134,6 +134,8 @@ extern struct platform_device exynos4_device_pcm2;
134extern struct platform_device exynos4_device_pd[]; 134extern struct platform_device exynos4_device_pd[];
135extern struct platform_device exynos4_device_spdif; 135extern struct platform_device exynos4_device_spdif;
136 136
137extern struct platform_device exynos_device_drm;
138
137extern struct platform_device samsung_asoc_dma; 139extern struct platform_device samsung_asoc_dma;
138extern struct platform_device samsung_asoc_idma; 140extern struct platform_device samsung_asoc_idma;
139extern struct platform_device samsung_device_keypad; 141extern struct platform_device samsung_device_keypad;
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index 0670f37aaaed..d384a8016b47 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -90,6 +90,7 @@ enum dma_ch {
90 DMACH_MIPI_HSI5, 90 DMACH_MIPI_HSI5,
91 DMACH_MIPI_HSI6, 91 DMACH_MIPI_HSI6,
92 DMACH_MIPI_HSI7, 92 DMACH_MIPI_HSI7,
93 DMACH_DISP1,
93 DMACH_MTOM_0, 94 DMACH_MTOM_0,
94 DMACH_MTOM_1, 95 DMACH_MTOM_1,
95 DMACH_MTOM_2, 96 DMACH_MTOM_2,
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 00c024039c97..cd2fe350e724 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -311,7 +311,7 @@ config SPI_S3C24XX_FIQ
311 311
312config SPI_S3C64XX 312config SPI_S3C64XX
313 tristate "Samsung S3C64XX series type SPI" 313 tristate "Samsung S3C64XX series type SPI"
314 depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS) 314 depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
315 select S3C64XX_DMA if ARCH_S3C64XX 315 select S3C64XX_DMA if ARCH_S3C64XX
316 help 316 help
317 SPI driver for Samsung S3C64XX and newer SoCs. 317 SPI driver for Samsung S3C64XX and newer SoCs.
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 18:53:22 -0500