diff options
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv04.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv10.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv20.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv30.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv40.c | 32 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nv50.c | 28 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nvc0.c | 18 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/include/subdev/instmem.h | 19 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/instmem/base.c | 94 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c | 77 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c | 44 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c | 37 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h | 30 |
15 files changed, 223 insertions, 208 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c index dbd2dde7b7e7..a50d1b468f76 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c | |||
| @@ -54,7 +54,7 @@ nv04_identify(struct nouveau_device *device) | |||
| 54 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 54 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 55 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 55 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 56 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; | 56 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; |
| 57 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 57 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 58 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 59 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 59 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 60 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; | 60 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; |
| @@ -72,7 +72,7 @@ nv04_identify(struct nouveau_device *device) | |||
| 72 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 72 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 73 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; | 74 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 77 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 77 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 78 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; | 78 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c index 6e03dd6abeea..1541a97a1a15 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c | |||
| @@ -56,7 +56,7 @@ nv10_identify(struct nouveau_device *device) | |||
| 56 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 56 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 57 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 57 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 58 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 59 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 59 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 60 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 60 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 61 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 61 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 62 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | 62 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
| @@ -73,7 +73,7 @@ nv10_identify(struct nouveau_device *device) | |||
| 73 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 73 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 75 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 76 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 77 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 78 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 78 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 79 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; | 79 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
| @@ -92,7 +92,7 @@ nv10_identify(struct nouveau_device *device) | |||
| 92 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 92 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 93 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 93 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 94 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 94 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 95 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 95 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 96 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 97 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 97 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 98 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; | 98 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
| @@ -111,7 +111,7 @@ nv10_identify(struct nouveau_device *device) | |||
| 111 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 111 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 112 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 112 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 113 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; | 113 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; |
| 114 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 114 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 115 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 115 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 116 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 116 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 117 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; | 117 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
| @@ -130,7 +130,7 @@ nv10_identify(struct nouveau_device *device) | |||
| 130 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 130 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 131 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 131 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 132 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 132 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 133 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 133 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 134 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 134 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 135 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 135 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 136 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; | 136 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
| @@ -149,7 +149,7 @@ nv10_identify(struct nouveau_device *device) | |||
| 149 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 149 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 150 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 150 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 151 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 151 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 152 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 152 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 153 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 153 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 154 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 154 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 155 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 155 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -168,7 +168,7 @@ nv10_identify(struct nouveau_device *device) | |||
| 168 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 168 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 169 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 169 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 170 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; | 170 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; |
| 171 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 171 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 172 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 172 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 173 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 173 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 174 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 174 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -187,7 +187,7 @@ nv10_identify(struct nouveau_device *device) | |||
| 187 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 187 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 188 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 188 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 189 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 189 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 190 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 190 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 191 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 191 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 192 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 192 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 193 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 193 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c index dcde53b9f07f..d47ba090b32f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c | |||
| @@ -57,7 +57,7 @@ nv20_identify(struct nouveau_device *device) | |||
| 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; | 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; |
| 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -76,7 +76,7 @@ nv20_identify(struct nouveau_device *device) | |||
| 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; | 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; |
| 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -95,7 +95,7 @@ nv20_identify(struct nouveau_device *device) | |||
| 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; | 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; |
| 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -114,7 +114,7 @@ nv20_identify(struct nouveau_device *device) | |||
| 114 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 114 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 115 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 115 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 116 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; | 116 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; |
| 117 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 117 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 118 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 118 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 119 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 119 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 120 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 120 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c index 7b8662ef4f59..86a4ec73377c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c | |||
| @@ -57,7 +57,7 @@ nv30_identify(struct nouveau_device *device) | |||
| 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; | 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
| 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -76,7 +76,7 @@ nv30_identify(struct nouveau_device *device) | |||
| 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; | 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; |
| 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -95,7 +95,7 @@ nv30_identify(struct nouveau_device *device) | |||
| 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; | 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
| 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -115,7 +115,7 @@ nv30_identify(struct nouveau_device *device) | |||
| 115 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 115 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 116 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 116 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 117 | device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; | 117 | device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; |
| 118 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 118 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 119 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 119 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 120 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 120 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 121 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 121 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -135,7 +135,7 @@ nv30_identify(struct nouveau_device *device) | |||
| 135 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 135 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 136 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 136 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 137 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 137 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 138 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 138 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 139 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 139 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 140 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 140 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 141 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 141 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c index c8c41e93695e..688257bd0cc0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c | |||
| @@ -62,7 +62,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 62 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 62 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 63 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 63 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 64 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; | 64 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; |
| 65 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 65 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 66 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 66 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 67 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 67 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 68 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 68 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -85,7 +85,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 85 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 85 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 86 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 86 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 87 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; | 87 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 88 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 88 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 89 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 89 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 90 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 90 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 91 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 91 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -108,7 +108,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 108 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 108 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 109 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 109 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; | 110 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 111 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 112 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 112 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 113 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 113 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 114 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 114 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -131,7 +131,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 131 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 131 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 132 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 132 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 133 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; | 133 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 134 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 134 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 135 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 135 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 136 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 136 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 137 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 137 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -154,7 +154,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 154 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 154 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 155 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 155 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 156 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; | 156 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; |
| 157 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 157 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 158 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 158 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 159 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 159 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 160 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 160 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -177,7 +177,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 177 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 177 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 178 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 178 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 179 | device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; | 179 | device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; |
| 180 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 180 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 181 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 181 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 182 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 182 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 183 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 183 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -200,7 +200,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 200 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 200 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 201 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 201 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 202 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; | 202 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; |
| 203 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 203 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 204 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 204 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 205 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 205 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 206 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 206 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -223,7 +223,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 223 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 223 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 224 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 224 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 225 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; | 225 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; |
| 226 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 226 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 227 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 227 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 228 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 228 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 229 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 229 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -246,7 +246,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 246 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 246 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 247 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 247 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 248 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; | 248 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; |
| 249 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 249 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 250 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 250 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 251 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 251 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 252 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 252 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -269,7 +269,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 269 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 269 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 270 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 270 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 271 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 271 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 272 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 272 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 273 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 273 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 274 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 274 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 275 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 275 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -292,7 +292,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 292 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 292 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 293 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 293 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 294 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; | 294 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; |
| 295 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 295 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 296 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 296 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 298 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 298 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -315,7 +315,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 315 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 315 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 316 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 316 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 317 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 317 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 318 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 318 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 319 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 319 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 320 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 320 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 321 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 321 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -338,7 +338,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 338 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 338 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 339 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 339 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 340 | device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; | 340 | device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; |
| 341 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 341 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 342 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 342 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 343 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 343 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 344 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 344 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -361,7 +361,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 361 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 361 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 362 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 362 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 363 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 363 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 364 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 364 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 365 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 365 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 366 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 366 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 367 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 367 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -384,7 +384,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 384 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 384 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 385 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 385 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 386 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 386 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 387 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 387 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 388 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 388 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 389 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 389 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 390 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 390 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -407,7 +407,7 @@ nv40_identify(struct nouveau_device *device) | |||
| 407 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 407 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 408 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 408 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 409 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 409 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 410 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 410 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 411 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 411 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 412 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 412 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 413 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 413 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c index db3fc7be856a..5ee426985d45 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c | |||
| @@ -70,7 +70,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; | 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; | 72 | device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 73 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 74 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 75 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 76 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -95,7 +95,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; | 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 100 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 100 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 101 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 101 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -123,7 +123,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 123 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; | 123 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 124 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 124 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 125 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 125 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 126 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 126 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 127 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 127 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 128 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 128 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 129 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 129 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -151,7 +151,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 151 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; | 151 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 152 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 152 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 153 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 153 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 154 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 154 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 155 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 155 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 156 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 156 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 157 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 157 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -179,7 +179,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 179 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 179 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 180 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 180 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 181 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 181 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 182 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 182 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 183 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 183 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 184 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 184 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 185 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 185 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -207,7 +207,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 207 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 207 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 208 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 208 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 209 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 209 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 210 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 210 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 211 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 211 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 212 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 212 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 213 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 213 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -235,7 +235,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 235 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 235 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 236 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 236 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 237 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 237 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 238 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 238 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 239 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 239 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 240 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 240 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 241 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 241 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -263,7 +263,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 263 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 263 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 264 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 264 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 265 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 265 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 266 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 266 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 267 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 267 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 268 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 268 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 269 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 269 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -291,7 +291,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 291 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 291 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 292 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 292 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 293 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; | 293 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; |
| 294 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 294 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 295 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 295 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 296 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 296 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -319,7 +319,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 319 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 319 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 320 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 320 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 321 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; | 321 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; |
| 322 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 322 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 323 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 323 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 324 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 324 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 325 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 325 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -347,7 +347,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 347 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 347 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 348 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 348 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 349 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; | 349 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 350 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 350 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 351 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 351 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 352 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 352 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 353 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; | 353 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
| @@ -377,7 +377,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 377 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 377 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 378 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 378 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 379 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; | 379 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 380 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 380 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 381 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 381 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 382 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 382 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 383 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; | 383 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
| @@ -406,7 +406,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 406 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 406 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 407 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 407 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 408 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; | 408 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 409 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 409 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 410 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 410 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 411 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 411 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 412 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; | 412 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
| @@ -435,7 +435,7 @@ nv50_identify(struct nouveau_device *device) | |||
| 435 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 435 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 436 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 436 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 437 | device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; | 437 | device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; |
| 438 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 438 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 439 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 439 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 440 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 440 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 441 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; | 441 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c index dbc5e33de94f..f3d634e32590 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c | |||
| @@ -72,7 +72,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 72 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 72 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -104,7 +104,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 104 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 104 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 105 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 105 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 106 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 106 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 107 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 107 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 108 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 108 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 109 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 109 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 110 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -136,7 +136,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 136 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 136 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 137 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 137 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 138 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 138 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 139 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 139 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 140 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 140 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 141 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 141 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 142 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 142 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -167,7 +167,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 167 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 167 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 168 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 168 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 169 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 169 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 170 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 170 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 171 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 171 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 172 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 172 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 173 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 173 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -199,7 +199,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 199 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 199 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 200 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 200 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 201 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 201 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 202 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 202 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 203 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 203 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 204 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 204 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 205 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 205 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -231,7 +231,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 231 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 231 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 232 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 232 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 233 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 233 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 234 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 234 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 235 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 235 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 236 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 236 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 237 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 237 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -262,7 +262,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 262 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 262 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 263 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 263 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 264 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 264 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 265 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 265 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 266 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 266 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 267 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 267 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 268 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 268 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -294,7 +294,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 294 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 294 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 295 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 295 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 296 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 296 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 297 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 297 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 298 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 298 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 299 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 299 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 300 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 300 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -325,7 +325,7 @@ nvc0_identify(struct nouveau_device *device) | |||
| 325 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 325 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 326 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 326 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 327 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 327 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 328 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 328 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 329 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 329 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 330 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 330 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 331 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; | 331 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c index ae8d3c10ed65..a370e9ed2085 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c | |||
| @@ -72,7 +72,7 @@ nve0_identify(struct nouveau_device *device) | |||
| 72 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 72 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -105,7 +105,7 @@ nve0_identify(struct nouveau_device *device) | |||
| 105 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 105 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 106 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 106 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 107 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 107 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 108 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 108 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 109 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 109 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 110 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 111 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -138,7 +138,7 @@ nve0_identify(struct nouveau_device *device) | |||
| 138 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 138 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 139 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 139 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 140 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 140 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 141 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 141 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 142 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 142 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 143 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 143 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 144 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 144 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -171,7 +171,7 @@ nve0_identify(struct nouveau_device *device) | |||
| 171 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 171 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 172 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 172 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 173 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 173 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 174 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 174 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 175 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 175 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 176 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 176 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 177 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 177 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -206,7 +206,7 @@ nve0_identify(struct nouveau_device *device) | |||
| 206 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 206 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 207 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 207 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 208 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 208 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 209 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 209 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 210 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 210 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 211 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 211 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 212 | device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass; | 212 | device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h index 4aca33887aaa..7c20478064e3 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h | |||
| @@ -60,21 +60,8 @@ nouveau_instmem(void *obj) | |||
| 60 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_INSTMEM]; | 60 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_INSTMEM]; |
| 61 | } | 61 | } |
| 62 | 62 | ||
| 63 | #define nouveau_instmem_create(p,e,o,d) \ | 63 | extern struct nouveau_oclass *nv04_instmem_oclass; |
| 64 | nouveau_instmem_create_((p), (e), (o), sizeof(**d), (void **)d) | 64 | extern struct nouveau_oclass *nv40_instmem_oclass; |
| 65 | #define nouveau_instmem_destroy(p) \ | 65 | extern struct nouveau_oclass *nv50_instmem_oclass; |
| 66 | nouveau_subdev_destroy(&(p)->base) | ||
| 67 | int nouveau_instmem_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 68 | struct nouveau_oclass *, int, void **); | ||
| 69 | int nouveau_instmem_init(struct nouveau_instmem *); | ||
| 70 | int nouveau_instmem_fini(struct nouveau_instmem *, bool); | ||
| 71 | |||
| 72 | #define _nouveau_instmem_dtor _nouveau_subdev_dtor | ||
| 73 | int _nouveau_instmem_init(struct nouveau_object *); | ||
| 74 | int _nouveau_instmem_fini(struct nouveau_object *, bool); | ||
| 75 | |||
| 76 | extern struct nouveau_oclass nv04_instmem_oclass; | ||
| 77 | extern struct nouveau_oclass nv40_instmem_oclass; | ||
| 78 | extern struct nouveau_oclass nv50_instmem_oclass; | ||
| 79 | 66 | ||
| 80 | #endif | 67 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c index 6565f3dbbe04..5f5abf564ade 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <subdev/instmem.h> | 25 | #include "priv.h" |
| 26 | 26 | ||
| 27 | int | 27 | int |
| 28 | nouveau_instobj_create_(struct nouveau_object *parent, | 28 | nouveau_instobj_create_(struct nouveau_object *parent, |
| @@ -65,54 +65,31 @@ _nouveau_instobj_dtor(struct nouveau_object *object) | |||
| 65 | return nouveau_instobj_destroy(iobj); | 65 | return nouveau_instobj_destroy(iobj); |
| 66 | } | 66 | } |
| 67 | 67 | ||
| 68 | int | 68 | /****************************************************************************** |
| 69 | nouveau_instmem_create_(struct nouveau_object *parent, | 69 | * instmem subdev base implementation |
| 70 | struct nouveau_object *engine, | 70 | *****************************************************************************/ |
| 71 | struct nouveau_oclass *oclass, | ||
| 72 | int length, void **pobject) | ||
| 73 | { | ||
| 74 | struct nouveau_instmem *imem; | ||
| 75 | int ret; | ||
| 76 | 71 | ||
| 77 | ret = nouveau_subdev_create_(parent, engine, oclass, 0, | 72 | static int |
| 78 | "INSTMEM", "instmem", length, pobject); | 73 | nouveau_instmem_alloc(struct nouveau_instmem *imem, |
| 79 | imem = *pobject; | 74 | struct nouveau_object *parent, u32 size, u32 align, |
| 80 | if (ret) | 75 | struct nouveau_object **pobject) |
| 81 | return ret; | ||
| 82 | |||
| 83 | INIT_LIST_HEAD(&imem->list); | ||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | int | ||
| 88 | nouveau_instmem_init(struct nouveau_instmem *imem) | ||
| 89 | { | 76 | { |
| 90 | struct nouveau_instobj *iobj; | 77 | struct nouveau_object *engine = nv_object(imem); |
| 91 | int ret, i; | 78 | struct nouveau_instmem_impl *impl = (void *)engine->oclass; |
| 79 | int ret; | ||
| 92 | 80 | ||
| 93 | ret = nouveau_subdev_init(&imem->base); | 81 | ret = nouveau_object_ctor(parent, engine, impl->instobj, |
| 82 | (void *)(unsigned long)align, size, pobject); | ||
| 94 | if (ret) | 83 | if (ret) |
| 95 | return ret; | 84 | return ret; |
| 96 | 85 | ||
| 97 | mutex_lock(&imem->base.mutex); | ||
| 98 | |||
| 99 | list_for_each_entry(iobj, &imem->list, head) { | ||
| 100 | if (iobj->suspend) { | ||
| 101 | for (i = 0; i < iobj->size; i += 4) | ||
| 102 | nv_wo32(iobj, i, iobj->suspend[i / 4]); | ||
| 103 | vfree(iobj->suspend); | ||
| 104 | iobj->suspend = NULL; | ||
| 105 | } | ||
| 106 | } | ||
| 107 | |||
| 108 | mutex_unlock(&imem->base.mutex); | ||
| 109 | |||
| 110 | return 0; | 86 | return 0; |
| 111 | } | 87 | } |
| 112 | 88 | ||
| 113 | int | 89 | int |
| 114 | nouveau_instmem_fini(struct nouveau_instmem *imem, bool suspend) | 90 | _nouveau_instmem_fini(struct nouveau_object *object, bool suspend) |
| 115 | { | 91 | { |
| 92 | struct nouveau_instmem *imem = (void *)object; | ||
| 116 | struct nouveau_instobj *iobj; | 93 | struct nouveau_instobj *iobj; |
| 117 | int i, ret = 0; | 94 | int i, ret = 0; |
| 118 | 95 | ||
| @@ -143,12 +120,45 @@ int | |||
| 143 | _nouveau_instmem_init(struct nouveau_object *object) | 120 | _nouveau_instmem_init(struct nouveau_object *object) |
| 144 | { | 121 | { |
| 145 | struct nouveau_instmem *imem = (void *)object; | 122 | struct nouveau_instmem *imem = (void *)object; |
| 146 | return nouveau_instmem_init(imem); | 123 | struct nouveau_instobj *iobj; |
| 124 | int ret, i; | ||
| 125 | |||
| 126 | ret = nouveau_subdev_init(&imem->base); | ||
| 127 | if (ret) | ||
| 128 | return ret; | ||
| 129 | |||
| 130 | mutex_lock(&imem->base.mutex); | ||
| 131 | |||
| 132 | list_for_each_entry(iobj, &imem->list, head) { | ||
| 133 | if (iobj->suspend) { | ||
| 134 | for (i = 0; i < iobj->size; i += 4) | ||
| 135 | nv_wo32(iobj, i, iobj->suspend[i / 4]); | ||
| 136 | vfree(iobj->suspend); | ||
| 137 | iobj->suspend = NULL; | ||
| 138 | } | ||
| 139 | } | ||
| 140 | |||
| 141 | mutex_unlock(&imem->base.mutex); | ||
| 142 | |||
| 143 | return 0; | ||
| 147 | } | 144 | } |
| 148 | 145 | ||
| 149 | int | 146 | int |
| 150 | _nouveau_instmem_fini(struct nouveau_object *object, bool suspend) | 147 | nouveau_instmem_create_(struct nouveau_object *parent, |
| 148 | struct nouveau_object *engine, | ||
| 149 | struct nouveau_oclass *oclass, | ||
| 150 | int length, void **pobject) | ||
| 151 | { | 151 | { |
| 152 | struct nouveau_instmem *imem = (void *)object; | 152 | struct nouveau_instmem *imem; |
| 153 | return nouveau_instmem_fini(imem, suspend); | 153 | int ret; |
| 154 | |||
| 155 | ret = nouveau_subdev_create_(parent, engine, oclass, 0, | ||
| 156 | "INSTMEM", "instmem", length, pobject); | ||
| 157 | imem = *pobject; | ||
| 158 | if (ret) | ||
| 159 | return ret; | ||
| 160 | |||
| 161 | INIT_LIST_HEAD(&imem->list); | ||
| 162 | imem->alloc = nouveau_instmem_alloc; | ||
| 163 | return 0; | ||
| 154 | } | 164 | } |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c index 795393d7b2f5..226809d2f297 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c | |||
| @@ -22,8 +22,6 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <subdev/fb.h> | ||
| 26 | |||
| 27 | #include "nv04.h" | 25 | #include "nv04.h" |
| 28 | 26 | ||
| 29 | static int | 27 | static int |
| @@ -76,7 +74,7 @@ nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data) | |||
| 76 | nv_wo32(object->engine, node->mem->offset + addr, data); | 74 | nv_wo32(object->engine, node->mem->offset + addr, data); |
| 77 | } | 75 | } |
| 78 | 76 | ||
| 79 | static struct nouveau_oclass | 77 | struct nouveau_oclass |
| 80 | nv04_instobj_oclass = { | 78 | nv04_instobj_oclass = { |
| 81 | .ofuncs = &(struct nouveau_ofuncs) { | 79 | .ofuncs = &(struct nouveau_ofuncs) { |
| 82 | .ctor = nv04_instobj_ctor, | 80 | .ctor = nv04_instobj_ctor, |
| @@ -88,19 +86,34 @@ nv04_instobj_oclass = { | |||
| 88 | }, | 86 | }, |
| 89 | }; | 87 | }; |
| 90 | 88 | ||
| 91 | int | 89 | /****************************************************************************** |
| 92 | nv04_instmem_alloc(struct nouveau_instmem *imem, struct nouveau_object *parent, | 90 | * instmem subdev implementation |
| 93 | u32 size, u32 align, struct nouveau_object **pobject) | 91 | *****************************************************************************/ |
| 92 | |||
| 93 | static u32 | ||
| 94 | nv04_instmem_rd32(struct nouveau_object *object, u64 addr) | ||
| 94 | { | 95 | { |
| 95 | struct nouveau_object *engine = nv_object(imem); | 96 | return nv_rd32(object, 0x700000 + addr); |
| 96 | int ret; | 97 | } |
| 97 | 98 | ||
| 98 | ret = nouveau_object_ctor(parent, engine, &nv04_instobj_oclass, | 99 | static void |
| 99 | (void *)(unsigned long)align, size, pobject); | 100 | nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) |
| 100 | if (ret) | 101 | { |
| 101 | return ret; | 102 | return nv_wr32(object, 0x700000 + addr, data); |
| 103 | } | ||
| 102 | 104 | ||
| 103 | return 0; | 105 | void |
| 106 | nv04_instmem_dtor(struct nouveau_object *object) | ||
| 107 | { | ||
| 108 | struct nv04_instmem_priv *priv = (void *)object; | ||
| 109 | nouveau_gpuobj_ref(NULL, &priv->ramfc); | ||
| 110 | nouveau_gpuobj_ref(NULL, &priv->ramro); | ||
| 111 | nouveau_ramht_ref(NULL, &priv->ramht); | ||
| 112 | nouveau_gpuobj_ref(NULL, &priv->vbios); | ||
| 113 | nouveau_mm_fini(&priv->heap); | ||
| 114 | if (priv->iomem) | ||
| 115 | iounmap(priv->iomem); | ||
| 116 | nouveau_instmem_destroy(&priv->base); | ||
| 104 | } | 117 | } |
| 105 | 118 | ||
| 106 | static int | 119 | static int |
| @@ -118,7 +131,6 @@ nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 118 | 131 | ||
| 119 | /* PRAMIN aperture maps over the end of VRAM, reserve it */ | 132 | /* PRAMIN aperture maps over the end of VRAM, reserve it */ |
| 120 | priv->base.reserved = 512 * 1024; | 133 | priv->base.reserved = 512 * 1024; |
| 121 | priv->base.alloc = nv04_instmem_alloc; | ||
| 122 | 134 | ||
| 123 | ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); | 135 | ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); |
| 124 | if (ret) | 136 | if (ret) |
| @@ -150,36 +162,10 @@ nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 150 | return 0; | 162 | return 0; |
| 151 | } | 163 | } |
| 152 | 164 | ||
| 153 | void | 165 | struct nouveau_oclass * |
| 154 | nv04_instmem_dtor(struct nouveau_object *object) | 166 | nv04_instmem_oclass = &(struct nouveau_instmem_impl) { |
| 155 | { | 167 | .base.handle = NV_SUBDEV(INSTMEM, 0x04), |
| 156 | struct nv04_instmem_priv *priv = (void *)object; | 168 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 157 | nouveau_gpuobj_ref(NULL, &priv->ramfc); | ||
| 158 | nouveau_gpuobj_ref(NULL, &priv->ramro); | ||
| 159 | nouveau_ramht_ref(NULL, &priv->ramht); | ||
| 160 | nouveau_gpuobj_ref(NULL, &priv->vbios); | ||
| 161 | nouveau_mm_fini(&priv->heap); | ||
| 162 | if (priv->iomem) | ||
| 163 | iounmap(priv->iomem); | ||
| 164 | nouveau_instmem_destroy(&priv->base); | ||
| 165 | } | ||
| 166 | |||
| 167 | static u32 | ||
| 168 | nv04_instmem_rd32(struct nouveau_object *object, u64 addr) | ||
| 169 | { | ||
| 170 | return nv_rd32(object, 0x700000 + addr); | ||
| 171 | } | ||
| 172 | |||
| 173 | static void | ||
| 174 | nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) | ||
| 175 | { | ||
| 176 | return nv_wr32(object, 0x700000 + addr, data); | ||
| 177 | } | ||
| 178 | |||
| 179 | struct nouveau_oclass | ||
| 180 | nv04_instmem_oclass = { | ||
| 181 | .handle = NV_SUBDEV(INSTMEM, 0x04), | ||
| 182 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 183 | .ctor = nv04_instmem_ctor, | 169 | .ctor = nv04_instmem_ctor, |
| 184 | .dtor = nv04_instmem_dtor, | 170 | .dtor = nv04_instmem_dtor, |
| 185 | .init = _nouveau_instmem_init, | 171 | .init = _nouveau_instmem_init, |
| @@ -187,4 +173,5 @@ nv04_instmem_oclass = { | |||
| 187 | .rd32 = nv04_instmem_rd32, | 173 | .rd32 = nv04_instmem_rd32, |
| 188 | .wr32 = nv04_instmem_wr32, | 174 | .wr32 = nv04_instmem_wr32, |
| 189 | }, | 175 | }, |
| 190 | }; | 176 | .instobj = &nv04_instobj_oclass, |
| 177 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h index b15b61310236..fd866c4d441a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h | |||
| @@ -5,7 +5,9 @@ | |||
| 5 | #include <core/ramht.h> | 5 | #include <core/ramht.h> |
| 6 | #include <core/mm.h> | 6 | #include <core/mm.h> |
| 7 | 7 | ||
| 8 | #include <subdev/instmem.h> | 8 | #include "priv.h" |
| 9 | |||
| 10 | extern struct nouveau_oclass nv04_instobj_oclass; | ||
| 9 | 11 | ||
| 10 | struct nv04_instmem_priv { | 12 | struct nv04_instmem_priv { |
| 11 | struct nouveau_instmem base; | 13 | struct nouveau_instmem base; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c index b10a143787a7..02ea5e060c49 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c | |||
| @@ -26,6 +26,24 @@ | |||
| 26 | 26 | ||
| 27 | #include "nv04.h" | 27 | #include "nv04.h" |
| 28 | 28 | ||
| 29 | /****************************************************************************** | ||
| 30 | * instmem subdev implementation | ||
| 31 | *****************************************************************************/ | ||
| 32 | |||
| 33 | static u32 | ||
| 34 | nv40_instmem_rd32(struct nouveau_object *object, u64 addr) | ||
| 35 | { | ||
| 36 | struct nv04_instmem_priv *priv = (void *)object; | ||
| 37 | return ioread32_native(priv->iomem + addr); | ||
| 38 | } | ||
| 39 | |||
| 40 | static void | ||
| 41 | nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) | ||
| 42 | { | ||
| 43 | struct nv04_instmem_priv *priv = (void *)object; | ||
| 44 | iowrite32_native(data, priv->iomem + addr); | ||
| 45 | } | ||
| 46 | |||
| 29 | static int | 47 | static int |
| 30 | nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 48 | nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 31 | struct nouveau_oclass *oclass, void *data, u32 size, | 49 | struct nouveau_oclass *oclass, void *data, u32 size, |
| @@ -69,7 +87,6 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 69 | priv->base.reserved += 512 * 1024; /* object storage */ | 87 | priv->base.reserved += 512 * 1024; /* object storage */ |
| 70 | 88 | ||
| 71 | priv->base.reserved = round_up(priv->base.reserved, 4096); | 89 | priv->base.reserved = round_up(priv->base.reserved, 4096); |
| 72 | priv->base.alloc = nv04_instmem_alloc; | ||
| 73 | 90 | ||
| 74 | ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); | 91 | ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); |
| 75 | if (ret) | 92 | if (ret) |
| @@ -106,24 +123,10 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 106 | return 0; | 123 | return 0; |
| 107 | } | 124 | } |
| 108 | 125 | ||
| 109 | static u32 | 126 | struct nouveau_oclass * |
| 110 | nv40_instmem_rd32(struct nouveau_object *object, u64 addr) | 127 | nv40_instmem_oclass = &(struct nouveau_instmem_impl) { |
| 111 | { | 128 | .base.handle = NV_SUBDEV(INSTMEM, 0x40), |
| 112 | struct nv04_instmem_priv *priv = (void *)object; | 129 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 113 | return ioread32_native(priv->iomem + addr); | ||
| 114 | } | ||
| 115 | |||
| 116 | static void | ||
| 117 | nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) | ||
| 118 | { | ||
| 119 | struct nv04_instmem_priv *priv = (void *)object; | ||
| 120 | iowrite32_native(data, priv->iomem + addr); | ||
| 121 | } | ||
| 122 | |||
| 123 | struct nouveau_oclass | ||
| 124 | nv40_instmem_oclass = { | ||
| 125 | .handle = NV_SUBDEV(INSTMEM, 0x40), | ||
| 126 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 127 | .ctor = nv40_instmem_ctor, | 130 | .ctor = nv40_instmem_ctor, |
| 128 | .dtor = nv04_instmem_dtor, | 131 | .dtor = nv04_instmem_dtor, |
| 129 | .init = _nouveau_instmem_init, | 132 | .init = _nouveau_instmem_init, |
| @@ -131,4 +134,5 @@ nv40_instmem_oclass = { | |||
| 131 | .rd32 = nv40_instmem_rd32, | 134 | .rd32 = nv40_instmem_rd32, |
| 132 | .wr32 = nv40_instmem_wr32, | 135 | .wr32 = nv40_instmem_wr32, |
| 133 | }, | 136 | }, |
| 134 | }; | 137 | .instobj = &nv04_instobj_oclass, |
| 138 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c index 97bc5dff93e7..57b7589b16fc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c | |||
| @@ -22,11 +22,11 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <subdev/instmem.h> | ||
| 26 | #include <subdev/fb.h> | 25 | #include <subdev/fb.h> |
| 27 | |||
| 28 | #include <core/mm.h> | 26 | #include <core/mm.h> |
| 29 | 27 | ||
| 28 | #include "priv.h" | ||
| 29 | |||
| 30 | struct nv50_instmem_priv { | 30 | struct nv50_instmem_priv { |
| 31 | struct nouveau_instmem base; | 31 | struct nouveau_instmem base; |
| 32 | spinlock_t lock; | 32 | spinlock_t lock; |
| @@ -125,13 +125,16 @@ nv50_instobj_oclass = { | |||
| 125 | }, | 125 | }, |
| 126 | }; | 126 | }; |
| 127 | 127 | ||
| 128 | /****************************************************************************** | ||
| 129 | * instmem subdev implementation | ||
| 130 | *****************************************************************************/ | ||
| 131 | |||
| 128 | static int | 132 | static int |
| 129 | nv50_instmem_alloc(struct nouveau_instmem *imem, struct nouveau_object *parent, | 133 | nv50_instmem_fini(struct nouveau_object *object, bool suspend) |
| 130 | u32 size, u32 align, struct nouveau_object **pobject) | ||
| 131 | { | 134 | { |
| 132 | struct nouveau_object *engine = nv_object(imem); | 135 | struct nv50_instmem_priv *priv = (void *)object; |
| 133 | return nouveau_object_ctor(parent, engine, &nv50_instobj_oclass, | 136 | priv->addr = ~0ULL; |
| 134 | (void *)(unsigned long)align, size, pobject); | 137 | return nouveau_instmem_fini(&priv->base, suspend); |
| 135 | } | 138 | } |
| 136 | 139 | ||
| 137 | static int | 140 | static int |
| @@ -148,25 +151,17 @@ nv50_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 148 | return ret; | 151 | return ret; |
| 149 | 152 | ||
| 150 | spin_lock_init(&priv->lock); | 153 | spin_lock_init(&priv->lock); |
| 151 | priv->base.alloc = nv50_instmem_alloc; | ||
| 152 | return 0; | 154 | return 0; |
| 153 | } | 155 | } |
| 154 | 156 | ||
| 155 | static int | 157 | struct nouveau_oclass * |
| 156 | nv50_instmem_fini(struct nouveau_object *object, bool suspend) | 158 | nv50_instmem_oclass = &(struct nouveau_instmem_impl) { |
| 157 | { | 159 | .base.handle = NV_SUBDEV(INSTMEM, 0x50), |
| 158 | struct nv50_instmem_priv *priv = (void *)object; | 160 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 159 | priv->addr = ~0ULL; | ||
| 160 | return nouveau_instmem_fini(&priv->base, suspend); | ||
| 161 | } | ||
| 162 | |||
| 163 | struct nouveau_oclass | ||
| 164 | nv50_instmem_oclass = { | ||
| 165 | .handle = NV_SUBDEV(INSTMEM, 0x50), | ||
| 166 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 167 | .ctor = nv50_instmem_ctor, | 161 | .ctor = nv50_instmem_ctor, |
| 168 | .dtor = _nouveau_instmem_dtor, | 162 | .dtor = _nouveau_instmem_dtor, |
| 169 | .init = _nouveau_instmem_init, | 163 | .init = _nouveau_instmem_init, |
| 170 | .fini = nv50_instmem_fini, | 164 | .fini = nv50_instmem_fini, |
| 171 | }, | 165 | }, |
| 172 | }; | 166 | .instobj = &nv50_instobj_oclass, |
| 167 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h new file mode 100644 index 000000000000..17c7874f3ab7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | #ifndef __NVKM_INSTMEM_PRIV_H__ | ||
| 2 | #define __NVKM_INSTMEM_PRIV_H__ | ||
| 3 | |||
| 4 | #include <subdev/instmem.h> | ||
| 5 | |||
| 6 | struct nouveau_instmem_impl { | ||
| 7 | struct nouveau_oclass base; | ||
| 8 | struct nouveau_oclass *instobj; | ||
| 9 | }; | ||
| 10 | |||
| 11 | #define nouveau_instmem_create(p,e,o,d) \ | ||
| 12 | nouveau_instmem_create_((p), (e), (o), sizeof(**d), (void **)d) | ||
| 13 | #define nouveau_instmem_destroy(p) \ | ||
| 14 | nouveau_subdev_destroy(&(p)->base) | ||
| 15 | #define nouveau_instmem_init(p) ({ \ | ||
| 16 | struct nouveau_instmem *imem = (p); \ | ||
| 17 | _nouveau_instmem_init(nv_object(imem)); \ | ||
| 18 | }) | ||
| 19 | #define nouveau_instmem_fini(p,s) ({ \ | ||
| 20 | struct nouveau_instmem *imem = (p); \ | ||
| 21 | _nouveau_instmem_fini(nv_object(imem), (s)); \ | ||
| 22 | }) | ||
| 23 | |||
| 24 | int nouveau_instmem_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 25 | struct nouveau_oclass *, int, void **); | ||
| 26 | #define _nouveau_instmem_dtor _nouveau_subdev_dtor | ||
| 27 | int _nouveau_instmem_init(struct nouveau_object *); | ||
| 28 | int _nouveau_instmem_fini(struct nouveau_object *, bool); | ||
| 29 | |||
| 30 | #endif | ||
