1 files changed, 28 insertions, 8 deletions

diff --git a/drivers/net/ethernet/ibm/emac/core.c b/drivers/net/ethernet/ibm/emac/core.c
index 4989481c19f0..d300a0c0eafc 100644
--- a/drivers/net/ethernet/ibm/emac/core.c
+++ b/drivers/net/ethernet/ibm/emac/core.c
@@ -359,10 +359,26 @@ static int emac_reset(struct emac_instance *dev)
         }
 
 #ifdef CONFIG_PPC_DCR_NATIVE
-        /* Enable internal clock source */
-        if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
-                dcri_clrset(SDR0, SDR0_ETH_CFG,
-                            0, SDR0_ETH_CFG_ECS << dev->cell_index);
+        /*
+         * PPC460EX/GT Embedded Processor Advanced User's Manual
+         * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
+         * Note: The PHY must provide a TX Clk in order to perform a soft reset
+         * of the EMAC. If none is present, select the internal clock
+         * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
+         * After a soft reset, select the external clock.
+         */
+        if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
+                if (dev->phy_address == 0xffffffff &&
+                    dev->phy_map == 0xffffffff) {
+                        /* No PHY: select internal loop clock before reset */
+                        dcri_clrset(SDR0, SDR0_ETH_CFG,
+                                    0, SDR0_ETH_CFG_ECS << dev->cell_index);
+                } else {
+                        /* PHY present: select external clock before reset */
+                        dcri_clrset(SDR0, SDR0_ETH_CFG,
+                                    SDR0_ETH_CFG_ECS << dev->cell_index, 0);
+                }
+        }
 #endif
 
         out_be32(&p->mr0, EMAC_MR0_SRST);
@@ -370,10 +386,14 @@ static int emac_reset(struct emac_instance *dev)
                 --n;
 
 #ifdef CONFIG_PPC_DCR_NATIVE
-         /* Enable external clock source */
-        if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
-                dcri_clrset(SDR0, SDR0_ETH_CFG,
-                            SDR0_ETH_CFG_ECS << dev->cell_index, 0);
+        if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
+                if (dev->phy_address == 0xffffffff &&
+                    dev->phy_map == 0xffffffff) {
+                        /* No PHY: restore external clock source after reset */
+                        dcri_clrset(SDR0, SDR0_ETH_CFG,
+                                    SDR0_ETH_CFG_ECS << dev->cell_index, 0);
+                }
+        }
 #endif
 
         if (n) {