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-rw-r--r--arch/arm/boot/dts/hi3620.dtsi79
-rw-r--r--arch/arm/boot/dts/hi4511.dts3
2 files changed, 46 insertions, 36 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index e311937a1e2c..ab1116d086be 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -11,7 +11,8 @@
11 * publishhed by the Free Software Foundation. 11 * publishhed by the Free Software Foundation.
12 */ 12 */
13 13
14/include/ "skeleton.dtsi" 14#include "skeleton.dtsi"
15#include <dt-bindings/clock/hi3620-clock.h>
15 16
16/ { 17/ {
17 aliases { 18 aliases {
@@ -63,6 +64,7 @@
63 }; 64 };
64 65
65 amba { 66 amba {
67
66 #address-cells = <1>; 68 #address-cells = <1>;
67 #size-cells = <1>; 69 #size-cells = <1>;
68 compatible = "arm,amba-bus"; 70 compatible = "arm,amba-bus";
@@ -88,13 +90,20 @@
88 90
89 sysctrl: system-controller@802000 { 91 sysctrl: system-controller@802000 {
90 compatible = "hisilicon,sysctrl"; 92 compatible = "hisilicon,sysctrl";
91 reg = <0x802000 0x1000>;
92 #address-cells = <1>; 93 #address-cells = <1>;
93 #size-cells = <0>; 94 #size-cells = <1>;
95 ranges = <0 0x802000 0x1000>;
96 reg = <0x802000 0x1000>;
94 97
95 smp-offset = <0x31c>; 98 smp-offset = <0x31c>;
96 resume-offset = <0x308>; 99 resume-offset = <0x308>;
97 reboot-offset = <0x4>; 100 reboot-offset = <0x4>;
101
102 clock: clock@0 {
103 compatible = "hisilicon,hi3620-clock";
104 reg = <0 0x10000>;
105 #clock-cells = <1>;
106 };
98 }; 107 };
99 108
100 dual_timer0: dual_timer@800000 { 109 dual_timer0: dual_timer@800000 {
@@ -102,7 +111,7 @@
102 reg = <0x800000 0x1000>; 111 reg = <0x800000 0x1000>;
103 /* timer00 & timer01 */ 112 /* timer00 & timer01 */
104 interrupts = <0 0 4>, <0 1 4>; 113 interrupts = <0 0 4>, <0 1 4>;
105 clocks = <&pclk>; 114 clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
106 clock-names = "apb_pclk"; 115 clock-names = "apb_pclk";
107 status = "disabled"; 116 status = "disabled";
108 }; 117 };
@@ -112,7 +121,7 @@
112 reg = <0x801000 0x1000>; 121 reg = <0x801000 0x1000>;
113 /* timer10 & timer11 */ 122 /* timer10 & timer11 */
114 interrupts = <0 2 4>, <0 3 4>; 123 interrupts = <0 2 4>, <0 3 4>;
115 clocks = <&pclk>; 124 clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
116 clock-names = "apb_pclk"; 125 clock-names = "apb_pclk";
117 status = "disabled"; 126 status = "disabled";
118 }; 127 };
@@ -122,7 +131,7 @@
122 reg = <0xa01000 0x1000>; 131 reg = <0xa01000 0x1000>;
123 /* timer20 & timer21 */ 132 /* timer20 & timer21 */
124 interrupts = <0 4 4>, <0 5 4>; 133 interrupts = <0 4 4>, <0 5 4>;
125 clocks = <&pclk>; 134 clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
126 clock-names = "apb_pclk"; 135 clock-names = "apb_pclk";
127 status = "disabled"; 136 status = "disabled";
128 }; 137 };
@@ -132,7 +141,7 @@
132 reg = <0xa02000 0x1000>; 141 reg = <0xa02000 0x1000>;
133 /* timer30 & timer31 */ 142 /* timer30 & timer31 */
134 interrupts = <0 6 4>, <0 7 4>; 143 interrupts = <0 6 4>, <0 7 4>;
135 clocks = <&pclk>; 144 clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
136 clock-names = "apb_pclk"; 145 clock-names = "apb_pclk";
137 status = "disabled"; 146 status = "disabled";
138 }; 147 };
@@ -142,7 +151,7 @@
142 reg = <0xa03000 0x1000>; 151 reg = <0xa03000 0x1000>;
143 /* timer40 & timer41 */ 152 /* timer40 & timer41 */
144 interrupts = <0 96 4>, <0 97 4>; 153 interrupts = <0 96 4>, <0 97 4>;
145 clocks = <&pclk>; 154 clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
146 clock-names = "apb_pclk"; 155 clock-names = "apb_pclk";
147 status = "disabled"; 156 status = "disabled";
148 }; 157 };
@@ -157,7 +166,7 @@
157 compatible = "arm,pl011", "arm,primecell"; 166 compatible = "arm,pl011", "arm,primecell";
158 reg = <0xb00000 0x1000>; 167 reg = <0xb00000 0x1000>;
159 interrupts = <0 20 4>; 168 interrupts = <0 20 4>;
160 clocks = <&pclk>; 169 clocks = <&clock HI3620_UARTCLK0>;
161 clock-names = "apb_pclk"; 170 clock-names = "apb_pclk";
162 status = "disabled"; 171 status = "disabled";
163 }; 172 };
@@ -166,7 +175,7 @@
166 compatible = "arm,pl011", "arm,primecell"; 175 compatible = "arm,pl011", "arm,primecell";
167 reg = <0xb01000 0x1000>; 176 reg = <0xb01000 0x1000>;
168 interrupts = <0 21 4>; 177 interrupts = <0 21 4>;
169 clocks = <&pclk>; 178 clocks = <&clock HI3620_UARTCLK1>;
170 clock-names = "apb_pclk"; 179 clock-names = "apb_pclk";
171 status = "disabled"; 180 status = "disabled";
172 }; 181 };
@@ -175,7 +184,7 @@
175 compatible = "arm,pl011", "arm,primecell"; 184 compatible = "arm,pl011", "arm,primecell";
176 reg = <0xb02000 0x1000>; 185 reg = <0xb02000 0x1000>;
177 interrupts = <0 22 4>; 186 interrupts = <0 22 4>;
178 clocks = <&pclk>; 187 clocks = <&clock HI3620_UARTCLK2>;
179 clock-names = "apb_pclk"; 188 clock-names = "apb_pclk";
180 status = "disabled"; 189 status = "disabled";
181 }; 190 };
@@ -184,7 +193,7 @@
184 compatible = "arm,pl011", "arm,primecell"; 193 compatible = "arm,pl011", "arm,primecell";
185 reg = <0xb03000 0x1000>; 194 reg = <0xb03000 0x1000>;
186 interrupts = <0 23 4>; 195 interrupts = <0 23 4>;
187 clocks = <&pclk>; 196 clocks = <&clock HI3620_UARTCLK3>;
188 clock-names = "apb_pclk"; 197 clock-names = "apb_pclk";
189 status = "disabled"; 198 status = "disabled";
190 }; 199 };
@@ -193,7 +202,7 @@
193 compatible = "arm,pl011", "arm,primecell"; 202 compatible = "arm,pl011", "arm,primecell";
194 reg = <0xb04000 0x1000>; 203 reg = <0xb04000 0x1000>;
195 interrupts = <0 24 4>; 204 interrupts = <0 24 4>;
196 clocks = <&pclk>; 205 clocks = <&clock HI3620_UARTCLK4>;
197 clock-names = "apb_pclk"; 206 clock-names = "apb_pclk";
198 status = "disabled"; 207 status = "disabled";
199 }; 208 };
@@ -208,7 +217,7 @@
208 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; 217 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
209 interrupt-controller; 218 interrupt-controller;
210 #interrupt-cells = <2>; 219 #interrupt-cells = <2>;
211 clocks = <&pclk>; 220 clocks = <&clock HI3620_GPIOCLK0>;
212 clock-names = "apb_pclk"; 221 clock-names = "apb_pclk";
213 }; 222 };
214 223
@@ -223,7 +232,7 @@
223 &pmx0 6 5 1 &pmx0 7 6 1>; 232 &pmx0 6 5 1 &pmx0 7 6 1>;
224 interrupt-controller; 233 interrupt-controller;
225 #interrupt-cells = <2>; 234 #interrupt-cells = <2>;
226 clocks = <&pclk>; 235 clocks = <&clock HI3620_GPIOCLK1>;
227 clock-names = "apb_pclk"; 236 clock-names = "apb_pclk";
228 }; 237 };
229 238
@@ -238,7 +247,7 @@
238 &pmx0 6 3 1 &pmx0 7 3 1>; 247 &pmx0 6 3 1 &pmx0 7 3 1>;
239 interrupt-controller; 248 interrupt-controller;
240 #interrupt-cells = <2>; 249 #interrupt-cells = <2>;
241 clocks = <&pclk>; 250 clocks = <&clock HI3620_GPIOCLK2>;
242 clock-names = "apb_pclk"; 251 clock-names = "apb_pclk";
243 }; 252 };
244 253
@@ -253,7 +262,7 @@
253 &pmx0 6 11 1 &pmx0 7 11 1>; 262 &pmx0 6 11 1 &pmx0 7 11 1>;
254 interrupt-controller; 263 interrupt-controller;
255 #interrupt-cells = <2>; 264 #interrupt-cells = <2>;
256 clocks = <&pclk>; 265 clocks = <&clock HI3620_GPIOCLK3>;
257 clock-names = "apb_pclk"; 266 clock-names = "apb_pclk";
258 }; 267 };
259 268
@@ -268,7 +277,7 @@
268 &pmx0 6 13 1 &pmx0 7 13 1>; 277 &pmx0 6 13 1 &pmx0 7 13 1>;
269 interrupt-controller; 278 interrupt-controller;
270 #interrupt-cells = <2>; 279 #interrupt-cells = <2>;
271 clocks = <&pclk>; 280 clocks = <&clock HI3620_GPIOCLK4>;
272 clock-names = "apb_pclk"; 281 clock-names = "apb_pclk";
273 }; 282 };
274 283
@@ -283,7 +292,7 @@
283 &pmx0 6 16 1 &pmx0 7 16 1>; 292 &pmx0 6 16 1 &pmx0 7 16 1>;
284 interrupt-controller; 293 interrupt-controller;
285 #interrupt-cells = <2>; 294 #interrupt-cells = <2>;
286 clocks = <&pclk>; 295 clocks = <&clock HI3620_GPIOCLK5>;
287 clock-names = "apb_pclk"; 296 clock-names = "apb_pclk";
288 }; 297 };
289 298
@@ -298,7 +307,7 @@
298 &pmx0 6 18 1 &pmx0 7 19 1>; 307 &pmx0 6 18 1 &pmx0 7 19 1>;
299 interrupt-controller; 308 interrupt-controller;
300 #interrupt-cells = <2>; 309 #interrupt-cells = <2>;
301 clocks = <&pclk>; 310 clocks = <&clock HI3620_GPIOCLK6>;
302 clock-names = "apb_pclk"; 311 clock-names = "apb_pclk";
303 }; 312 };
304 313
@@ -313,7 +322,7 @@
313 &pmx0 6 25 1 &pmx0 7 26 1>; 322 &pmx0 6 25 1 &pmx0 7 26 1>;
314 interrupt-controller; 323 interrupt-controller;
315 #interrupt-cells = <2>; 324 #interrupt-cells = <2>;
316 clocks = <&pclk>; 325 clocks = <&clock HI3620_GPIOCLK7>;
317 clock-names = "apb_pclk"; 326 clock-names = "apb_pclk";
318 }; 327 };
319 328
@@ -328,7 +337,7 @@
328 &pmx0 6 33 1 &pmx0 7 34 1>; 337 &pmx0 6 33 1 &pmx0 7 34 1>;
329 interrupt-controller; 338 interrupt-controller;
330 #interrupt-cells = <2>; 339 #interrupt-cells = <2>;
331 clocks = <&pclk>; 340 clocks = <&clock HI3620_GPIOCLK8>;
332 clock-names = "apb_pclk"; 341 clock-names = "apb_pclk";
333 }; 342 };
334 343
@@ -343,7 +352,7 @@
343 &pmx0 6 41 1>; 352 &pmx0 6 41 1>;
344 interrupt-controller; 353 interrupt-controller;
345 #interrupt-cells = <2>; 354 #interrupt-cells = <2>;
346 clocks = <&pclk>; 355 clocks = <&clock HI3620_GPIOCLK9>;
347 clock-names = "apb_pclk"; 356 clock-names = "apb_pclk";
348 }; 357 };
349 358
@@ -357,7 +366,7 @@
357 &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; 366 &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
358 interrupt-controller; 367 interrupt-controller;
359 #interrupt-cells = <2>; 368 #interrupt-cells = <2>;
360 clocks = <&pclk>; 369 clocks = <&clock HI3620_GPIOCLK10>;
361 clock-names = "apb_pclk"; 370 clock-names = "apb_pclk";
362 }; 371 };
363 372
@@ -372,7 +381,7 @@
372 &pmx0 6 49 1 &pmx0 7 49 1>; 381 &pmx0 6 49 1 &pmx0 7 49 1>;
373 interrupt-controller; 382 interrupt-controller;
374 #interrupt-cells = <2>; 383 #interrupt-cells = <2>;
375 clocks = <&pclk>; 384 clocks = <&clock HI3620_GPIOCLK11>;
376 clock-names = "apb_pclk"; 385 clock-names = "apb_pclk";
377 }; 386 };
378 387
@@ -387,7 +396,7 @@
387 &pmx0 6 51 1 &pmx0 7 52 1>; 396 &pmx0 6 51 1 &pmx0 7 52 1>;
388 interrupt-controller; 397 interrupt-controller;
389 #interrupt-cells = <2>; 398 #interrupt-cells = <2>;
390 clocks = <&pclk>; 399 clocks = <&clock HI3620_GPIOCLK12>;
391 clock-names = "apb_pclk"; 400 clock-names = "apb_pclk";
392 }; 401 };
393 402
@@ -402,7 +411,7 @@
402 &pmx0 6 55 1 &pmx0 7 56 1>; 411 &pmx0 6 55 1 &pmx0 7 56 1>;
403 interrupt-controller; 412 interrupt-controller;
404 #interrupt-cells = <2>; 413 #interrupt-cells = <2>;
405 clocks = <&pclk>; 414 clocks = <&clock HI3620_GPIOCLK13>;
406 clock-names = "apb_pclk"; 415 clock-names = "apb_pclk";
407 }; 416 };
408 417
@@ -417,7 +426,7 @@
417 &pmx0 6 60 1 &pmx0 7 61 1>; 426 &pmx0 6 60 1 &pmx0 7 61 1>;
418 interrupt-controller; 427 interrupt-controller;
419 #interrupt-cells = <2>; 428 #interrupt-cells = <2>;
420 clocks = <&pclk>; 429 clocks = <&clock HI3620_GPIOCLK14>;
421 clock-names = "apb_pclk"; 430 clock-names = "apb_pclk";
422 }; 431 };
423 432
@@ -432,7 +441,7 @@
432 &pmx0 6 64 1 &pmx0 7 65 1>; 441 &pmx0 6 64 1 &pmx0 7 65 1>;
433 interrupt-controller; 442 interrupt-controller;
434 #interrupt-cells = <2>; 443 #interrupt-cells = <2>;
435 clocks = <&pclk>; 444 clocks = <&clock HI3620_GPIOCLK15>;
436 clock-names = "apb_pclk"; 445 clock-names = "apb_pclk";
437 }; 446 };
438 447
@@ -447,7 +456,7 @@
447 &pmx0 6 72 1 &pmx0 7 73 1>; 456 &pmx0 6 72 1 &pmx0 7 73 1>;
448 interrupt-controller; 457 interrupt-controller;
449 #interrupt-cells = <2>; 458 #interrupt-cells = <2>;
450 clocks = <&pclk>; 459 clocks = <&clock HI3620_GPIOCLK16>;
451 clock-names = "apb_pclk"; 460 clock-names = "apb_pclk";
452 }; 461 };
453 462
@@ -462,7 +471,7 @@
462 &pmx0 6 80 1 &pmx0 7 81 1>; 471 &pmx0 6 80 1 &pmx0 7 81 1>;
463 interrupt-controller; 472 interrupt-controller;
464 #interrupt-cells = <2>; 473 #interrupt-cells = <2>;
465 clocks = <&pclk>; 474 clocks = <&clock HI3620_GPIOCLK17>;
466 clock-names = "apb_pclk"; 475 clock-names = "apb_pclk";
467 }; 476 };
468 477
@@ -477,7 +486,7 @@
477 &pmx0 6 86 1 &pmx0 7 87 1>; 486 &pmx0 6 86 1 &pmx0 7 87 1>;
478 interrupt-controller; 487 interrupt-controller;
479 #interrupt-cells = <2>; 488 #interrupt-cells = <2>;
480 clocks = <&pclk>; 489 clocks = <&clock HI3620_GPIOCLK18>;
481 clock-names = "apb_pclk"; 490 clock-names = "apb_pclk";
482 }; 491 };
483 492
@@ -491,7 +500,7 @@
491 &pmx0 3 88 1>; 500 &pmx0 3 88 1>;
492 interrupt-controller; 501 interrupt-controller;
493 #interrupt-cells = <2>; 502 #interrupt-cells = <2>;
494 clocks = <&pclk>; 503 clocks = <&clock HI3620_GPIOCLK19>;
495 clock-names = "apb_pclk"; 504 clock-names = "apb_pclk";
496 }; 505 };
497 506
@@ -505,7 +514,7 @@
505 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; 514 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
506 interrupt-controller; 515 interrupt-controller;
507 #interrupt-cells = <2>; 516 #interrupt-cells = <2>;
508 clocks = <&pclk>; 517 clocks = <&clock HI3620_GPIOCLK20>;
509 clock-names = "apb_pclk"; 518 clock-names = "apb_pclk";
510 }; 519 };
511 520
@@ -518,7 +527,7 @@
518 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; 527 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
519 interrupt-controller; 528 interrupt-controller;
520 #interrupt-cells = <2>; 529 #interrupt-cells = <2>;
521 clocks = <&pclk>; 530 clocks = <&clock HI3620_GPIOCLK21>;
522 clock-names = "apb_pclk"; 531 clock-names = "apb_pclk";
523 }; 532 };
524 533
diff --git a/arch/arm/boot/dts/hi4511.dts b/arch/arm/boot/dts/hi4511.dts
index 96e69abfcdaa..fe623928f687 100644
--- a/arch/arm/boot/dts/hi4511.dts
+++ b/arch/arm/boot/dts/hi4511.dts
@@ -8,7 +8,8 @@
8 */ 8 */
9 9
10/dts-v1/; 10/dts-v1/;
11/include/ "hi3620.dtsi" 11
12#include "hi3620.dtsi"
12 13
13/ { 14/ {
14 model = "Hisilicon Hi4511 Development Board"; 15 model = "Hisilicon Hi4511 Development Board";