diff options
-rw-r--r-- | drivers/net/tg3.c | 26 | ||||
-rw-r--r-- | drivers/net/tg3.h | 8 | ||||
-rw-r--r-- | include/linux/mii.h | 2 |
3 files changed, 14 insertions, 22 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 7b1e2abf0cea..da5e9105b9f4 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -861,7 +861,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |||
861 | int ret; | 861 | int ret; |
862 | 862 | ||
863 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && | 863 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
864 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) | 864 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
865 | return 0; | 865 | return 0; |
866 | 866 | ||
867 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | 867 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
@@ -1981,15 +1981,14 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |||
1981 | 1981 | ||
1982 | /* Set full-duplex, 1000 mbps. */ | 1982 | /* Set full-duplex, 1000 mbps. */ |
1983 | tg3_writephy(tp, MII_BMCR, | 1983 | tg3_writephy(tp, MII_BMCR, |
1984 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | 1984 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1985 | 1985 | ||
1986 | /* Set to master mode. */ | 1986 | /* Set to master mode. */ |
1987 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | 1987 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1988 | continue; | 1988 | continue; |
1989 | 1989 | ||
1990 | tg3_writephy(tp, MII_TG3_CTRL, | 1990 | tg3_writephy(tp, MII_CTRL1000, |
1991 | (MII_TG3_CTRL_AS_MASTER | | 1991 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); |
1992 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | ||
1993 | 1992 | ||
1994 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); | 1993 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
1995 | if (err) | 1994 | if (err) |
@@ -2014,7 +2013,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |||
2014 | 2013 | ||
2015 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | 2014 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
2016 | 2015 | ||
2017 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | 2016 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
2018 | 2017 | ||
2019 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | 2018 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { |
2020 | reg32 &= ~0x3000; | 2019 | reg32 &= ~0x3000; |
@@ -2958,16 +2957,15 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) | |||
2958 | 2957 | ||
2959 | new_adv = 0; | 2958 | new_adv = 0; |
2960 | if (advertise & ADVERTISED_1000baseT_Half) | 2959 | if (advertise & ADVERTISED_1000baseT_Half) |
2961 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | 2960 | new_adv |= ADVERTISE_1000HALF; |
2962 | if (advertise & ADVERTISED_1000baseT_Full) | 2961 | if (advertise & ADVERTISED_1000baseT_Full) |
2963 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | 2962 | new_adv |= ADVERTISE_1000FULL; |
2964 | 2963 | ||
2965 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | 2964 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
2966 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | 2965 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) |
2967 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | 2966 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
2968 | MII_TG3_CTRL_ENABLE_AS_MASTER); | ||
2969 | 2967 | ||
2970 | err = tg3_writephy(tp, MII_TG3_CTRL, new_adv); | 2968 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
2971 | if (err) | 2969 | if (err) |
2972 | goto done; | 2970 | goto done; |
2973 | 2971 | ||
@@ -3076,7 +3074,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp) | |||
3076 | break; | 3074 | break; |
3077 | 3075 | ||
3078 | case SPEED_1000: | 3076 | case SPEED_1000: |
3079 | bmcr |= TG3_BMCR_SPEED1000; | 3077 | bmcr |= BMCR_SPEED1000; |
3080 | break; | 3078 | break; |
3081 | } | 3079 | } |
3082 | 3080 | ||
@@ -3153,7 +3151,7 @@ static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) | |||
3153 | if (mask & ADVERTISED_1000baseT_Full) | 3151 | if (mask & ADVERTISED_1000baseT_Full) |
3154 | all_mask |= ADVERTISE_1000FULL; | 3152 | all_mask |= ADVERTISE_1000FULL; |
3155 | 3153 | ||
3156 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) | 3154 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
3157 | return 0; | 3155 | return 0; |
3158 | 3156 | ||
3159 | if ((tg3_ctrl & all_mask) != all_mask) | 3157 | if ((tg3_ctrl & all_mask) != all_mask) |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 54441a346cb3..bedc3b4557b5 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -2152,14 +2152,6 @@ | |||
2152 | 2152 | ||
2153 | 2153 | ||
2154 | /*** Tigon3 specific PHY MII registers. ***/ | 2154 | /*** Tigon3 specific PHY MII registers. ***/ |
2155 | #define TG3_BMCR_SPEED1000 0x0040 | ||
2156 | |||
2157 | #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ | ||
2158 | #define MII_TG3_CTRL_ADV_1000_HALF 0x0100 | ||
2159 | #define MII_TG3_CTRL_ADV_1000_FULL 0x0200 | ||
2160 | #define MII_TG3_CTRL_AS_MASTER 0x0800 | ||
2161 | #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 | ||
2162 | |||
2163 | #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */ | 2155 | #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */ |
2164 | #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000 | 2156 | #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000 |
2165 | #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */ | 2157 | #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */ |
diff --git a/include/linux/mii.h b/include/linux/mii.h index 359fba880274..103113a2fd18 100644 --- a/include/linux/mii.h +++ b/include/linux/mii.h | |||
@@ -128,6 +128,8 @@ | |||
128 | /* 1000BASE-T Control register */ | 128 | /* 1000BASE-T Control register */ |
129 | #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ | 129 | #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ |
130 | #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ | 130 | #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ |
131 | #define CTL1000_AS_MASTER 0x0800 | ||
132 | #define CTL1000_ENABLE_MASTER 0x1000 | ||
131 | 133 | ||
132 | /* 1000BASE-T Status register */ | 134 | /* 1000BASE-T Status register */ |
133 | #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ | 135 | #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ |