4 files changed, 68 insertions, 142 deletions
diff --git a/include/asm-x86/Kbuild b/include/asm-x86/Kbuild
index 24bbde8c1b72..559830ece755 100644
--- a/include/asm-x86/Kbuild
+++ b/include/asm-x86/Kbuild
@@ -1,8 +1,6 @@
 include include/asm-generic/Kbuild.asm
 header-y += boot.h
-header-y += debugreg_32.h
-header-y += debugreg_64.h
 header-y += debugreg.h
 header-y += ldt.h
 header-y += msr-index.h
diff --git a/include/asm-x86/debugreg.h b/include/asm-x86/debugreg.h
index b6ce7e4fa002..c6344d572b03 100644
--- a/include/asm-x86/debugreg.h
+++ b/include/asm-x86/debugreg.h
@@ -1,13 +1,70 @@
-#ifdef __KERNEL__
+#ifndef _ASM_X86_DEBUGREG_H
-# ifdef CONFIG_X86_32
+#define _ASM_X86_DEBUGREG_H
-#  include "debugreg_32.h"
-# else
-#  include "debugreg_64.h"
+/* Indicate the register numbers for a number of the specific
-# endif
+   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
+#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
+#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
+#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
+#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
+/* Define a few things for the status register.  We can use this to determine
+   which debugging register was responsible for the trap.  The other bits
+   are either reserved or not of interest to us. */
+#define DR_TRAP0        (0x1)           /* db0 */
+#define DR_TRAP1        (0x2)           /* db1 */
+#define DR_TRAP2        (0x4)           /* db2 */
+#define DR_TRAP3        (0x8)           /* db3 */
+#define DR_STEP         (0x4000)        /* single-step */
+#define DR_SWITCH       (0x8000)        /* task switch */
+/* Now define a bunch of things for manipulating the control register.
+   The top two bytes of the control register consist of 4 fields of 4
+   bits - each field corresponds to one of the four debug registers,
+   and indicates what types of access we trap on, and how large the data
+   field is that we are looking at */
+#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
+#define DR_CONTROL_SIZE 4   /* 4 control bits per register */
+#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
+#define DR_RW_WRITE (0x1)
+#define DR_RW_READ (0x3)
+#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
+#define DR_LEN_2 (0x4)
+#define DR_LEN_4 (0xC)
+#define DR_LEN_8 (0x8)
+/* The low byte to the control register determine which registers are
+   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
+   that the processor will reset the bit after a task switch and the other
+   is global meaning that we have to explicitly reset the bit.  With linux,
+   you can use either one, since we explicitly zero the register when we enter
+   kernel mode. */
+#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
+#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
+#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
+#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
+#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
+/* The second byte to the control register has a few special things.
+   We can slow the instruction pipeline for instructions coming via the
+   gdt or the ldt if we want to.  I am not sure why this is an advantage */
+#ifdef __i386__
+#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
 #else
-# ifdef __i386__
+#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
-#  include "debugreg_32.h"
+#endif
-# else
-#  include "debugreg_64.h"
+#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
-# endif
+#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
 #endif
diff --git a/include/asm-x86/debugreg_32.h b/include/asm-x86/debugreg_32.h
deleted file mode 100644
index f0b2b06ae0f7..000000000000
--- a/include/asm-x86/debugreg_32.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef _I386_DEBUGREG_H
-#define _I386_DEBUGREG_H
-/* Indicate the register numbers for a number of the specific
-   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
-#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
-#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
-#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
-#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
-/* Define a few things for the status register.  We can use this to determine
-   which debugging register was responsible for the trap.  The other bits
-   are either reserved or not of interest to us. */
-#define DR_TRAP0        (0x1)           /* db0 */
-#define DR_TRAP1        (0x2)           /* db1 */
-#define DR_TRAP2        (0x4)           /* db2 */
-#define DR_TRAP3        (0x8)           /* db3 */
-#define DR_STEP         (0x4000)        /* single-step */
-#define DR_SWITCH       (0x8000)        /* task switch */
-/* Now define a bunch of things for manipulating the control register.
-   The top two bytes of the control register consist of 4 fields of 4
-   bits - each field corresponds to one of the four debug registers,
-   and indicates what types of access we trap on, and how large the data
-   field is that we are looking at */
-#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
-#define DR_CONTROL_SIZE 4   /* 4 control bits per register */
-#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
-#define DR_RW_WRITE (0x1)
-#define DR_RW_READ (0x3)
-#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
-#define DR_LEN_2 (0x4)
-#define DR_LEN_4 (0xC)
-/* The low byte to the control register determine which registers are
-   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
-   that the processor will reset the bit after a task switch and the other
-   is global meaning that we have to explicitly reset the bit.  With linux,
-   you can use either one, since we explicitly zero the register when we enter
-   kernel mode. */
-#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
-#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
-#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
-#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
-#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
-/* The second byte to the control register has a few special things.
-   We can slow the instruction pipeline for instructions coming via the
-   gdt or the ldt if we want to.  I am not sure why this is an advantage */
-#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
-#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
-#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
-#endif
diff --git a/include/asm-x86/debugreg_64.h b/include/asm-x86/debugreg_64.h
deleted file mode 100644
index bd1aab1d8c4a..000000000000
--- a/include/asm-x86/debugreg_64.h
+++ /dev/null
@@ -1,65 +0,0 @@
-#ifndef _X86_64_DEBUGREG_H
-#define _X86_64_DEBUGREG_H
-/* Indicate the register numbers for a number of the specific
-   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
-#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
-#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
-#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
-#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
-/* Define a few things for the status register.  We can use this to determine
-   which debugging register was responsible for the trap.  The other bits
-   are either reserved or not of interest to us. */
-#define DR_TRAP0        (0x1)           /* db0 */
-#define DR_TRAP1        (0x2)           /* db1 */
-#define DR_TRAP2        (0x4)           /* db2 */
-#define DR_TRAP3        (0x8)           /* db3 */
-#define DR_STEP         (0x4000)        /* single-step */
-#define DR_SWITCH       (0x8000)        /* task switch */
-/* Now define a bunch of things for manipulating the control register.
-   The top two bytes of the control register consist of 4 fields of 4
-   bits - each field corresponds to one of the four debug registers,
-   and indicates what types of access we trap on, and how large the data
-   field is that we are looking at */
-#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
-#define DR_CONTROL_SIZE 4   /* 4 control bits per register */
-#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
-#define DR_RW_WRITE (0x1)
-#define DR_RW_READ (0x3)
-#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
-#define DR_LEN_2 (0x4)
-#define DR_LEN_4 (0xC)
-#define DR_LEN_8 (0x8)
-/* The low byte to the control register determine which registers are
-   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
-   that the processor will reset the bit after a task switch and the other
-   is global meaning that we have to explicitly reset the bit.  With linux,
-   you can use either one, since we explicitly zero the register when we enter
-   kernel mode. */
-#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
-#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
-#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
-#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
-#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
-/* The second byte to the control register has a few special things.
-   We can slow the instruction pipeline for instructions coming via the
-   gdt or the ldt if we want to.  I am not sure why this is an advantage */
-#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
-#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
-#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
-#endif

diff --git a/include/asm-x86/Kbuild b/include/asm-x86/Kbuild index 24bbde8c1b72..559830ece755 100644 --- a/include/asm-x86/Kbuild +++ b/include/asm-x86/Kbuild
@@ -1,8 +1,6 @@
1	include include/asm-generic/Kbuild.asm	1	include include/asm-generic/Kbuild.asm
2		2
3	header-y += boot.h	3	header-y += boot.h
4	header-y += debugreg_32.h
5	header-y += debugreg_64.h
6	header-y += debugreg.h	4	header-y += debugreg.h
7	header-y += ldt.h	5	header-y += ldt.h
8	header-y += msr-index.h	6	header-y += msr-index.h


diff --git a/include/asm-x86/debugreg.h b/include/asm-x86/debugreg.h index b6ce7e4fa002..c6344d572b03 100644 --- a/include/asm-x86/debugreg.h +++ b/include/asm-x86/debugreg.h
@@ -1,13 +1,70 @@
1	#ifdef __KERNEL__	1	#ifndef _ASM_X86_DEBUGREG_H
2	# ifdef CONFIG_X86_32	2	#define _ASM_X86_DEBUGREG_H
3	# include "debugreg_32.h"	3
4	# else	4
5	# include "debugreg_64.h"	5	/* Indicate the register numbers for a number of the specific
6	# endif	6	debug registers. Registers 0-3 contain the addresses we wish to trap on */
		7	#define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
		8	#define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
		9
		10	#define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
		11	#define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
		12
		13	/* Define a few things for the status register. We can use this to determine
		14	which debugging register was responsible for the trap. The other bits
		15	are either reserved or not of interest to us. */
		16
		17	#define DR_TRAP0 (0x1) /* db0 */
		18	#define DR_TRAP1 (0x2) /* db1 */
		19	#define DR_TRAP2 (0x4) /* db2 */
		20	#define DR_TRAP3 (0x8) /* db3 */
		21
		22	#define DR_STEP (0x4000) /* single-step */
		23	#define DR_SWITCH (0x8000) /* task switch */
		24
		25	/* Now define a bunch of things for manipulating the control register.
		26	The top two bytes of the control register consist of 4 fields of 4
		27	bits - each field corresponds to one of the four debug registers,
		28	and indicates what types of access we trap on, and how large the data
		29	field is that we are looking at */
		30
		31	#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
		32	#define DR_CONTROL_SIZE 4 /* 4 control bits per register */
		33
		34	#define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
		35	#define DR_RW_WRITE (0x1)
		36	#define DR_RW_READ (0x3)
		37
		38	#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
		39	#define DR_LEN_2 (0x4)
		40	#define DR_LEN_4 (0xC)
		41	#define DR_LEN_8 (0x8)
		42
		43	/* The low byte to the control register determine which registers are
		44	enabled. There are 4 fields of two bits. One bit is "local", meaning
		45	that the processor will reset the bit after a task switch and the other
		46	is global meaning that we have to explicitly reset the bit. With linux,
		47	you can use either one, since we explicitly zero the register when we enter
		48	kernel mode. */
		49
		50	#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
		51	#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
		52	#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
		53
		54	#define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
		55	#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
		56
		57	/* The second byte to the control register has a few special things.
		58	We can slow the instruction pipeline for instructions coming via the
		59	gdt or the ldt if we want to. I am not sure why this is an advantage */
		60
		61	#ifdef __i386__
		62	#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
7	#else	63	#else
8	# ifdef __i386__	64	#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
9	# include "debugreg_32.h"	65	#endif
10	# else	66
11	# include "debugreg_64.h"	67	#define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
12	# endif	68	#define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
		69
13	#endif	70	#endif


diff --git a/include/asm-x86/debugreg_32.h b/include/asm-x86/debugreg_32.h deleted file mode 100644 index f0b2b06ae0f7..000000000000 --- a/include/asm-x86/debugreg_32.h +++ /dev/null
@@ -1,64 +0,0 @@
1	#ifndef _I386_DEBUGREG_H
2	#define _I386_DEBUGREG_H
3
4
5	/* Indicate the register numbers for a number of the specific
6	debug registers. Registers 0-3 contain the addresses we wish to trap on */
7	#define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
8	#define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
9
10	#define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
11	#define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
12
13	/* Define a few things for the status register. We can use this to determine
14	which debugging register was responsible for the trap. The other bits
15	are either reserved or not of interest to us. */
16
17	#define DR_TRAP0 (0x1) /* db0 */
18	#define DR_TRAP1 (0x2) /* db1 */
19	#define DR_TRAP2 (0x4) /* db2 */
20	#define DR_TRAP3 (0x8) /* db3 */
21
22	#define DR_STEP (0x4000) /* single-step */
23	#define DR_SWITCH (0x8000) /* task switch */
24
25	/* Now define a bunch of things for manipulating the control register.
26	The top two bytes of the control register consist of 4 fields of 4
27	bits - each field corresponds to one of the four debug registers,
28	and indicates what types of access we trap on, and how large the data
29	field is that we are looking at */
30
31	#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
32	#define DR_CONTROL_SIZE 4 /* 4 control bits per register */
33
34	#define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
35	#define DR_RW_WRITE (0x1)
36	#define DR_RW_READ (0x3)
37
38	#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
39	#define DR_LEN_2 (0x4)
40	#define DR_LEN_4 (0xC)
41
42	/* The low byte to the control register determine which registers are
43	enabled. There are 4 fields of two bits. One bit is "local", meaning
44	that the processor will reset the bit after a task switch and the other
45	is global meaning that we have to explicitly reset the bit. With linux,
46	you can use either one, since we explicitly zero the register when we enter
47	kernel mode. */
48
49	#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
50	#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
51	#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
52
53	#define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
54	#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
55
56	/* The second byte to the control register has a few special things.
57	We can slow the instruction pipeline for instructions coming via the
58	gdt or the ldt if we want to. I am not sure why this is an advantage */
59
60	#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
61	#define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
62	#define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
63
64	#endif


diff --git a/include/asm-x86/debugreg_64.h b/include/asm-x86/debugreg_64.h deleted file mode 100644 index bd1aab1d8c4a..000000000000 --- a/include/asm-x86/debugreg_64.h +++ /dev/null
@@ -1,65 +0,0 @@
1	#ifndef _X86_64_DEBUGREG_H
2	#define _X86_64_DEBUGREG_H
3
4
5	/* Indicate the register numbers for a number of the specific
6	debug registers. Registers 0-3 contain the addresses we wish to trap on */
7	#define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
8	#define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
9
10	#define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
11	#define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
12
13	/* Define a few things for the status register. We can use this to determine
14	which debugging register was responsible for the trap. The other bits
15	are either reserved or not of interest to us. */
16
17	#define DR_TRAP0 (0x1) /* db0 */
18	#define DR_TRAP1 (0x2) /* db1 */
19	#define DR_TRAP2 (0x4) /* db2 */
20	#define DR_TRAP3 (0x8) /* db3 */
21
22	#define DR_STEP (0x4000) /* single-step */
23	#define DR_SWITCH (0x8000) /* task switch */
24
25	/* Now define a bunch of things for manipulating the control register.
26	The top two bytes of the control register consist of 4 fields of 4
27	bits - each field corresponds to one of the four debug registers,
28	and indicates what types of access we trap on, and how large the data
29	field is that we are looking at */
30
31	#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
32	#define DR_CONTROL_SIZE 4 /* 4 control bits per register */
33
34	#define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
35	#define DR_RW_WRITE (0x1)
36	#define DR_RW_READ (0x3)
37
38	#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
39	#define DR_LEN_2 (0x4)
40	#define DR_LEN_4 (0xC)
41	#define DR_LEN_8 (0x8)
42
43	/* The low byte to the control register determine which registers are
44	enabled. There are 4 fields of two bits. One bit is "local", meaning
45	that the processor will reset the bit after a task switch and the other
46	is global meaning that we have to explicitly reset the bit. With linux,
47	you can use either one, since we explicitly zero the register when we enter
48	kernel mode. */
49
50	#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
51	#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
52	#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
53
54	#define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
55	#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
56
57	/* The second byte to the control register has a few special things.
58	We can slow the instruction pipeline for instructions coming via the
59	gdt or the ldt if we want to. I am not sure why this is an advantage */
60
61	#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
62	#define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
63	#define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
64
65	#endif