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-rw-r--r--drivers/net/ixgbe/ixgbe.h29
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c603
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_nl.c13
-rw-r--r--drivers/net/ixgbe/ixgbe_ethtool.c544
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c89
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h28
6 files changed, 850 insertions, 456 deletions
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index d5674fc8bc02..d6bfb2f6ba86 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -482,6 +482,17 @@ struct ixgbe_adapter {
482 struct vf_macvlans vf_mvs; 482 struct vf_macvlans vf_mvs;
483 struct vf_macvlans *mv_list; 483 struct vf_macvlans *mv_list;
484 bool antispoofing_enabled; 484 bool antispoofing_enabled;
485
486 struct hlist_head fdir_filter_list;
487 union ixgbe_atr_input fdir_mask;
488 int fdir_filter_count;
489};
490
491struct ixgbe_fdir_filter {
492 struct hlist_node fdir_node;
493 union ixgbe_atr_input filter;
494 u16 sw_idx;
495 u16 action;
485}; 496};
486 497
487enum ixbge_state_t { 498enum ixbge_state_t {
@@ -543,16 +554,22 @@ extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
543extern void ixgbe_write_eitr(struct ixgbe_q_vector *); 554extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
544extern int ethtool_ioctl(struct ifreq *ifr); 555extern int ethtool_ioctl(struct ifreq *ifr);
545extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 556extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
546extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc); 557extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
547extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc); 558extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
548extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 559extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
549 union ixgbe_atr_hash_dword input, 560 union ixgbe_atr_hash_dword input,
550 union ixgbe_atr_hash_dword common, 561 union ixgbe_atr_hash_dword common,
551 u8 queue); 562 u8 queue);
552extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 563extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
553 union ixgbe_atr_input *input, 564 union ixgbe_atr_input *input_mask);
554 struct ixgbe_atr_input_masks *input_masks, 565extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
555 u16 soft_id, u8 queue); 566 union ixgbe_atr_input *input,
567 u16 soft_id, u8 queue);
568extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
569 union ixgbe_atr_input *input,
570 u16 soft_id);
571extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
572 union ixgbe_atr_input *mask);
556extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 573extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
557 struct ixgbe_ring *ring); 574 struct ixgbe_ring *ring);
558extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter, 575extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index 4a6826bf9338..3b3dd4df4c5c 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -1107,115 +1107,87 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1107} 1107}
1108 1108
1109/** 1109/**
1110 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1110 * ixgbe_set_fdir_rxpba_82599 - Initialize Flow Director Rx packet buffer
1111 * @hw: pointer to hardware structure 1111 * @hw: pointer to hardware structure
1112 * @pballoc: which mode to allocate filters with 1112 * @pballoc: which mode to allocate filters with
1113 **/ 1113 **/
1114s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) 1114static s32 ixgbe_set_fdir_rxpba_82599(struct ixgbe_hw *hw, const u32 pballoc)
1115{ 1115{
1116 u32 fdirctrl = 0; 1116 u32 fdir_pbsize = hw->mac.rx_pb_size << IXGBE_RXPBSIZE_SHIFT;
1117 u32 current_rxpbsize = 0;
1117 int i; 1118 int i;
1118 1119
1119 /* Send interrupt when 64 filters are left */ 1120 /* reserve space for Flow Director filters */
1120 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1121
1122 /* Set the maximum length per hash bucket to 0xA filters */
1123 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1124
1125 switch (pballoc) { 1121 switch (pballoc) {
1126 case IXGBE_FDIR_PBALLOC_64K: 1122 case IXGBE_FDIR_PBALLOC_256K:
1127 /* 8k - 1 signature filters */ 1123 fdir_pbsize -= 256 << IXGBE_RXPBSIZE_SHIFT;
1128 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1129 break; 1124 break;
1130 case IXGBE_FDIR_PBALLOC_128K: 1125 case IXGBE_FDIR_PBALLOC_128K:
1131 /* 16k - 1 signature filters */ 1126 fdir_pbsize -= 128 << IXGBE_RXPBSIZE_SHIFT;
1132 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1133 break; 1127 break;
1134 case IXGBE_FDIR_PBALLOC_256K: 1128 case IXGBE_FDIR_PBALLOC_64K:
1135 /* 32k - 1 signature filters */ 1129 fdir_pbsize -= 64 << IXGBE_RXPBSIZE_SHIFT;
1136 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1137 break; 1130 break;
1131 case IXGBE_FDIR_PBALLOC_NONE:
1138 default: 1132 default:
1139 /* bad value */ 1133 return IXGBE_ERR_PARAM;
1140 return IXGBE_ERR_CONFIG;
1141 } 1134 }
1142 1135
1143 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1136 /* determine current RX packet buffer size */
1144 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1137 for (i = 0; i < 8; i++)
1138 current_rxpbsize += IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
1145 1139
1140 /* if there is already room for the filters do nothing */
1141 if (current_rxpbsize <= fdir_pbsize)
1142 return 0;
1146 1143
1147 /* Prime the keys for hashing */ 1144 if (current_rxpbsize > hw->mac.rx_pb_size) {
1148 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1145 /*
1149 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1146 * if rxpbsize is greater than max then HW max the Rx buffer
1150 1147 * sizes are unconfigured or misconfigured since HW default is
1151 /* 1148 * to give the full buffer to each traffic class resulting in
1152 * Poll init-done after we write the register. Estimated times: 1149 * the total size being buffer size 8x actual size
1153 * 10G: PBALLOC = 11b, timing is 60us 1150 *
1154 * 1G: PBALLOC = 11b, timing is 600us 1151 * This assumes no DCB since the RXPBSIZE registers appear to
1155 * 100M: PBALLOC = 11b, timing is 6ms 1152 * be unconfigured.
1156 * 1153 */
1157 * Multiple these timings by 4 if under full Rx load 1154 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), fdir_pbsize);
1158 * 1155 for (i = 1; i < 8; i++)
1159 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1156 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1160 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1157 } else {
1161 * this might not finish in our poll time, but we can live with that 1158 /*
1162 * for now. 1159 * Since the Rx packet buffer appears to have already been
1163 */ 1160 * configured we need to shrink each packet buffer by enough
1164 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1161 * to make room for the filters. As such we take each rxpbsize
1165 IXGBE_WRITE_FLUSH(hw); 1162 * value and multiply it by a fraction representing the size
1166 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1163 * needed over the size we currently have.
1167 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1164 *
1168 IXGBE_FDIRCTRL_INIT_DONE) 1165 * We need to reduce fdir_pbsize and current_rxpbsize to
1169 break; 1166 * 1/1024 of their original values in order to avoid
1170 usleep_range(1000, 2000); 1167 * overflowing the u32 being used to store rxpbsize.
1168 */
1169 fdir_pbsize >>= IXGBE_RXPBSIZE_SHIFT;
1170 current_rxpbsize >>= IXGBE_RXPBSIZE_SHIFT;
1171 for (i = 0; i < 8; i++) {
1172 u32 rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
1173 rxpbsize *= fdir_pbsize;
1174 rxpbsize /= current_rxpbsize;
1175 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
1176 }
1171 } 1177 }
1172 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1173 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1174 1178
1175 return 0; 1179 return 0;
1176} 1180}
1177 1181
1178/** 1182/**
1179 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1183 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1180 * @hw: pointer to hardware structure 1184 * @hw: pointer to hardware structure
1181 * @pballoc: which mode to allocate filters with 1185 * @fdirctrl: value to write to flow director control register
1182 **/ 1186 **/
1183s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) 1187static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1184{ 1188{
1185 u32 fdirctrl = 0;
1186 int i; 1189 int i;
1187 1190
1188 /* Send interrupt when 64 filters are left */
1189 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1190
1191 /* Initialize the drop queue to Rx queue 127 */
1192 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1193
1194 switch (pballoc) {
1195 case IXGBE_FDIR_PBALLOC_64K:
1196 /* 2k - 1 perfect filters */
1197 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1198 break;
1199 case IXGBE_FDIR_PBALLOC_128K:
1200 /* 4k - 1 perfect filters */
1201 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1202 break;
1203 case IXGBE_FDIR_PBALLOC_256K:
1204 /* 8k - 1 perfect filters */
1205 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1206 break;
1207 default:
1208 /* bad value */
1209 return IXGBE_ERR_CONFIG;
1210 }
1211
1212 /* Turn perfect match filtering on */
1213 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1214 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1215
1216 /* Move the flexible bytes to use the ethertype - shift 6 words */
1217 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1218
1219 /* Prime the keys for hashing */ 1191 /* Prime the keys for hashing */
1220 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1192 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1221 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1193 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
@@ -1233,10 +1205,6 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1233 * this might not finish in our poll time, but we can live with that 1205 * this might not finish in our poll time, but we can live with that
1234 * for now. 1206 * for now.
1235 */ 1207 */
1236
1237 /* Set the maximum length per hash bucket to 0xA filters */
1238 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1239
1240 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1208 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1241 IXGBE_WRITE_FLUSH(hw); 1209 IXGBE_WRITE_FLUSH(hw);
1242 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1210 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
@@ -1245,101 +1213,77 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1245 break; 1213 break;
1246 usleep_range(1000, 2000); 1214 usleep_range(1000, 2000);
1247 } 1215 }
1248 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1249 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1250 1216
1251 return 0; 1217 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1218 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1252} 1219}
1253 1220
1254
1255/** 1221/**
1256 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR 1222 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1257 * @stream: input bitstream to compute the hash on 1223 * @hw: pointer to hardware structure
1258 * @key: 32-bit hash key 1224 * @fdirctrl: value to write to flow director control register, initially
1225 * contains just the value of the Rx packet buffer allocation
1259 **/ 1226 **/
1260static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, 1227s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1261 u32 key)
1262{ 1228{
1263 /* 1229 s32 err;
1264 * The algorithm is as follows:
1265 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1266 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1267 * and A[n] x B[n] is bitwise AND between same length strings
1268 *
1269 * K[n] is 16 bits, defined as:
1270 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1271 * for n modulo 32 < 15, K[n] =
1272 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1273 *
1274 * S[n] is 16 bits, defined as:
1275 * for n >= 15, S[n] = S[n:n - 15]
1276 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1277 *
1278 * To simplify for programming, the algorithm is implemented
1279 * in software this way:
1280 *
1281 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1282 *
1283 * for (i = 0; i < 352; i+=32)
1284 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1285 *
1286 * lo_hash_dword[15:0] ^= Stream[15:0];
1287 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1288 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1289 *
1290 * hi_hash_dword[31:0] ^= Stream[351:320];
1291 *
1292 * if(key[0])
1293 * hash[15:0] ^= Stream[15:0];
1294 *
1295 * for (i = 0; i < 16; i++) {
1296 * if (key[i])
1297 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1298 * if (key[i + 16])
1299 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1300 * }
1301 *
1302 */
1303 __be32 common_hash_dword = 0;
1304 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1305 u32 hash_result = 0;
1306 u8 i;
1307 1230
1308 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1231 /* Before enabling Flow Director, verify the Rx Packet Buffer size */
1309 flow_vm_vlan = ntohl(atr_input->dword_stream[0]); 1232 err = ixgbe_set_fdir_rxpba_82599(hw, fdirctrl);
1233 if (err)
1234 return err;
1310 1235
1311 /* generate common hash dword */ 1236 /*
1312 for (i = 10; i; i -= 2) 1237 * Continue setup of fdirctrl register bits:
1313 common_hash_dword ^= atr_input->dword_stream[i] ^ 1238 * Move the flexible bytes to use the ethertype - shift 6 words
1314 atr_input->dword_stream[i - 1]; 1239 * Set the maximum length per hash bucket to 0xA filters
1240 * Send interrupt when 64 filters are left
1241 */
1242 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1243 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1244 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1315 1245
1316 hi_hash_dword = ntohl(common_hash_dword); 1246 /* write hashes and fdirctrl register, poll for completion */
1247 ixgbe_fdir_enable_82599(hw, fdirctrl);
1317 1248
1318 /* low dword is word swapped version of common */ 1249 return 0;
1319 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1250}
1320 1251
1321 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1252/**
1322 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1253 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1254 * @hw: pointer to hardware structure
1255 * @fdirctrl: value to write to flow director control register, initially
1256 * contains just the value of the Rx packet buffer allocation
1257 **/
1258s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1259{
1260 s32 err;
1323 1261
1324 /* Process bits 0 and 16 */ 1262 /* Before enabling Flow Director, verify the Rx Packet Buffer size */
1325 if (key & 0x0001) hash_result ^= lo_hash_dword; 1263 err = ixgbe_set_fdir_rxpba_82599(hw, fdirctrl);
1326 if (key & 0x00010000) hash_result ^= hi_hash_dword; 1264 if (err)
1265 return err;
1327 1266
1328 /* 1267 /*
1329 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1268 * Continue setup of fdirctrl register bits:
1330 * delay this because bit 0 of the stream should not be processed 1269 * Turn perfect match filtering on
1331 * so we do not add the vlan until after bit 0 was processed 1270 * Report hash in RSS field of Rx wb descriptor
1271 * Initialize the drop queue
1272 * Move the flexible bytes to use the ethertype - shift 6 words
1273 * Set the maximum length per hash bucket to 0xA filters
1274 * Send interrupt when 64 (0x4 * 16) filters are left
1332 */ 1275 */
1333 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1276 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1277 IXGBE_FDIRCTRL_REPORT_STATUS |
1278 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1279 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1280 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1281 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1334 1282
1283 /* write hashes and fdirctrl register, poll for completion */
1284 ixgbe_fdir_enable_82599(hw, fdirctrl);
1335 1285
1336 /* process the remaining 30 bits in the key 2 bits at a time */ 1286 return 0;
1337 for (i = 15; i; i-- ) {
1338 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1339 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
1340 }
1341
1342 return hash_result & IXGBE_ATR_HASH_MASK;
1343} 1287}
1344 1288
1345/* 1289/*
@@ -1476,7 +1420,6 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1476 */ 1420 */
1477 fdirhashcmd = (u64)fdircmd << 32; 1421 fdirhashcmd = (u64)fdircmd << 32;
1478 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1422 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1479
1480 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1423 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1481 1424
1482 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1425 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
@@ -1484,6 +1427,101 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1484 return 0; 1427 return 0;
1485} 1428}
1486 1429
1430#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1431do { \
1432 u32 n = (_n); \
1433 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1434 bucket_hash ^= lo_hash_dword >> n; \
1435 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1436 bucket_hash ^= hi_hash_dword >> n; \
1437} while (0);
1438
1439/**
1440 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1441 * @atr_input: input bitstream to compute the hash on
1442 * @input_mask: mask for the input bitstream
1443 *
1444 * This function serves two main purposes. First it applys the input_mask
1445 * to the atr_input resulting in a cleaned up atr_input data stream.
1446 * Secondly it computes the hash and stores it in the bkt_hash field at
1447 * the end of the input byte stream. This way it will be available for
1448 * future use without needing to recompute the hash.
1449 **/
1450void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1451 union ixgbe_atr_input *input_mask)
1452{
1453
1454 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1455 u32 bucket_hash = 0;
1456
1457 /* Apply masks to input data */
1458 input->dword_stream[0] &= input_mask->dword_stream[0];
1459 input->dword_stream[1] &= input_mask->dword_stream[1];
1460 input->dword_stream[2] &= input_mask->dword_stream[2];
1461 input->dword_stream[3] &= input_mask->dword_stream[3];
1462 input->dword_stream[4] &= input_mask->dword_stream[4];
1463 input->dword_stream[5] &= input_mask->dword_stream[5];
1464 input->dword_stream[6] &= input_mask->dword_stream[6];
1465 input->dword_stream[7] &= input_mask->dword_stream[7];
1466 input->dword_stream[8] &= input_mask->dword_stream[8];
1467 input->dword_stream[9] &= input_mask->dword_stream[9];
1468 input->dword_stream[10] &= input_mask->dword_stream[10];
1469
1470 /* record the flow_vm_vlan bits as they are a key part to the hash */
1471 flow_vm_vlan = ntohl(input->dword_stream[0]);
1472
1473 /* generate common hash dword */
1474 hi_hash_dword = ntohl(input->dword_stream[1] ^
1475 input->dword_stream[2] ^
1476 input->dword_stream[3] ^
1477 input->dword_stream[4] ^
1478 input->dword_stream[5] ^
1479 input->dword_stream[6] ^
1480 input->dword_stream[7] ^
1481 input->dword_stream[8] ^
1482 input->dword_stream[9] ^
1483 input->dword_stream[10]);
1484
1485 /* low dword is word swapped version of common */
1486 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1487
1488 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1489 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1490
1491 /* Process bits 0 and 16 */
1492 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1493
1494 /*
1495 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1496 * delay this because bit 0 of the stream should not be processed
1497 * so we do not add the vlan until after bit 0 was processed
1498 */
1499 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1500
1501 /* Process remaining 30 bit of the key */
1502 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1503 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1504 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1505 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1506 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1507 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1508 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1509 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1510 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1511 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1515 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1516 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1517
1518 /*
1519 * Limit hash to 13 bits since max bucket count is 8K.
1520 * Store result at the end of the input stream.
1521 */
1522 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1523}
1524
1487/** 1525/**
1488 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1526 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1489 * @input_mask: mask to be bit swapped 1527 * @input_mask: mask to be bit swapped
@@ -1493,11 +1531,11 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1493 * generate a correctly swapped value we need to bit swap the mask and that 1531 * generate a correctly swapped value we need to bit swap the mask and that
1494 * is what is accomplished by this function. 1532 * is what is accomplished by this function.
1495 **/ 1533 **/
1496static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks) 1534static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1497{ 1535{
1498 u32 mask = ntohs(input_masks->dst_port_mask); 1536 u32 mask = ntohs(input_mask->formatted.dst_port);
1499 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1537 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1500 mask |= ntohs(input_masks->src_port_mask); 1538 mask |= ntohs(input_mask->formatted.src_port);
1501 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1539 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1502 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1540 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1503 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1541 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
@@ -1519,52 +1557,14 @@ static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1519 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1557 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1520 1558
1521#define IXGBE_STORE_AS_BE16(_value) \ 1559#define IXGBE_STORE_AS_BE16(_value) \
1522 (((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1560 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1523 1561
1524/** 1562s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1525 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1563 union ixgbe_atr_input *input_mask)
1526 * @hw: pointer to hardware structure
1527 * @input: input bitstream
1528 * @input_masks: bitwise masks for relevant fields
1529 * @soft_id: software index into the silicon hash tables for filter storage
1530 * @queue: queue index to direct traffic to
1531 *
1532 * Note that the caller to this function must lock before calling, since the
1533 * hardware writes must be protected from one another.
1534 **/
1535s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1536 union ixgbe_atr_input *input,
1537 struct ixgbe_atr_input_masks *input_masks,
1538 u16 soft_id, u8 queue)
1539{ 1564{
1540 u32 fdirhash; 1565 /* mask IPv6 since it is currently not supported */
1541 u32 fdircmd; 1566 u32 fdirm = IXGBE_FDIRM_DIPv6;
1542 u32 fdirport, fdirtcpm; 1567 u32 fdirtcpm;
1543 u32 fdirvlan;
1544 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1545 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1546 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
1547
1548 /*
1549 * Check flow_type formatting, and bail out before we touch the hardware
1550 * if there's a configuration issue
1551 */
1552 switch (input->formatted.flow_type) {
1553 case IXGBE_ATR_FLOW_TYPE_IPV4:
1554 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1555 fdirm |= IXGBE_FDIRM_L4P;
1556 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1557 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1558 hw_dbg(hw, " Error on src/dst port mask\n");
1559 return IXGBE_ERR_CONFIG;
1560 }
1561 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1562 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1563 break;
1564 default:
1565 hw_dbg(hw, " Error on flow type input\n");
1566 return IXGBE_ERR_CONFIG;
1567 }
1568 1568
1569 /* 1569 /*
1570 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1570 * Program the relevant mask registers. If src/dst_port or src/dst_addr
@@ -1576,41 +1576,71 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1576 * point in time. 1576 * point in time.
1577 */ 1577 */
1578 1578
1579 /* Program FDIRM */ 1579 /* verify bucket hash is cleared on hash generation */
1580 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) { 1580 if (input_mask->formatted.bkt_hash)
1581 case 0xEFFF: 1581 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1582 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */ 1582
1583 fdirm &= ~IXGBE_FDIRM_VLANID; 1583 /* Program FDIRM and verify partial masks */
1584 case 0xE000: 1584 switch (input_mask->formatted.vm_pool & 0x7F) {
1585 /* Unmask VLAN prio - bit 1 */ 1585 case 0x0:
1586 fdirm &= ~IXGBE_FDIRM_VLANP; 1586 fdirm |= IXGBE_FDIRM_POOL;
1587 case 0x7F:
1587 break; 1588 break;
1588 case 0x0FFF: 1589 default:
1589 /* Unmask VLAN ID - bit 0 */ 1590 hw_dbg(hw, " Error on vm pool mask\n");
1590 fdirm &= ~IXGBE_FDIRM_VLANID; 1591 return IXGBE_ERR_CONFIG;
1592 }
1593
1594 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1595 case 0x0:
1596 fdirm |= IXGBE_FDIRM_L4P;
1597 if (input_mask->formatted.dst_port ||
1598 input_mask->formatted.src_port) {
1599 hw_dbg(hw, " Error on src/dst port mask\n");
1600 return IXGBE_ERR_CONFIG;
1601 }
1602 case IXGBE_ATR_L4TYPE_MASK:
1591 break; 1603 break;
1604 default:
1605 hw_dbg(hw, " Error on flow type mask\n");
1606 return IXGBE_ERR_CONFIG;
1607 }
1608
1609 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1592 case 0x0000: 1610 case 0x0000:
1593 /* do nothing, vlans already masked */ 1611 /* mask VLAN ID, fall through to mask VLAN priority */
1612 fdirm |= IXGBE_FDIRM_VLANID;
1613 case 0x0FFF:
1614 /* mask VLAN priority */
1615 fdirm |= IXGBE_FDIRM_VLANP;
1616 break;
1617 case 0xE000:
1618 /* mask VLAN ID only, fall through */
1619 fdirm |= IXGBE_FDIRM_VLANID;
1620 case 0xEFFF:
1621 /* no VLAN fields masked */
1594 break; 1622 break;
1595 default: 1623 default:
1596 hw_dbg(hw, " Error on VLAN mask\n"); 1624 hw_dbg(hw, " Error on VLAN mask\n");
1597 return IXGBE_ERR_CONFIG; 1625 return IXGBE_ERR_CONFIG;
1598 } 1626 }
1599 1627
1600 if (input_masks->flex_mask & 0xFFFF) { 1628 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1601 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) { 1629 case 0x0000:
1602 hw_dbg(hw, " Error on flexible byte mask\n"); 1630 /* Mask Flex Bytes, fall through */
1603 return IXGBE_ERR_CONFIG; 1631 fdirm |= IXGBE_FDIRM_FLEX;
1604 } 1632 case 0xFFFF:
1605 /* Unmask Flex Bytes - bit 4 */ 1633 break;
1606 fdirm &= ~IXGBE_FDIRM_FLEX; 1634 default:
1635 hw_dbg(hw, " Error on flexible byte mask\n");
1636 return IXGBE_ERR_CONFIG;
1607 } 1637 }
1608 1638
1609 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1639 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1610 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1640 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1611 1641
1612 /* store the TCP/UDP port masks, bit reversed from port layout */ 1642 /* store the TCP/UDP port masks, bit reversed from port layout */
1613 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks); 1643 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1614 1644
1615 /* write both the same so that UDP and TCP use the same mask */ 1645 /* write both the same so that UDP and TCP use the same mask */
1616 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1646 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
@@ -1618,24 +1648,32 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1618 1648
1619 /* store source and destination IP masks (big-enian) */ 1649 /* store source and destination IP masks (big-enian) */
1620 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1621 ~input_masks->src_ip_mask[0]); 1651 ~input_mask->formatted.src_ip[0]);
1622 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1623 ~input_masks->dst_ip_mask[0]); 1653 ~input_mask->formatted.dst_ip[0]);
1624 1654
1625 /* Apply masks to input data */ 1655 return 0;
1626 input->formatted.vlan_id &= input_masks->vlan_id_mask; 1656}
1627 input->formatted.flex_bytes &= input_masks->flex_mask;
1628 input->formatted.src_port &= input_masks->src_port_mask;
1629 input->formatted.dst_port &= input_masks->dst_port_mask;
1630 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1631 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1632 1657
1633 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1658s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1634 fdirvlan = 1659 union ixgbe_atr_input *input,
1635 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes)); 1660 u16 soft_id, u8 queue)
1636 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1661{
1637 fdirvlan |= ntohs(input->formatted.vlan_id); 1662 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1638 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1663
1664 /* currently IPv6 is not supported, must be programmed with 0 */
1665 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1666 input->formatted.src_ip[0]);
1667 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1668 input->formatted.src_ip[1]);
1669 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1670 input->formatted.src_ip[2]);
1671
1672 /* record the source address (big-endian) */
1673 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1674
1675 /* record the first 32 bits of the destination address (big-endian) */
1676 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1639 1677
1640 /* record source and destination port (little-endian)*/ 1678 /* record source and destination port (little-endian)*/
1641 fdirport = ntohs(input->formatted.dst_port); 1679 fdirport = ntohs(input->formatted.dst_port);
@@ -1643,29 +1681,80 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1643 fdirport |= ntohs(input->formatted.src_port); 1681 fdirport |= ntohs(input->formatted.src_port);
1644 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1682 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1645 1683
1646 /* record the first 32 bits of the destination address (big-endian) */ 1684 /* record vlan (little-endian) and flex_bytes(big-endian) */
1647 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1685 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1686 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1687 fdirvlan |= ntohs(input->formatted.vlan_id);
1688 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1648 1689
1649 /* record the source address (big-endian) */ 1690 /* configure FDIRHASH register */
1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1691 fdirhash = input->formatted.bkt_hash;
1692 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1693 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1694
1695 /*
1696 * flush all previous writes to make certain registers are
1697 * programmed prior to issuing the command
1698 */
1699 IXGBE_WRITE_FLUSH(hw);
1651 1700
1652 /* configure FDIRCMD register */ 1701 /* configure FDIRCMD register */
1653 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1702 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1654 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1703 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1704 if (queue == IXGBE_FDIR_DROP_QUEUE)
1705 fdircmd |= IXGBE_FDIRCMD_DROP;
1655 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1706 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1656 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1707 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1708 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1657 1709
1658 /* we only want the bucket hash so drop the upper 16 bits */
1659 fdirhash = ixgbe_atr_compute_hash_82599(input,
1660 IXGBE_ATR_BUCKET_HASH_KEY);
1661 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1662
1663 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1664 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1710 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1665 1711
1666 return 0; 1712 return 0;
1667} 1713}
1668 1714
1715s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1716 union ixgbe_atr_input *input,
1717 u16 soft_id)
1718{
1719 u32 fdirhash;
1720 u32 fdircmd = 0;
1721 u32 retry_count;
1722 s32 err = 0;
1723
1724 /* configure FDIRHASH register */
1725 fdirhash = input->formatted.bkt_hash;
1726 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1727 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1728
1729 /* flush hash to HW */
1730 IXGBE_WRITE_FLUSH(hw);
1731
1732 /* Query if filter is present */
1733 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1734
1735 for (retry_count = 10; retry_count; retry_count--) {
1736 /* allow 10us for query to process */
1737 udelay(10);
1738 /* verify query completed successfully */
1739 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1740 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1741 break;
1742 }
1743
1744 if (!retry_count)
1745 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1746
1747 /* if filter exists in hardware then remove it */
1748 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1749 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1750 IXGBE_WRITE_FLUSH(hw);
1751 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1752 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1753 }
1754
1755 return err;
1756}
1757
1669/** 1758/**
1670 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1759 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1671 * @hw: pointer to hardware structure 1760 * @hw: pointer to hardware structure
diff --git a/drivers/net/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ixgbe/ixgbe_dcb_nl.c
index 08c7aebe99f5..bd2d75265389 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c
@@ -114,11 +114,12 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
114 u8 err = 0; 114 u8 err = 0;
115 struct ixgbe_adapter *adapter = netdev_priv(netdev); 115 struct ixgbe_adapter *adapter = netdev_priv(netdev);
116 116
117 /* verify there is something to do, if not then exit */
118 if (!!state != !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
119 return err;
120
117 if (state > 0) { 121 if (state > 0) {
118 /* Turn on DCB */ 122 /* Turn on DCB */
119 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
120 goto out;
121
122 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 123 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
123 e_err(drv, "Enable failed, needs MSI-X\n"); 124 e_err(drv, "Enable failed, needs MSI-X\n");
124 err = 1; 125 err = 1;
@@ -143,9 +144,6 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
143 ixgbe_setup_tc(netdev, MAX_TRAFFIC_CLASS); 144 ixgbe_setup_tc(netdev, MAX_TRAFFIC_CLASS);
144 } else { 145 } else {
145 /* Turn off DCB */ 146 /* Turn off DCB */
146 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
147 goto out;
148
149 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 147 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
150 adapter->temp_dcb_cfg.pfc_mode_enable = false; 148 adapter->temp_dcb_cfg.pfc_mode_enable = false;
151 adapter->dcb_cfg.pfc_mode_enable = false; 149 adapter->dcb_cfg.pfc_mode_enable = false;
@@ -153,7 +151,8 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
153 switch (adapter->hw.mac.type) { 151 switch (adapter->hw.mac.type) {
154 case ixgbe_mac_82599EB: 152 case ixgbe_mac_82599EB:
155 case ixgbe_mac_X540: 153 case ixgbe_mac_X540:
156 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 154 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
155 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
157 break; 156 break;
158 default: 157 default:
159 break; 158 break;
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index 4950d03d3ef8..074e9baf069a 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -442,20 +442,67 @@ static int ixgbe_set_pauseparam(struct net_device *netdev,
442 return 0; 442 return 0;
443} 443}
444 444
445static void ixgbe_do_reset(struct net_device *netdev)
446{
447 struct ixgbe_adapter *adapter = netdev_priv(netdev);
448
449 if (netif_running(netdev))
450 ixgbe_reinit_locked(adapter);
451 else
452 ixgbe_reset(adapter);
453}
454
445static u32 ixgbe_get_rx_csum(struct net_device *netdev) 455static u32 ixgbe_get_rx_csum(struct net_device *netdev)
446{ 456{
447 struct ixgbe_adapter *adapter = netdev_priv(netdev); 457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
448 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED; 458 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
449} 459}
450 460
461static void ixgbe_set_rsc(struct ixgbe_adapter *adapter)
462{
463 int i;
464
465 for (i = 0; i < adapter->num_rx_queues; i++) {
466 struct ixgbe_ring *ring = adapter->rx_ring[i];
467 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
468 set_ring_rsc_enabled(ring);
469 ixgbe_configure_rscctl(adapter, ring);
470 } else {
471 ixgbe_clear_rscctl(adapter, ring);
472 }
473 }
474}
475
451static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data) 476static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
452{ 477{
453 struct ixgbe_adapter *adapter = netdev_priv(netdev); 478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
454 if (data) 479 bool need_reset = false;
480
481 if (data) {
455 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; 482 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
456 else 483 } else {
457 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED; 484 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
458 485
486 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {
487 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
488 netdev->features &= ~NETIF_F_LRO;
489 }
490
491 switch (adapter->hw.mac.type) {
492 case ixgbe_mac_X540:
493 ixgbe_set_rsc(adapter);
494 break;
495 case ixgbe_mac_82599EB:
496 need_reset = true;
497 break;
498 default:
499 break;
500 }
501 }
502
503 if (need_reset)
504 ixgbe_do_reset(netdev);
505
459 return 0; 506 return 0;
460} 507}
461 508
@@ -2234,12 +2281,8 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
2234 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2281 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2235 * also locks in RSC enable/disable which requires reset 2282 * also locks in RSC enable/disable which requires reset
2236 */ 2283 */
2237 if (need_reset) { 2284 if (need_reset)
2238 if (netif_running(netdev)) 2285 ixgbe_do_reset(netdev);
2239 ixgbe_reinit_locked(adapter);
2240 else
2241 ixgbe_reset(adapter);
2242 }
2243 2286
2244 return 0; 2287 return 0;
2245} 2288}
@@ -2281,25 +2324,12 @@ static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2281 } else { 2324 } else {
2282 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED; 2325 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2283 switch (adapter->hw.mac.type) { 2326 switch (adapter->hw.mac.type) {
2327 case ixgbe_mac_X540:
2328 ixgbe_set_rsc(adapter);
2329 break;
2284 case ixgbe_mac_82599EB: 2330 case ixgbe_mac_82599EB:
2285 need_reset = true; 2331 need_reset = true;
2286 break; 2332 break;
2287 case ixgbe_mac_X540: {
2288 int i;
2289 for (i = 0; i < adapter->num_rx_queues; i++) {
2290 struct ixgbe_ring *ring =
2291 adapter->rx_ring[i];
2292 if (adapter->flags2 &
2293 IXGBE_FLAG2_RSC_ENABLED) {
2294 ixgbe_configure_rscctl(adapter,
2295 ring);
2296 } else {
2297 ixgbe_clear_rscctl(adapter,
2298 ring);
2299 }
2300 }
2301 }
2302 break;
2303 default: 2333 default:
2304 break; 2334 break;
2305 } 2335 }
@@ -2310,165 +2340,392 @@ static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2310 * Check if Flow Director n-tuple support was enabled or disabled. If 2340 * Check if Flow Director n-tuple support was enabled or disabled. If
2311 * the state changed, we need to reset. 2341 * the state changed, we need to reset.
2312 */ 2342 */
2313 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) && 2343 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
2314 (!(data & ETH_FLAG_NTUPLE))) { 2344 /* turn off ATR, enable perfect filters and reset */
2315 /* turn off Flow Director perfect, set hash and reset */ 2345 if (data & ETH_FLAG_NTUPLE) {
2346 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2347 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2348 need_reset = true;
2349 }
2350 } else if (!(data & ETH_FLAG_NTUPLE)) {
2351 /* turn off Flow Director, set ATR and reset */
2316 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 2352 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2317 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 2353 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
2318 need_reset = true; 2354 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2319 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) && 2355 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2320 (data & ETH_FLAG_NTUPLE)) {
2321 /* turn off Flow Director hash, enable perfect and reset */
2322 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2323 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2324 need_reset = true; 2356 need_reset = true;
2325 } else {
2326 /* no state change */
2327 } 2357 }
2328 2358
2329 if (need_reset) { 2359 if (need_reset)
2330 if (netif_running(netdev)) 2360 ixgbe_do_reset(netdev);
2331 ixgbe_reinit_locked(adapter); 2361
2332 else 2362 return 0;
2333 ixgbe_reset(adapter); 2363}
2364
2365static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2366 struct ethtool_rxnfc *cmd)
2367{
2368 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2369 struct ethtool_rx_flow_spec *fsp =
2370 (struct ethtool_rx_flow_spec *)&cmd->fs;
2371 struct hlist_node *node, *node2;
2372 struct ixgbe_fdir_filter *rule = NULL;
2373
2374 /* report total rule count */
2375 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2376
2377 hlist_for_each_entry_safe(rule, node, node2,
2378 &adapter->fdir_filter_list, fdir_node) {
2379 if (fsp->location <= rule->sw_idx)
2380 break;
2334 } 2381 }
2335 2382
2383 if (!rule || fsp->location != rule->sw_idx)
2384 return -EINVAL;
2385
2386 /* fill out the flow spec entry */
2387
2388 /* set flow type field */
2389 switch (rule->filter.formatted.flow_type) {
2390 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2391 fsp->flow_type = TCP_V4_FLOW;
2392 break;
2393 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2394 fsp->flow_type = UDP_V4_FLOW;
2395 break;
2396 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2397 fsp->flow_type = SCTP_V4_FLOW;
2398 break;
2399 case IXGBE_ATR_FLOW_TYPE_IPV4:
2400 fsp->flow_type = IP_USER_FLOW;
2401 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2402 fsp->h_u.usr_ip4_spec.proto = 0;
2403 fsp->m_u.usr_ip4_spec.proto = 0;
2404 break;
2405 default:
2406 return -EINVAL;
2407 }
2408
2409 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2410 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2411 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2412 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2413 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2414 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2415 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2416 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2417 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2418 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2419 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2420 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2421 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2422 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2423 fsp->flow_type |= FLOW_EXT;
2424
2425 /* record action */
2426 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2427 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2428 else
2429 fsp->ring_cookie = rule->action;
2430
2336 return 0; 2431 return 0;
2337} 2432}
2338 2433
2339static int ixgbe_set_rx_ntuple(struct net_device *dev, 2434static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2340 struct ethtool_rx_ntuple *cmd) 2435 struct ethtool_rxnfc *cmd,
2436 u32 *rule_locs)
2437{
2438 struct hlist_node *node, *node2;
2439 struct ixgbe_fdir_filter *rule;
2440 int cnt = 0;
2441
2442 /* report total rule count */
2443 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2444
2445 hlist_for_each_entry_safe(rule, node, node2,
2446 &adapter->fdir_filter_list, fdir_node) {
2447 if (cnt == cmd->rule_cnt)
2448 return -EMSGSIZE;
2449 rule_locs[cnt] = rule->sw_idx;
2450 cnt++;
2451 }
2452
2453 return 0;
2454}
2455
2456static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2457 void *rule_locs)
2341{ 2458{
2342 struct ixgbe_adapter *adapter = netdev_priv(dev); 2459 struct ixgbe_adapter *adapter = netdev_priv(dev);
2343 struct ethtool_rx_ntuple_flow_spec *fs = &cmd->fs; 2460 int ret = -EOPNOTSUPP;
2344 union ixgbe_atr_input input_struct;
2345 struct ixgbe_atr_input_masks input_masks;
2346 int target_queue;
2347 int err;
2348 2461
2349 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 2462 switch (cmd->cmd) {
2350 return -EOPNOTSUPP; 2463 case ETHTOOL_GRXRINGS:
2464 cmd->data = adapter->num_rx_queues;
2465 ret = 0;
2466 break;
2467 case ETHTOOL_GRXCLSRLCNT:
2468 cmd->rule_cnt = adapter->fdir_filter_count;
2469 ret = 0;
2470 break;
2471 case ETHTOOL_GRXCLSRULE:
2472 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2473 break;
2474 case ETHTOOL_GRXCLSRLALL:
2475 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd,
2476 (u32 *)rule_locs);
2477 break;
2478 default:
2479 break;
2480 }
2481
2482 return ret;
2483}
2484
2485static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2486 struct ixgbe_fdir_filter *input,
2487 u16 sw_idx)
2488{
2489 struct ixgbe_hw *hw = &adapter->hw;
2490 struct hlist_node *node, *node2, *parent;
2491 struct ixgbe_fdir_filter *rule;
2492 int err = -EINVAL;
2493
2494 parent = NULL;
2495 rule = NULL;
2496
2497 hlist_for_each_entry_safe(rule, node, node2,
2498 &adapter->fdir_filter_list, fdir_node) {
2499 /* hash found, or no matching entry */
2500 if (rule->sw_idx >= sw_idx)
2501 break;
2502 parent = node;
2503 }
2504
2505 /* if there is an old rule occupying our place remove it */
2506 if (rule && (rule->sw_idx == sw_idx)) {
2507 if (!input || (rule->filter.formatted.bkt_hash !=
2508 input->filter.formatted.bkt_hash)) {
2509 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2510 &rule->filter,
2511 sw_idx);
2512 }
2513
2514 hlist_del(&rule->fdir_node);
2515 kfree(rule);
2516 adapter->fdir_filter_count--;
2517 }
2351 2518
2352 /* 2519 /*
2353 * Don't allow programming if the action is a queue greater than 2520 * If no input this was a delete, err should be 0 if a rule was
2354 * the number of online Tx queues. 2521 * successfully found and removed from the list else -EINVAL
2355 */ 2522 */
2356 if ((fs->action >= adapter->num_tx_queues) || 2523 if (!input)
2357 (fs->action < ETHTOOL_RXNTUPLE_ACTION_DROP)) 2524 return err;
2358 return -EINVAL;
2359 2525
2360 memset(&input_struct, 0, sizeof(union ixgbe_atr_input)); 2526 /* initialize node and set software index */
2361 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks)); 2527 INIT_HLIST_NODE(&input->fdir_node);
2362 2528
2363 /* record flow type */ 2529 /* add filter to the list */
2364 switch (fs->flow_type) { 2530 if (parent)
2365 case IPV4_FLOW: 2531 hlist_add_after(parent, &input->fdir_node);
2366 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2532 else
2367 break; 2533 hlist_add_head(&input->fdir_node,
2534 &adapter->fdir_filter_list);
2535
2536 /* update counts */
2537 adapter->fdir_filter_count++;
2538
2539 return 0;
2540}
2541
2542static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2543 u8 *flow_type)
2544{
2545 switch (fsp->flow_type & ~FLOW_EXT) {
2368 case TCP_V4_FLOW: 2546 case TCP_V4_FLOW:
2369 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2547 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2370 break; 2548 break;
2371 case UDP_V4_FLOW: 2549 case UDP_V4_FLOW:
2372 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2550 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2373 break; 2551 break;
2374 case SCTP_V4_FLOW: 2552 case SCTP_V4_FLOW:
2375 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2553 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2376 break; 2554 break;
2377 default: 2555 case IP_USER_FLOW:
2378 return -1; 2556 switch (fsp->h_u.usr_ip4_spec.proto) {
2379 } 2557 case IPPROTO_TCP:
2380 2558 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2381 /* copy vlan tag minus the CFI bit */ 2559 break;
2382 if ((fs->vlan_tag & 0xEFFF) || (~fs->vlan_tag_mask & 0xEFFF)) { 2560 case IPPROTO_UDP:
2383 input_struct.formatted.vlan_id = htons(fs->vlan_tag & 0xEFFF); 2561 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2384 if (!fs->vlan_tag_mask) { 2562 break;
2385 input_masks.vlan_id_mask = htons(0xEFFF); 2563 case IPPROTO_SCTP:
2386 } else { 2564 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2387 switch (~fs->vlan_tag_mask & 0xEFFF) { 2565 break;
2388 /* all of these are valid vlan-mask values */ 2566 case 0:
2389 case 0xEFFF: 2567 if (!fsp->m_u.usr_ip4_spec.proto) {
2390 case 0xE000: 2568 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2391 case 0x0FFF:
2392 case 0x0000:
2393 input_masks.vlan_id_mask =
2394 htons(~fs->vlan_tag_mask);
2395 break; 2569 break;
2396 /* exit with error if vlan-mask is invalid */
2397 default:
2398 e_err(drv, "Partial VLAN ID or "
2399 "priority mask in vlan-mask is not "
2400 "supported by hardware\n");
2401 return -1;
2402 } 2570 }
2571 default:
2572 return 0;
2403 } 2573 }
2574 break;
2575 default:
2576 return 0;
2404 } 2577 }
2405 2578
2406 /* make sure we only use the first 2 bytes of user data */ 2579 return 1;
2407 if ((fs->data & 0xFFFF) || (~fs->data_mask & 0xFFFF)) { 2580}
2408 input_struct.formatted.flex_bytes = htons(fs->data & 0xFFFF); 2581
2409 if (!(fs->data_mask & 0xFFFF)) { 2582static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2410 input_masks.flex_mask = 0xFFFF; 2583 struct ethtool_rxnfc *cmd)
2411 } else if (~fs->data_mask & 0xFFFF) { 2584{
2412 e_err(drv, "Partial user-def-mask is not " 2585 struct ethtool_rx_flow_spec *fsp =
2413 "supported by hardware\n"); 2586 (struct ethtool_rx_flow_spec *)&cmd->fs;
2414 return -1; 2587 struct ixgbe_hw *hw = &adapter->hw;
2415 } 2588 struct ixgbe_fdir_filter *input;
2416 } 2589 union ixgbe_atr_input mask;
2590 int err;
2591
2592 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2593 return -EOPNOTSUPP;
2417 2594
2418 /* 2595 /*
2419 * Copy input into formatted structures 2596 * Don't allow programming if the action is a queue greater than
2420 * 2597 * the number of online Rx queues.
2421 * These assignments are based on the following logic
2422 * If neither input or mask are set assume value is masked out.
2423 * If input is set, but mask is not mask should default to accept all.
2424 * If input is not set, but mask is set then mask likely results in 0.
2425 * If input is set and mask is set then assign both.
2426 */ 2598 */
2427 if (fs->h_u.tcp_ip4_spec.ip4src || ~fs->m_u.tcp_ip4_spec.ip4src) { 2599 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2428 input_struct.formatted.src_ip[0] = fs->h_u.tcp_ip4_spec.ip4src; 2600 (fsp->ring_cookie >= adapter->num_rx_queues))
2429 if (!fs->m_u.tcp_ip4_spec.ip4src) 2601 return -EINVAL;
2430 input_masks.src_ip_mask[0] = 0xFFFFFFFF; 2602
2431 else 2603 /* Don't allow indexes to exist outside of available space */
2432 input_masks.src_ip_mask[0] = 2604 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2433 ~fs->m_u.tcp_ip4_spec.ip4src; 2605 e_err(drv, "Location out of range\n");
2434 } 2606 return -EINVAL;
2435 if (fs->h_u.tcp_ip4_spec.ip4dst || ~fs->m_u.tcp_ip4_spec.ip4dst) {
2436 input_struct.formatted.dst_ip[0] = fs->h_u.tcp_ip4_spec.ip4dst;
2437 if (!fs->m_u.tcp_ip4_spec.ip4dst)
2438 input_masks.dst_ip_mask[0] = 0xFFFFFFFF;
2439 else
2440 input_masks.dst_ip_mask[0] =
2441 ~fs->m_u.tcp_ip4_spec.ip4dst;
2442 } 2607 }
2443 if (fs->h_u.tcp_ip4_spec.psrc || ~fs->m_u.tcp_ip4_spec.psrc) { 2608
2444 input_struct.formatted.src_port = fs->h_u.tcp_ip4_spec.psrc; 2609 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2445 if (!fs->m_u.tcp_ip4_spec.psrc) 2610 if (!input)
2446 input_masks.src_port_mask = 0xFFFF; 2611 return -ENOMEM;
2447 else 2612
2448 input_masks.src_port_mask = ~fs->m_u.tcp_ip4_spec.psrc; 2613 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2614
2615 /* set SW index */
2616 input->sw_idx = fsp->location;
2617
2618 /* record flow type */
2619 if (!ixgbe_flowspec_to_flow_type(fsp,
2620 &input->filter.formatted.flow_type)) {
2621 e_err(drv, "Unrecognized flow type\n");
2622 goto err_out;
2449 } 2623 }
2450 if (fs->h_u.tcp_ip4_spec.pdst || ~fs->m_u.tcp_ip4_spec.pdst) { 2624
2451 input_struct.formatted.dst_port = fs->h_u.tcp_ip4_spec.pdst; 2625 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2452 if (!fs->m_u.tcp_ip4_spec.pdst) 2626 IXGBE_ATR_L4TYPE_MASK;
2453 input_masks.dst_port_mask = 0xFFFF; 2627
2454 else 2628 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2455 input_masks.dst_port_mask = ~fs->m_u.tcp_ip4_spec.pdst; 2629 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2630
2631 /* Copy input into formatted structures */
2632 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2633 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2634 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2635 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2636 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2637 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2638 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2639 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2640
2641 if (fsp->flow_type & FLOW_EXT) {
2642 input->filter.formatted.vm_pool =
2643 (unsigned char)ntohl(fsp->h_ext.data[1]);
2644 mask.formatted.vm_pool =
2645 (unsigned char)ntohl(fsp->m_ext.data[1]);
2646 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2647 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2648 input->filter.formatted.flex_bytes =
2649 fsp->h_ext.vlan_etype;
2650 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2456 } 2651 }
2457 2652
2458 /* determine if we need to drop or route the packet */ 2653 /* determine if we need to drop or route the packet */
2459 if (fs->action == ETHTOOL_RXNTUPLE_ACTION_DROP) 2654 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2460 target_queue = MAX_RX_QUEUES - 1; 2655 input->action = IXGBE_FDIR_DROP_QUEUE;
2461 else 2656 else
2462 target_queue = fs->action; 2657 input->action = fsp->ring_cookie;
2463 2658
2464 spin_lock(&adapter->fdir_perfect_lock); 2659 spin_lock(&adapter->fdir_perfect_lock);
2465 err = ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, 2660
2466 &input_struct, 2661 if (hlist_empty(&adapter->fdir_filter_list)) {
2467 &input_masks, 0, 2662 /* save mask and program input mask into HW */
2468 target_queue); 2663 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2664 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2665 if (err) {
2666 e_err(drv, "Error writing mask\n");
2667 goto err_out_w_lock;
2668 }
2669 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2670 e_err(drv, "Only one mask supported per port\n");
2671 goto err_out_w_lock;
2672 }
2673
2674 /* apply mask and compute/store hash */
2675 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2676
2677 /* program filters to filter memory */
2678 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2679 &input->filter, input->sw_idx,
2680 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2681 IXGBE_FDIR_DROP_QUEUE :
2682 adapter->rx_ring[input->action]->reg_idx);
2683 if (err)
2684 goto err_out_w_lock;
2685
2686 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2687
2469 spin_unlock(&adapter->fdir_perfect_lock); 2688 spin_unlock(&adapter->fdir_perfect_lock);
2470 2689
2471 return err ? -1 : 0; 2690 return err;
2691err_out_w_lock:
2692 spin_unlock(&adapter->fdir_perfect_lock);
2693err_out:
2694 kfree(input);
2695 return -EINVAL;
2696}
2697
2698static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2699 struct ethtool_rxnfc *cmd)
2700{
2701 struct ethtool_rx_flow_spec *fsp =
2702 (struct ethtool_rx_flow_spec *)&cmd->fs;
2703 int err;
2704
2705 spin_lock(&adapter->fdir_perfect_lock);
2706 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2707 spin_unlock(&adapter->fdir_perfect_lock);
2708
2709 return err;
2710}
2711
2712static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2713{
2714 struct ixgbe_adapter *adapter = netdev_priv(dev);
2715 int ret = -EOPNOTSUPP;
2716
2717 switch (cmd->cmd) {
2718 case ETHTOOL_SRXCLSRLINS:
2719 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2720 break;
2721 case ETHTOOL_SRXCLSRLDEL:
2722 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2723 break;
2724 default:
2725 break;
2726 }
2727
2728 return ret;
2472} 2729}
2473 2730
2474static const struct ethtool_ops ixgbe_ethtool_ops = { 2731static const struct ethtool_ops ixgbe_ethtool_ops = {
@@ -2506,7 +2763,8 @@ static const struct ethtool_ops ixgbe_ethtool_ops = {
2506 .set_coalesce = ixgbe_set_coalesce, 2763 .set_coalesce = ixgbe_set_coalesce,
2507 .get_flags = ethtool_op_get_flags, 2764 .get_flags = ethtool_op_get_flags,
2508 .set_flags = ixgbe_set_flags, 2765 .set_flags = ixgbe_set_flags,
2509 .set_rx_ntuple = ixgbe_set_rx_ntuple, 2766 .get_rxnfc = ixgbe_get_rxnfc,
2767 .set_rxnfc = ixgbe_set_rxnfc,
2510}; 2768};
2511 2769
2512void ixgbe_set_ethtool_ops(struct net_device *netdev) 2770void ixgbe_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 4cd66ae70ccc..2496a27b5991 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -54,11 +54,10 @@ char ixgbe_driver_name[] = "ixgbe";
54static const char ixgbe_driver_string[] = 54static const char ixgbe_driver_string[] =
55 "Intel(R) 10 Gigabit PCI Express Network Driver"; 55 "Intel(R) 10 Gigabit PCI Express Network Driver";
56#define MAJ 3 56#define MAJ 3
57#define MIN 3 57#define MIN 4
58#define BUILD 8 58#define BUILD 8
59#define KFIX 2
60#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 59#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k" __stringify(KFIX) 60 __stringify(BUILD) "-k"
62const char ixgbe_driver_version[] = DRV_VERSION; 61const char ixgbe_driver_version[] = DRV_VERSION;
63static const char ixgbe_copyright[] = 62static const char ixgbe_copyright[] =
64 "Copyright (c) 1999-2011 Intel Corporation."; 63 "Copyright (c) 1999-2011 Intel Corporation.";
@@ -1555,9 +1554,8 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1555 q_vector->eitr = adapter->rx_eitr_param; 1554 q_vector->eitr = adapter->rx_eitr_param;
1556 1555
1557 ixgbe_write_eitr(q_vector); 1556 ixgbe_write_eitr(q_vector);
1558 /* If Flow Director is enabled, set interrupt affinity */ 1557 /* If ATR is enabled, set interrupt affinity */
1559 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || 1558 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1560 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1561 /* 1559 /*
1562 * Allocate the affinity_hint cpumask, assign the mask 1560 * Allocate the affinity_hint cpumask, assign the mask
1563 * for this vector, and set our affinity_hint for 1561 * for this vector, and set our affinity_hint for
@@ -2468,8 +2466,7 @@ static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2468 default: 2466 default:
2469 break; 2467 break;
2470 } 2468 }
2471 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 2469 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2472 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2473 mask |= IXGBE_EIMS_FLOW_DIR; 2470 mask |= IXGBE_EIMS_FLOW_DIR;
2474 2471
2475 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2472 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
@@ -3743,6 +3740,30 @@ static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3743 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL); 3740 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3744} 3741}
3745 3742
3743static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3744{
3745 struct ixgbe_hw *hw = &adapter->hw;
3746 struct hlist_node *node, *node2;
3747 struct ixgbe_fdir_filter *filter;
3748
3749 spin_lock(&adapter->fdir_perfect_lock);
3750
3751 if (!hlist_empty(&adapter->fdir_filter_list))
3752 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3753
3754 hlist_for_each_entry_safe(filter, node, node2,
3755 &adapter->fdir_filter_list, fdir_node) {
3756 ixgbe_fdir_write_perfect_filter_82599(hw,
3757 &filter->filter,
3758 filter->sw_idx,
3759 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3760 IXGBE_FDIR_DROP_QUEUE :
3761 adapter->rx_ring[filter->action]->reg_idx);
3762 }
3763
3764 spin_unlock(&adapter->fdir_perfect_lock);
3765}
3766
3746static void ixgbe_configure(struct ixgbe_adapter *adapter) 3767static void ixgbe_configure(struct ixgbe_adapter *adapter)
3747{ 3768{
3748 struct net_device *netdev = adapter->netdev; 3769 struct net_device *netdev = adapter->netdev;
@@ -3768,7 +3789,9 @@ static void ixgbe_configure(struct ixgbe_adapter *adapter)
3768 adapter->atr_sample_rate; 3789 adapter->atr_sample_rate;
3769 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); 3790 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3770 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 3791 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3771 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); 3792 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3793 adapter->fdir_pballoc);
3794 ixgbe_fdir_filter_restore(adapter);
3772 } 3795 }
3773 ixgbe_configure_virtualization(adapter); 3796 ixgbe_configure_virtualization(adapter);
3774 3797
@@ -4145,6 +4168,23 @@ static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4145 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 4168 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4146} 4169}
4147 4170
4171static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4172{
4173 struct hlist_node *node, *node2;
4174 struct ixgbe_fdir_filter *filter;
4175
4176 spin_lock(&adapter->fdir_perfect_lock);
4177
4178 hlist_for_each_entry_safe(filter, node, node2,
4179 &adapter->fdir_filter_list, fdir_node) {
4180 hlist_del(&filter->fdir_node);
4181 kfree(filter);
4182 }
4183 adapter->fdir_filter_count = 0;
4184
4185 spin_unlock(&adapter->fdir_perfect_lock);
4186}
4187
4148void ixgbe_down(struct ixgbe_adapter *adapter) 4188void ixgbe_down(struct ixgbe_adapter *adapter)
4149{ 4189{
4150 struct net_device *netdev = adapter->netdev; 4190 struct net_device *netdev = adapter->netdev;
@@ -4334,15 +4374,13 @@ static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4334 f_fdir->mask = 0; 4374 f_fdir->mask = 0;
4335 4375
4336 /* Flow Director must have RSS enabled */ 4376 /* Flow Director must have RSS enabled */
4337 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && 4377 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4338 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 4378 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4339 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4340 adapter->num_tx_queues = f_fdir->indices; 4379 adapter->num_tx_queues = f_fdir->indices;
4341 adapter->num_rx_queues = f_fdir->indices; 4380 adapter->num_rx_queues = f_fdir->indices;
4342 ret = true; 4381 ret = true;
4343 } else { 4382 } else {
4344 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 4383 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4345 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4346 } 4384 }
4347 return ret; 4385 return ret;
4348} 4386}
@@ -4372,12 +4410,12 @@ static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4372 4410
4373 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { 4411 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4374 e_info(probe, "FCoE enabled with RSS\n"); 4412 e_info(probe, "FCoE enabled with RSS\n");
4375 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || 4413 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4376 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4377 ixgbe_set_fdir_queues(adapter); 4414 ixgbe_set_fdir_queues(adapter);
4378 else 4415 else
4379 ixgbe_set_rss_queues(adapter); 4416 ixgbe_set_rss_queues(adapter);
4380 } 4417 }
4418
4381 /* adding FCoE rx rings to the end */ 4419 /* adding FCoE rx rings to the end */
4382 f->mask = adapter->num_rx_queues; 4420 f->mask = adapter->num_rx_queues;
4383 adapter->num_rx_queues += f->indices; 4421 adapter->num_rx_queues += f->indices;
@@ -4670,9 +4708,8 @@ static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4670 int i; 4708 int i;
4671 bool ret = false; 4709 bool ret = false;
4672 4710
4673 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && 4711 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4674 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || 4712 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4675 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4676 for (i = 0; i < adapter->num_rx_queues; i++) 4713 for (i = 0; i < adapter->num_rx_queues; i++)
4677 adapter->rx_ring[i]->reg_idx = i; 4714 adapter->rx_ring[i]->reg_idx = i;
4678 for (i = 0; i < adapter->num_tx_queues; i++) 4715 for (i = 0; i < adapter->num_tx_queues; i++)
@@ -4701,8 +4738,7 @@ static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4701 return false; 4738 return false;
4702 4739
4703 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { 4740 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4704 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || 4741 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4705 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4706 ixgbe_cache_ring_fdir(adapter); 4742 ixgbe_cache_ring_fdir(adapter);
4707 else 4743 else
4708 ixgbe_cache_ring_rss(adapter); 4744 ixgbe_cache_ring_rss(adapter);
@@ -4882,14 +4918,12 @@ static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4882 4918
4883 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 4919 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4884 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; 4920 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4885 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE | 4921 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4886 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4887 e_err(probe, 4922 e_err(probe,
4888 "Flow Director is not supported while multiple " 4923 "ATR is not supported while multiple "
4889 "queues are disabled. Disabling Flow Director\n"); 4924 "queues are disabled. Disabling Flow Director\n");
4890 } 4925 }
4891 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 4926 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4892 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4893 adapter->atr_sample_rate = 0; 4927 adapter->atr_sample_rate = 0;
4894 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4928 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4895 ixgbe_disable_sriov(adapter); 4929 ixgbe_disable_sriov(adapter);
@@ -5140,7 +5174,7 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5140 adapter->atr_sample_rate = 20; 5174 adapter->atr_sample_rate = 20;
5141 adapter->ring_feature[RING_F_FDIR].indices = 5175 adapter->ring_feature[RING_F_FDIR].indices =
5142 IXGBE_MAX_FDIR_INDICES; 5176 IXGBE_MAX_FDIR_INDICES;
5143 adapter->fdir_pballoc = 0; 5177 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5144#ifdef IXGBE_FCOE 5178#ifdef IXGBE_FCOE
5145 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 5179 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5146 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5180 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
@@ -5537,6 +5571,8 @@ static int ixgbe_close(struct net_device *netdev)
5537 ixgbe_down(adapter); 5571 ixgbe_down(adapter);
5538 ixgbe_free_irq(adapter); 5572 ixgbe_free_irq(adapter);
5539 5573
5574 ixgbe_fdir_filter_exit(adapter);
5575
5540 ixgbe_free_all_tx_resources(adapter); 5576 ixgbe_free_all_tx_resources(adapter);
5541 ixgbe_free_all_rx_resources(adapter); 5577 ixgbe_free_all_rx_resources(adapter);
5542 5578
@@ -7676,7 +7712,8 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
7676 7712
7677 /* Inform firmware of driver version */ 7713 /* Inform firmware of driver version */
7678 if (hw->mac.ops.set_fw_drv_ver) 7714 if (hw->mac.ops.set_fw_drv_ver)
7679 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD, KFIX); 7715 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7716 FW_CEM_UNUSED_VER);
7680 7717
7681 /* add san mac addr to netdev */ 7718 /* add san mac addr to netdev */
7682 ixgbe_add_sanmac_netdev(netdev); 7719 ixgbe_add_sanmac_netdev(netdev);
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 9a499a61d141..1eefc0c68409 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -2056,9 +2056,10 @@ enum {
2056#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4)) 2056#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
2057 2057
2058enum ixgbe_fdir_pballoc_type { 2058enum ixgbe_fdir_pballoc_type {
2059 IXGBE_FDIR_PBALLOC_64K = 0, 2059 IXGBE_FDIR_PBALLOC_NONE = 0,
2060 IXGBE_FDIR_PBALLOC_128K, 2060 IXGBE_FDIR_PBALLOC_64K = 1,
2061 IXGBE_FDIR_PBALLOC_256K, 2061 IXGBE_FDIR_PBALLOC_128K = 2,
2062 IXGBE_FDIR_PBALLOC_256K = 3,
2062}; 2063};
2063#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16 2064#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
2064 2065
@@ -2112,7 +2113,7 @@ enum ixgbe_fdir_pballoc_type {
2112#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2113#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2113#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2114#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2114#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2115#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2115#define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH 0x00000007 2116#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
2116#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2117#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2117#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2118#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2118#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2119#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
@@ -2131,6 +2132,8 @@ enum ixgbe_fdir_pballoc_type {
2131#define IXGBE_FDIR_INIT_DONE_POLL 10 2132#define IXGBE_FDIR_INIT_DONE_POLL 10
2132#define IXGBE_FDIRCMD_CMD_POLL 10 2133#define IXGBE_FDIRCMD_CMD_POLL 10
2133 2134
2135#define IXGBE_FDIR_DROP_QUEUE 127
2136
2134/* Manageablility Host Interface defines */ 2137/* Manageablility Host Interface defines */
2135#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 2138#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
2136#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 2139#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
@@ -2140,7 +2143,8 @@ enum ixgbe_fdir_pballoc_type {
2140#define FW_CEM_HDR_LEN 0x4 2143#define FW_CEM_HDR_LEN 0x4
2141#define FW_CEM_CMD_DRIVER_INFO 0xDD 2144#define FW_CEM_CMD_DRIVER_INFO 0xDD
2142#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 2145#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
2143#define FW_CEM_CMD_RESERVED 0X0 2146#define FW_CEM_CMD_RESERVED 0x0
2147#define FW_CEM_UNUSED_VER 0x0
2144#define FW_CEM_MAX_RETRIES 3 2148#define FW_CEM_MAX_RETRIES 3
2145#define FW_CEM_RESP_STATUS_SUCCESS 0x1 2149#define FW_CEM_RESP_STATUS_SUCCESS 0x1
2146 2150
@@ -2350,7 +2354,7 @@ union ixgbe_atr_input {
2350 * src_port - 2 bytes 2354 * src_port - 2 bytes
2351 * dst_port - 2 bytes 2355 * dst_port - 2 bytes
2352 * flex_bytes - 2 bytes 2356 * flex_bytes - 2 bytes
2353 * rsvd0 - 2 bytes - space reserved must be 0. 2357 * bkt_hash - 2 bytes
2354 */ 2358 */
2355 struct { 2359 struct {
2356 u8 vm_pool; 2360 u8 vm_pool;
@@ -2361,7 +2365,7 @@ union ixgbe_atr_input {
2361 __be16 src_port; 2365 __be16 src_port;
2362 __be16 dst_port; 2366 __be16 dst_port;
2363 __be16 flex_bytes; 2367 __be16 flex_bytes;
2364 __be16 rsvd0; 2368 __be16 bkt_hash;
2365 } formatted; 2369 } formatted;
2366 __be32 dword_stream[11]; 2370 __be32 dword_stream[11];
2367}; 2371};
@@ -2382,16 +2386,6 @@ union ixgbe_atr_hash_dword {
2382 __be32 dword; 2386 __be32 dword;
2383}; 2387};
2384 2388
2385struct ixgbe_atr_input_masks {
2386 __be16 rsvd0;
2387 __be16 vlan_id_mask;
2388 __be32 dst_ip_mask[4];
2389 __be32 src_ip_mask[4];
2390 __be16 src_port_mask;
2391 __be16 dst_port_mask;
2392 __be16 flex_mask;
2393};
2394
2395enum ixgbe_eeprom_type { 2389enum ixgbe_eeprom_type {
2396 ixgbe_eeprom_uninitialized = 0, 2390 ixgbe_eeprom_uninitialized = 0,
2397 ixgbe_eeprom_spi, 2391 ixgbe_eeprom_spi,
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 15:42:50 -0500