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-rw-r--r--arch/arm/mach-at91/at91sam9260.c2
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c2
-rw-r--r--arch/arm/mach-at91/include/mach/at91_dbgu.h27
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h8
-rw-r--r--arch/arm/mach-at91/include/mach/debug-macro.S14
5 files changed, 28 insertions, 25 deletions
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 164873fa965f..57974b19d7a7 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -324,7 +324,7 @@ static void __init at91sam9xe_map_io(void)
324{ 324{
325 unsigned long cidr, sram_size; 325 unsigned long cidr, sram_size;
326 326
327 cidr = at91_sys_read(AT91_DBGU_CIDR); 327 cidr = dbgu_readl(AT91_DBGU, CIDR);
328 328
329 switch (cidr & AT91_CIDR_SRAMSIZ) { 329 switch (cidr & AT91_CIDR_SRAMSIZ) {
330 case AT91_CIDR_SRAMSIZ_32K: 330 case AT91_CIDR_SRAMSIZ_32K:
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 9c87bacd10f9..0788adb1b53c 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -283,7 +283,7 @@ static void __init at91sam9rl_map_io(void)
283{ 283{
284 unsigned long cidr, sram_size; 284 unsigned long cidr, sram_size;
285 285
286 cidr = at91_sys_read(AT91_DBGU_CIDR); 286 cidr = dbgu_readl(AT91_DBGU, CIDR);
287 287
288 switch (cidr & AT91_CIDR_SRAMSIZ) { 288 switch (cidr & AT91_CIDR_SRAMSIZ) {
289 case AT91_CIDR_SRAMSIZ_32K: 289 case AT91_CIDR_SRAMSIZ_32K:
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 6dcaa7716871..dbfe455a4c41 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -16,22 +16,25 @@
16#ifndef AT91_DBGU_H 16#ifndef AT91_DBGU_H
17#define AT91_DBGU_H 17#define AT91_DBGU_H
18 18
19#define dbgu_readl(dbgu, field) \
20 __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
21
19#ifdef AT91_DBGU 22#ifdef AT91_DBGU
20#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ 23#define AT91_DBGU_CR (0x00) /* Control Register */
21#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ 24#define AT91_DBGU_MR (0x04) /* Mode Register */
22#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ 25#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
23#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ 26#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
24#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ 27#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
25#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ 28#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
26#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ 29#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
27#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ 30#define AT91_DBGU_SR (0x14) /* Status Register */
28#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ 31#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
29#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ 32#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
30#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ 33#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
31 34
32#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ 35#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
33#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ 36#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
34#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ 37#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
35#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ 38#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
36 39
37#endif /* AT91_DBGU */ 40#endif /* AT91_DBGU */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index df966c2bc2d4..3cf69198f8a4 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -41,12 +41,12 @@
41 41
42static inline unsigned long at91_cpu_identify(void) 42static inline unsigned long at91_cpu_identify(void)
43{ 43{
44 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); 44 return (dbgu_readl(AT91_DBGU, CIDR) & ~AT91_CIDR_VERSION);
45} 45}
46 46
47static inline unsigned long at91_cpu_fully_identify(void) 47static inline unsigned long at91_cpu_fully_identify(void)
48{ 48{
49 return at91_sys_read(AT91_DBGU_CIDR); 49 return dbgu_readl(AT91_DBGU, CIDR);
50} 50}
51 51
52#define ARCH_EXID_AT91SAM9M11 0x00000001 52#define ARCH_EXID_AT91SAM9M11 0x00000001
@@ -62,7 +62,7 @@ static inline unsigned long at91_cpu_fully_identify(void)
62 62
63static inline unsigned long at91_exid_identify(void) 63static inline unsigned long at91_exid_identify(void)
64{ 64{
65 return at91_sys_read(AT91_DBGU_EXID); 65 return dbgu_readl(AT91_DBGU, EXID);
66} 66}
67 67
68 68
@@ -72,7 +72,7 @@ static inline unsigned long at91_exid_identify(void)
72 72
73static inline unsigned long at91_arch_identify(void) 73static inline unsigned long at91_arch_identify(void)
74{ 74{
75 return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); 75 return (dbgu_readl(AT91_DBGU, CIDR) & AT91_CIDR_ARCH);
76} 76}
77 77
78#ifdef CONFIG_ARCH_AT91CAP9 78#ifdef CONFIG_ARCH_AT91CAP9
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index 0f959faf74a9..bc1e0b2e2f4f 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -15,23 +15,23 @@
15#include <mach/at91_dbgu.h> 15#include <mach/at91_dbgu.h>
16 16
17 .macro addruart, rp, rv 17 .macro addruart, rp, rv
18 ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) 18 ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
19 ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) 19 ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
20 .endm 20 .endm
21 21
22 .macro senduart,rd,rx 22 .macro senduart,rd,rx
23 strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register 23 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
24 .endm 24 .endm
25 25
26 .macro waituart,rd,rx 26 .macro waituart,rd,rx
271001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register 271001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
28 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit 28 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
29 beq 1001b 29 beq 1001b
30 .endm 30 .endm
31 31
32 .macro busyuart,rd,rx 32 .macro busyuart,rd,rx
331001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register 331001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
34 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete 34 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
35 beq 1001b 35 beq 1001b
36 .endm 36 .endm
37 37
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-28 05:34:56 -0400