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-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h96
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ac97.h99
-rw-r--r--drivers/input/touchscreen/mainstone-wm97xx.c2
-rw-r--r--sound/arm/pxa2xx-ac97-lib.c2
-rw-r--r--sound/arm/pxa2xx-ac97.c1
-rw-r--r--sound/soc/pxa/pxa2xx-ac97.c1
6 files changed, 103 insertions, 98 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index cb9b46de97cc..a56502898030 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -132,102 +132,6 @@
132 */ 132 */
133 133
134/* 134/*
135 * AC97 Controller registers
136 */
137
138#define POCR __REG(0x40500000) /* PCM Out Control Register */
139#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
140#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
141
142#define PICR __REG(0x40500004) /* PCM In Control Register */
143#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
144#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
145
146#define MCCR __REG(0x40500008) /* Mic In Control Register */
147#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
148#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
149
150#define GCR __REG(0x4050000C) /* Global Control Register */
151#ifdef CONFIG_PXA3xx
152#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
153#endif
154#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
155#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
156#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
157#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
158#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
159#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
160#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
161#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
162#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
163#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
164#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
165
166#define POSR __REG(0x40500010) /* PCM Out Status Register */
167#define POSR_FIFOE (1 << 4) /* FIFO error */
168#define POSR_FSR (1 << 2) /* FIFO Service Request */
169
170#define PISR __REG(0x40500014) /* PCM In Status Register */
171#define PISR_FIFOE (1 << 4) /* FIFO error */
172#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
173#define PISR_FSR (1 << 2) /* FIFO Service Request */
174
175#define MCSR __REG(0x40500018) /* Mic In Status Register */
176#define MCSR_FIFOE (1 << 4) /* FIFO error */
177#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
178#define MCSR_FSR (1 << 2) /* FIFO Service Request */
179
180#define GSR __REG(0x4050001C) /* Global Status Register */
181#define GSR_CDONE (1 << 19) /* Command Done */
182#define GSR_SDONE (1 << 18) /* Status Done */
183#define GSR_RDCS (1 << 15) /* Read Completion Status */
184#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
185#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
186#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
187#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
188#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
189#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
190#define GSR_PCR (1 << 8) /* Primary Codec Ready */
191#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
192#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
193#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
194#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
195#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
196#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
197#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
198
199#define CAR __REG(0x40500020) /* CODEC Access Register */
200#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
201
202#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
203#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
204
205#define MOCR __REG(0x40500100) /* Modem Out Control Register */
206#define MOCR_FEIE (1 << 3) /* FIFO Error */
207#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
208
209#define MICR __REG(0x40500108) /* Modem In Control Register */
210#define MICR_FEIE (1 << 3) /* FIFO Error */
211#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
212
213#define MOSR __REG(0x40500110) /* Modem Out Status Register */
214#define MOSR_FIFOE (1 << 4) /* FIFO error */
215#define MOSR_FSR (1 << 2) /* FIFO Service Request */
216
217#define MISR __REG(0x40500118) /* Modem In Status Register */
218#define MISR_FIFOE (1 << 4) /* FIFO error */
219#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
220#define MISR_FSR (1 << 2) /* FIFO Service Request */
221
222#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
223
224#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
225#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
226#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
227#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
228
229
230/*
231 * Fast Infrared Communication Port - moved into drivers/net/irda/pxaficp_ir.c 135 * Fast Infrared Communication Port - moved into drivers/net/irda/pxaficp_ir.c
232 */ 136 */
233 137
diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h
new file mode 100644
index 000000000000..e41b9d202b8c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h
@@ -0,0 +1,99 @@
1#ifndef __ASM_ARCH_REGS_AC97_H
2#define __ASM_ARCH_REGS_AC97_H
3
4/*
5 * AC97 Controller registers
6 */
7
8#define POCR __REG(0x40500000) /* PCM Out Control Register */
9#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
10#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
11
12#define PICR __REG(0x40500004) /* PCM In Control Register */
13#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
14#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
15
16#define MCCR __REG(0x40500008) /* Mic In Control Register */
17#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
18#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
19
20#define GCR __REG(0x4050000C) /* Global Control Register */
21#ifdef CONFIG_PXA3xx
22#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
23#endif
24#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
25#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
26#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
27#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
28#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
29#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
30#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
31#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
32#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
33#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
34#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
35
36#define POSR __REG(0x40500010) /* PCM Out Status Register */
37#define POSR_FIFOE (1 << 4) /* FIFO error */
38#define POSR_FSR (1 << 2) /* FIFO Service Request */
39
40#define PISR __REG(0x40500014) /* PCM In Status Register */
41#define PISR_FIFOE (1 << 4) /* FIFO error */
42#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
43#define PISR_FSR (1 << 2) /* FIFO Service Request */
44
45#define MCSR __REG(0x40500018) /* Mic In Status Register */
46#define MCSR_FIFOE (1 << 4) /* FIFO error */
47#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
48#define MCSR_FSR (1 << 2) /* FIFO Service Request */
49
50#define GSR __REG(0x4050001C) /* Global Status Register */
51#define GSR_CDONE (1 << 19) /* Command Done */
52#define GSR_SDONE (1 << 18) /* Status Done */
53#define GSR_RDCS (1 << 15) /* Read Completion Status */
54#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
55#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
56#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
57#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
58#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
59#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
60#define GSR_PCR (1 << 8) /* Primary Codec Ready */
61#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
62#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
63#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
64#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
65#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
66#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
67#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
68
69#define CAR __REG(0x40500020) /* CODEC Access Register */
70#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
71
72#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
73#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
74
75#define MOCR __REG(0x40500100) /* Modem Out Control Register */
76#define MOCR_FEIE (1 << 3) /* FIFO Error */
77#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
78
79#define MICR __REG(0x40500108) /* Modem In Control Register */
80#define MICR_FEIE (1 << 3) /* FIFO Error */
81#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
82
83#define MOSR __REG(0x40500110) /* Modem Out Status Register */
84#define MOSR_FIFOE (1 << 4) /* FIFO error */
85#define MOSR_FSR (1 << 2) /* FIFO Service Request */
86
87#define MISR __REG(0x40500118) /* Modem In Status Register */
88#define MISR_FIFOE (1 << 4) /* FIFO error */
89#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
90#define MISR_FSR (1 << 2) /* FIFO Service Request */
91
92#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
93
94#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
95#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
96#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
97#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
98
99#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c
index ba648750a8d9..1d11e2be9ef8 100644
--- a/drivers/input/touchscreen/mainstone-wm97xx.c
+++ b/drivers/input/touchscreen/mainstone-wm97xx.c
@@ -31,7 +31,7 @@
31#include <linux/interrupt.h> 31#include <linux/interrupt.h>
32#include <linux/wm97xx.h> 32#include <linux/wm97xx.h>
33#include <linux/io.h> 33#include <linux/io.h>
34#include <mach/pxa-regs.h> 34#include <mach/regs-ac97.h>
35 35
36#define VERSION "0.13" 36#define VERSION "0.13"
37 37
diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c
index 34c1d94f921e..ef6539eea579 100644
--- a/sound/arm/pxa2xx-ac97-lib.c
+++ b/sound/arm/pxa2xx-ac97-lib.c
@@ -22,7 +22,7 @@
22 22
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25#include <mach/pxa-regs.h> 25#include <mach/regs-ac97.h>
26#include <mach/pxa2xx-gpio.h> 26#include <mach/pxa2xx-gpio.h>
27#include <mach/audio.h> 27#include <mach/audio.h>
28 28
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index c2635beb4c88..85cf591d4e11 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -22,6 +22,7 @@
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/pxa-regs.h> 24#include <mach/pxa-regs.h>
25#include <mach/regs-ac97.h>
25#include <mach/audio.h> 26#include <mach/audio.h>
26 27
27#include "pxa2xx-pcm.h" 28#include "pxa2xx-pcm.h"
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index a7a3a9c5c6ff..5e727393cfd4 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -21,6 +21,7 @@
21 21
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23#include <mach/pxa-regs.h> 23#include <mach/pxa-regs.h>
24#include <mach/regs-ac97.h>
24 25
25#include "pxa2xx-pcm.h" 26#include "pxa2xx-pcm.h"
26#include "pxa2xx-ac97.h" 27#include "pxa2xx-ac97.h"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 00:41:42 -0500