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-rw-r--r--arch/arm/mach-integrator/pci_v3.c46
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index a0e069d37e14..bef100527c42 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -52,7 +52,8 @@
52 * the V3 only has two windows (therefore we need to map stuff on the fly), 52 * the V3 only has two windows (therefore we need to map stuff on the fly),
53 * we maintain the same addresses, even if they're not mapped. 53 * we maintain the same addresses, even if they're not mapped.
54 */ 54 */
55#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M */ 55#define PHYS_PCI_MEM_BASE 0x40000000 /* 256M */
56#define PHYS_PCI_PRE_BASE 0x50000000 /* 256M */
56#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */ 57#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */
57#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */ 58#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */
58#define PHYS_PCI_V3_BASE 0x62000000 /* 64K */ 59#define PHYS_PCI_V3_BASE 0x62000000 /* 64K */
@@ -285,10 +286,16 @@
285 286
286/* Filled in by probe */ 287/* Filled in by probe */
287static void __iomem *pci_v3_base; 288static void __iomem *pci_v3_base;
289/* CPU side memory ranges */
288static struct resource conf_mem; /* FIXME: remap this instead of static map */ 290static struct resource conf_mem; /* FIXME: remap this instead of static map */
289static struct resource io_mem; 291static struct resource io_mem;
290static struct resource non_mem; 292static struct resource non_mem;
291static struct resource pre_mem; 293static struct resource pre_mem;
294/* PCI side memory ranges */
295static u64 non_mem_pci;
296static u64 non_mem_pci_sz;
297static u64 pre_mem_pci;
298static u64 pre_mem_pci_sz;
292 299
293// V3 access routines 300// V3 access routines
294#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o)) 301#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
@@ -354,19 +361,6 @@ static struct resource pre_mem;
354 */ 361 */
355static DEFINE_RAW_SPINLOCK(v3_lock); 362static DEFINE_RAW_SPINLOCK(v3_lock);
356 363
357#define PCI_BUS_NONMEM_START 0x00000000
358#define PCI_BUS_NONMEM_SIZE SZ_256M
359
360#define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
361#define PCI_BUS_PREMEM_SIZE SZ_256M
362
363#if PCI_BUS_NONMEM_START & 0x000fffff
364#error PCI_BUS_NONMEM_START must be megabyte aligned
365#endif
366#if PCI_BUS_PREMEM_START & 0x000fffff
367#error PCI_BUS_PREMEM_START must be megabyte aligned
368#endif
369
370#undef V3_LB_BASE_PREFETCH 364#undef V3_LB_BASE_PREFETCH
371#define V3_LB_BASE_PREFETCH 0 365#define V3_LB_BASE_PREFETCH 0
372 366
@@ -453,7 +447,7 @@ static void v3_close_config_window(void)
453 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | 447 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
454 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 448 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
455 V3_LB_BASE_ENABLE); 449 V3_LB_BASE_ENABLE);
456 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | 450 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
457 V3_LB_MAP_TYPE_MEM_MULTIPLE); 451 V3_LB_MAP_TYPE_MEM_MULTIPLE);
458 452
459 /* 453 /*
@@ -694,7 +688,7 @@ static void __init pci_v3_preinit(void)
694 */ 688 */
695 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | 689 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
696 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); 690 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
697 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | 691 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) |
698 V3_LB_MAP_TYPE_MEM); 692 V3_LB_MAP_TYPE_MEM);
699 693
700 /* 694 /*
@@ -704,7 +698,7 @@ static void __init pci_v3_preinit(void)
704 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | 698 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
705 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 699 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
706 V3_LB_BASE_ENABLE); 700 V3_LB_BASE_ENABLE);
707 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | 701 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
708 V3_LB_MAP_TYPE_MEM_MULTIPLE); 702 V3_LB_MAP_TYPE_MEM_MULTIPLE);
709 703
710 /* 704 /*
@@ -905,11 +899,15 @@ static int __init pci_v3_dtprobe(struct platform_device *pdev,
905 } 899 }
906 if ((range.flags & IORESOURCE_MEM) && 900 if ((range.flags & IORESOURCE_MEM) &&
907 !(range.flags & IORESOURCE_PREFETCH)) { 901 !(range.flags & IORESOURCE_PREFETCH)) {
902 non_mem_pci = range.pci_addr;
903 non_mem_pci_sz = range.size;
908 of_pci_range_to_resource(&range, np, &non_mem); 904 of_pci_range_to_resource(&range, np, &non_mem);
909 non_mem.name = "PCIv3 non-prefetched mem"; 905 non_mem.name = "PCIv3 non-prefetched mem";
910 } 906 }
911 if ((range.flags & IORESOURCE_MEM) && 907 if ((range.flags & IORESOURCE_MEM) &&
912 (range.flags & IORESOURCE_PREFETCH)) { 908 (range.flags & IORESOURCE_PREFETCH)) {
909 pre_mem_pci = range.pci_addr;
910 pre_mem_pci_sz = range.size;
913 of_pci_range_to_resource(&range, np, &pre_mem); 911 of_pci_range_to_resource(&range, np, &pre_mem);
914 pre_mem.name = "PCIv3 prefetched mem"; 912 pre_mem.name = "PCIv3 prefetched mem";
915 } 913 }
@@ -976,16 +974,18 @@ static int __init pci_v3_probe(struct platform_device *pdev)
976 io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1; 974 io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
977 io_mem.flags = IORESOURCE_MEM; 975 io_mem.flags = IORESOURCE_MEM;
978 976
977 non_mem_pci = 0x00000000;
978 non_mem_pci_sz = SZ_256M;
979 non_mem.name = "PCIv3 non-prefetched mem"; 979 non_mem.name = "PCIv3 non-prefetched mem";
980 non_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START; 980 non_mem.start = PHYS_PCI_MEM_BASE;
981 non_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + 981 non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1;
982 PCI_BUS_NONMEM_SIZE - 1;
983 non_mem.flags = IORESOURCE_MEM; 982 non_mem.flags = IORESOURCE_MEM;
984 983
984 pre_mem_pci = 0x10000000;
985 pre_mem_pci_sz = SZ_256M;
985 pre_mem.name = "PCIv3 prefetched mem"; 986 pre_mem.name = "PCIv3 prefetched mem";
986 pre_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START; 987 pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M;
987 pre_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + 988 pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1;
988 PCI_BUS_PREMEM_SIZE - 1;
989 pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 989 pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
990 990
991 pci_v3.map_irq = pci_v3_map_irq; 991 pci_v3.map_irq = pci_v3_map_irq;