diff options
| -rw-r--r-- | drivers/net/gianfar.c | 8 | ||||
| -rw-r--r-- | drivers/net/gianfar.h | 4 |
2 files changed, 11 insertions, 1 deletions
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 6850dc0a7b91..1616531a71f7 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c | |||
| @@ -357,8 +357,11 @@ static void gfar_init_mac(struct net_device *ndev) | |||
| 357 | /* Configure the coalescing support */ | 357 | /* Configure the coalescing support */ |
| 358 | gfar_configure_coalescing(priv, 0xFF, 0xFF); | 358 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
| 359 | 359 | ||
| 360 | if (priv->rx_filer_enable) | 360 | if (priv->rx_filer_enable) { |
| 361 | rctrl |= RCTRL_FILREN; | 361 | rctrl |= RCTRL_FILREN; |
| 362 | /* Program the RIR0 reg with the required distribution */ | ||
| 363 | gfar_write(®s->rir0, DEFAULT_RIR0); | ||
| 364 | } | ||
| 362 | 365 | ||
| 363 | if (priv->rx_csum_enable) | 366 | if (priv->rx_csum_enable) |
| 364 | rctrl |= RCTRL_CHECKSUMMING; | 367 | rctrl |= RCTRL_CHECKSUMMING; |
| @@ -1022,6 +1025,9 @@ static int gfar_probe(struct of_device *ofdev, | |||
| 1022 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | 1025 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; |
| 1023 | } | 1026 | } |
| 1024 | 1027 | ||
| 1028 | /* enable filer if using multiple RX queues*/ | ||
| 1029 | if(priv->num_rx_queues > 1) | ||
| 1030 | priv->rx_filer_enable = 1; | ||
| 1025 | /* Enable most messages by default */ | 1031 | /* Enable most messages by default */ |
| 1026 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | 1032 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; |
| 1027 | 1033 | ||
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h index cbb451011cb5..68d16dc6e7c8 100644 --- a/drivers/net/gianfar.h +++ b/drivers/net/gianfar.h | |||
| @@ -401,6 +401,10 @@ extern const char gfar_driver_version[]; | |||
| 401 | #define FPR_FILER_MASK 0xFFFFFFFF | 401 | #define FPR_FILER_MASK 0xFFFFFFFF |
| 402 | #define MAX_FILER_IDX 0xFF | 402 | #define MAX_FILER_IDX 0xFF |
| 403 | 403 | ||
| 404 | /* This default RIR value directly corresponds | ||
| 405 | * to the 3-bit hash value generated */ | ||
| 406 | #define DEFAULT_RIR0 0x05397700 | ||
| 407 | |||
| 404 | /* RQFCR register bits */ | 408 | /* RQFCR register bits */ |
| 405 | #define RQFCR_GPI 0x80000000 | 409 | #define RQFCR_GPI 0x80000000 |
| 406 | #define RQFCR_HASHTBL_Q 0x00000000 | 410 | #define RQFCR_HASHTBL_Q 0x00000000 |
