3 files changed, 27 insertions, 10 deletions

diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 7250c0281f9d..329f0356ad4a 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -870,7 +870,7 @@ void intel_pmu_lbr_enable(struct perf_event *event);
 
 void intel_pmu_lbr_disable(struct perf_event *event);
 
-void intel_pmu_lbr_enable_all(void);
+void intel_pmu_lbr_enable_all(bool pmi);
 
 void intel_pmu_lbr_disable_all(void);
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 59994602bb94..9da2400c2ec3 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1244,7 +1244,10 @@ static __initconst const u64 slm_hw_cache_event_ids
  },
 };
 
-static void intel_pmu_disable_all(void)
+/*
+ * Use from PMIs where the LBRs are already disabled.
+ */
+static void __intel_pmu_disable_all(void)
 {
         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 
@@ -1256,15 +1259,20 @@ static void intel_pmu_disable_all(void)
                 intel_bts_disable_local();
 
         intel_pmu_pebs_disable_all();
+}
+
+static void intel_pmu_disable_all(void)
+{
+        __intel_pmu_disable_all();
         intel_pmu_lbr_disable_all();
 }
 
-static void intel_pmu_enable_all(int added)
+static void __intel_pmu_enable_all(int added, bool pmi)
 {
         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 
         intel_pmu_pebs_enable_all();
-        intel_pmu_lbr_enable_all();
+        intel_pmu_lbr_enable_all(pmi);
         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
 
@@ -1280,6 +1288,11 @@ static void intel_pmu_enable_all(int added)
                 intel_bts_enable_local();
 }
 
+static void intel_pmu_enable_all(int added)
+{
+        __intel_pmu_enable_all(added, false);
+}
+
 /*
  * Workaround for:
  *   Intel Errata AAK100 (model 26)
@@ -1573,7 +1586,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
          */
         if (!x86_pmu.late_ack)
                 apic_write(APIC_LVTPC, APIC_DM_NMI);
-        intel_pmu_disable_all();
+        __intel_pmu_disable_all();
         handled = intel_pmu_drain_bts_buffer();
         handled += intel_bts_interrupt();
         status = intel_pmu_get_status();
@@ -1658,7 +1671,7 @@ again:
                 goto again;
 
 done:
-        intel_pmu_enable_all(0);
+        __intel_pmu_enable_all(0, true);
         /*
          * Only unmask the NMI after the overflow counters
          * have been reset. This avoids spurious NMIs on
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 0473874109cb..3d537252f011 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -132,12 +132,16 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
  * otherwise it becomes near impossible to get a reliable stack.
  */
 
-static void __intel_pmu_lbr_enable(void)
+static void __intel_pmu_lbr_enable(bool pmi)
 {
         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
         u64 debugctl, lbr_select = 0;
 
-        if (cpuc->lbr_sel) {
+        /*
+         * No need to reprogram LBR_SELECT in a PMI, as it
+         * did not change.
+         */
+        if (cpuc->lbr_sel && !pmi) {
                 lbr_select = cpuc->lbr_sel->config;
                 wrmsrl(MSR_LBR_SELECT, lbr_select);
         }
@@ -351,12 +355,12 @@ void intel_pmu_lbr_disable(struct perf_event *event)
         }
 }
 
-void intel_pmu_lbr_enable_all(void)
+void intel_pmu_lbr_enable_all(bool pmi)
 {
         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 
         if (cpuc->lbr_users)
-                __intel_pmu_lbr_enable();
+                __intel_pmu_lbr_enable(pmi);
 }
 
 void intel_pmu_lbr_disable_all(void)