aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--drivers/mfd/sta2x11-mfd.c350
-rw-r--r--include/linux/mfd/sta2x11-mfd.h156
2 files changed, 395 insertions, 111 deletions
diff --git a/drivers/mfd/sta2x11-mfd.c b/drivers/mfd/sta2x11-mfd.c
index d35da6820bea..9e01b84aa8bc 100644
--- a/drivers/mfd/sta2x11-mfd.c
+++ b/drivers/mfd/sta2x11-mfd.c
@@ -40,8 +40,7 @@ struct sta2x11_mfd {
40 struct sta2x11_instance *instance; 40 struct sta2x11_instance *instance;
41 spinlock_t lock; 41 spinlock_t lock;
42 struct list_head list; 42 struct list_head list;
43 void __iomem *sctl_regs; 43 void __iomem *regs[sta2x11_n_mfd_plat_devs];
44 void __iomem *apbreg_regs;
45}; 44};
46 45
47static LIST_HEAD(sta2x11_mfd_list); 46static LIST_HEAD(sta2x11_mfd_list);
@@ -100,56 +99,33 @@ static int __devexit mfd_remove(struct pci_dev *pdev)
100 return 0; 99 return 0;
101} 100}
102 101
103/* These two functions are exported and are not expected to fail */ 102/* This function is exported and is not expected to fail */
104u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) 103u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
104 enum sta2x11_mfd_plat_dev index)
105{ 105{
106 struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev); 106 struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
107 u32 r; 107 u32 r;
108 unsigned long flags; 108 unsigned long flags;
109 void __iomem *regs = mfd->regs[index];
109 110
110 if (!mfd) { 111 if (!mfd) {
111 dev_warn(&pdev->dev, ": can't access sctl regs\n"); 112 dev_warn(&pdev->dev, ": can't access sctl regs\n");
112 return 0; 113 return 0;
113 } 114 }
114 if (!mfd->sctl_regs) { 115 if (!regs) {
115 dev_warn(&pdev->dev, ": system ctl not initialized\n"); 116 dev_warn(&pdev->dev, ": system ctl not initialized\n");
116 return 0; 117 return 0;
117 } 118 }
118 spin_lock_irqsave(&mfd->lock, flags); 119 spin_lock_irqsave(&mfd->lock, flags);
119 r = readl(mfd->sctl_regs + reg); 120 r = readl(regs + reg);
120 r &= ~mask; 121 r &= ~mask;
121 r |= val; 122 r |= val;
122 if (mask) 123 if (mask)
123 writel(r, mfd->sctl_regs + reg); 124 writel(r, regs + reg);
124 spin_unlock_irqrestore(&mfd->lock, flags); 125 spin_unlock_irqrestore(&mfd->lock, flags);
125 return r; 126 return r;
126} 127}
127EXPORT_SYMBOL(sta2x11_sctl_mask); 128EXPORT_SYMBOL(__sta2x11_mfd_mask);
128
129u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
130{
131 struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
132 u32 r;
133 unsigned long flags;
134
135 if (!mfd) {
136 dev_warn(&pdev->dev, ": can't access apb regs\n");
137 return 0;
138 }
139 if (!mfd->apbreg_regs) {
140 dev_warn(&pdev->dev, ": apb bridge not initialized\n");
141 return 0;
142 }
143 spin_lock_irqsave(&mfd->lock, flags);
144 r = readl(mfd->apbreg_regs + reg);
145 r &= ~mask;
146 r |= val;
147 if (mask)
148 writel(r, mfd->apbreg_regs + reg);
149 spin_unlock_irqrestore(&mfd->lock, flags);
150 return r;
151}
152EXPORT_SYMBOL(sta2x11_apbreg_mask);
153 129
154/* Two debugfs files, for our registers (FIXME: one instance only) */ 130/* Two debugfs files, for our registers (FIXME: one instance only) */
155#define REG(regname) {.name = #regname, .offset = SCTL_ ## regname} 131#define REG(regname) {.name = #regname, .offset = SCTL_ ## regname}
@@ -180,51 +156,103 @@ static struct debugfs_regset32 apbreg_regset = {
180 .nregs = ARRAY_SIZE(sta2x11_apbreg_regs), 156 .nregs = ARRAY_SIZE(sta2x11_apbreg_regs),
181}; 157};
182 158
183static struct dentry *sta2x11_sctl_debugfs; 159#define REG(regname) {.name = #regname, .offset = regname}
184static struct dentry *sta2x11_apbreg_debugfs; 160static struct debugfs_reg32 sta2x11_apb_soc_regs_regs[] = {
161 REG(PCIE_EP1_FUNC3_0_INTR_REG), REG(PCIE_EP1_FUNC7_4_INTR_REG),
162 REG(PCIE_EP2_FUNC3_0_INTR_REG), REG(PCIE_EP2_FUNC7_4_INTR_REG),
163 REG(PCIE_EP3_FUNC3_0_INTR_REG), REG(PCIE_EP3_FUNC7_4_INTR_REG),
164 REG(PCIE_EP4_FUNC3_0_INTR_REG), REG(PCIE_EP4_FUNC7_4_INTR_REG),
165 REG(PCIE_INTR_ENABLE0_REG), REG(PCIE_INTR_ENABLE1_REG),
166 REG(PCIE_EP1_FUNC_TC_REG), REG(PCIE_EP2_FUNC_TC_REG),
167 REG(PCIE_EP3_FUNC_TC_REG), REG(PCIE_EP4_FUNC_TC_REG),
168 REG(PCIE_EP1_FUNC_F_REG), REG(PCIE_EP2_FUNC_F_REG),
169 REG(PCIE_EP3_FUNC_F_REG), REG(PCIE_EP4_FUNC_F_REG),
170 REG(PCIE_PAB_AMBA_SW_RST_REG), REG(PCIE_PM_STATUS_0_PORT_0_4),
171 REG(PCIE_PM_STATUS_7_0_EP1), REG(PCIE_PM_STATUS_7_0_EP2),
172 REG(PCIE_PM_STATUS_7_0_EP3), REG(PCIE_PM_STATUS_7_0_EP4),
173 REG(PCIE_DEV_ID_0_EP1_REG), REG(PCIE_CC_REV_ID_0_EP1_REG),
174 REG(PCIE_DEV_ID_1_EP1_REG), REG(PCIE_CC_REV_ID_1_EP1_REG),
175 REG(PCIE_DEV_ID_2_EP1_REG), REG(PCIE_CC_REV_ID_2_EP1_REG),
176 REG(PCIE_DEV_ID_3_EP1_REG), REG(PCIE_CC_REV_ID_3_EP1_REG),
177 REG(PCIE_DEV_ID_4_EP1_REG), REG(PCIE_CC_REV_ID_4_EP1_REG),
178 REG(PCIE_DEV_ID_5_EP1_REG), REG(PCIE_CC_REV_ID_5_EP1_REG),
179 REG(PCIE_DEV_ID_6_EP1_REG), REG(PCIE_CC_REV_ID_6_EP1_REG),
180 REG(PCIE_DEV_ID_7_EP1_REG), REG(PCIE_CC_REV_ID_7_EP1_REG),
181 REG(PCIE_DEV_ID_0_EP2_REG), REG(PCIE_CC_REV_ID_0_EP2_REG),
182 REG(PCIE_DEV_ID_1_EP2_REG), REG(PCIE_CC_REV_ID_1_EP2_REG),
183 REG(PCIE_DEV_ID_2_EP2_REG), REG(PCIE_CC_REV_ID_2_EP2_REG),
184 REG(PCIE_DEV_ID_3_EP2_REG), REG(PCIE_CC_REV_ID_3_EP2_REG),
185 REG(PCIE_DEV_ID_4_EP2_REG), REG(PCIE_CC_REV_ID_4_EP2_REG),
186 REG(PCIE_DEV_ID_5_EP2_REG), REG(PCIE_CC_REV_ID_5_EP2_REG),
187 REG(PCIE_DEV_ID_6_EP2_REG), REG(PCIE_CC_REV_ID_6_EP2_REG),
188 REG(PCIE_DEV_ID_7_EP2_REG), REG(PCIE_CC_REV_ID_7_EP2_REG),
189 REG(PCIE_DEV_ID_0_EP3_REG), REG(PCIE_CC_REV_ID_0_EP3_REG),
190 REG(PCIE_DEV_ID_1_EP3_REG), REG(PCIE_CC_REV_ID_1_EP3_REG),
191 REG(PCIE_DEV_ID_2_EP3_REG), REG(PCIE_CC_REV_ID_2_EP3_REG),
192 REG(PCIE_DEV_ID_3_EP3_REG), REG(PCIE_CC_REV_ID_3_EP3_REG),
193 REG(PCIE_DEV_ID_4_EP3_REG), REG(PCIE_CC_REV_ID_4_EP3_REG),
194 REG(PCIE_DEV_ID_5_EP3_REG), REG(PCIE_CC_REV_ID_5_EP3_REG),
195 REG(PCIE_DEV_ID_6_EP3_REG), REG(PCIE_CC_REV_ID_6_EP3_REG),
196 REG(PCIE_DEV_ID_7_EP3_REG), REG(PCIE_CC_REV_ID_7_EP3_REG),
197 REG(PCIE_DEV_ID_0_EP4_REG), REG(PCIE_CC_REV_ID_0_EP4_REG),
198 REG(PCIE_DEV_ID_1_EP4_REG), REG(PCIE_CC_REV_ID_1_EP4_REG),
199 REG(PCIE_DEV_ID_2_EP4_REG), REG(PCIE_CC_REV_ID_2_EP4_REG),
200 REG(PCIE_DEV_ID_3_EP4_REG), REG(PCIE_CC_REV_ID_3_EP4_REG),
201 REG(PCIE_DEV_ID_4_EP4_REG), REG(PCIE_CC_REV_ID_4_EP4_REG),
202 REG(PCIE_DEV_ID_5_EP4_REG), REG(PCIE_CC_REV_ID_5_EP4_REG),
203 REG(PCIE_DEV_ID_6_EP4_REG), REG(PCIE_CC_REV_ID_6_EP4_REG),
204 REG(PCIE_DEV_ID_7_EP4_REG), REG(PCIE_CC_REV_ID_7_EP4_REG),
205 REG(PCIE_SUBSYS_VEN_ID_REG), REG(PCIE_COMMON_CLOCK_CONFIG_0_4_0),
206 REG(PCIE_MIPHYP_SSC_EN_REG), REG(PCIE_MIPHYP_ADDR_REG),
207 REG(PCIE_L1_ASPM_READY_REG), REG(PCIE_EXT_CFG_RDY_REG),
208 REG(PCIE_SoC_INT_ROUTER_STATUS0_REG),
209 REG(PCIE_SoC_INT_ROUTER_STATUS1_REG),
210 REG(PCIE_SoC_INT_ROUTER_STATUS2_REG),
211 REG(PCIE_SoC_INT_ROUTER_STATUS3_REG),
212 REG(DMA_IP_CTRL_REG), REG(DISP_BRIDGE_PU_PD_CTRL_REG),
213 REG(VIP_PU_PD_CTRL_REG), REG(USB_MLB_PU_PD_CTRL_REG),
214 REG(SDIO_PU_PD_MISCFUNC_CTRL_REG1), REG(SDIO_PU_PD_MISCFUNC_CTRL_REG2),
215 REG(UART_PU_PD_CTRL_REG), REG(ARM_Lock), REG(SYS_IO_CHAR_REG1),
216 REG(SYS_IO_CHAR_REG2), REG(SATA_CORE_ID_REG), REG(SATA_CTRL_REG),
217 REG(I2C_HSFIX_MISC_REG), REG(SPARE2_RESERVED), REG(SPARE3_RESERVED),
218 REG(MASTER_LOCK_REG), REG(SYSTEM_CONFIG_STATUS_REG),
219 REG(MSP_CLK_CTRL_REG), REG(COMPENSATION_REG1), REG(COMPENSATION_REG2),
220 REG(COMPENSATION_REG3), REG(TEST_CTL_REG),
221};
222#undef REG
185 223
186/* Probe for the two platform devices */ 224static struct debugfs_regset32 apb_soc_regs_regset = {
187static int sta2x11_sctl_probe(struct platform_device *dev) 225 .regs = sta2x11_apb_soc_regs_regs,
188{ 226 .nregs = ARRAY_SIZE(sta2x11_apb_soc_regs_regs),
189 struct pci_dev **pdev; 227};
190 struct sta2x11_mfd *mfd;
191 struct resource *res;
192 228
193 pdev = dev->dev.platform_data;
194 mfd = sta2x11_mfd_find(*pdev);
195 if (!mfd)
196 return -ENODEV;
197 229
198 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 230static struct dentry *sta2x11_mfd_debugfs[sta2x11_n_mfd_plat_devs];
199 if (!res)
200 return -ENOMEM;
201 231
202 if (!request_mem_region(res->start, resource_size(res), 232static struct debugfs_regset32 *sta2x11_mfd_regset[sta2x11_n_mfd_plat_devs] = {
203 "sta2x11-sctl")) 233 [sta2x11_sctl] = &sctl_regset,
204 return -EBUSY; 234 [sta2x11_apbreg] = &apbreg_regset,
235 [sta2x11_apb_soc_regs] = &apb_soc_regs_regset,
236};
205 237
206 mfd->sctl_regs = ioremap(res->start, resource_size(res)); 238static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
207 if (!mfd->sctl_regs) { 239 [sta2x11_sctl] = "sta2x11-sctl",
208 release_mem_region(res->start, resource_size(res)); 240 [sta2x11_apbreg] = "sta2x11-apbreg",
209 return -ENOMEM; 241 [sta2x11_apb_soc_regs] = "sta2x11-apb-soc-regs",
210 } 242};
211 sctl_regset.base = mfd->sctl_regs;
212 sta2x11_sctl_debugfs = debugfs_create_regset32("sta2x11-sctl",
213 S_IFREG | S_IRUGO,
214 NULL, &sctl_regset);
215 return 0;
216}
217 243
218static int sta2x11_apbreg_probe(struct platform_device *dev) 244/* Probe for the three platform devices */
245
246static int sta2x11_mfd_platform_probe(struct platform_device *dev,
247 enum sta2x11_mfd_plat_dev index)
219{ 248{
220 struct pci_dev **pdev; 249 struct pci_dev **pdev;
221 struct sta2x11_mfd *mfd; 250 struct sta2x11_mfd *mfd;
222 struct resource *res; 251 struct resource *res;
252 const char *name = sta2x11_mfd_names[index];
253 struct debugfs_regset32 *regset = sta2x11_mfd_regset[index];
223 254
224 pdev = dev->dev.platform_data; 255 pdev = dev->dev.platform_data;
225 dev_dbg(&dev->dev, "%s: pdata is %p\n", __func__, pdev);
226 dev_dbg(&dev->dev, "%s: *pdata is %p\n", __func__, *pdev);
227
228 mfd = sta2x11_mfd_find(*pdev); 256 mfd = sta2x11_mfd_find(*pdev);
229 if (!mfd) 257 if (!mfd)
230 return -ENODEV; 258 return -ENODEV;
@@ -233,25 +261,37 @@ static int sta2x11_apbreg_probe(struct platform_device *dev)
233 if (!res) 261 if (!res)
234 return -ENOMEM; 262 return -ENOMEM;
235 263
236 if (!request_mem_region(res->start, resource_size(res), 264 if (!request_mem_region(res->start, resource_size(res), name))
237 "sta2x11-apbreg"))
238 return -EBUSY; 265 return -EBUSY;
239 266
240 mfd->apbreg_regs = ioremap(res->start, resource_size(res)); 267 mfd->regs[index] = ioremap(res->start, resource_size(res));
241 if (!mfd->apbreg_regs) { 268 if (!mfd->regs[index]) {
242 release_mem_region(res->start, resource_size(res)); 269 release_mem_region(res->start, resource_size(res));
243 return -ENOMEM; 270 return -ENOMEM;
244 } 271 }
245 dev_dbg(&dev->dev, "%s: regbase %p\n", __func__, mfd->apbreg_regs); 272 regset->base = mfd->regs[index];
246 273 sta2x11_mfd_debugfs[index] = debugfs_create_regset32(name,
247 apbreg_regset.base = mfd->apbreg_regs; 274 S_IFREG | S_IRUGO,
248 sta2x11_apbreg_debugfs = debugfs_create_regset32("sta2x11-apbreg", 275 NULL, regset);
249 S_IFREG | S_IRUGO,
250 NULL, &apbreg_regset);
251 return 0; 276 return 0;
252} 277}
253 278
254/* The two platform drivers */ 279static int sta2x11_sctl_probe(struct platform_device *dev)
280{
281 return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
282}
283
284static int sta2x11_apbreg_probe(struct platform_device *dev)
285{
286 return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
287}
288
289static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
290{
291 return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
292}
293
294/* The three platform drivers */
255static struct platform_driver sta2x11_sctl_platform_driver = { 295static struct platform_driver sta2x11_sctl_platform_driver = {
256 .driver = { 296 .driver = {
257 .name = "sta2x11-sctl", 297 .name = "sta2x11-sctl",
@@ -280,13 +320,29 @@ static int __init sta2x11_apbreg_init(void)
280 return platform_driver_register(&sta2x11_platform_driver); 320 return platform_driver_register(&sta2x11_platform_driver);
281} 321}
282 322
323static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
324 .driver = {
325 .name = "sta2x11-apb-soc-regs",
326 .owner = THIS_MODULE,
327 },
328 .probe = sta2x11_apb_soc_regs_probe,
329};
330
331static int __init sta2x11_apb_soc_regs_init(void)
332{
333 pr_info("%s\n", __func__);
334 return platform_driver_register(&sta2x11_apb_soc_regs_platform_driver);
335}
336
283/* 337/*
284 * What follows is the PCI device that hosts the above two pdevs. 338 * What follows are the PCI devices that host the above pdevs.
285 * Each logic block is 4kB and they are all consecutive: we use this info. 339 * Each logic block is 4kB and they are all consecutive: we use this info.
286 */ 340 */
287 341
288/* Bar 0 */ 342/* Mfd 0 device */
289enum bar0_cells { 343
344/* Mfd 0, Bar 0 */
345enum mfd0_bar0_cells {
290 STA2X11_GPIO_0 = 0, 346 STA2X11_GPIO_0 = 0,
291 STA2X11_GPIO_1, 347 STA2X11_GPIO_1,
292 STA2X11_GPIO_2, 348 STA2X11_GPIO_2,
@@ -295,8 +351,8 @@ enum bar0_cells {
295 STA2X11_SCR, 351 STA2X11_SCR,
296 STA2X11_TIME, 352 STA2X11_TIME,
297}; 353};
298/* Bar 1 */ 354/* Mfd 0 , Bar 1 */
299enum bar1_cells { 355enum mfd0_bar1_cells {
300 STA2X11_APBREG = 0, 356 STA2X11_APBREG = 0,
301}; 357};
302#define CELL_4K(_name, _cell) { \ 358#define CELL_4K(_name, _cell) { \
@@ -330,17 +386,46 @@ static const __devinitconst struct resource apbreg_resources[] = {
330#define DEV(_name, _r) \ 386#define DEV(_name, _r) \
331 { .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, } 387 { .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
332 388
333static __devinitdata struct mfd_cell sta2x11_mfd_bar0[] = { 389static __devinitdata struct mfd_cell sta2x11_mfd0_bar0[] = {
334 DEV("sta2x11-gpio", gpio_resources), /* offset 0: we add pdata later */ 390 DEV("sta2x11-gpio", gpio_resources), /* offset 0: we add pdata later */
335 DEV("sta2x11-sctl", sctl_resources), 391 DEV("sta2x11-sctl", sctl_resources),
336 DEV("sta2x11-scr", scr_resources), 392 DEV("sta2x11-scr", scr_resources),
337 DEV("sta2x11-time", time_resources), 393 DEV("sta2x11-time", time_resources),
338}; 394};
339 395
340static __devinitdata struct mfd_cell sta2x11_mfd_bar1[] = { 396static __devinitdata struct mfd_cell sta2x11_mfd0_bar1[] = {
341 DEV("sta2x11-apbreg", apbreg_resources), 397 DEV("sta2x11-apbreg", apbreg_resources),
342}; 398};
343 399
400/* Mfd 1 devices */
401
402/* Mfd 1, Bar 0 */
403enum mfd1_bar0_cells {
404 STA2X11_VIC = 0,
405};
406
407/* Mfd 1, Bar 1 */
408enum mfd1_bar1_cells {
409 STA2X11_APB_SOC_REGS = 0,
410};
411
412static const __devinitconst struct resource vic_resources[] = {
413 CELL_4K("sta2x11-vic", STA2X11_VIC),
414};
415
416static const __devinitconst struct resource apb_soc_regs_resources[] = {
417 CELL_4K("sta2x11-apb-soc-regs", STA2X11_APB_SOC_REGS),
418};
419
420static __devinitdata struct mfd_cell sta2x11_mfd1_bar0[] = {
421 DEV("sta2x11-vic", vic_resources),
422};
423
424static __devinitdata struct mfd_cell sta2x11_mfd1_bar1[] = {
425 DEV("sta2x11-apb-soc-regs", apb_soc_regs_resources),
426};
427
428
344static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state) 429static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
345{ 430{
346 pci_save_state(pdev); 431 pci_save_state(pdev);
@@ -363,10 +448,63 @@ static int sta2x11_mfd_resume(struct pci_dev *pdev)
363 return 0; 448 return 0;
364} 449}
365 450
451struct sta2x11_mfd_bar_setup_data {
452 struct mfd_cell *cells;
453 int ncells;
454};
455
456struct sta2x11_mfd_setup_data {
457 struct sta2x11_mfd_bar_setup_data bars[2];
458};
459
460#define STA2X11_MFD0 0
461#define STA2X11_MFD1 1
462
463static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
464 /* Mfd 0: gpio, sctl, scr, timers / apbregs */
465 [STA2X11_MFD0] = {
466 .bars = {
467 [0] = {
468 .cells = sta2x11_mfd0_bar0,
469 .ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
470 },
471 [1] = {
472 .cells = sta2x11_mfd0_bar1,
473 .ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
474 },
475 },
476 },
477 /* Mfd 1: vic / apb-soc-regs */
478 [STA2X11_MFD1] = {
479 .bars = {
480 [0] = {
481 .cells = sta2x11_mfd1_bar0,
482 .ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
483 },
484 [1] = {
485 .cells = sta2x11_mfd1_bar1,
486 .ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
487 },
488 },
489 },
490};
491
492static void __devinit sta2x11_mfd_setup(struct pci_dev *pdev,
493 struct sta2x11_mfd_setup_data *sd)
494{
495 int i, j;
496 for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
497 for (j = 0; j < sd->bars[i].ncells; j++) {
498 sd->bars[i].cells[j].pdata_size = sizeof(pdev);
499 sd->bars[i].cells[j].platform_data = &pdev;
500 }
501}
502
366static int __devinit sta2x11_mfd_probe(struct pci_dev *pdev, 503static int __devinit sta2x11_mfd_probe(struct pci_dev *pdev,
367 const struct pci_device_id *pci_id) 504 const struct pci_device_id *pci_id)
368{ 505{
369 int err, i; 506 int err, i;
507 struct sta2x11_mfd_setup_data *setup_data;
370 struct sta2x11_gpio_pdata *gpio_data; 508 struct sta2x11_gpio_pdata *gpio_data;
371 509
372 dev_info(&pdev->dev, "%s\n", __func__); 510 dev_info(&pdev->dev, "%s\n", __func__);
@@ -381,6 +519,10 @@ static int __devinit sta2x11_mfd_probe(struct pci_dev *pdev,
381 if (err) 519 if (err)
382 dev_info(&pdev->dev, "Enable msi failed\n"); 520 dev_info(&pdev->dev, "Enable msi failed\n");
383 521
522 setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
523 &mfd_setup_data[STA2X11_MFD0] :
524 &mfd_setup_data[STA2X11_MFD1];
525
384 /* Read gpio config data as pci device's platform data */ 526 /* Read gpio config data as pci device's platform data */
385 gpio_data = dev_get_platdata(&pdev->dev); 527 gpio_data = dev_get_platdata(&pdev->dev);
386 if (!gpio_data) 528 if (!gpio_data)
@@ -392,35 +534,23 @@ static int __devinit sta2x11_mfd_probe(struct pci_dev *pdev,
392 pdev, &pdev); 534 pdev, &pdev);
393 535
394 /* platform data is the pci device for all of them */ 536 /* platform data is the pci device for all of them */
395 for (i = 0; i < ARRAY_SIZE(sta2x11_mfd_bar0); i++) { 537 sta2x11_mfd_setup(pdev, setup_data);
396 sta2x11_mfd_bar0[i].pdata_size = sizeof(pdev);
397 sta2x11_mfd_bar0[i].platform_data = &pdev;
398 }
399 sta2x11_mfd_bar1[0].pdata_size = sizeof(pdev);
400 sta2x11_mfd_bar1[0].platform_data = &pdev;
401 538
402 /* Record this pdev before mfd_add_devices: their probe looks for it */ 539 /* Record this pdev before mfd_add_devices: their probe looks for it */
403 sta2x11_mfd_add(pdev, GFP_ATOMIC); 540 sta2x11_mfd_add(pdev, GFP_ATOMIC);
404 541
405 542 /* Just 2 bars for all mfd's at present */
406 err = mfd_add_devices(&pdev->dev, -1, 543 for (i = 0; i < 2; i++) {
407 sta2x11_mfd_bar0, 544 err = mfd_add_devices(&pdev->dev, -1,
408 ARRAY_SIZE(sta2x11_mfd_bar0), 545 setup_data->bars[i].cells,
409 &pdev->resource[0], 546 setup_data->bars[i].ncells,
410 0, NULL); 547 &pdev->resource[i],
411 if (err) { 548 0, NULL);
412 dev_err(&pdev->dev, "mfd_add_devices[0] failed: %d\n", err); 549 if (err) {
413 goto err_disable; 550 dev_err(&pdev->dev,
414 } 551 "mfd_add_devices[%d] failed: %d\n", i, err);
415 552 goto err_disable;
416 err = mfd_add_devices(&pdev->dev, -1, 553 }
417 sta2x11_mfd_bar1,
418 ARRAY_SIZE(sta2x11_mfd_bar1),
419 &pdev->resource[1],
420 0, NULL);
421 if (err) {
422 dev_err(&pdev->dev, "mfd_add_devices[1] failed: %d\n", err);
423 goto err_disable;
424 } 554 }
425 555
426 return 0; 556 return 0;
@@ -434,6 +564,7 @@ err_disable:
434 564
435static DEFINE_PCI_DEVICE_TABLE(sta2x11_mfd_tbl) = { 565static DEFINE_PCI_DEVICE_TABLE(sta2x11_mfd_tbl) = {
436 {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)}, 566 {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
567 {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
437 {0,}, 568 {0,},
438}; 569};
439 570
@@ -459,6 +590,7 @@ static int __init sta2x11_mfd_init(void)
459 */ 590 */
460subsys_initcall(sta2x11_apbreg_init); 591subsys_initcall(sta2x11_apbreg_init);
461subsys_initcall(sta2x11_sctl_init); 592subsys_initcall(sta2x11_sctl_init);
593subsys_initcall(sta2x11_apb_soc_regs_init);
462rootfs_initcall(sta2x11_mfd_init); 594rootfs_initcall(sta2x11_mfd_init);
463 595
464MODULE_LICENSE("GPL v2"); 596MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/sta2x11-mfd.h b/include/linux/mfd/sta2x11-mfd.h
index d179227e866f..4d858797d7e2 100644
--- a/include/linux/mfd/sta2x11-mfd.h
+++ b/include/linux/mfd/sta2x11-mfd.h
@@ -26,6 +26,20 @@
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/pci.h> 27#include <linux/pci.h>
28 28
29enum sta2x11_mfd_plat_dev {
30 sta2x11_sctl = 0,
31 sta2x11_gpio,
32 sta2x11_scr,
33 sta2x11_time,
34 sta2x11_apbreg,
35 sta2x11_apb_soc_regs,
36 sta2x11_vic,
37 sta2x11_n_mfd_plat_devs,
38};
39
40extern u32
41__sta2x11_mfd_mask(struct pci_dev *, u32, u32, u32, enum sta2x11_mfd_plat_dev);
42
29/* 43/*
30 * The MFD PCI block includes the GPIO peripherals and other register blocks. 44 * The MFD PCI block includes the GPIO peripherals and other register blocks.
31 * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".) 45 * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
@@ -182,7 +196,11 @@ struct sta2x11_gpio_pdata {
182 * The APB bridge has its own registers, needed by our users as well. 196 * The APB bridge has its own registers, needed by our users as well.
183 * They are accessed with the following read/mask/write function. 197 * They are accessed with the following read/mask/write function.
184 */ 198 */
185u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val); 199static inline u32
200sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
201{
202 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg);
203}
186 204
187/* CAN and MLB */ 205/* CAN and MLB */
188#define APBREG_BSR 0x00 /* Bridge Status Reg */ 206#define APBREG_BSR 0x00 /* Bridge Status Reg */
@@ -211,7 +229,11 @@ u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
211 * The system controller has its own registers. Some of these are accessed 229 * The system controller has its own registers. Some of these are accessed
212 * by out users as well, using the following read/mask/write/function 230 * by out users as well, using the following read/mask/write/function
213 */ 231 */
214u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val); 232static inline
233u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
234{
235 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl);
236}
215 237
216#define SCTL_SCCTL 0x00 /* System controller control register */ 238#define SCTL_SCCTL 0x00 /* System controller control register */
217#define SCTL_ARMCFG 0x04 /* ARM configuration register */ 239#define SCTL_ARMCFG 0x04 /* ARM configuration register */
@@ -321,4 +343,134 @@ u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
321#define SCTL_SCPEREN1_I2C3 (1 << 16) 343#define SCTL_SCPEREN1_I2C3 (1 << 16)
322#define SCTL_SCPEREN1_USB_PHY (1 << 17) 344#define SCTL_SCPEREN1_USB_PHY (1 << 17)
323 345
346/*
347 * APB-SOC registers
348 */
349static inline
350u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
351{
352 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs);
353}
354
355#define PCIE_EP1_FUNC3_0_INTR_REG 0x000
356#define PCIE_EP1_FUNC7_4_INTR_REG 0x004
357#define PCIE_EP2_FUNC3_0_INTR_REG 0x008
358#define PCIE_EP2_FUNC7_4_INTR_REG 0x00c
359#define PCIE_EP3_FUNC3_0_INTR_REG 0x010
360#define PCIE_EP3_FUNC7_4_INTR_REG 0x014
361#define PCIE_EP4_FUNC3_0_INTR_REG 0x018
362#define PCIE_EP4_FUNC7_4_INTR_REG 0x01c
363#define PCIE_INTR_ENABLE0_REG 0x020
364#define PCIE_INTR_ENABLE1_REG 0x024
365#define PCIE_EP1_FUNC_TC_REG 0x028
366#define PCIE_EP2_FUNC_TC_REG 0x02c
367#define PCIE_EP3_FUNC_TC_REG 0x030
368#define PCIE_EP4_FUNC_TC_REG 0x034
369#define PCIE_EP1_FUNC_F_REG 0x038
370#define PCIE_EP2_FUNC_F_REG 0x03c
371#define PCIE_EP3_FUNC_F_REG 0x040
372#define PCIE_EP4_FUNC_F_REG 0x044
373#define PCIE_PAB_AMBA_SW_RST_REG 0x048
374#define PCIE_PM_STATUS_0_PORT_0_4 0x04c
375#define PCIE_PM_STATUS_7_0_EP1 0x050
376#define PCIE_PM_STATUS_7_0_EP2 0x054
377#define PCIE_PM_STATUS_7_0_EP3 0x058
378#define PCIE_PM_STATUS_7_0_EP4 0x05c
379#define PCIE_DEV_ID_0_EP1_REG 0x060
380#define PCIE_CC_REV_ID_0_EP1_REG 0x064
381#define PCIE_DEV_ID_1_EP1_REG 0x068
382#define PCIE_CC_REV_ID_1_EP1_REG 0x06c
383#define PCIE_DEV_ID_2_EP1_REG 0x070
384#define PCIE_CC_REV_ID_2_EP1_REG 0x074
385#define PCIE_DEV_ID_3_EP1_REG 0x078
386#define PCIE_CC_REV_ID_3_EP1_REG 0x07c
387#define PCIE_DEV_ID_4_EP1_REG 0x080
388#define PCIE_CC_REV_ID_4_EP1_REG 0x084
389#define PCIE_DEV_ID_5_EP1_REG 0x088
390#define PCIE_CC_REV_ID_5_EP1_REG 0x08c
391#define PCIE_DEV_ID_6_EP1_REG 0x090
392#define PCIE_CC_REV_ID_6_EP1_REG 0x094
393#define PCIE_DEV_ID_7_EP1_REG 0x098
394#define PCIE_CC_REV_ID_7_EP1_REG 0x09c
395#define PCIE_DEV_ID_0_EP2_REG 0x0a0
396#define PCIE_CC_REV_ID_0_EP2_REG 0x0a4
397#define PCIE_DEV_ID_1_EP2_REG 0x0a8
398#define PCIE_CC_REV_ID_1_EP2_REG 0x0ac
399#define PCIE_DEV_ID_2_EP2_REG 0x0b0
400#define PCIE_CC_REV_ID_2_EP2_REG 0x0b4
401#define PCIE_DEV_ID_3_EP2_REG 0x0b8
402#define PCIE_CC_REV_ID_3_EP2_REG 0x0bc
403#define PCIE_DEV_ID_4_EP2_REG 0x0c0
404#define PCIE_CC_REV_ID_4_EP2_REG 0x0c4
405#define PCIE_DEV_ID_5_EP2_REG 0x0c8
406#define PCIE_CC_REV_ID_5_EP2_REG 0x0cc
407#define PCIE_DEV_ID_6_EP2_REG 0x0d0
408#define PCIE_CC_REV_ID_6_EP2_REG 0x0d4
409#define PCIE_DEV_ID_7_EP2_REG 0x0d8
410#define PCIE_CC_REV_ID_7_EP2_REG 0x0dC
411#define PCIE_DEV_ID_0_EP3_REG 0x0e0
412#define PCIE_CC_REV_ID_0_EP3_REG 0x0e4
413#define PCIE_DEV_ID_1_EP3_REG 0x0e8
414#define PCIE_CC_REV_ID_1_EP3_REG 0x0ec
415#define PCIE_DEV_ID_2_EP3_REG 0x0f0
416#define PCIE_CC_REV_ID_2_EP3_REG 0x0f4
417#define PCIE_DEV_ID_3_EP3_REG 0x0f8
418#define PCIE_CC_REV_ID_3_EP3_REG 0x0fc
419#define PCIE_DEV_ID_4_EP3_REG 0x100
420#define PCIE_CC_REV_ID_4_EP3_REG 0x104
421#define PCIE_DEV_ID_5_EP3_REG 0x108
422#define PCIE_CC_REV_ID_5_EP3_REG 0x10c
423#define PCIE_DEV_ID_6_EP3_REG 0x110
424#define PCIE_CC_REV_ID_6_EP3_REG 0x114
425#define PCIE_DEV_ID_7_EP3_REG 0x118
426#define PCIE_CC_REV_ID_7_EP3_REG 0x11c
427#define PCIE_DEV_ID_0_EP4_REG 0x120
428#define PCIE_CC_REV_ID_0_EP4_REG 0x124
429#define PCIE_DEV_ID_1_EP4_REG 0x128
430#define PCIE_CC_REV_ID_1_EP4_REG 0x12c
431#define PCIE_DEV_ID_2_EP4_REG 0x130
432#define PCIE_CC_REV_ID_2_EP4_REG 0x134
433#define PCIE_DEV_ID_3_EP4_REG 0x138
434#define PCIE_CC_REV_ID_3_EP4_REG 0x13c
435#define PCIE_DEV_ID_4_EP4_REG 0x140
436#define PCIE_CC_REV_ID_4_EP4_REG 0x144
437#define PCIE_DEV_ID_5_EP4_REG 0x148
438#define PCIE_CC_REV_ID_5_EP4_REG 0x14c
439#define PCIE_DEV_ID_6_EP4_REG 0x150
440#define PCIE_CC_REV_ID_6_EP4_REG 0x154
441#define PCIE_DEV_ID_7_EP4_REG 0x158
442#define PCIE_CC_REV_ID_7_EP4_REG 0x15c
443#define PCIE_SUBSYS_VEN_ID_REG 0x160
444#define PCIE_COMMON_CLOCK_CONFIG_0_4_0 0x164
445#define PCIE_MIPHYP_SSC_EN_REG 0x168
446#define PCIE_MIPHYP_ADDR_REG 0x16c
447#define PCIE_L1_ASPM_READY_REG 0x170
448#define PCIE_EXT_CFG_RDY_REG 0x174
449#define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178
450#define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c
451#define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180
452#define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184
453#define DMA_IP_CTRL_REG 0x324
454#define DISP_BRIDGE_PU_PD_CTRL_REG 0x328
455#define VIP_PU_PD_CTRL_REG 0x32c
456#define USB_MLB_PU_PD_CTRL_REG 0x330
457#define SDIO_PU_PD_MISCFUNC_CTRL_REG1 0x334
458#define SDIO_PU_PD_MISCFUNC_CTRL_REG2 0x338
459#define UART_PU_PD_CTRL_REG 0x33c
460#define ARM_Lock 0x340
461#define SYS_IO_CHAR_REG1 0x344
462#define SYS_IO_CHAR_REG2 0x348
463#define SATA_CORE_ID_REG 0x34c
464#define SATA_CTRL_REG 0x350
465#define I2C_HSFIX_MISC_REG 0x354
466#define SPARE2_RESERVED 0x358
467#define SPARE3_RESERVED 0x35c
468#define MASTER_LOCK_REG 0x368
469#define SYSTEM_CONFIG_STATUS_REG 0x36c
470#define MSP_CLK_CTRL_REG 0x39c
471#define COMPENSATION_REG1 0x3c4
472#define COMPENSATION_REG2 0x3c8
473#define COMPENSATION_REG3 0x3cc
474#define TEST_CTL_REG 0x3d0
475
324#endif /* __STA2X11_MFD_H */ 476#endif /* __STA2X11_MFD_H */