diff options
| -rw-r--r-- | Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt | 12 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/flowctrl.c | 44 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/flowctrl.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra.c | 2 | ||||
| -rw-r--r-- | include/linux/platform_data/tegra_emc.h | 34 |
5 files changed, 53 insertions, 41 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt new file mode 100644 index 000000000000..ccf0adddc820 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | NVIDIA Tegra Flow Controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: Should be "nvidia,tegra<chip>-flowctrl" | ||
| 5 | - reg: Should contain one register range (address and length) | ||
| 6 | |||
| 7 | Example: | ||
| 8 | |||
| 9 | flow-controller@60007000 { | ||
| 10 | compatible = "nvidia,tegra20-flowctrl"; | ||
| 11 | reg = <0x60007000 0x1000>; | ||
| 12 | }; | ||
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index ec55d1de1b55..475e783992fd 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c | |||
| @@ -22,11 +22,12 @@ | |||
| 22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
| 25 | #include <linux/of.h> | ||
| 26 | #include <linux/of_address.h> | ||
| 25 | 27 | ||
| 26 | #include <soc/tegra/fuse.h> | 28 | #include <soc/tegra/fuse.h> |
| 27 | 29 | ||
| 28 | #include "flowctrl.h" | 30 | #include "flowctrl.h" |
| 29 | #include "iomap.h" | ||
| 30 | 31 | ||
| 31 | static u8 flowctrl_offset_halt_cpu[] = { | 32 | static u8 flowctrl_offset_halt_cpu[] = { |
| 32 | FLOW_CTRL_HALT_CPU0_EVENTS, | 33 | FLOW_CTRL_HALT_CPU0_EVENTS, |
| @@ -42,23 +43,22 @@ static u8 flowctrl_offset_cpu_csr[] = { | |||
| 42 | FLOW_CTRL_CPU1_CSR + 16, | 43 | FLOW_CTRL_CPU1_CSR + 16, |
| 43 | }; | 44 | }; |
| 44 | 45 | ||
| 46 | static void __iomem *tegra_flowctrl_base; | ||
| 47 | |||
| 45 | static void flowctrl_update(u8 offset, u32 value) | 48 | static void flowctrl_update(u8 offset, u32 value) |
| 46 | { | 49 | { |
| 47 | void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset; | 50 | writel(value, tegra_flowctrl_base + offset); |
| 48 | |||
| 49 | writel(value, addr); | ||
| 50 | 51 | ||
| 51 | /* ensure the update has reached the flow controller */ | 52 | /* ensure the update has reached the flow controller */ |
| 52 | wmb(); | 53 | wmb(); |
| 53 | readl_relaxed(addr); | 54 | readl_relaxed(tegra_flowctrl_base + offset); |
| 54 | } | 55 | } |
| 55 | 56 | ||
| 56 | u32 flowctrl_read_cpu_csr(unsigned int cpuid) | 57 | u32 flowctrl_read_cpu_csr(unsigned int cpuid) |
| 57 | { | 58 | { |
| 58 | u8 offset = flowctrl_offset_cpu_csr[cpuid]; | 59 | u8 offset = flowctrl_offset_cpu_csr[cpuid]; |
| 59 | void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset; | ||
| 60 | 60 | ||
| 61 | return readl(addr); | 61 | return readl(tegra_flowctrl_base + offset); |
| 62 | } | 62 | } |
| 63 | 63 | ||
| 64 | void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) | 64 | void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) |
| @@ -139,3 +139,33 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) | |||
| 139 | reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ | 139 | reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ |
| 140 | flowctrl_write_cpu_csr(cpuid, reg); | 140 | flowctrl_write_cpu_csr(cpuid, reg); |
| 141 | } | 141 | } |
| 142 | |||
| 143 | static const struct of_device_id matches[] __initconst = { | ||
| 144 | { .compatible = "nvidia,tegra124-flowctrl" }, | ||
| 145 | { .compatible = "nvidia,tegra114-flowctrl" }, | ||
| 146 | { .compatible = "nvidia,tegra30-flowctrl" }, | ||
| 147 | { .compatible = "nvidia,tegra20-flowctrl" }, | ||
| 148 | { } | ||
| 149 | }; | ||
| 150 | |||
| 151 | void __init tegra_flowctrl_init(void) | ||
| 152 | { | ||
| 153 | /* hardcoded fallback if device tree node is missing */ | ||
| 154 | unsigned long base = 0x60007000; | ||
| 155 | unsigned long size = SZ_4K; | ||
| 156 | struct device_node *np; | ||
| 157 | |||
| 158 | np = of_find_matching_node(NULL, matches); | ||
| 159 | if (np) { | ||
| 160 | struct resource res; | ||
| 161 | |||
| 162 | if (of_address_to_resource(np, 0, &res) == 0) { | ||
| 163 | size = resource_size(&res); | ||
| 164 | base = res.start; | ||
| 165 | } | ||
| 166 | |||
| 167 | of_node_put(np); | ||
| 168 | } | ||
| 169 | |||
| 170 | tegra_flowctrl_base = ioremap_nocache(base, size); | ||
| 171 | } | ||
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index c89aac60a143..73a9c5016c1a 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h | |||
| @@ -59,6 +59,8 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); | |||
| 59 | 59 | ||
| 60 | void flowctrl_cpu_suspend_enter(unsigned int cpuid); | 60 | void flowctrl_cpu_suspend_enter(unsigned int cpuid); |
| 61 | void flowctrl_cpu_suspend_exit(unsigned int cpuid); | 61 | void flowctrl_cpu_suspend_exit(unsigned int cpuid); |
| 62 | |||
| 63 | void tegra_flowctrl_init(void); | ||
| 62 | #endif | 64 | #endif |
| 63 | 65 | ||
| 64 | #endif | 66 | #endif |
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 5ef5173dec83..ef016af1c9e7 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c | |||
| @@ -48,6 +48,7 @@ | |||
| 48 | #include "board.h" | 48 | #include "board.h" |
| 49 | #include "common.h" | 49 | #include "common.h" |
| 50 | #include "cpuidle.h" | 50 | #include "cpuidle.h" |
| 51 | #include "flowctrl.h" | ||
| 51 | #include "iomap.h" | 52 | #include "iomap.h" |
| 52 | #include "irq.h" | 53 | #include "irq.h" |
| 53 | #include "pm.h" | 54 | #include "pm.h" |
| @@ -74,6 +75,7 @@ static void __init tegra_init_early(void) | |||
| 74 | { | 75 | { |
| 75 | of_register_trusted_foundations(); | 76 | of_register_trusted_foundations(); |
| 76 | tegra_cpu_reset_handler_init(); | 77 | tegra_cpu_reset_handler_init(); |
| 78 | tegra_flowctrl_init(); | ||
| 77 | } | 79 | } |
| 78 | 80 | ||
| 79 | static void __init tegra_dt_init_irq(void) | 81 | static void __init tegra_dt_init_irq(void) |
diff --git a/include/linux/platform_data/tegra_emc.h b/include/linux/platform_data/tegra_emc.h deleted file mode 100644 index df67505e98f8..000000000000 --- a/include/linux/platform_data/tegra_emc.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Google, Inc. | ||
| 3 | * | ||
| 4 | * Author: | ||
| 5 | * Colin Cross <ccross@android.com> | ||
| 6 | * Olof Johansson <olof@lixom.net> | ||
| 7 | * | ||
| 8 | * This software is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2, as published by the Free Software Foundation, and | ||
| 10 | * may be copied, distributed, and modified under those terms. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __TEGRA_EMC_H_ | ||
| 20 | #define __TEGRA_EMC_H_ | ||
| 21 | |||
| 22 | #define TEGRA_EMC_NUM_REGS 46 | ||
| 23 | |||
| 24 | struct tegra_emc_table { | ||
| 25 | unsigned long rate; | ||
| 26 | u32 regs[TEGRA_EMC_NUM_REGS]; | ||
| 27 | }; | ||
| 28 | |||
| 29 | struct tegra_emc_pdata { | ||
| 30 | int num_tables; | ||
| 31 | struct tegra_emc_table *tables; | ||
| 32 | }; | ||
| 33 | |||
| 34 | #endif | ||
