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-rw-r--r--drivers/iommu/amd_iommu_init.c13
-rw-r--r--drivers/iommu/amd_iommu_types.h10
2 files changed, 23 insertions, 0 deletions
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 38784733cbb4..bdea288dc185 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -306,6 +306,16 @@ static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
306 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 306 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
307} 307}
308 308
309static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
310{
311 u32 ctrl;
312
313 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
314 ctrl &= ~CTRL_INV_TO_MASK;
315 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
316 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
317}
318
309/* Function to enable the hardware */ 319/* Function to enable the hardware */
310static void iommu_enable(struct amd_iommu *iommu) 320static void iommu_enable(struct amd_iommu *iommu)
311{ 321{
@@ -1300,6 +1310,9 @@ static void iommu_init_flags(struct amd_iommu *iommu)
1300 * make IOMMU memory accesses cache coherent 1310 * make IOMMU memory accesses cache coherent
1301 */ 1311 */
1302 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 1312 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1313
1314 /* Set IOTLB invalidation timeout to 1s */
1315 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1303} 1316}
1304 1317
1305static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 1318static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index 6ad8b10b3130..2452f3b71736 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -127,6 +127,7 @@
127#define CONTROL_EVT_LOG_EN 0x02ULL 127#define CONTROL_EVT_LOG_EN 0x02ULL
128#define CONTROL_EVT_INT_EN 0x03ULL 128#define CONTROL_EVT_INT_EN 0x03ULL
129#define CONTROL_COMWAIT_EN 0x04ULL 129#define CONTROL_COMWAIT_EN 0x04ULL
130#define CONTROL_INV_TIMEOUT 0x05ULL
130#define CONTROL_PASSPW_EN 0x08ULL 131#define CONTROL_PASSPW_EN 0x08ULL
131#define CONTROL_RESPASSPW_EN 0x09ULL 132#define CONTROL_RESPASSPW_EN 0x09ULL
132#define CONTROL_COHERENT_EN 0x0aULL 133#define CONTROL_COHERENT_EN 0x0aULL
@@ -137,6 +138,15 @@
137#define CONTROL_PPR_EN 0x0fULL 138#define CONTROL_PPR_EN 0x0fULL
138#define CONTROL_GT_EN 0x10ULL 139#define CONTROL_GT_EN 0x10ULL
139 140
141#define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
142#define CTRL_INV_TO_NONE 0
143#define CTRL_INV_TO_1MS 1
144#define CTRL_INV_TO_10MS 2
145#define CTRL_INV_TO_100MS 3
146#define CTRL_INV_TO_1S 4
147#define CTRL_INV_TO_10S 5
148#define CTRL_INV_TO_100S 6
149
140/* command specific defines */ 150/* command specific defines */
141#define CMD_COMPL_WAIT 0x01 151#define CMD_COMPL_WAIT 0x01
142#define CMD_INV_DEV_ENTRY 0x02 152#define CMD_INV_DEV_ENTRY 0x02