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-rw-r--r--arch/x86/pci/acpi.c2
-rw-r--r--drivers/pci/pci.c2
-rw-r--r--drivers/pci/probe.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 0972315c3860..68c3c1395202 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -188,7 +188,7 @@ static bool resource_contains(struct resource *res, resource_size_t point)
188 return false; 188 return false;
189} 189}
190 190
191static void coalesce_windows(struct pci_root_info *info, int type) 191static void coalesce_windows(struct pci_root_info *info, unsigned long type)
192{ 192{
193 int i, j; 193 int i, j;
194 struct resource *res1, *res2; 194 struct resource *res1, *res2;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 5f10c23dff94..2c5b9b991279 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3284,7 +3284,7 @@ static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3284 * @dev: the PCI device 3284 * @dev: the PCI device
3285 * @decode: true = enable decoding, false = disable decoding 3285 * @decode: true = enable decoding, false = disable decoding
3286 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 3286 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3287 * @change_bridge_flags: traverse ancestors and change bridges 3287 * @flags: traverse ancestors and change bridges
3288 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE 3288 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3289 */ 3289 */
3290int pci_set_vga_state(struct pci_dev *dev, bool decode, 3290int pci_set_vga_state(struct pci_dev *dev, bool decode,
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 48849ffdd672..bafb3c3d4a89 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -168,7 +168,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
168 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; 168 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
169 if (type == pci_bar_io) { 169 if (type == pci_bar_io) {
170 l &= PCI_BASE_ADDRESS_IO_MASK; 170 l &= PCI_BASE_ADDRESS_IO_MASK;
171 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; 171 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
172 } else { 172 } else {
173 l &= PCI_BASE_ADDRESS_MEM_MASK; 173 l &= PCI_BASE_ADDRESS_MEM_MASK;
174 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 174 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;