3 files changed, 35 insertions, 11 deletions

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 03ef2481c640..a0a3b2829208 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -274,6 +274,20 @@
                 #power-domain-cells = <0>;
         };
 
+        disp_pd: power-domain@100440C0 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x100440C0 0x20>;
+                #power-domain-cells = <0>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
+                         <&clock CLK_MOUT_USER_ACLK200_DISP1>,
+                         <&clock CLK_MOUT_SW_ACLK300>,
+                         <&clock CLK_MOUT_USER_ACLK300_DISP1>,
+                         <&clock CLK_MOUT_SW_ACLK400>,
+                         <&clock CLK_MOUT_USER_ACLK400_DISP1>;
+                clock-names = "oscclk", "pclk0", "clk0",
+                              "pclk1", "clk1", "pclk2", "clk2";
+        };
+
         pinctrl_0: pinctrl@13400000 {
                 compatible = "samsung,exynos5420-pinctrl";
                 reg = <0x13400000 0x1000>;
@@ -541,6 +555,7 @@
         fimd: fimd@14400000 {
                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
                 clock-names = "sclk_fimd", "fimd";
+                power-domains = <&disp_pd>;
         };
 
         adc: adc@12D10000 {
@@ -714,6 +729,7 @@
                 phy = <&hdmiphy>;
                 samsung,syscon-phandle = <&pmu_system_controller>;
                 status = "disabled";
+                power-domains = <&disp_pd>;
         };
 
         hdmiphy: hdmiphy@145D0000 {
@@ -726,6 +742,7 @@
                 interrupts = <0 94 0>;
                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
                 clock-names = "mixer", "sclk_hdmi";
+                power-domains = <&disp_pd>;
         };
 
         gsc_0: video-scaler@13e00000 {
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 848d602efc06..07d666cc6a29 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -635,8 +635,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP3, 0, 1),
         MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
                         SRC_TOP3, 4, 1),
-        MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
-                        SRC_TOP3, 8, 1),
+        MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
+                        mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
         MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
                         SRC_TOP3, 12, 1),
         MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
@@ -663,8 +663,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
         MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
                         SRC_TOP4, 28, 1),
 
-        MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
-                        SRC_TOP5, 0, 1),
+        MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
+                        mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
         MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
                         SRC_TOP5, 4, 1),
         MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
@@ -675,8 +675,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP5, 16, 1),
         MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
                         SRC_TOP5, 20, 1),
-        MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
-                        SRC_TOP5, 24, 1),
+        MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
+                        mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
         MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
                         SRC_TOP5, 28, 1),
 
@@ -693,7 +693,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP10, 0, 1),
         MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
                         SRC_TOP10, 4, 1),
-        MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
+        MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
+                        SRC_TOP10, 8, 1),
         MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
                         SRC_TOP10, 12, 1),
         MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
@@ -717,8 +718,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
         MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
                         SRC_TOP11, 28, 1),
 
-        MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
-                        SRC_TOP12, 4, 1),
+        MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
+                        mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
         MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
                         SRC_TOP12, 8, 1),
         MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
@@ -726,8 +727,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
         MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
         MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
                         SRC_TOP12, 20, 1),
-        MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
-                        SRC_TOP12, 24, 1),
+        MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
+                        mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
         MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
                         SRC_TOP12, 28, 1),
 
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 8dc0913f1775..99da0d117a7d 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -204,6 +204,12 @@
 #define CLK_MOUT_MAUDIO0        643
 #define CLK_MOUT_USER_ACLK333   644
 #define CLK_MOUT_SW_ACLK333     645
+#define CLK_MOUT_USER_ACLK200_DISP1     646
+#define CLK_MOUT_SW_ACLK200     647
+#define CLK_MOUT_USER_ACLK300_DISP1     648
+#define CLK_MOUT_SW_ACLK300     649
+#define CLK_MOUT_USER_ACLK400_DISP1     650
+#define CLK_MOUT_SW_ACLK400     651
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL          768