151 files changed, 5881 insertions, 3863 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d70cece2ea2..62065531b639 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -671,6 +671,7 @@ config ARCH_S5P6440
         select CPU_V6
         select GENERIC_GPIO
         select HAVE_CLK
+        select ARCH_USES_GETTIMEOFFSET
         help
           Samsung S5P6440 CPU based systems
 
@@ -679,17 +680,19 @@ config ARCH_S5P6442
         select CPU_V6
         select GENERIC_GPIO
         select HAVE_CLK
+        select ARCH_USES_GETTIMEOFFSET
         help
           Samsung S5P6442 CPU based systems
 
-config ARCH_S5PC1XX
-        bool "Samsung S5PC1XX"
+config ARCH_S5PC100
+        bool "Samsung S5PC100"
         select GENERIC_GPIO
         select HAVE_CLK
         select CPU_V7
         select ARM_L1_CACHE_SHIFT_6
+        select ARCH_USES_GETTIMEOFFSET
         help
-          Samsung S5PC1XX series based systems
+          Samsung S5PC100 series based systems
 
 config ARCH_S5PV210
         bool "Samsung S5PV210/S5PC110"
@@ -697,6 +700,7 @@ config ARCH_S5PV210
         select GENERIC_GPIO
         select HAVE_CLK
         select ARM_L1_CACHE_SHIFT_6
+        select ARCH_USES_GETTIMEOFFSET
         help
           Samsung S5PV210/S5PC110 series based systems
 
@@ -876,7 +880,7 @@ source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s5p/Kconfig"
-source "arch/arm/plat-s5pc1xx/Kconfig"
+
 source "arch/arm/plat-spear/Kconfig"
 
 if ARCH_S3C2410
@@ -896,9 +900,7 @@ source "arch/arm/mach-s5p6440/Kconfig"
 
 source "arch/arm/mach-s5p6442/Kconfig"
 
-if ARCH_S5PC1XX
 source "arch/arm/mach-s5pc100/Kconfig"
-endif
 
 source "arch/arm/mach-s5pv210/Kconfig"
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 4b857fbe4314..64ba313724d2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -168,7 +168,7 @@ machine-$(CONFIG_ARCH_S3C24A0)		:= s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
 machine-$(CONFIG_ARCH_S5P6440)          := s5p6440
 machine-$(CONFIG_ARCH_S5P6442)          := s5p6442
-machine-$(CONFIG_ARCH_S5PC1XX)          := s5pc100
+machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          := s5pv210
 machine-$(CONFIG_ARCH_SA1100)           := sa1100
 machine-$(CONFIG_ARCH_SHARK)            := shark
@@ -198,7 +198,6 @@ plat-$(CONFIG_PLAT_NOMADIK)	:= nomadik
 plat-$(CONFIG_PLAT_ORION)       := orion
 plat-$(CONFIG_PLAT_PXA)         := pxa
 plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx samsung
-plat-$(CONFIG_PLAT_S5PC1XX)     := s5pc1xx samsung
 plat-$(CONFIG_PLAT_S5P)         := s5p samsung
 plat-$(CONFIG_PLAT_SPEAR)       := spear
 plat-$(CONFIG_PLAT_VERSATILE)   := versatile
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index c88e9527a8ec..a708fd6d6ffe 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -809,7 +809,22 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_SOUND is not set
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_MXC=y
+
+
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index 8e94c3caeb8c..9236475e7131 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -1,14 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc2
+# Linux kernel version: 2.6.34
+# Sat May 22 03:17:31 2010
 #
 CONFIG_ARM=y
 CONFIG_HAVE_PWM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_TIME is not set
-# CONFIG_GENERIC_CLOCKEVENTS is not set
-CONFIG_MMU=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_NO_IOPORT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -18,13 +17,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_HAS_CPUFREQ=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -34,6 +34,12 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
@@ -45,15 +51,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=m
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -69,6 +76,7 @@ CONFIG_INITRAMFS_SOURCE=""
 CONFIG_RD_GZIP=y
 CONFIG_RD_BZIP2=y
 CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -78,7 +86,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -91,19 +98,30 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_CLK=y
-# CONFIG_SLOW_WORK is not set
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_SLOW_WORK=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -115,7 +133,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -123,32 +141,62 @@ CONFIG_BLOCK=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 CONFIG_FREEZER=y
 
 #
 # System Type
 #
+CONFIG_MMU=y
 # CONFIG_ARCH_AAEC2000 is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -156,42 +204,36 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 CONFIG_ARCH_S3C2410=y
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
-CONFIG_PLAT_S3C24XX=y
-CONFIG_S3C2410_CLOCK=y
-CONFIG_S3C24XX_DCLK=y
-CONFIG_CPU_S3C244X=y
-CONFIG_S3C24XX_PWM=y
-CONFIG_S3C24XX_GPIO_EXTRA=128
-CONFIG_S3C24XX_GPIO_EXTRA64=y
-CONFIG_S3C24XX_GPIO_EXTRA128=y
-CONFIG_PM_SIMTEC=y
-CONFIG_S3C2410_DMA=y
-# CONFIG_S3C2410_DMA_DEBUG is not set
-CONFIG_S3C_ADC=y
-CONFIG_MACH_SMDK=y
-CONFIG_PLAT_S3C=y
-CONFIG_CPU_LLSERIAL_S3C2410=y
-CONFIG_CPU_LLSERIAL_S3C2440=y
+CONFIG_PLAT_SAMSUNG=y
 
 #
 # Boot options
@@ -199,15 +241,35 @@ CONFIG_CPU_LLSERIAL_S3C2440=y
 # CONFIG_S3C_BOOT_WATCHDOG is not set
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
+CONFIG_SAMSUNG_CLKSRC=y
+CONFIG_SAMSUNG_GPIO_EXTRA=0
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_ADC=y
+CONFIG_S3C_DEV_HSMMC=y
+CONFIG_S3C_DEV_USB_HOST=y
+CONFIG_S3C_DEV_NAND=y
+CONFIG_S3C_DMA=y
 
 #
 # Power management
 #
 # CONFIG_SAMSUNG_PM_DEBUG is not set
 # CONFIG_SAMSUNG_PM_CHECK is not set
-CONFIG_S3C_LOWLEVEL_UART_PORT=0
-CONFIG_S3C_GPIO_SPACE=0
-CONFIG_S3C_DEV_HSMMC=y
+CONFIG_PLAT_S3C24XX=y
+CONFIG_CPU_LLSERIAL_S3C2410=y
+CONFIG_CPU_LLSERIAL_S3C2440=y
+CONFIG_S3C2410_CLOCK=y
+CONFIG_S3C24XX_DCLK=y
+CONFIG_S3C24XX_PWM=y
+CONFIG_S3C24XX_GPIO_EXTRA=128
+CONFIG_S3C24XX_GPIO_EXTRA64=y
+CONFIG_S3C24XX_GPIO_EXTRA128=y
+CONFIG_PM_SIMTEC=y
+CONFIG_S3C2410_DMA=y
+# CONFIG_S3C2410_DMA_DEBUG is not set
+CONFIG_MACH_SMDK=y
+CONFIG_S3C24XX_SIMTEC_AUDIO=y
 
 #
 # S3C2400 Machines
@@ -224,6 +286,7 @@ CONFIG_MACH_BAST_IDE=y
 #
 CONFIG_ARCH_SMDK2410=y
 CONFIG_ARCH_H1940=y
+# CONFIG_H1940BT is not set
 CONFIG_PM_H1940=y
 CONFIG_MACH_N30=y
 CONFIG_ARCH_BAST=y
@@ -247,25 +310,26 @@ CONFIG_MACH_S3C2413=y
 CONFIG_MACH_SMDK2412=y
 CONFIG_MACH_VSTMS=y
 CONFIG_CPU_S3C2440=y
+CONFIG_CPU_S3C2442=y
+CONFIG_CPU_S3C244X=y
+CONFIG_S3C2440_XTAL_12000000=y
+CONFIG_S3C2440_XTAL_16934400=y
 CONFIG_S3C2440_DMA=y
 
 #
-# S3C2440 Machines
+# S3C2440 and S3C2442 Machines
 #
 CONFIG_MACH_ANUBIS=y
+# CONFIG_MACH_NEO1973_GTA02 is not set
 CONFIG_MACH_OSIRIS=y
+# CONFIG_MACH_OSIRIS_DVS is not set
 CONFIG_MACH_RX3715=y
 CONFIG_ARCH_S3C2440=y
 CONFIG_MACH_NEXCODER_2440=y
 CONFIG_SMDK2440_CPU2440=y
+CONFIG_SMDK2440_CPU2442=y
 CONFIG_MACH_AT2440EVB=y
-CONFIG_CPU_S3C2442=y
 CONFIG_MACH_MINI2440=y
-
-#
-# S3C2442 Machines
-#
-CONFIG_SMDK2440_CPU2442=y
 CONFIG_CPU_S3C2443=y
 CONFIG_S3C2443_DMA=y
 
@@ -283,7 +347,7 @@ CONFIG_CPU_32v4T=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV4T=y
 CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_PABRT_LEGACY=y
 CONFIG_CPU_CACHE_V4WT=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
@@ -299,7 +363,7 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-# CONFIG_OUTER_CACHE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
 
 #
 # Bus support
@@ -316,10 +380,11 @@ CONFIG_VMSPLIT_3G=y
 # CONFIG_VMSPLIT_2G is not set
 # CONFIG_VMSPLIT_1G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=200
 # CONFIG_AEABI is not set
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -330,14 +395,14 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
+CONFIG_SPLIT_PTLOCK_CPUS=999999
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -351,6 +416,7 @@ CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
 #
 # CPU Power Management
 #
+# CONFIG_CPU_FREQ is not set
 # CONFIG_CPU_IDLE is not set
 
 #
@@ -384,6 +450,8 @@ CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
 CONFIG_APM_EMULATION=m
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_OPS=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
 
@@ -391,7 +459,6 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 CONFIG_XFRM_USER=m
@@ -463,6 +530,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m
 CONFIG_INET6_XFRM_MODE_BEET=m
 CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
 CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
 CONFIG_IPV6_NDISC_NODETYPE=y
 CONFIG_IPV6_TUNNEL=m
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
@@ -500,6 +568,7 @@ CONFIG_NF_CT_NETLINK=m
 CONFIG_NETFILTER_XTABLES=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
 # CONFIG_NETFILTER_XT_TARGET_DSCP is not set
 CONFIG_NETFILTER_XT_TARGET_HL=m
 CONFIG_NETFILTER_XT_TARGET_LED=m
@@ -544,6 +613,7 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
 CONFIG_IP_VS=m
 # CONFIG_IP_VS_IPV6 is not set
 # CONFIG_IP_VS_DEBUG is not set
@@ -556,6 +626,7 @@ CONFIG_IP_VS_TAB_BITS=12
 # CONFIG_IP_VS_PROTO_UDP is not set
 # CONFIG_IP_VS_PROTO_ESP is not set
 # CONFIG_IP_VS_PROTO_AH is not set
+# CONFIG_IP_VS_PROTO_SCTP is not set
 
 #
 # IPVS scheduler
@@ -639,6 +710,7 @@ CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -653,6 +725,7 @@ CONFIG_IP6_NF_RAW=m
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 # CONFIG_DCB is not set
@@ -687,19 +760,21 @@ CONFIG_BT_HCIBCM203X=m
 CONFIG_BT_HCIBPA10X=m
 CONFIG_BT_HCIBFUSB=m
 CONFIG_BT_HCIVHCI=m
+# CONFIG_BT_MRVL is not set
 # CONFIG_AF_RXRPC is not set
 CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
 CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
 # CONFIG_CFG80211_REG_DEBUG is not set
-# CONFIG_WIRELESS_OLD_REGULATORY is not set
-CONFIG_WIRELESS_EXT=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
 # CONFIG_LIB80211 is not set
 CONFIG_MAC80211=m
-
-#
-# Rate control algorithm selection
-#
 CONFIG_MAC80211_RC_MINSTREL=y
 # CONFIG_MAC80211_RC_DEFAULT_PID is not set
 CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
@@ -719,6 +794,7 @@ CONFIG_MAC80211_LEDS=y
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
@@ -730,9 +806,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
 CONFIG_MTD_REDBOOT_PARTS=y
 CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
@@ -793,6 +869,7 @@ CONFIG_MTD_ROM=y
 #
 # CONFIG_MTD_DATAFLASH is not set
 # CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -843,6 +920,10 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_UB=m
 CONFIG_BLK_DEV_RAM=y
@@ -851,19 +932,26 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_MG_DISK is not set
 CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
 # CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
 # CONFIG_C2PORT is not set
 
 #
 # EEPROM support
 #
-CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=m
 CONFIG_EEPROM_LEGACY=m
+# CONFIG_EEPROM_MAX6875 is not set
 CONFIG_EEPROM_93CX6=m
+# CONFIG_IWMC3200TOP is not set
 CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 
@@ -890,6 +978,7 @@ CONFIG_BLK_DEV_PLATFORM=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
@@ -907,10 +996,6 @@ CONFIG_BLK_DEV_SR=m
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
 CONFIG_CHR_DEV_SCH=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 # CONFIG_SCSI_LOGGING is not set
@@ -951,7 +1036,6 @@ CONFIG_SCSI_LOWLEVEL=y
 CONFIG_HAVE_PATA_PLATFORM=y
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -989,16 +1073,30 @@ CONFIG_DM9000_DEBUGLEVEL=4
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
 # CONFIG_CS89x0 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NET_POCKET is not set
 CONFIG_NETDEV_1000=y
 CONFIG_NETDEV_10000=y
 # CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -1012,6 +1110,7 @@ CONFIG_NETDEV_10000=y
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
 # CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
 # CONFIG_WAN is not set
 # CONFIG_PLIP is not set
 # CONFIG_PPP is not set
@@ -1020,6 +1119,7 @@ CONFIG_NETDEV_10000=y
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
 
 #
 # Input device support
@@ -1027,6 +1127,7 @@ CONFIG_NETDEV_10000=y
 CONFIG_INPUT=y
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
@@ -1043,13 +1144,19 @@ CONFIG_INPUT_EVDEV=y
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
 CONFIG_MOUSE_PS2_ALPS=y
@@ -1057,6 +1164,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
 CONFIG_MOUSE_PS2_SYNAPTICS=y
 CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
 # CONFIG_MOUSE_SERIAL is not set
 CONFIG_MOUSE_APPLETOUCH=m
@@ -1066,6 +1174,7 @@ CONFIG_MOUSE_BCM5974=m
 # CONFIG_MOUSE_PC110PAD is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
 CONFIG_INPUT_JOYSTICK=y
 CONFIG_JOYSTICK_ANALOG=m
 CONFIG_JOYSTICK_A3D=m
@@ -1102,10 +1211,14 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_AD7879_I2C is not set
 # CONFIG_TOUCHSCREEN_AD7879_SPI is not set
 # CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_S3C2410 is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
@@ -1126,8 +1239,14 @@ CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
 CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
 CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
 CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC5UH=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_ATI_REMOTE=m
 CONFIG_INPUT_ATI_REMOTE2=m
@@ -1146,6 +1265,7 @@ CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_PARKBD is not set
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
 CONFIG_GAMEPORT=m
 # CONFIG_GAMEPORT_NS558 is not set
 # CONFIG_GAMEPORT_L4 is not set
@@ -1169,8 +1289,6 @@ CONFIG_SERIAL_NONSTANDARD=y
 # CONFIG_N_HDLC is not set
 # CONFIG_RISCOM8 is not set
 # CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_RIO is not set
 # CONFIG_STALDRV is not set
 
 #
@@ -1195,6 +1313,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
 # Non-8250 serial port support
 #
 CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS_4=y
 CONFIG_SERIAL_SAMSUNG_UARTS=4
 # CONFIG_SERIAL_SAMSUNG_DEBUG is not set
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
@@ -1204,6 +1323,7 @@ CONFIG_SERIAL_S3C2440=y
 # CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -1221,6 +1341,7 @@ CONFIG_HW_RANDOM=y
 CONFIG_DEVPORT=y
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_ALGOBIT=y
@@ -1232,10 +1353,12 @@ CONFIG_I2C_ALGOBIT=y
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 CONFIG_I2C_S3C2410=y
 CONFIG_I2C_SIMTEC=y
+# CONFIG_I2C_XILINX is not set
 
 #
 # External I2C/SMBus adapter drivers
@@ -1252,20 +1375,9 @@ CONFIG_I2C_SIMTEC=y
 # CONFIG_I2C_PCA_ISA is not set
 # CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
 CONFIG_SPI=y
 # CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
@@ -1278,13 +1390,21 @@ CONFIG_SPI_BITBANG=m
 CONFIG_SPI_GPIO=m
 # CONFIG_SPI_LM70_LLP is not set
 CONFIG_SPI_S3C24XX=m
+# CONFIG_SPI_S3C24XX_FIQ is not set
 CONFIG_SPI_S3C24XX_GPIO=m
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
 
 #
 # SPI Protocol Masters
 #
 CONFIG_SPI_SPIDEV=m
 CONFIG_SPI_TLE62X0=m
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
@@ -1293,13 +1413,16 @@ CONFIG_GPIOLIB=y
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX7300 is not set
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
 
 #
 # PCI GPIO expanders:
@@ -1310,10 +1433,20 @@ CONFIG_GPIOLIB=y
 #
 # CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 CONFIG_HWMON_VID=m
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
 # CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADCXX is not set
@@ -1323,10 +1456,11 @@ CONFIG_HWMON_VID=m
 # CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
 # CONFIG_SENSORS_ADT7462 is not set
 # CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
@@ -1338,6 +1472,7 @@ CONFIG_HWMON_VID=m
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM63 is not set
 # CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
 CONFIG_SENSORS_LM75=m
 # CONFIG_SENSORS_LM77 is not set
 CONFIG_SENSORS_LM78=m
@@ -1358,12 +1493,16 @@ CONFIG_SENSORS_LM85=m
 # CONFIG_SENSORS_PC87427 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_S3C is not set
 # CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83791D is not set
@@ -1374,9 +1513,8 @@ CONFIG_SENSORS_LM85=m
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_SENSORS_LIS3_SPI is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -1385,6 +1523,7 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_S3C2410_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
 
 #
 # ISA-based Watchdog Cards
@@ -1408,11 +1547,13 @@ CONFIG_SSB_POSSIBLE=y
 # Multifunction device drivers
 #
 # CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
 CONFIG_MFD_SM501=y
 # CONFIG_MFD_SM501_GPIO is not set
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
 # CONFIG_UCB1400_CORE is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
@@ -1421,200 +1562,19 @@ CONFIG_MFD_SM501=y
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
 # CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
 # CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=m
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-CONFIG_DVB_CORE=m
-CONFIG_VIDEO_MEDIA=m
-
-#
-# Multimedia drivers
-#
-CONFIG_MEDIA_ATTACH=y
-CONFIG_MEDIA_TUNER=m
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L1=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_VMALLOC=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_VIDEO_VIVI=m
-CONFIG_VIDEO_PMS=m
-CONFIG_VIDEO_BWQCAM=m
-CONFIG_VIDEO_CQCAM=m
-CONFIG_VIDEO_W9966=m
-CONFIG_VIDEO_CPIA=m
-CONFIG_VIDEO_CPIA_PP=m
-CONFIG_VIDEO_CPIA_USB=m
-CONFIG_VIDEO_CPIA2=m
-CONFIG_VIDEO_SAA5246A=m
-CONFIG_VIDEO_SAA5249=m
-CONFIG_VIDEO_AU0828=m
-# CONFIG_SOC_CAMERA is not set
-CONFIG_V4L_USB_DRIVERS=y
-# CONFIG_USB_VIDEO_CLASS is not set
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_HDPVR is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_CX231XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_VICAM is not set
-# CONFIG_USB_IBMCAM is not set
-# CONFIG_USB_KONICAWC is not set
-# CONFIG_USB_QUICKCAM_MESSENGER is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_VIDEO_OVCAMCHIP is not set
-# CONFIG_USB_OV511 is not set
-# CONFIG_USB_SE401 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_STV680 is not set
-# CONFIG_USB_ZC0301 is not set
-# CONFIG_USB_PWC is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_CADET=m
-CONFIG_RADIO_RTRACK=m
-CONFIG_RADIO_RTRACK2=m
-CONFIG_RADIO_AZTECH=m
-CONFIG_RADIO_GEMTEK=m
-CONFIG_RADIO_SF16FMI=m
-CONFIG_RADIO_SF16FMR2=m
-CONFIG_RADIO_TERRATEC=m
-CONFIG_RADIO_TRUST=m
-CONFIG_RADIO_TYPHOON=m
-CONFIG_RADIO_TYPHOON_PROC_FS=y
-CONFIG_RADIO_ZOLTRIX=m
-CONFIG_USB_DSBR=m
-CONFIG_USB_SI470X=m
-CONFIG_USB_MR800=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_DVB_DYNAMIC_MINORS=y
-CONFIG_DVB_CAPTURE_DRIVERS=y
-# CONFIG_TTPCI_EEPROM is not set
-
-#
-# Supported USB Adapters
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-# CONFIG_DVB_USB_A800 is not set
-CONFIG_DVB_USB_DIBUSB_MB=m
-# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_M920X=m
-# CONFIG_DVB_USB_GL861 is not set
-# CONFIG_DVB_USB_AU6610 is not set
-# CONFIG_DVB_USB_DIGITV is not set
-# CONFIG_DVB_USB_VP7045 is not set
-# CONFIG_DVB_USB_VP702X is not set
-# CONFIG_DVB_USB_GP8PSK is not set
-# CONFIG_DVB_USB_NOVA_T_USB2 is not set
-# CONFIG_DVB_USB_TTUSB2 is not set
-# CONFIG_DVB_USB_DTT200U is not set
-# CONFIG_DVB_USB_OPERA1 is not set
-CONFIG_DVB_USB_AF9005=m
-# CONFIG_DVB_USB_AF9005_REMOTE is not set
-# CONFIG_DVB_USB_DW2102 is not set
-# CONFIG_DVB_USB_CINERGY_T2 is not set
-# CONFIG_DVB_USB_ANYSEE is not set
-# CONFIG_DVB_USB_DTV5100 is not set
-# CONFIG_DVB_USB_AF9015 is not set
-# CONFIG_DVB_USB_CE6230 is not set
-# CONFIG_DVB_SIANO_SMS1XXX is not set
-
-#
-# Supported FlexCopII (B2C2) Adapters
-#
-# CONFIG_DVB_B2C2_FLEXCOP is not set
-
-#
-# Supported DVB Frontends
-#
-# CONFIG_DVB_FE_CUSTOMISE is not set
-CONFIG_DVB_CX22702=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_S5H1411=m
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_LGS8GL5=m
-CONFIG_DAB=y
-CONFIG_USB_DABUSB=m
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_AB4500_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -1653,6 +1613,8 @@ CONFIG_FB_SM501=y
 # CONFIG_FB_BROADSHEET is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
 # CONFIG_LCD_LTV350QV is not set
 # CONFIG_LCD_ILI9320 is not set
 # CONFIG_LCD_TDO24M is not set
@@ -1682,6 +1644,7 @@ CONFIG_FONT_8x16=y
 # CONFIG_LOGO is not set
 CONFIG_SOUND=y
 CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
@@ -1701,36 +1664,43 @@ CONFIG_SND_VERBOSE_PROCFS=y
 CONFIG_SND_VERBOSE_PRINTK=y
 # CONFIG_SND_DEBUG is not set
 CONFIG_SND_VMASTER=y
+CONFIG_SND_RAWMIDI_SEQ=m
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_DRIVERS is not set
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 CONFIG_SND_USB=y
 CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
 CONFIG_SND_USB_CAIAQ=m
 # CONFIG_SND_USB_CAIAQ_INPUT is not set
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_S3C24XX_SOC=y
-CONFIG_SND_S3C24XX_SOC_I2S=m
+CONFIG_SND_S3C24XX_SOC_I2S=y
 CONFIG_SND_S3C_I2SV2_SOC=m
 CONFIG_SND_S3C2412_SOC_I2S=m
-CONFIG_SND_S3C2443_SOC_AC97=m
+CONFIG_SND_S3C_SOC_AC97=m
 CONFIG_SND_S3C24XX_SOC_JIVE_WM8750=m
 CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710=m
 CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650=m
-CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=m
+CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y
+# CONFIG_SND_S3C24XX_SOC_SIMTEC_TLV320AIC23 is not set
+# CONFIG_SND_S3C24XX_SOC_SIMTEC_HERMES is not set
 CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ALL_CODECS is not set
 CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_L3=m
-CONFIG_SND_SOC_UDA134X=m
+CONFIG_SND_SOC_L3=y
+CONFIG_SND_SOC_UDA134X=y
 CONFIG_SND_SOC_WM8750=m
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=y
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
 
 #
@@ -1743,6 +1713,8 @@ CONFIG_HID=y
 # Special HID drivers
 #
 CONFIG_HID_APPLE=m
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_WACOM is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1757,8 +1729,6 @@ CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
 CONFIG_USB_MON=y
 # CONFIG_USB_WUSB is not set
 # CONFIG_USB_WUSB_CBAF is not set
@@ -1770,6 +1740,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1854,6 +1825,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y
 CONFIG_USB_SERIAL_NAVMAN=m
 CONFIG_USB_SERIAL_PL2303=y
 # CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
 # CONFIG_USB_SERIAL_QUALCOMM is not set
 # CONFIG_USB_SERIAL_SPCP8X5 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
@@ -1867,6 +1839,7 @@ CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_SERIAL_OPTION=m
 # CONFIG_USB_SERIAL_OMNINET is not set
 # CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
 # CONFIG_USB_SERIAL_DEBUG is not set
 
 #
@@ -1879,7 +1852,6 @@ CONFIG_USB_SEVSEG=m
 CONFIG_USB_RIO500=m
 CONFIG_USB_LEGOTOWER=m
 CONFIG_USB_LCD=m
-CONFIG_USB_BERRY_CHARGE=m
 CONFIG_USB_LED=m
 CONFIG_USB_CYPRESS_CY7C63=m
 CONFIG_USB_CYTHERM=m
@@ -1891,13 +1863,13 @@ CONFIG_USB_TRANCEVIBRATOR=m
 CONFIG_USB_IOWARRIOR=m
 CONFIG_USB_TEST=m
 # CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 
 #
 # OTG and related infrastructure
 #
 # CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
 # CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
@@ -1915,10 +1887,15 @@ CONFIG_MMC_TEST=m
 # MMC/SD/SDIO Host Controller Drivers
 #
 CONFIG_MMC_SDHCI=m
+# CONFIG_MMC_SDHCI_PLTFM is not set
+# CONFIG_MMC_SDHCI_S3C is not set
 CONFIG_MMC_SPI=m
 CONFIG_MMC_S3C=y
+# CONFIG_MMC_S3C_HW_SDIO_IRQ is not set
+CONFIG_MMC_S3C_PIO=y
+# CONFIG_MMC_S3C_DMA is not set
+# CONFIG_MMC_S3C_PIODMA is not set
 # CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=m
 
@@ -1930,26 +1907,28 @@ CONFIG_LEDS_H1940=m
 CONFIG_LEDS_PCA9532=m
 CONFIG_LEDS_GPIO=m
 CONFIG_LEDS_GPIO_PLATFORM=y
-CONFIG_LEDS_LP5521=m
+# CONFIG_LEDS_LP3944 is not set
 CONFIG_LEDS_PCA955X=m
 CONFIG_LEDS_DAC124S085=m
 CONFIG_LEDS_PWM=m
 CONFIG_LEDS_BD2802=m
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
 
 #
 # LED Triggers
 #
-CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=m
 # CONFIG_LEDS_TRIGGER_IDE_DISK is not set
 CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_LEDS_TRIGGER_GPIO=m
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
 
 #
 # iptables trigger is under Netfilter config (LED target)
 #
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1978,9 +1957,11 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
@@ -1992,6 +1973,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
 # CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 
 #
 # Platform RTC drivers
@@ -2005,7 +1987,9 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
 # CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
@@ -2014,8 +1998,11 @@ CONFIG_RTC_INTF_DEV=y
 CONFIG_RTC_DRV_S3C=y
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
-# CONFIG_REGULATOR is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -2032,20 +2019,23 @@ CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 # CONFIG_EXT3_FS_SECURITY is not set
 CONFIG_EXT4_FS=m
-# CONFIG_EXT4DEV_COMPAT is not set
 CONFIG_EXT4_FS_XATTR=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 # CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
 CONFIG_JBD=y
 CONFIG_JBD2=m
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -2053,6 +2043,7 @@ CONFIG_INOTIFY_USER=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
 CONFIG_GENERIC_ACL=y
 
 #
@@ -2111,6 +2102,7 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 CONFIG_SQUASHFS=m
 # CONFIG_SQUASHFS_EMBEDDED is not set
@@ -2127,7 +2119,6 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y
 CONFIG_ROMFS_ON_BLOCK=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -2149,6 +2140,7 @@ CONFIG_SUNRPC_GSS=m
 CONFIG_RPCSEC_GSS_KRB5=m
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
 CONFIG_CIFS=m
 # CONFIG_CIFS_STATS is not set
 # CONFIG_CIFS_WEAK_PW_HASH is not set
@@ -2230,6 +2222,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
@@ -2246,6 +2239,7 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -2264,28 +2258,28 @@ CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_PAGE_POISONING is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
+CONFIG_FTRACE=y
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
@@ -2297,7 +2291,9 @@ CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
+# CONFIG_EARLY_PRINTK is not set
 # CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_OC_ETM is not set
 CONFIG_DEBUG_S3C_UART=0
 
 #
@@ -2306,13 +2302,16 @@ CONFIG_DEBUG_S3C_UART=0
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=m
 CONFIG_CRYPTO_ALGAPI2=m
 CONFIG_CRYPTO_AEAD=m
@@ -2355,11 +2354,13 @@ CONFIG_CRYPTO_ECB=m
 #
 CONFIG_CRYPTO_HMAC=m
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=m
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
@@ -2420,9 +2421,11 @@ CONFIG_CRC7=m
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_DECOMPRESS_GZIP=y
 CONFIG_DECOMPRESS_BZIP2=y
 CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
 CONFIG_TEXTSEARCH=y
 CONFIG_TEXTSEARCH_KMP=m
 CONFIG_TEXTSEARCH_BM=m
@@ -2430,3 +2433,4 @@ CONFIG_TEXTSEARCH_FSM=m
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_DMA=y
 CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index 5e7d4c1b8fc1..a3a9993e5cd0 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -1,11 +1,12 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.33-rc4
-# Tue Jan 19 13:12:40 2010
+# Linux kernel version: 2.6.34
+# Sat May 22 03:17:32 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_NO_IOPORT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -18,6 +19,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_ARCH_HAS_CPUFREQ=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -53,7 +55,6 @@ CONFIG_RCU_FANOUT=32
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -89,10 +90,14 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
 # Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
@@ -164,7 +169,7 @@ CONFIG_DEFAULT_IOSCHED="cfq"
 # CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
 # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
 # CONFIG_MUTEX_SPIN_ON_OWNER is not set
-# CONFIG_FREEZER is not set
+CONFIG_FREEZER=y
 
 #
 # System Type
@@ -175,6 +180,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
@@ -184,7 +190,6 @@ CONFIG_MMU=y
 # CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -201,30 +206,44 @@ CONFIG_MMU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 CONFIG_ARCH_S3C64XX=y
 # CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
 # CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_U8500 is not set
 CONFIG_PLAT_SAMSUNG=y
+
+#
+# Boot options
+#
+CONFIG_S3C_BOOT_ERROR_RESET=y
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
 CONFIG_SAMSUNG_CLKSRC=y
 CONFIG_SAMSUNG_IRQ_VIC_TIMER=y
 CONFIG_SAMSUNG_IRQ_UART=y
+CONFIG_SAMSUNG_GPIOLIB_4BIT=y
 CONFIG_S3C_GPIO_CFG_S3C24XX=y
 CONFIG_S3C_GPIO_CFG_S3C64XX=y
 CONFIG_S3C_GPIO_PULL_UPDOWN=y
 CONFIG_SAMSUNG_GPIO_EXTRA=0
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
 # CONFIG_S3C_ADC is not set
 CONFIG_S3C_DEV_HSMMC=y
 CONFIG_S3C_DEV_HSMMC1=y
@@ -233,36 +252,29 @@ CONFIG_S3C_DEV_FB=y
 CONFIG_S3C_DEV_USB_HOST=y
 CONFIG_S3C_DEV_USB_HSOTG=y
 CONFIG_S3C_DEV_NAND=y
+CONFIG_S3C_DMA=y
+
+#
+# Power management
+#
+# CONFIG_SAMSUNG_PM_DEBUG is not set
+# CONFIG_S3C_PM_DEBUG_LED_SMDK is not set
+# CONFIG_SAMSUNG_PM_CHECK is not set
 CONFIG_PLAT_S3C64XX=y
-CONFIG_CPU_S3C6400_INIT=y
-CONFIG_CPU_S3C6400_CLOCK=y
-# CONFIG_S3C64XX_DMA is not set
+CONFIG_CPU_S3C6410=y
+CONFIG_S3C64XX_DMA=y
+CONFIG_S3C64XX_SETUP_SDHCI=y
 CONFIG_S3C64XX_SETUP_I2C0=y
 CONFIG_S3C64XX_SETUP_I2C1=y
 CONFIG_S3C64XX_SETUP_FB_24BPP=y
 CONFIG_S3C64XX_SETUP_SDHCI_GPIO=y
-CONFIG_PLAT_S3C=y
-
-#
-# Boot options
-#
-CONFIG_S3C_BOOT_ERROR_RESET=y
-CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
-
-#
-# Power management
-#
-CONFIG_S3C_LOWLEVEL_UART_PORT=0
-CONFIG_S3C_GPIO_SPACE=0
-CONFIG_S3C_GPIO_TRACK=y
 # CONFIG_MACH_SMDK6400 is not set
-CONFIG_CPU_S3C6410=y
-CONFIG_S3C6410_SETUP_SDHCI=y
 # CONFIG_MACH_ANW6410 is not set
 CONFIG_MACH_SMDK6410=y
 CONFIG_SMDK6410_SD_CH0=y
 # CONFIG_SMDK6410_SD_CH1 is not set
 # CONFIG_SMDK6410_WM1190_EV1 is not set
+# CONFIG_SMDK6410_WM1192_EV1 is not set
 # CONFIG_MACH_NCP is not set
 # CONFIG_MACH_HMT is not set
 
@@ -290,6 +302,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_ARM_VIC=y
 CONFIG_ARM_VIC_NR=2
@@ -371,7 +384,14 @@ CONFIG_HAVE_AOUT=y
 #
 # Power management options
 #
-# CONFIG_PM is not set
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_OPS=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_NET is not set
 
@@ -392,7 +412,88 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_PARTITIONS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+# CONFIG_MTD_BLKDEVS is not set
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_S3C2410=y
+# CONFIG_MTD_NAND_S3C2410_DEBUG is not set
+# CONFIG_MTD_NAND_S3C2410_HWECC is not set
+# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -413,6 +514,7 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_DS1682 is not set
 # CONFIG_C2PORT is not set
 
@@ -430,6 +532,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_DMA is not set
@@ -527,12 +630,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 # Non-8250 serial port support
 #
 CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS_4=y
 CONFIG_SERIAL_SAMSUNG_UARTS=4
 # CONFIG_SERIAL_SAMSUNG_DEBUG is not set
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_S3C6400=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -561,6 +666,7 @@ CONFIG_I2C_HELPER_AUTO=y
 # CONFIG_I2C_OCORES is not set
 CONFIG_I2C_S3C2410=y
 # CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
 
 #
 # External I2C/SMBus adapter drivers
@@ -573,15 +679,9 @@ CONFIG_I2C_S3C2410=y
 #
 # CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
 
 #
@@ -596,10 +696,12 @@ CONFIG_GPIOLIB=y
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX7300 is not set
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
@@ -633,10 +735,11 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
 # CONFIG_SENSORS_ADT7462 is not set
 # CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
@@ -699,10 +802,13 @@ CONFIG_SSB_POSSIBLE=y
 # Multifunction device drivers
 #
 # CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_UCB1400_CORE is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
@@ -711,12 +817,13 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_TC6393XB is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_AB3100_CORE is not set
-# CONFIG_MFD_88PM8607 is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
@@ -738,7 +845,44 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_S3C24XX_SOC=m
+CONFIG_SND_S3C_SOC_AC97=m
+CONFIG_SND_SOC_SMDK_WM9713=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM9713=m
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HIDRAW is not set
@@ -784,8 +928,6 @@ CONFIG_MMC_SDHCI=y
 # CONFIG_MMC_SDHCI_PLTFM is not set
 CONFIG_MMC_SDHCI_S3C=y
 # CONFIG_MMC_SDHCI_S3C_DMA is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
@@ -869,6 +1011,8 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p6440_defconfig
index 279a15e53114..619bfab3ab39 100644
--- a/arch/arm/configs/s5p6440_defconfig
+++ b/arch/arm/configs/s5p6440_defconfig
@@ -1,11 +1,12 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.33-rc2
-# Sat Jan  9 16:33:55 2010
+# Linux kernel version: 2.6.34
+# Sat May 22 03:18:18 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_NO_IOPORT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -17,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -30,6 +32,12 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 # CONFIG_SYSVIPC is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
@@ -46,7 +54,6 @@ CONFIG_RCU_FANOUT=32
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -60,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
 CONFIG_RD_GZIP=y
 CONFIG_RD_BZIP2=y
 CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -81,10 +89,14 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
 # Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
@@ -167,6 +179,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
@@ -176,7 +189,6 @@ CONFIG_MMU=y
 # CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -193,44 +205,50 @@ CONFIG_MMU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
 CONFIG_ARCH_S5P6440=y
+# CONFIG_ARCH_S5P6442 is not set
 # CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_U8500 is not set
 CONFIG_PLAT_SAMSUNG=y
-CONFIG_SAMSUNG_CLKSRC=y
-CONFIG_SAMSUNG_IRQ_VIC_TIMER=y
-CONFIG_SAMSUNG_IRQ_UART=y
-CONFIG_SAMSUNG_GPIO_EXTRA=0
-CONFIG_PLAT_S3C=y
 
 #
 # Boot options
 #
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+CONFIG_S3C_LOWLEVEL_UART_PORT=1
+CONFIG_SAMSUNG_CLKSRC=y
+CONFIG_SAMSUNG_IRQ_VIC_TIMER=y
+CONFIG_SAMSUNG_IRQ_UART=y
+CONFIG_SAMSUNG_GPIOLIB_4BIT=y
+CONFIG_S3C_GPIO_CFG_S3C24XX=y
+CONFIG_S3C_GPIO_CFG_S3C64XX=y
+CONFIG_S3C_GPIO_PULL_UPDOWN=y
+CONFIG_SAMSUNG_GPIO_EXTRA=0
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+# CONFIG_S3C_ADC is not set
 
 #
 # Power management
 #
-CONFIG_S3C_LOWLEVEL_UART_PORT=1
-CONFIG_S3C_GPIO_SPACE=0
-CONFIG_S3C_GPIO_TRACK=y
 CONFIG_PLAT_S5P=y
-CONFIG_CPU_S5P6440_INIT=y
-CONFIG_CPU_S5P6440_CLOCK=y
 CONFIG_CPU_S5P6440=y
 CONFIG_MACH_SMDK6440=y
 
@@ -258,6 +276,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_ARM_VIC=y
 CONFIG_ARM_VIC_NR=2
@@ -382,6 +401,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
@@ -518,12 +538,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=3
 # Non-8250 serial port support
 #
 CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS_4=y
 CONFIG_SERIAL_SAMSUNG_UARTS=4
 # CONFIG_SERIAL_SAMSUNG_DEBUG is not set
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_SERIAL_S5P6440=y
+CONFIG_SERIAL_S3C6400=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -549,6 +571,7 @@ CONFIG_GPIOLIB=y
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
@@ -704,6 +727,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -962,8 +986,10 @@ CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_DECOMPRESS_GZIP=y
 CONFIG_DECOMPRESS_BZIP2=y
 CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/s5p6442_defconfig b/arch/arm/configs/s5p6442_defconfig
index 74e20bfc0487..d7ea27509cf4 100644
--- a/arch/arm/configs/s5p6442_defconfig
+++ b/arch/arm/configs/s5p6442_defconfig
@@ -1,11 +1,12 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.33-rc4
-# Mon Jan 25 08:50:28 2010
+# Linux kernel version: 2.6.34
+# Sat May 22 03:18:19 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_NO_IOPORT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -17,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -52,7 +54,6 @@ CONFIG_RCU_FANOUT=32
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -88,10 +89,14 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
 # Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
@@ -174,6 +179,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
@@ -183,7 +189,6 @@ CONFIG_MMU=y
 # CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -200,9 +205,11 @@ CONFIG_MMU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
@@ -210,14 +217,22 @@ CONFIG_MMU=y
 # CONFIG_ARCH_S5P6440 is not set
 CONFIG_ARCH_S5P6442=y
 # CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_U8500 is not set
 CONFIG_PLAT_SAMSUNG=y
+
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_SAMSUNG_CLKSRC=y
 CONFIG_SAMSUNG_IRQ_VIC_TIMER=y
 CONFIG_SAMSUNG_IRQ_UART=y
@@ -226,21 +241,13 @@ CONFIG_S3C_GPIO_CFG_S3C24XX=y
 CONFIG_S3C_GPIO_CFG_S3C64XX=y
 CONFIG_S3C_GPIO_PULL_UPDOWN=y
 CONFIG_SAMSUNG_GPIO_EXTRA=0
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
 # CONFIG_S3C_ADC is not set
 
 #
 # Power management
 #
-CONFIG_PLAT_S3C=y
-
-#
-# Boot options
-#
-# CONFIG_S3C_BOOT_ERROR_RESET is not set
-CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
-CONFIG_S3C_LOWLEVEL_UART_PORT=1
-CONFIG_S3C_GPIO_SPACE=0
-CONFIG_S3C_GPIO_TRACK=y
 CONFIG_PLAT_S5P=y
 CONFIG_CPU_S5P6442=y
 CONFIG_MACH_SMDK6442=y
@@ -269,6 +276,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_ARM_VIC=y
 CONFIG_ARM_VIC_NR=2
@@ -394,6 +402,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
@@ -515,6 +524,7 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_S5PV210=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -540,6 +550,7 @@ CONFIG_GPIOLIB=y
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
@@ -685,6 +696,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig
index dc108afc060c..2053be6c9af1 100644
--- a/arch/arm/configs/s5pc100_defconfig
+++ b/arch/arm/configs/s5pc100_defconfig
@@ -171,7 +171,7 @@ CONFIG_DEFAULT_IOSCHED="cfq"
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
-CONFIG_ARCH_S5PC1XX=y
+CONFIG_ARCH_S5PC100=y
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
diff --git a/arch/arm/configs/s5pc110_defconfig b/arch/arm/configs/s5pc110_defconfig
index 6ea636131ac8..796cb78498c3 100644
--- a/arch/arm/configs/s5pc110_defconfig
+++ b/arch/arm/configs/s5pc110_defconfig
@@ -1,11 +1,12 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.33-rc4
-# Wed Feb 24 15:36:54 2010
+# Linux kernel version: 2.6.34
+# Sat May 22 03:18:21 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_NO_IOPORT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -17,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_ARM_L1_CACHE_SHIFT_6=y
 CONFIG_VECTORS_BASE=0xffff0000
@@ -54,7 +56,6 @@ CONFIG_RCU_FANOUT=32
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -90,10 +91,14 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
 # Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
@@ -176,6 +181,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
@@ -185,7 +191,6 @@ CONFIG_MMU=y
 # CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -202,9 +207,11 @@ CONFIG_MMU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
@@ -216,10 +223,10 @@ CONFIG_ARCH_S5PV210=y
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_U8500 is not set
 CONFIG_PLAT_SAMSUNG=y
 
 #
@@ -274,6 +281,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
 CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_430973 is not set
 # CONFIG_ARM_ERRATA_458693 is not set
 # CONFIG_ARM_ERRATA_460075 is not set
@@ -404,6 +412,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
@@ -526,6 +535,7 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_S5PV210=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -551,6 +561,7 @@ CONFIG_GPIOLIB=y
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
@@ -696,6 +707,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index 3f7d47491b54..6831dab97d96 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -1,11 +1,12 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.33-rc4
-# Wed Feb 24 15:36:16 2010
+# Linux kernel version: 2.6.34
+# Sat May 22 03:18:22 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_NO_IOPORT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -17,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_ARM_L1_CACHE_SHIFT_6=y
 CONFIG_VECTORS_BASE=0xffff0000
@@ -54,7 +56,6 @@ CONFIG_RCU_FANOUT=32
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -90,10 +91,14 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
 # Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
@@ -176,6 +181,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
@@ -185,7 +191,6 @@ CONFIG_MMU=y
 # CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -202,9 +207,11 @@ CONFIG_MMU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
@@ -216,10 +223,10 @@ CONFIG_ARCH_S5PV210=y
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_U8500 is not set
 CONFIG_PLAT_SAMSUNG=y
 
 #
@@ -274,6 +281,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
 CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_430973 is not set
 # CONFIG_ARM_ERRATA_458693 is not set
 # CONFIG_ARM_ERRATA_460075 is not set
@@ -404,6 +412,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
@@ -526,6 +535,7 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_S5PV210=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -551,6 +561,7 @@ CONFIG_GPIOLIB=y
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
@@ -696,6 +707,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index b91e412f7b3e..a9377cec662a 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -109,12 +109,7 @@ DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
 #endif
 
-/*
- * Watchdog:
- * - i.MX1
- * - i.MX21
- * - i.MX27
- */
+/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
 static struct resource mxc_wdt_resources[] = {
         {
                 .start = MX2x_WDOG_BASE_ADDR,
@@ -124,7 +119,7 @@ static struct resource mxc_wdt_resources[] = {
 };
 
 struct platform_device mxc_wdt = {
-        .name = "mxc_wdt",
+        .name = "imx2-wdt",
         .id = 0,
         .num_resources = ARRAY_SIZE(mxc_wdt_resources),
         .resource = mxc_wdt_resources,
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index 778fff230918..a87422ed4ff5 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -145,6 +145,7 @@ static struct mxc_nand_platform_data pca100_nand_board_info = {
 static struct platform_device *platform_devices[] __initdata = {
         &mxc_w1_master_device,
         &mxc_fec_device,
+        &mxc_wdt,
 };
 
 static struct imxi2c_platform_data pca100_i2c_1_data = {
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c
index 035fbe046ec0..36c89431679a 100644
--- a/arch/arm/mach-mx2/mach-pcm038.c
+++ b/arch/arm/mach-mx2/mach-pcm038.c
@@ -182,6 +182,7 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_w1_master_device,
         &mxc_fec_device,
         &pcm038_sram_mtd_device,
+        &mxc_wdt,
 };
 
 /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3f4b8a0b5fac..3a405fa400eb 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -500,3 +500,18 @@ struct platform_device mx25_fb_device = {
                 .coherent_dma_mask = 0xFFFFFFFF,
         },
 };
+
+static struct resource mxc_wdt_resources[] = {
+        {
+                .start = MX25_WDOG_BASE_ADDR,
+                .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_wdt = {
+        .name = "imx2-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
+        .resource = mxc_wdt_resources,
+};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index 39560e13bc0d..cee12c0a0be6 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -21,3 +21,4 @@ extern struct platform_device mx25_fec_device;
 extern struct platform_device mxc_nand_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
+extern struct platform_device mxc_wdt;
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 170f68e46dd5..344753fdf25e 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -82,6 +82,7 @@ config MACH_MX31MOBOARD
 config MACH_MX31LILLY
         bool "Support MX31 LILLY-1131 platforms (INCO startec)"
         select ARCH_MX31
+        select MXC_ULPI if USB_ULPI
         help
           Include support for mx31 based LILLY1131 modules. This includes
           specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index f8911154a9fa..db7acd6e9101 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -582,12 +582,50 @@ static struct resource imx_wdt_resources[] = {
 };
 
 struct platform_device imx_wdt_device0 = {
-        .name           = "imx-wdt",
+        .name           = "imx2-wdt",
         .id             = 0,
         .num_resources  = ARRAY_SIZE(imx_wdt_resources),
         .resource       = imx_wdt_resources,
 };
 
+static struct resource imx_rtc_resources[] = {
+        {
+                .start  = MX31_RTC_BASE_ADDR,
+                .end    = MX31_RTC_BASE_ADDR + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = MX31_INT_RTC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_rtc_device0 = {
+        .name           = "mxc_rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(imx_rtc_resources),
+        .resource       = imx_rtc_resources,
+};
+
+static struct resource imx_kpp_resources[] = {
+        {
+                .start  = MX3x_KPP_BASE_ADDR,
+                .end    = MX3x_KPP_BASE_ADDR + 0xf,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MX3x_INT_KPP,
+                .end    = MX3x_INT_KPP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_kpp_device = {
+        .name = "imx-keypad",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(imx_kpp_resources),
+        .resource = imx_kpp_resources,
+};
+
 static int __init mx3_devices_init(void)
 {
         if (cpu_is_mx31()) {
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 4f77eb501274..2c3c8646a29e 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -27,3 +27,5 @@ extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_wdt_device0;
+extern struct platform_device imx_rtc_device0;
+extern struct platform_device imx_kpp_device;
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index f54af1e29ca4..58e57291b79d 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -16,6 +16,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/delay.h>
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/clk.h>
@@ -26,6 +27,8 @@
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/regulator/machine.h>
+#include <linux/fsl_devices.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -65,6 +68,50 @@ static int mx31_3ds_pins[] = {
         MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
         /* MC13783 IRQ */
         IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
+        /* USB OTG reset */
+        IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
+        /* USB OTG */
+        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+        MX31_PIN_USBOTG_CLK__USBOTG_CLK,
+        MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+        MX31_PIN_USBOTG_NXT__USBOTG_NXT,
+        MX31_PIN_USBOTG_STP__USBOTG_STP,
+        /*Keyboard*/
+        MX31_PIN_KEY_ROW0_KEY_ROW0,
+        MX31_PIN_KEY_ROW1_KEY_ROW1,
+        MX31_PIN_KEY_ROW2_KEY_ROW2,
+        MX31_PIN_KEY_COL0_KEY_COL0,
+        MX31_PIN_KEY_COL1_KEY_COL1,
+        MX31_PIN_KEY_COL2_KEY_COL2,
+        MX31_PIN_KEY_COL3_KEY_COL3,
+};
+
+/*
+ * Matrix keyboard
+ */
+
+static const uint32_t mx31_3ds_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(1, 1, KEY_LEFT),
+        KEY(1, 2, KEY_ENTER),
+        KEY(2, 0, KEY_F6),
+        KEY(2, 1, KEY_F8),
+        KEY(2, 2, KEY_F9),
+        KEY(2, 3, KEY_F10),
+};
+
+static struct matrix_keymap_data mx31_3ds_keymap_data = {
+        .keymap         = mx31_3ds_keymap,
+        .keymap_size    = ARRAY_SIZE(mx31_3ds_keymap),
 };
 
 /* Regulators */
@@ -126,6 +173,41 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
 #endif
 };
 
+/*
+ * USB OTG
+ */
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                     PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
+
+static void mx31_3ds_usbotg_init(void)
+{
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+
+        gpio_request(USBOTG_RST_B, "otgusb-reset");
+        gpio_direction_output(USBOTG_RST_B, 0);
+        mdelay(1);
+        gpio_set_value(USBOTG_RST_B, 1);
+}
+
+static struct fsl_usb2_platform_data usbotg_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
 static struct imxuart_platform_data uart_pdata = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -315,6 +397,11 @@ static void __init mxc_board_init(void)
         spi_register_board_info(mx31_3ds_spi_devs,
                                                 ARRAY_SIZE(mx31_3ds_spi_devs));
 
+        mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
+
+        mx31_3ds_usbotg_init();
+        mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
+
         if (!mx31_3ds_init_expio())
                 platform_device_register(&smsc911x_device);
 }
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 80847b04c063..d3d5877c750e 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -27,12 +27,15 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/mc13783.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -44,6 +47,8 @@
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
 #include <mach/spi.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 
 #include "devices.h"
 
@@ -108,6 +113,137 @@ static struct platform_device physmap_flash_device = {
         .num_resources = 1,
 };
 
+/* USB */
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int usbotg_init(struct platform_device *pdev)
+{
+        unsigned int pins[] = {
+                MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+                MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+                MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+                MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+                MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+                MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+                MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+                MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+                MX31_PIN_USBOTG_CLK__USBOTG_CLK,
+                MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+                MX31_PIN_USBOTG_NXT__USBOTG_NXT,
+                MX31_PIN_USBOTG_STP__USBOTG_STP,
+        };
+
+        mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG");
+
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+
+        mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true);
+        mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true);
+
+        /* chip select */
+        mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO),
+                                "USBOTG_CS");
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
+        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
+
+        return 0;
+}
+
+static int usbh1_init(struct platform_device *pdev)
+{
+        int pins[] = {
+                MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
+                MX31_PIN_CSPI1_MISO__USBH1_RXDP,
+                MX31_PIN_CSPI1_SS0__USBH1_TXDM,
+                MX31_PIN_CSPI1_SS1__USBH1_TXDP,
+                MX31_PIN_CSPI1_SS2__USBH1_RCV,
+                MX31_PIN_CSPI1_SCLK__USBH1_OEB,
+                MX31_PIN_CSPI1_SPI_RDY__USBH1_FS,
+        };
+
+        mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1");
+
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
+
+        mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+
+        return 0;
+}
+
+static int usbh2_init(struct platform_device *pdev)
+{
+        int pins[] = {
+                MX31_PIN_USBH2_DATA0__USBH2_DATA0,
+                MX31_PIN_USBH2_DATA1__USBH2_DATA1,
+                MX31_PIN_USBH2_CLK__USBH2_CLK,
+                MX31_PIN_USBH2_DIR__USBH2_DIR,
+                MX31_PIN_USBH2_NXT__USBH2_NXT,
+                MX31_PIN_USBH2_STP__USBH2_STP,
+        };
+
+        mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
+
+        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+
+        mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+
+        /* chip select */
+        mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
+                                "USBH2_CS");
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
+        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
+
+        return 0;
+}
+
+static struct mxc_usbh_platform_data usbotg_pdata = {
+        .init   = usbotg_init,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+
+static struct mxc_usbh_platform_data usbh1_pdata = {
+        .init   = usbh1_init,
+        .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .init   = usbh2_init,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+
 static struct platform_device *devices[] __initdata = {
         &smsc91x_device,
         &physmap_flash_device,
@@ -183,6 +319,15 @@ static void __init mx31lilly_board_init(void)
         spi_register_board_info(&mc13783_dev, 1);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        /* USB */
+        usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+        mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
 }
 
 static void __init mx31lilly_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index fccb9207b78d..33a8d35498a7 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -18,7 +18,6 @@
 
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
-#include <linux/fsl_devices.h>
 #include <linux/gfp.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
@@ -306,84 +305,56 @@ static struct imxmmc_platform_data sdhc1_pdata = {
  * this pin is dedicated for all mx31moboard systems, so we do it here
  */
 #define USB_RESET_B     IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
-
-static void usb_xcvr_reset(void)
-{
-        gpio_request(USB_RESET_B, "usb-reset");
-        gpio_direction_output(USB_RESET_B, 0);
-        mdelay(1);
-        gpio_set_value(USB_RESET_B, 1);
-}
-
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
-                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+                      PAD_CTL_ODE_CMOS)
 
 #define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
-
-static void moboard_usbotg_init(void)
-{
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
-
-        gpio_request(OTG_EN_B, "usb-udc-en");
-        gpio_direction_output(OTG_EN_B, 0);
-}
-
-static struct fsl_usb2_platform_data usb_pdata = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_ULPI,
-};
-
-#if defined(CONFIG_USB_ULPI)
-
 #define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
 
-static int moboard_usbh2_hw_init(struct platform_device *pdev)
+static void usb_xcvr_reset(void)
 {
-        int ret;
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
 
         mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
+        mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
 
-        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
-
-        ret = gpio_request(USBH2_EN_B, "usbh2-en");
-        if (ret)
-                return ret;
+        gpio_request(OTG_EN_B, "usb-udc-en");
+        gpio_direction_output(OTG_EN_B, 0);
+        gpio_request(USBH2_EN_B, "usbh2-en");
         gpio_direction_output(USBH2_EN_B, 0);
 
-        return 0;
+        gpio_request(USB_RESET_B, "usb-reset");
+        gpio_direction_output(USB_RESET_B, 0);
+        mdelay(1);
+        gpio_set_value(USB_RESET_B, 1);
+        mdelay(1);
 }
 
-static int moboard_usbh2_hw_exit(struct platform_device *pdev)
-{
-        gpio_free(USBH2_EN_B);
-        return 0;
-}
+#if defined(CONFIG_USB_ULPI)
 
 static struct mxc_usbh_platform_data usbh2_pdata = {
-        .init   = moboard_usbh2_hw_init,
-        .exit   = moboard_usbh2_hw_exit,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
@@ -508,8 +479,6 @@ static void __init mxc_board_init(void)
 
         usb_xcvr_reset();
 
-        moboard_usbotg_init();
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
         moboard_usbh2_init();
 
         switch (mx31moboard_baseboard) {
@@ -522,7 +491,8 @@ static void __init mxc_board_init(void)
                 mx31moboard_marxbot_init();
                 break;
         case MX31SMARTBOT:
-                mx31moboard_smartbot_init();
+        case MX31EYEBOT:
+                mx31moboard_smartbot_init(mx31moboard_baseboard);
                 break;
         default:
                 printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 2df1ec55a97e..5024284d6455 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -449,6 +449,7 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
 static struct platform_device *devices[] __initdata = {
         &pcm037_flash,
         &pcm037_sram_device,
+        &imx_wdt_device0,
         &pcm037_mt9t031,
         &pcm037_mt9v022,
 };
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 1bf1ec2eef5e..78d9185a9d4b 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -150,6 +150,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
 static struct platform_device *devices[] __initdata = {
         &pcm043_flash,
         &mxc_fec_device,
+        &imx_wdt_device0,
 };
 
 static struct pad_desc pcm043_pads[] = {
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 093c595ca581..5f05bfbec380 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -206,5 +206,6 @@ void __init mx31lite_db_init(void)
         mxc_register_device(&mxc_spi_device0, &spi0_pdata);
         platform_device_register(&litekit_led_device);
         mxc_register_device(&imx_wdt_device0, NULL);
+        mxc_register_device(&imx_rtc_device0, NULL);
 }
 
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 11b906ce7eae..582299cb2c08 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/types.h>
+#include <linux/fsl_devices.h>
 
 #include <linux/usb/otg.h>
 
@@ -213,6 +214,12 @@ static int __init devboard_usbh1_init(void)
         return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
 }
 
+
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
 /*
  * system init for baseboard usage. Will be called by mx31moboard init.
  */
@@ -229,5 +236,7 @@ void __init mx31moboard_devboard_init(void)
 
         devboard_init_sel_gpios();
 
+        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+
         devboard_usbh1_init();
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index ffb105e14d88..4930f8c27e66 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -25,6 +25,7 @@
 #include <linux/slab.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include <linux/fsl_devices.h>
 
 #include <linux/usb/otg.h>
 
@@ -329,6 +330,11 @@ static int __init marxbot_usbh1_init(void)
         return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
 }
 
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
 /*
  * system init for baseboard usage. Will be called by mx31moboard init.
  */
@@ -356,5 +362,7 @@ void __init mx31moboard_marxbot_init(void)
         gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
         gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
 
+        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+
         marxbot_usbh1_init();
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 52a69fc8b14f..293eea6d9d97 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -23,11 +23,18 @@
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include <linux/fsl_devices.h>
+
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/board-mx31moboard.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 
 #include <media/soc_camera.h>
 
@@ -116,10 +123,33 @@ static int __init smartbot_cam_init(void)
         return 0;
 }
 
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
+#if defined(CONFIG_USB_ULPI)
+
+static struct mxc_usbh_platform_data otg_host_pdata = {
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+
+static int __init smartbot_otg_host_init(void)
+{
+        otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                        USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+        return mxc_register_device(&mxc_otg_host, &otg_host_pdata);
+}
+#else
+static inline int smartbot_otg_host_init(void) { return 0; }
+#endif
+
 #define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
 #define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
 #define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
-#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
+#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
 
 static void smartbot_resets_init(void)
 {
@@ -138,15 +168,15 @@ static void smartbot_resets_init(void)
                 gpio_export(TRSLAT_RST_B, false);
         }
 
-        if (!gpio_request(SEL3, "sel3")) {
-                gpio_direction_input(SEL3);
-                gpio_export(SEL3, true);
+        if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) {
+                gpio_direction_output(TRSLAT_SRC_CHOICE, 0);
+                gpio_export(TRSLAT_SRC_CHOICE, false);
         }
 }
 /*
  * system init for baseboard usage. Will be called by mx31moboard init.
  */
-void __init mx31moboard_smartbot_init(void)
+void __init mx31moboard_smartbot_init(int board)
 {
         printk(KERN_INFO "Initializing mx31smartbot peripherals\n");
 
@@ -155,6 +185,19 @@ void __init mx31moboard_smartbot_init(void)
 
         mxc_register_device(&mxc_uart_device1, &uart_pdata);
 
+
+        switch (board) {
+        case MX31SMARTBOT:
+                mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+                break;
+        case MX31EYEBOT:
+                smartbot_otg_host_init();
+                break;
+        default:
+                printk(KERN_WARNING "Unknown board %d, USB OTG not initialized",
+                        board);
+        }
+
         smartbot_resets_init();
 
         smartbot_cam_init();
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ee67a71db80d..ed885f9d7b73 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -12,11 +12,16 @@
 
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
+#include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
 #include <asm/setup.h>
@@ -26,6 +31,18 @@
 
 #include "devices.h"
 
+#define BABBAGE_USB_HUB_RESET   (0*32 + 7)      /* GPIO_1_7 */
+#define BABBAGE_USBH1_STP       (0*32 + 27)     /* GPIO_1_27 */
+#define BABBAGE_PHY_RESET (1*32 +5)     /* GPIO_2_5 */
+
+/* USB_CTRL_1 */
+#define MX51_USB_CTRL_1_OFFSET                  0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN            (1 << 25)
+
+#define MX51_USB_PLLDIV_12_MHZ          0x00
+#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define MX51_USB_PLL_DIV_24_MHZ 0x02
+
 static struct platform_device *devices[] __initdata = {
         &mxc_fec_device,
 };
@@ -46,6 +63,22 @@ static struct pad_desc mx51babbage_pads[] = {
         MX51_PAD_EIM_D26__UART3_TXD,
         MX51_PAD_EIM_D27__UART3_RTS,
         MX51_PAD_EIM_D24__UART3_CTS,
+
+        /* USB HOST1 */
+        MX51_PAD_USBH1_CLK__USBH1_CLK,
+        MX51_PAD_USBH1_DIR__USBH1_DIR,
+        MX51_PAD_USBH1_NXT__USBH1_NXT,
+        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+
+        /* USB HUB reset line*/
+        MX51_PAD_GPIO_1_7__GPIO1_7,
 };
 
 /* Serial ports */
@@ -66,15 +99,149 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
+static int gpio_usbh1_active(void)
+{
+        struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
+        struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
+        int ret;
+
+        /* Set USBH1_STP to GPIO and toggle it */
+        mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
+        ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
+
+        if (ret) {
+                pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
+                return ret;
+        }
+        gpio_direction_output(BABBAGE_USBH1_STP, 0);
+        gpio_set_value(BABBAGE_USBH1_STP, 1);
+        msleep(100);
+        gpio_free(BABBAGE_USBH1_STP);
+
+        /* De-assert USB PHY RESETB */
+        mxc_iomux_v3_setup_pad(&phyreset_gpio);
+        ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
+
+        if (ret) {
+                pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
+                return ret;
+        }
+        gpio_direction_output(BABBAGE_PHY_RESET, 1);
+        return 0;
+}
+
+static inline void babbage_usbhub_reset(void)
+{
+        int ret;
+
+        /* Bring USB hub out of reset */
+        ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
+        if (ret) {
+                printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
+                return;
+        }
+        gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
+
+        /* USB HUB RESET - De-assert USB HUB RESET_N */
+        msleep(1);
+        gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
+        msleep(1);
+        gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
+}
+
+/* This function is board specific as the bit mask for the plldiv will also
+be different for other Freescale SoCs, thus a common bitmask is not
+possible and cannot get place in /plat-mxc/ehci.c.*/
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        u32 usbother_base;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_19_2_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        u32 usbother_base;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        /* The clock for the USBH1 ULPI port will come externally from the PHY. */
+        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
+        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init           = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+};
+
+static struct mxc_usbh_platform_data usbh1_config = {
+        .init           = initialize_usbh1_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
+};
+
+static int otg_mode_host;
+
+static int __init babbage_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", babbage_otg_mode);
+
 /*
  * Board specific initialization.
  */
 static void __init mxc_board_init(void)
 {
+        struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+
         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
                                         ARRAY_SIZE(mx51babbage_pads));
         mxc_init_imx_uart();
         platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        if (otg_mode_host)
+                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        else {
+                initialize_otg_port(NULL);
+                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+        }
+
+        gpio_usbh1_active();
+        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+        /* setback USBH1_STP to be function */
+        mxc_iomux_v3_setup_pad(&usbh1stp);
+        babbage_usbhub_reset();
 }
 
 static void __init mx51_babbage_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 1ee6ce4087b8..d9f612d3370e 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -37,6 +37,7 @@ static struct clk lp_apm_clk;
 static struct clk periph_apm_clk;
 static struct clk ahb_clk;
 static struct clk ipg_clk;
+static struct clk usboh3_clk;
 
 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
 
@@ -570,6 +571,35 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
         return 0;
 }
 
+static unsigned long clk_usboh3_get_rate(struct clk *clk)
+{
+        u32 reg, prediv, podf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(MXC_CCM_CSCDR1);
+        prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
+                  MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
+        podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
+                MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
+
+        return parent_rate / (prediv * podf);
+}
+
+static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg, mux;
+
+        mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+                       &lp_apm_clk);
+        reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
+        reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 {
         return external_high_reference;
@@ -691,6 +721,12 @@ static struct clk uart_root_clk = {
         .set_parent = _clk_uart_set_parent,
 };
 
+static struct clk usboh3_clk = {
+        .parent = &pll2_sw_clk,
+        .get_rate = clk_usboh3_get_rate,
+        .set_parent = _clk_usboh3_set_parent,
+};
+
 static struct clk ahb_max_clk = {
         .parent = &ahb_clk,
         .enable_reg = MXC_CCM_CCGR0,
@@ -779,6 +815,12 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
 };
 
 static void clk_tree_init(void)
@@ -819,6 +861,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
         clk_enable(&cpu_clk);
         clk_enable(&main_bus_clk);
 
+        /* set the usboh3_clk parent to pll2_sw_clk */
+        clk_set_parent(&usboh3_clk, &pll2_sw_clk);
+
         /* System timer */
         mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
                 MX51_MXC_INT_GPT);
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index d6fd3961ade9..7130449aacdc 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -10,8 +11,11 @@
  */
 
 #include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
+#include <mach/irqs.h>
 
 static struct resource uart0[] = {
         {
@@ -89,8 +93,109 @@ struct platform_device mxc_fec_device = {
         .resource = mxc_fec_resources,
 };
 
-/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */
+static u64 usb_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource usbotg_resources[] = {
+        {
+                .start = MX51_OTG_BASE_ADDR,
+                .end = MX51_OTG_BASE_ADDR + 0x1ff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = MX51_MXC_INT_USB_OTG,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+/* OTG gadget device */
+struct platform_device mxc_usbdr_udc_device = {
+        .name           = "fsl-usb2-udc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(usbotg_resources),
+        .resource       = usbotg_resources,
+        .dev            = {
+                .dma_mask               = &usb_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct platform_device mxc_usbdr_host_device = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(usbotg_resources),
+        .resource = usbotg_resources,
+        .dev = {
+                .dma_mask = &usb_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource usbh1_resources[] = {
+        {
+                .start = MX51_OTG_BASE_ADDR + 0x200,
+                .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = MX51_MXC_INT_USB_H1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh1_device = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(usbh1_resources),
+        .resource = usbh1_resources,
+        .dev = {
+                .dma_mask = &usb_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource mxc_wdt_resources[] = {
+        {
+                .start = MX51_WDOG_BASE_ADDR,
+                .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_wdt = {
+        .name = "imx2-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
+        .resource = mxc_wdt_resources,
+};
+
+static struct mxc_gpio_port mxc_gpio_ports[] = {
+        {
+                .chip.label = "gpio-0",
+                .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
+                .irq = MX51_MXC_INT_GPIO1_LOW,
+                .virtual_irq_start = MXC_GPIO_IRQ_START
+        },
+        {
+                .chip.label = "gpio-1",
+                .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
+                .irq = MX51_MXC_INT_GPIO2_LOW,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
+        },
+        {
+                .chip.label = "gpio-2",
+                .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
+                .irq = MX51_MXC_INT_GPIO3_LOW,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
+        },
+        {
+                .chip.label = "gpio-3",
+                .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
+                .irq = MX51_MXC_INT_GPIO4_LOW,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
+        },
+};
+
 int __init mxc_register_gpios(void)
 {
-        return 0;
+        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index f339ab8c19be..c879ae71cd5b 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -2,3 +2,7 @@ extern struct platform_device mxc_uart_device0;
 extern struct platform_device mxc_uart_device1;
 extern struct platform_device mxc_uart_device2;
 extern struct platform_device mxc_fec_device;
+extern struct platform_device mxc_usbdr_host_device;
+extern struct platform_device mxc_usbh1_device;
+extern struct platform_device mxc_usbdr_udc_device;
+extern struct platform_device mxc_wdt;
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 091c98a639d9..cd3983ad4160 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -114,6 +114,7 @@
 #define S3C_PA_USBHOST  S3C2410_PA_USBHOST
 #define S3C_PA_HSMMC0       S3C2443_PA_HSMMC
 #define S3C_PA_HSMMC1       S3C2416_PA_HSMMC0
+#define S3C_PA_WDT          S3C2410_PA_WATCHDOG
 #define S3C_PA_NAND         S3C24XX_PA_NAND
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 69e9fbfea917..f5a59727949f 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -7,6 +7,7 @@
 config PLAT_S3C64XX
         bool
         depends on ARCH_S3C64XX
+        select SAMSUNG_WAKEMASK
         default y
         help
           Base platform code for any Samsung S3C64XX device
@@ -35,6 +36,11 @@ config S3C64XX_SETUP_SDHCI
           Internal configuration for default SDHCI setup for S3C6400 and
           S3C6410 SoCs.
 
+config S3C64XX_DEV_ONENAND1
+        bool
+        help
+          Compile in platform device definition for OneNAND1 controller
+
 # platform specific device setup
 
 config S3C64XX_SETUP_I2C0
@@ -90,8 +96,11 @@ config MACH_SMDK6410
         select S3C_DEV_HSMMC1
         select S3C_DEV_I2C1
         select S3C_DEV_FB
+        select SAMSUNG_DEV_TS
         select S3C_DEV_USB_HOST
         select S3C_DEV_USB_HSOTG
+        select S3C_DEV_WDT
+        select HAVE_S3C2410_WATCHDOG
         select S3C64XX_SETUP_SDHCI
         select S3C64XX_SETUP_I2C1
         select S3C64XX_SETUP_FB_24BPP
@@ -179,3 +188,34 @@ config MACH_HMT
         select HAVE_PWM
         help
           Machine support for the Airgoo HMT
+
+config MACH_SMARTQ
+        bool
+        select CPU_S3C6410
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_FB
+        select S3C_DEV_HWMON
+        select S3C_DEV_RTC
+        select S3C_DEV_USB_HSOTG
+        select S3C_DEV_USB_HOST
+        select S3C64XX_SETUP_SDHCI
+        select S3C64XX_SETUP_FB_24BPP
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select HAVE_PWM
+        help
+            Shared machine support for SmartQ 5/7
+
+config MACH_SMARTQ5
+        bool "SmartQ 5"
+        select MACH_SMARTQ
+        help
+            Machine support for the SmartQ 5
+
+config MACH_SMARTQ7
+        bool "SmartQ 7"
+        select MACH_SMARTQ
+        help
+            Machine support for the SmartQ 7
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index a10f1fc6b023..9d1006938f5c 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -52,6 +52,9 @@ obj-$(CONFIG_MACH_SMDK6400)	+= mach-smdk6400.o
 obj-$(CONFIG_MACH_SMDK6410)     += mach-smdk6410.o
 obj-$(CONFIG_MACH_NCP)          += mach-ncp.o
 obj-$(CONFIG_MACH_HMT)          += mach-hmt.o
+obj-$(CONFIG_MACH_SMARTQ)       += mach-smartq.o
+obj-$(CONFIG_MACH_SMARTQ5)      += mach-smartq5.o
+obj-$(CONFIG_MACH_SMARTQ7)      += mach-smartq7.o
 
 # device support
 
@@ -59,3 +62,4 @@ obj-y				+= dev-uart.o
 obj-y                           += dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 obj-$(CONFIG_S3C64XX_DEV_TS)    += dev-ts.o
+obj-$(CONFIG_S3C64XX_DEV_ONENAND1)      += dev-onenand1.o
diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c
new file mode 100644
index 000000000000..92ffd5bac104
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/dev-onenand1.c
@@ -0,0 +1,55 @@
+/*
+ * linux/arch/arm/mach-s3c64xx/dev-onenand1.c
+ *
+ *  Copyright (c) 2008-2010 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S3C64XX series device definition for OneNAND devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+static struct resource s3c64xx_onenand1_resources[] = {
+        [0] = {
+                .start  = S3C64XX_PA_ONENAND1,
+                .end    = S3C64XX_PA_ONENAND1 + 0x400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = S3C64XX_PA_ONENAND1_BUF,
+                .end    = S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = IRQ_ONENAND1,
+                .end    = IRQ_ONENAND1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c64xx_device_onenand1 = {
+        .name           = "samsung-onenand",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s3c64xx_onenand1_resources),
+        .resource       = s3c64xx_onenand1_resources,
+};
+
+void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
+{
+        struct onenand_platform_data *pd;
+
+        pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
+        if (!pd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        s3c64xx_device_onenand1.dev.platform_data = pd;
+}
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index e9ab4ac0b9a8..8e2df26cf14a 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -212,5 +212,9 @@
 
 #define NR_IRQS (IRQ_BOARD_END + 1)
 
+/* Compatibility */
+
+#define IRQ_ONENAND     IRQ_ONENAND0
+
 #endif /* __ASM_MACH_S3C64XX_IRQS_H */
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 9fdd50c8c767..e1eab3c94aea 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -52,6 +52,16 @@
 
 #define S3C64XX_PA_SROM         (0x70000000)
 
+#define S3C64XX_PA_ONENAND0     (0x70100000)
+#define S3C64XX_PA_ONENAND0_BUF (0x20000000)
+#define S3C64XX_SZ_ONENAND0_BUF (SZ_64M)
+
+/* NAND and OneNAND1 controllers occupy the same register region
+   (depending on SoC POP version) */
+#define S3C64XX_PA_ONENAND1     (0x70200000)
+#define S3C64XX_PA_ONENAND1_BUF (0x28000000)
+#define S3C64XX_SZ_ONENAND1_BUF (SZ_64M)
+
 #define S3C64XX_PA_NAND         (0x70200000)
 #define S3C64XX_PA_FB           (0x77100000)
 #define S3C64XX_PA_USB_HSOTG    (0x7C000000)
@@ -99,11 +109,15 @@
 #define S3C_PA_IIC              S3C64XX_PA_IIC0
 #define S3C_PA_IIC1             S3C64XX_PA_IIC1
 #define S3C_PA_NAND             S3C64XX_PA_NAND
+#define S3C_PA_ONENAND          S3C64XX_PA_ONENAND0
+#define S3C_PA_ONENAND_BUF      S3C64XX_PA_ONENAND0_BUF
+#define S3C_SZ_ONENAND_BUF      S3C64XX_SZ_ONENAND0_BUF
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
 #define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
 #define S3C_PA_RTC              S3C64XX_PA_RTC
+#define S3C_PA_WDT              S3C64XX_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC          S3C64XX_PA_ADC
 
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
new file mode 100644
index 000000000000..028d080dcd35
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -0,0 +1,363 @@
+/*
+ * linux/arch/arm/mach-s3c64xx/mach-smartq.c
+ *
+ * Copyright (C) 2010 Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/serial_core.h>
+#include <linux/usb/gpio_vbus.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-modem.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/hwmon.h>
+#include <plat/regs-serial.h>
+#include <plat/udc-hs.h>
+#include <plat/usb-control.h>
+#include <plat/sdhci.h>
+#include <plat/ts.h>
+
+#include <video/platform_lcd.h>
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg smartq_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+};
+
+static void smartq_usb_host_powercontrol(int port, int to)
+{
+        pr_debug("%s(%d, %d)\n", __func__, port, to);
+
+        if (port == 0) {
+                gpio_set_value(S3C64XX_GPL(0), to);
+                gpio_set_value(S3C64XX_GPL(1), to);
+        }
+}
+
+static irqreturn_t smartq_usb_host_ocirq(int irq, void *pw)
+{
+        struct s3c2410_hcd_info *info = pw;
+
+        if (gpio_get_value(S3C64XX_GPL(10)) == 0) {
+                pr_debug("%s: over-current irq (oc detected)\n", __func__);
+                s3c2410_usb_report_oc(info, 3);
+        } else {
+                pr_debug("%s: over-current irq (oc cleared)\n", __func__);
+                s3c2410_usb_report_oc(info, 0);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static void smartq_usb_host_enableoc(struct s3c2410_hcd_info *info, int on)
+{
+        int ret;
+
+        /* This isn't present on a SmartQ 5 board */
+        if (machine_is_smartq5())
+                return;
+
+        if (on) {
+                ret = request_irq(gpio_to_irq(S3C64XX_GPL(10)),
+                                  smartq_usb_host_ocirq, IRQF_DISABLED |
+                                  IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                                  "USB host overcurrent", info);
+                if (ret != 0)
+                        pr_err("failed to request usb oc irq: %d\n", ret);
+        } else {
+                free_irq(gpio_to_irq(S3C64XX_GPL(10)), info);
+        }
+}
+
+static struct s3c2410_hcd_info smartq_usb_host_info = {
+        .port[0]        = {
+                .flags  = S3C_HCDFLG_USED
+        },
+        .port[1]        = {
+                .flags  = 0
+        },
+
+        .power_control  = smartq_usb_host_powercontrol,
+        .enable_oc      = smartq_usb_host_enableoc,
+};
+
+static struct gpio_vbus_mach_info smartq_usb_otg_vbus_pdata = {
+        .gpio_vbus              = S3C64XX_GPL(9),
+        .gpio_pullup            = -1,
+        .gpio_vbus_inverted     = true,
+};
+
+static struct platform_device smartq_usb_otg_vbus_dev = {
+        .name                   = "gpio-vbus",
+        .dev.platform_data      = &smartq_usb_otg_vbus_pdata,
+};
+
+static int __init smartq_bl_init(struct device *dev)
+{
+    s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
+
+    return 0;
+}
+
+static struct platform_pwm_backlight_data smartq_backlight_data = {
+        .pwm_id         = 1,
+        .max_brightness = 1000,
+        .dft_brightness = 600,
+        .pwm_period_ns  = 1000000000 / (1000 * 20),
+        .init           = smartq_bl_init,
+};
+
+static struct platform_device smartq_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &s3c_device_timer[1].dev,
+                .platform_data = &smartq_backlight_data,
+        },
+};
+
+static struct s3c2410_ts_mach_info smartq_touchscreen_pdata __initdata = {
+        .delay                  = 65535,
+        .presc                  = 99,
+        .oversampling_shift     = 4,
+};
+
+static struct s3c_sdhci_platdata smartq_internal_hsmmc_pdata = {
+        .max_width              = 4,
+        /*.broken_card_detection        = true,*/
+};
+
+static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
+        /* Battery voltage (?-4.2V) */
+        .in[0] = &(struct s3c_hwmon_chcfg) {
+                .name           = "smartq:battery-voltage",
+                .mult           = 3300,
+                .div            = 2048,
+        },
+        /* Reference voltage (1.2V) */
+        .in[1] = &(struct s3c_hwmon_chcfg) {
+                .name           = "smartq:reference-voltage",
+                .mult           = 3300,
+                .div            = 4096,
+        },
+};
+
+static void smartq_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
+{
+        gpio_direction_output(S3C64XX_GPM(3), power);
+}
+
+static struct plat_lcd_data smartq_lcd_power_data = {
+        .set_power      = smartq_lcd_power_set,
+};
+
+static struct platform_device smartq_lcd_power_device = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &smartq_lcd_power_data,
+};
+
+
+static struct platform_device *smartq_devices[] __initdata = {
+        &s3c_device_hsmmc1,     /* Init iNAND first, ... */
+        &s3c_device_hsmmc0,     /* ... then the external SD card */
+        &s3c_device_hsmmc2,
+        &s3c_device_adc,
+        &s3c_device_fb,
+        &s3c_device_hwmon,
+        &s3c_device_i2c0,
+        &s3c_device_ohci,
+        &s3c_device_rtc,
+        &s3c_device_timer[1],
+        &s3c_device_ts,
+        &s3c_device_usb_hsotg,
+        &smartq_backlight_device,
+        &smartq_lcd_power_device,
+        &smartq_usb_otg_vbus_dev,
+};
+
+static void __init smartq_lcd_mode_set(void)
+{
+        u32 tmp;
+
+        /* set the LCD type */
+        tmp = __raw_readl(S3C64XX_SPCON);
+        tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+        tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+        __raw_writel(tmp, S3C64XX_SPCON);
+
+        /* remove the LCD bypass */
+        tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+        tmp &= ~MIFPCON_LCD_BYPASS;
+        __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+
+static void smartq_power_off(void)
+{
+        gpio_direction_output(S3C64XX_GPK(15), 1);
+}
+
+static int __init smartq_power_off_init(void)
+{
+        int ret;
+
+        ret = gpio_request(S3C64XX_GPK(15), "Power control");
+        if (ret < 0) {
+                pr_err("%s: failed to get GPK15\n", __func__);
+                return ret;
+        }
+
+        /* leave power on */
+        gpio_direction_output(S3C64XX_GPK(15), 0);
+
+
+        pm_power_off = smartq_power_off;
+
+        return ret;
+}
+
+static int __init smartq_usb_host_init(void)
+{
+        int ret;
+
+        ret = gpio_request(S3C64XX_GPL(0), "USB power control");
+        if (ret < 0) {
+                pr_err("%s: failed to get GPL0\n", __func__);
+                return ret;
+        }
+
+        ret = gpio_request(S3C64XX_GPL(1), "USB host power control");
+        if (ret < 0) {
+                pr_err("%s: failed to get GPL1\n", __func__);
+                goto err;
+        }
+
+        if (!machine_is_smartq5()) {
+                /* This isn't present on a SmartQ 5 board */
+                ret = gpio_request(S3C64XX_GPL(10), "USB host overcurrent");
+                if (ret < 0) {
+                        pr_err("%s: failed to get GPL10\n", __func__);
+                        goto err2;
+                }
+        }
+
+        /* turn power off */
+        gpio_direction_output(S3C64XX_GPL(0), 0);
+        gpio_direction_output(S3C64XX_GPL(1), 0);
+        if (!machine_is_smartq5())
+                gpio_direction_input(S3C64XX_GPL(10));
+
+        s3c_device_ohci.dev.platform_data = &smartq_usb_host_info;
+
+        return 0;
+
+err2:
+        gpio_free(S3C64XX_GPL(1));
+err:
+        gpio_free(S3C64XX_GPL(0));
+        return ret;
+}
+
+static int __init smartq_usb_otg_init(void)
+{
+        clk_xusbxti.rate = 12000000;
+
+        return 0;
+}
+
+static int __init smartq_wifi_init(void)
+{
+        int ret;
+
+        ret = gpio_request(S3C64XX_GPK(1), "wifi control");
+        if (ret < 0) {
+                pr_err("%s: failed to get GPK1\n", __func__);
+                return ret;
+        }
+
+        ret = gpio_request(S3C64XX_GPK(2), "wifi reset");
+        if (ret < 0) {
+                pr_err("%s: failed to get GPK2\n", __func__);
+                gpio_free(S3C64XX_GPK(1));
+                return ret;
+        }
+
+        /* turn power on */
+        gpio_direction_output(S3C64XX_GPK(1), 1);
+
+        /* reset device */
+        gpio_direction_output(S3C64XX_GPK(2), 0);
+        mdelay(100);
+        gpio_set_value(S3C64XX_GPK(2), 1);
+        gpio_direction_input(S3C64XX_GPK(2));
+
+        return 0;
+}
+
+static struct map_desc smartq_iodesc[] __initdata = {};
+void __init smartq_map_io(void)
+{
+        s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
+
+        smartq_lcd_mode_set();
+}
+
+void __init smartq_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
+        s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
+        s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
+        s3c24xx_ts_set_platdata(&smartq_touchscreen_pdata);
+
+        WARN_ON(smartq_power_off_init());
+        WARN_ON(smartq_usb_host_init());
+        WARN_ON(smartq_usb_otg_init());
+        WARN_ON(smartq_wifi_init());
+
+        platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
+}
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.h b/arch/arm/mach-s3c64xx/mach-smartq.h
new file mode 100644
index 000000000000..8e8b693db3af
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-smartq.h
@@ -0,0 +1,20 @@
+/*
+ * linux/arch/arm/mach-s3c64xx/mach-smartq.h
+ *
+ * Copyright (C) 2010 Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __MACH_SMARTQ_H
+#define __MACH_SMARTQ_H __FILE__
+
+#include <linux/init.h>
+
+extern void __init smartq_map_io(void);
+extern void __init smartq_machine_init(void);
+
+#endif /* __MACH_SMARTQ_H */
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
new file mode 100644
index 000000000000..1d0326ead90f
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -0,0 +1,185 @@
+/*
+ * linux/arch/arm/mach-s3c64xx/mach-smartq5.c
+ *
+ * Copyright (C) 2010 Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c-gpio.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
+#include <mach/s3c6410.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+
+#include "mach-smartq.h"
+
+static void __init smartq5_lcd_setup_gpio(void)
+{
+        gpio_request(S3C64XX_GPM(0), "LCD SCEN pin");
+        gpio_request(S3C64XX_GPM(1), "LCD SCL pin");
+        gpio_request(S3C64XX_GPM(2), "LCD SDA pin");
+        gpio_request(S3C64XX_GPM(3), "LCD power");
+
+        /* turn power off */
+        gpio_direction_output(S3C64XX_GPM(0), 1);
+        gpio_direction_input(S3C64XX_GPM(1));
+        gpio_direction_input(S3C64XX_GPM(2));
+        gpio_direction_output(S3C64XX_GPM(3), 0);
+}
+
+static struct i2c_gpio_platform_data smartq5_lcd_control = {
+        .sda_pin                = S3C64XX_GPM(2),
+        .scl_pin                = S3C64XX_GPM(1),
+};
+
+static struct platform_device smartq5_lcd_control_device = {
+        .name                   = "i2c-gpio",
+        .id                     = 1,
+        .dev.platform_data      = &smartq5_lcd_control,
+};
+
+static struct gpio_led smartq5_leds[] __initdata = {
+        {
+                .name                   = "smartq5:green",
+                .active_low             = 1,
+                .gpio                   = S3C64XX_GPN(8),
+        },
+        {
+                .name                   = "smartq5:red",
+                .active_low             = 1,
+                .gpio                   = S3C64XX_GPN(9),
+        },
+};
+
+static struct gpio_led_platform_data smartq5_led_data = {
+        .num_leds = ARRAY_SIZE(smartq5_leds),
+        .leds = smartq5_leds,
+};
+
+static struct platform_device smartq5_leds_device = {
+        .name                   = "leds-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &smartq5_led_data,
+};
+
+/* Labels according to the SmartQ manual */
+static struct gpio_keys_button smartq5_buttons[] = {
+        {
+                .gpio                   = S3C64XX_GPL(14),
+                .code                   = KEY_POWER,
+                .desc                   = "Power",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+        {
+                .gpio                   = S3C64XX_GPN(2),
+                .code                   = KEY_KPMINUS,
+                .desc                   = "Minus",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+        {
+                .gpio                   = S3C64XX_GPN(12),
+                .code                   = KEY_KPPLUS,
+                .desc                   = "Plus",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+        {
+                .gpio                   = S3C64XX_GPN(15),
+                .code                   = KEY_ENTER,
+                .desc                   = "Move",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+};
+
+static struct gpio_keys_platform_data smartq5_buttons_data  = {
+        .buttons        = smartq5_buttons,
+        .nbuttons       = ARRAY_SIZE(smartq5_buttons),
+};
+
+static struct platform_device smartq5_buttons_device  = {
+        .name           = "gpio-keys",
+        .id             = 0,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &smartq5_buttons_data,
+        }
+};
+
+static struct s3c_fb_pd_win smartq5_fb_win0 = {
+        .win_mode       = {
+                .pixclock       = 1000000000000ULL /
+                                ((40+1+216+800)*(10+1+35+480)*80),
+                .left_margin    = 40,
+                .right_margin   = 216,
+                .upper_margin   = 10,
+                .lower_margin   = 35,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 16,
+};
+
+static struct s3c_fb_platdata smartq5_lcd_pdata __initdata = {
+        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
+        .win[0]         = &smartq5_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
+                          VIDCON1_INV_VDEN,
+};
+
+static struct platform_device *smartq5_devices[] __initdata = {
+        &smartq5_leds_device,
+        &smartq5_buttons_device,
+        &smartq5_lcd_control_device,
+};
+
+static void __init smartq5_machine_init(void)
+{
+        s3c_fb_set_platdata(&smartq5_lcd_pdata);
+
+        smartq_machine_init();
+        smartq5_lcd_setup_gpio();
+
+        platform_add_devices(smartq5_devices, ARRAY_SIZE(smartq5_devices));
+}
+
+MACHINE_START(SMARTQ5, "SmartQ 5")
+        /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .init_irq       = s3c6410_init_irq,
+        .map_io         = smartq_map_io,
+        .init_machine   = smartq5_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
new file mode 100644
index 000000000000..e0bc78ecb156
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -0,0 +1,201 @@
+/*
+ * linux/arch/arm/mach-s3c64xx/mach-smartq7.c
+ *
+ * Copyright (C) 2010 Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c-gpio.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
+#include <mach/s3c6410.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+
+#include "mach-smartq.h"
+
+static void __init smartq7_lcd_setup_gpio(void)
+{
+        gpio_request(S3C64XX_GPM(0), "LCD CSB pin");
+        gpio_request(S3C64XX_GPM(3), "LCD power");
+        gpio_request(S3C64XX_GPM(4), "LCD power status");
+
+        /* turn power off */
+        gpio_direction_output(S3C64XX_GPM(0), 1);
+        gpio_direction_output(S3C64XX_GPM(3), 0);
+        gpio_direction_input(S3C64XX_GPM(4));
+}
+
+static struct i2c_gpio_platform_data smartq7_lcd_control = {
+        .sda_pin                = S3C64XX_GPM(2),
+        .scl_pin                = S3C64XX_GPM(1),
+        .sda_is_open_drain      = 1,
+        .scl_is_open_drain      = 1,
+};
+
+static struct platform_device smartq7_lcd_control_device = {
+        .name                   = "i2c-gpio",
+        .id                     = 1,
+        .dev.platform_data      = &smartq7_lcd_control,
+};
+
+static struct gpio_led smartq7_leds[] __initdata = {
+        {
+                .name                   = "smartq7:red",
+                .active_low             = 1,
+                .gpio                   = S3C64XX_GPN(8),
+        },
+        {
+                .name                   = "smartq7:green",
+                .active_low             = 1,
+                .gpio                   = S3C64XX_GPN(9),
+        },
+};
+
+static struct gpio_led_platform_data smartq7_led_data = {
+        .num_leds = ARRAY_SIZE(smartq7_leds),
+        .leds = smartq7_leds,
+};
+
+static struct platform_device smartq7_leds_device = {
+        .name                   = "leds-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &smartq7_led_data,
+};
+
+/* Labels according to the SmartQ manual */
+static struct gpio_keys_button smartq7_buttons[] = {
+        {
+                .gpio                   = S3C64XX_GPL(14),
+                .code                   = KEY_POWER,
+                .desc                   = "Power",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+        {
+                .gpio                   = S3C64XX_GPN(2),
+                .code                   = KEY_FN,
+                .desc                   = "Function",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+        {
+                .gpio                   = S3C64XX_GPN(3),
+                .code                   = KEY_KPMINUS,
+                .desc                   = "Minus",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+        {
+                .gpio                   = S3C64XX_GPN(4),
+                .code                   = KEY_KPPLUS,
+                .desc                   = "Plus",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+        {
+                .gpio                   = S3C64XX_GPN(12),
+                .code                   = KEY_ENTER,
+                .desc                   = "Enter",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+        {
+                .gpio                   = S3C64XX_GPN(15),
+                .code                   = KEY_ESC,
+                .desc                   = "Cancel",
+                .active_low             = 1,
+                .debounce_interval      = 5,
+                .type                   = EV_KEY,
+        },
+};
+
+static struct gpio_keys_platform_data smartq7_buttons_data  = {
+        .buttons        = smartq7_buttons,
+        .nbuttons       = ARRAY_SIZE(smartq7_buttons),
+};
+
+static struct platform_device smartq7_buttons_device  = {
+        .name           = "gpio-keys",
+        .id             = 0,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &smartq7_buttons_data,
+        }
+};
+
+static struct s3c_fb_pd_win smartq7_fb_win0 = {
+        .win_mode       = {
+                .pixclock       = 1000000000000ULL /
+                                ((3+10+5+800)*(1+3+20+480)*80),
+                .left_margin    = 3,
+                .right_margin   = 5,
+                .upper_margin   = 1,
+                .lower_margin   = 20,
+                .hsync_len      = 10,
+                .vsync_len      = 3,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 16,
+};
+
+static struct s3c_fb_platdata smartq7_lcd_pdata __initdata = {
+        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
+        .win[0]         = &smartq7_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
+                          VIDCON1_INV_VCLK,
+};
+
+static struct platform_device *smartq7_devices[] __initdata = {
+        &smartq7_leds_device,
+        &smartq7_buttons_device,
+        &smartq7_lcd_control_device,
+};
+
+static void __init smartq7_machine_init(void)
+{
+        s3c_fb_set_platdata(&smartq7_lcd_pdata);
+
+        smartq_machine_init();
+        smartq7_lcd_setup_gpio();
+
+        platform_add_devices(smartq7_devices, ARRAY_SIZE(smartq7_devices));
+}
+
+MACHINE_START(SMARTQ7, "SmartQ 7")
+        /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .init_irq       = s3c6410_init_irq,
+        .map_io         = smartq_map_io,
+        .init_machine   = smartq7_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 9d51455feb31..d9a03555f88b 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -64,6 +64,8 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
@@ -262,6 +264,9 @@ static struct platform_device *smdk6410_devices[] __initdata = {
         &smdk6410_lcd_powerdev,
 
         &smdk6410_smsc911x,
+        &s3c_device_adc,
+        &s3c_device_ts,
+        &s3c_device_wdt,
 };
 
 #ifdef CONFIG_REGULATOR
@@ -596,6 +601,12 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("24c128", 0x57), },    /* Samsung S524AD0XD1 */
 };
 
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
+
 static void __init smdk6410_map_io(void)
 {
         u32 tmp;
@@ -625,6 +636,8 @@ static void __init smdk6410_machine_init(void)
         s3c_i2c1_set_platdata(NULL);
         s3c_fb_set_platdata(&smdk6410_lcd_pdata);
 
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
         /* configure nCS1 width to 16 bits */
 
         cs1 = __raw_readl(S3C64XX_SROM_BW) &
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b8ac4597fad7..79412f735a8d 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -18,8 +18,11 @@
 #include <linux/io.h>
 
 #include <mach/map.h>
+#include <mach/irqs.h>
 
 #include <plat/pm.h>
+#include <plat/wakeup-mask.h>
+
 #include <mach/regs-sys.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
@@ -153,8 +156,25 @@ static void s3c64xx_cpu_suspend(void)
         panic("sleep resumed to originator?");
 }
 
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask wake_irqs[] = {
+        { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
+        { .irq = IRQ_RTC_TIC,   .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
+        { .irq = IRQ_PENDN,     .bit = S3C64XX_PWRCFG_TS_DISABLE, },
+        { .irq = IRQ_HSMMC0,    .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
+        { .irq = IRQ_HSMMC1,    .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
+        { .irq = IRQ_HSMMC2,    .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
+        { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
+        { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
+        { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
+        { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
+};
+
 static void s3c64xx_pm_prepare(void)
 {
+        samsung_sync_wakemask(S3C64XX_PWR_CFG,
+                              wake_irqs, ARRAY_SIZE(wake_irqs));
+
         /* store address of resume. */
         __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
 
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 707e34e3afd1..5e93fe3f3f40 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -37,6 +37,7 @@
 #include <plat/clock.h>
 #include <plat/sdhci.h>
 #include <plat/iic-core.h>
+#include <plat/onenand-core.h>
 #include <mach/s3c6400.h>
 
 void __init s3c6400_map_io(void)
@@ -51,6 +52,9 @@ void __init s3c6400_map_io(void)
         s3c_i2c0_setname("s3c2440-i2c");
 
         s3c_device_nand.name = "s3c6400-nand";
+
+        s3c_onenand_setname("s3c6400-onenand");
+        s3c64xx_onenand1_setname("s3c6400-onenand");
 }
 
 void __init s3c6400_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 3ab695c691ee..014401c39f36 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -39,6 +39,7 @@
 #include <plat/sdhci.h>
 #include <plat/iic-core.h>
 #include <plat/adc.h>
+#include <plat/onenand-core.h>
 #include <mach/s3c6400.h>
 #include <mach/s3c6410.h>
 
@@ -55,6 +56,8 @@ void __init s3c6410_map_io(void)
 
         s3c_device_adc.name     = "s3c64xx-adc";
         s3c_device_nand.name = "s3c6400-nand";
+        s3c_onenand_setname("s3c6410-onenand");
+        s3c64xx_onenand1_setname("s3c6410-onenand");
 }
 
 void __init s3c6410_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
index 77aeffd17330..f066fae07c57 100644
--- a/arch/arm/mach-s5p6440/Kconfig
+++ b/arch/arm/mach-s5p6440/Kconfig
@@ -16,6 +16,10 @@ config CPU_S5P6440
 config MACH_SMDK6440
         bool "SMDK6440"
         select CPU_S5P6440
+        select SAMSUNG_DEV_TS
+        select SAMSUNG_DEV_ADC
+        select S3C_DEV_WDT
+        select HAVE_S3C2410_WATCHDOG
         help
           Machine support for the Samsung SMDK6440
 
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile
index 44facf43d59f..be3c53aab23f 100644
--- a/arch/arm/mach-s5p6440/Makefile
+++ b/arch/arm/mach-s5p6440/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_SMDK6440)	+= mach-smdk6440.o
 
 # device support
 obj-y                           += dev-audio.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
index ca3b3206e6f8..b2fe6a58155a 100644
--- a/arch/arm/mach-s5p6440/cpu.c
+++ b/arch/arm/mach-s5p6440/cpu.c
@@ -61,6 +61,7 @@ static void s5p6440_idle(void)
 void __init s5p6440_map_io(void)
 {
         /* initialize any device information early */
+        s3c_device_adc.name     = "s3c64xx-adc";
 }
 
 void __init s5p6440_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c
new file mode 100644
index 000000000000..0a30280019c0
--- /dev/null
+++ b/arch/arm/mach-s5p6440/dev-spi.c
@@ -0,0 +1,176 @@
+/* linux/arch/arm/mach-s5p6440/dev-spi.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/spi-clocks.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+
+static char *spi_src_clks[] = {
+        [S5P6440_SPI_SRCCLK_PCLK] = "pclk",
+        [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s5p6440_spi0_resource[] = {
+        [0] = {
+                .start = S5P6440_PA_SPI0,
+                .end   = S5P6440_PA_SPI0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI0_TX,
+                .end   = DMACH_SPI0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI0_RX,
+                .end   = DMACH_SPI0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
+        .cfg_gpio = s5p6440_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x1ff,
+        .rx_lvl_offset = 15,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p6440_device_spi0 = {
+        .name             = "s3c64xx-spi",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5p6440_spi0_resource),
+        .resource         = s5p6440_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5p6440_spi0_pdata,
+        },
+};
+
+static struct resource s5p6440_spi1_resource[] = {
+        [0] = {
+                .start = S5P6440_PA_SPI1,
+                .end   = S5P6440_PA_SPI1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI1_TX,
+                .end   = DMACH_SPI1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI1_RX,
+                .end   = DMACH_SPI1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
+        .cfg_gpio = s5p6440_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 15,
+};
+
+struct platform_device s5p6440_device_spi1 = {
+        .name             = "s3c64xx-spi",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5p6440_spi1_resource),
+        .resource         = s5p6440_spi1_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5p6440_spi1_pdata,
+        },
+};
+
+void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        struct s3c64xx_spi_info *pd;
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                pd = &s5p6440_spi0_pdata;
+                break;
+        case 1:
+                pd = &s5p6440_spi1_pdata;
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        pd->src_clk_name = spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c
index 262dc75d5bea..92efc05b1ba2 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p6440/gpio.c
@@ -46,6 +46,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
         void __iomem *base = ourchip->base;
         void __iomem *regcon = base;
         unsigned long con;
+        unsigned long flags;
 
         switch (offset) {
         case 6:
@@ -63,10 +64,14 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
                 break;
         }
 
+        s3c_gpio_lock(ourchip, flags);
+
         con = __raw_readl(regcon);
         con &= ~(0xf << con_4bit_shift(offset));
         __raw_writel(con, regcon);
 
+        s3c_gpio_unlock(ourchip, flags);
+
         return 0;
 }
 
@@ -78,6 +83,7 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
         void __iomem *regcon = base;
         unsigned long con;
         unsigned long dat;
+        unsigned long flags;
         unsigned con_offset  = offset;
 
         switch (con_offset) {
@@ -96,6 +102,8 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
                 break;
         }
 
+        s3c_gpio_lock(ourchip, flags);
+
         con = __raw_readl(regcon);
         con &= ~(0xf << con_4bit_shift(con_offset));
         con |= 0x1 << con_4bit_shift(con_offset);
@@ -109,6 +117,8 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
         __raw_writel(con, regcon);
         __raw_writel(dat, base + GPIODAT_OFF);
 
+        s3c_gpio_unlock(ourchip, flags);
+
         return 0;
 }
 
@@ -117,6 +127,7 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
 {
         void __iomem *reg = chip->base;
         unsigned int shift;
+        unsigned long flags;
         u32 con;
 
         switch (off) {
@@ -142,11 +153,15 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
                 cfg <<= shift;
         }
 
+        s3c_gpio_lock(chip, flags);
+
         con = __raw_readl(reg);
         con &= ~(0xf << shift);
         con |= cfg;
         __raw_writel(con, reg);
 
+        s3c_gpio_unlock(chip, flags);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
index 72aedadd412c..44011b91fbd1 100644
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ b/arch/arm/mach-s5p6440/include/mach/map.h
@@ -54,6 +54,9 @@
 
 #define S5P6440_PA_IIC0         (0xEC104000)
 
+#define S5P6440_PA_SPI0         0xEC400000
+#define S5P6440_PA_SPI1         0xEC500000
+
 #define S5P6440_PA_HSOTG        (0xED100000)
 
 #define S5P6440_PA_HSMMC0       (0xED800000)
@@ -69,8 +72,13 @@
 /* PCM */
 #define S5P6440_PA_PCM          0xF2100000
 
+#define S5P6440_PA_ADC          (0xF3000000)
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART             S5P6440_PA_UART
 #define S3C_PA_IIC              S5P6440_PA_IIC0
+#define S3C_PA_WDT              S5P6440_PA_WDT
+
+#define SAMSUNG_PA_ADC          S5P6440_PA_ADC
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..5fbca50d1cfb
--- /dev/null
+++ b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S5P6440_PLAT_SPI_CLKS_H
+#define __S5P6440_PLAT_SPI_CLKS_H __FILE__
+
+#define S5P6440_SPI_SRCCLK_PCLK         0
+#define S5P6440_SPI_SRCCLK_SCLK         1
+
+#endif /* __S5P6440_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c
index d7fede971ca6..8291fecc701a 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p6440/mach-smdk6440.c
@@ -38,6 +38,8 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pll.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
 
 #define S5P6440_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |         \
@@ -85,6 +87,15 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
 
 static struct platform_device *smdk6440_devices[] __initdata = {
         &s5p6440_device_iis,
+        &s3c_device_adc,
+        &s3c_device_ts,
+        &s3c_device_wdt,
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
 };
 
 static void __init smdk6440_map_io(void)
@@ -96,6 +107,8 @@ static void __init smdk6440_map_io(void)
 
 static void __init smdk6440_machine_init(void)
 {
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
         platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
 }
 
diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile
index e30a7f76aee6..90a3d8373416 100644
--- a/arch/arm/mach-s5p6442/Makefile
+++ b/arch/arm/mach-s5p6442/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_SMDK6442)	+= mach-smdk6442.o
 
 # device support
 obj-y                           += dev-audio.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c
new file mode 100644
index 000000000000..30199525daca
--- /dev/null
+++ b/arch/arm/mach-s5p6442/dev-spi.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/mach-s5p6442/dev-spi.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/spi-clocks.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+
+static char *spi_src_clks[] = {
+        [S5P6442_SPI_SRCCLK_PCLK] = "pclk",
+        [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6442_GPB(2), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6442_GPB(3), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6442_GPB(2), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6442_GPB(3), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s5p6442_spi0_resource[] = {
+        [0] = {
+                .start = S5P6442_PA_SPI,
+                .end   = S5P6442_PA_SPI + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI0_TX,
+                .end   = DMACH_SPI0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI0_RX,
+                .end   = DMACH_SPI0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6442_spi0_pdata = {
+        .cfg_gpio = s5p6442_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x1ff,
+        .rx_lvl_offset = 15,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p6442_device_spi = {
+        .name             = "s3c64xx-spi",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5p6442_spi0_resource),
+        .resource         = s5p6442_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5p6442_spi0_pdata,
+        },
+};
+
+void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        struct s3c64xx_spi_info *pd;
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                pd = &s5p6442_spi0_pdata;
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        pd->src_clk_name = spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 7568dc0d6be0..32ca424ef7f9 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -54,6 +54,8 @@
 #define S5P6442_PA_SDRAM        (0x20000000)
 #define S5P_PA_SDRAM            S5P6442_PA_SDRAM
 
+#define S5P6442_PA_SPI          0xEC300000
+
 /* I2S */
 #define S5P6442_PA_I2S0         0xC0B00000
 #define S5P6442_PA_I2S1         0xF2200000
diff --git a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..7fd88205a97c
--- /dev/null
+++ b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S5P6442_PLAT_SPI_CLKS_H
+#define __S5P6442_PLAT_SPI_CLKS_H __FILE__
+
+#define S5P6442_SPI_SRCCLK_PCLK         0
+#define S5P6442_SPI_SRCCLK_SCLK         1
+
+#endif /* __S5P6442_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 8593337784e1..b2a11dfa3399 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -5,10 +5,13 @@
 
 # Configuration options for the S5PC100 CPU
 
+if ARCH_S5PC100
+
 config CPU_S5PC100
         bool
-        select CPU_S5PC100_INIT
-        select CPU_S5PC100_CLOCK
+        select PLAT_S5P
+        select S5P_EXT_INT
+        select S3C_PL330_DMA
         help
           Enable S5PC100 CPU support
 
@@ -17,17 +20,22 @@ config S5PC100_SETUP_FB_24BPP
         help
           Common setup code for S5PC1XX with an 24bpp RGB display helper.
 
-config S5PC100_SETUP_SDHCI
-        bool
-        select S5PC1XX_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for S5PC100 based SDHCI systems
-
 config S5PC100_SETUP_I2C1
         bool
         help
           Common setup code for i2c bus 1.
 
+config S5PC100_SETUP_SDHCI
+        bool
+        select S5PC100_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S5PC100 based SDHCI systems
+
+config S5PC100_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
 config MACH_SMDKC100
         bool "SMDKC100"
         select CPU_S5PC100
@@ -41,3 +49,5 @@ config MACH_SMDKC100
         select S5PC100_SETUP_SDHCI
         help
           Machine support for the Samsung SMDKC100
+
+endif
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 373bc546eae8..543f3de5131e 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,14 +11,24 @@ obj-				:=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)       += cpu.o gpiolib.o
+obj-$(CONFIG_CPU_S5PC100)       += cpu.o init.o clock.o gpiolib.o irq-gpio.o
 obj-$(CONFIG_CPU_S5PC100)       += setup-i2c0.o
+obj-$(CONFIG_CPU_S5PC100)       += dma.o
 
 # Helper and device support
 
 obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)    += setup-fb-24bpp.o
 obj-$(CONFIG_S5PC100_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+
+# device support
+obj-y                           += dev-audio.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 # machine support
+
 obj-$(CONFIG_MACH_SMDKC100)     += mach-smdkc100.o
+
+# device support
+obj-y                           += dev-audio.o
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index d79e7574a852..7b5bdbc9a5df 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -22,47 +22,55 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 
-#include <asm/proc-fns.h>
-
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <asm/proc-fns.h>
+
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <asm/irq.h>
 
-#include <plat/cpu-freq.h>
 #include <plat/regs-serial.h>
-#include <plat/regs-power.h>
+#include <mach/regs-clock.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
-#include <plat/sdhci.h>
 #include <plat/iic-core.h>
+#include <plat/sdhci.h>
+#include <plat/onenand-core.h>
+
 #include <plat/s5pc100.h>
 
 /* Initial IO mappings */
 
 static struct map_desc s5pc100_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+                .pfn            = __phys_to_pfn(S5PC100_PA_SYSTIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC2,
+                .pfn            = __phys_to_pfn(S5P_PA_VIC2),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC100_VA_OTHERS,
+                .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }
 };
 
 static void s5pc100_idle(void)
 {
-        unsigned long tmp;
-
-        tmp = __raw_readl(S5PC100_PWR_CFG);
-        tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE;
-        tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK;
-        tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE;
-        __raw_writel(tmp, S5PC100_PWR_CFG);
-
-        tmp = __raw_readl(S5PC100_OTHERS);
-        tmp |= S5PC100_PMU_INT_DISABLE;
-        __raw_writel(tmp, S5PC100_OTHERS);
+        if (!need_resched())
+                cpu_do_idle();
 
-        cpu_do_idle();
+        local_irq_enable();
 }
 
 /* s5pc100_map_io
@@ -82,26 +90,29 @@ void __init s5pc100_map_io(void)
         /* the i2c devices are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
         s3c_i2c1_setname("s3c2440-i2c");
+
+        s3c_onenand_setname("s5pc100-onenand");
 }
 
 void __init s5pc100_init_clocks(int xtal)
 {
-        printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
         s3c24xx_register_baseclocks(xtal);
-        s5pc1xx_register_clocks();
+        s5p_register_clocks(xtal);
         s5pc100_register_clocks();
         s5pc100_setup_clocks();
 }
 
 void __init s5pc100_init_irq(void)
 {
-        u32 vic_valid[] = {~0, ~0, ~0};
+        u32 vic[] = {~0, ~0, ~0};
 
         /* VIC0, VIC1, and VIC2 are fully populated. */
-        s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid));
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
 }
 
-struct sysdev_class s5pc100_sysclass = {
+static struct sysdev_class s5pc100_sysclass = {
         .name   = "s5pc100-core",
 };
 
@@ -118,9 +129,10 @@ core_initcall(s5pc100_core_init);
 
 int __init s5pc100_init(void)
 {
-        printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
+        printk(KERN_INFO "S5PC100: Initializing architecture\n");
 
-        s5pc1xx_idle = s5pc100_idle;
+        /* set idle function */
+        pm_idle = s5pc100_idle;
 
         return sysdev_register(&s5pc100_sysdev);
 }
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
new file mode 100644
index 000000000000..18cfe9ae1936
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -0,0 +1,287 @@
+/* linux/arch/arm/mach-s5pc100/dev-audio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+
+#include <mach/gpio.h>
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+static int s5pc100_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case 1:
+                s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2));
+                break;
+
+        case 2:
+                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4));
+                break;
+
+        case -1: /* Dedicated pins */
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s3c_i2s_pdata = {
+        .cfg_gpio = s5pc100_cfg_i2s,
+};
+
+static struct resource s5pc100_iis0_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_I2S0,
+                .end   = S5PC100_PA_I2S0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_I2S0_TX,
+                .end   = DMACH_I2S0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S0_RX,
+                .end   = DMACH_I2S0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_iis0 = {
+        .name             = "s3c64xx-iis-v4",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s5pc100_iis0_resource),
+        .resource         = s5pc100_iis0_resource,
+        .dev = {
+                .platform_data = &s3c_i2s_pdata,
+        },
+};
+
+static struct resource s5pc100_iis1_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_I2S1,
+                .end   = S5PC100_PA_I2S1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_I2S1_TX,
+                .end   = DMACH_I2S1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S1_RX,
+                .end   = DMACH_I2S1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_iis1 = {
+        .name             = "s3c64xx-iis",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5pc100_iis1_resource),
+        .resource         = s5pc100_iis1_resource,
+        .dev = {
+                .platform_data = &s3c_i2s_pdata,
+        },
+};
+
+static struct resource s5pc100_iis2_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_I2S2,
+                .end   = S5PC100_PA_I2S2 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_I2S2_TX,
+                .end   = DMACH_I2S2_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S2_RX,
+                .end   = DMACH_I2S2_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_iis2 = {
+        .name             = "s3c64xx-iis",
+        .id               = 2,
+        .num_resources    = ARRAY_SIZE(s5pc100_iis2_resource),
+        .resource         = s5pc100_iis2_resource,
+        .dev = {
+                .platform_data = &s3c_i2s_pdata,
+        },
+};
+
+/* PCM Controller platform_devices */
+
+static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5));
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3));
+                break;
+
+        default:
+                printk(KERN_DEBUG "Invalid PCM Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s3c_pcm_pdata = {
+        .cfg_gpio = s5pc100_pcm_cfg_gpio,
+};
+
+static struct resource s5pc100_pcm0_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_PCM0,
+                .end   = S5PC100_PA_PCM0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_PCM0_TX,
+                .end   = DMACH_PCM0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_PCM0_RX,
+                .end   = DMACH_PCM0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_pcm0 = {
+        .name             = "samsung-pcm",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5pc100_pcm0_resource),
+        .resource         = s5pc100_pcm0_resource,
+        .dev = {
+                .platform_data = &s3c_pcm_pdata,
+        },
+};
+
+static struct resource s5pc100_pcm1_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_PCM1,
+                .end   = S5PC100_PA_PCM1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_PCM1_TX,
+                .end   = DMACH_PCM1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_PCM1_RX,
+                .end   = DMACH_PCM1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_pcm1 = {
+        .name             = "samsung-pcm",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5pc100_pcm1_resource),
+        .resource         = s5pc100_pcm1_resource,
+        .dev = {
+                .platform_data = &s3c_pcm_pdata,
+        },
+};
+
+/* AC97 Controller platform devices */
+
+static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
+{
+        s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4));
+        s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4));
+        s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4));
+        s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4));
+        s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4));
+
+        return 0;
+}
+
+static struct resource s5pc100_ac97_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_AC97,
+                .end   = S5PC100_PA_AC97 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_AC97_PCMOUT,
+                .end   = DMACH_AC97_PCMOUT,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_AC97_PCMIN,
+                .end   = DMACH_AC97_PCMIN,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = DMACH_AC97_MICIN,
+                .end   = DMACH_AC97_MICIN,
+                .flags = IORESOURCE_DMA,
+        },
+        [4] = {
+                .start = IRQ_AC97,
+                .end   = IRQ_AC97,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_audio_pdata s3c_ac97_pdata = {
+        .cfg_gpio = s5pc100_ac97_cfg_gpio,
+};
+
+static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pc100_device_ac97 = {
+        .name             = "s3c-ac97",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s5pc100_ac97_resource),
+        .resource         = s5pc100_ac97_resource,
+        .dev = {
+                .platform_data = &s3c_ac97_pdata,
+                .dma_mask = &s5pc100_ac97_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
new file mode 100644
index 000000000000..14618c346057
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dev-spi.c
@@ -0,0 +1,233 @@
+/* linux/arch/arm/mach-s5pc100/dev-spi.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/gpio.h>
+#include <mach/spi-clocks.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+#include <plat/irqs.h>
+
+static char *spi_src_clks[] = {
+        [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
+        [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
+        [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP);
+                break;
+
+        case 2:
+                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3));
+                s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s5pc100_spi0_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_SPI0,
+                .end   = S5PC100_PA_SPI0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI0_TX,
+                .end   = DMACH_SPI0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI0_RX,
+                .end   = DMACH_SPI0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
+        .cfg_gpio = s5pc100_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 13,
+        .high_speed = 1,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pc100_device_spi0 = {
+        .name             = "s3c64xx-spi",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5pc100_spi0_resource),
+        .resource         = s5pc100_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_spi0_pdata,
+        },
+};
+
+static struct resource s5pc100_spi1_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_SPI1,
+                .end   = S5PC100_PA_SPI1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI1_TX,
+                .end   = DMACH_SPI1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI1_RX,
+                .end   = DMACH_SPI1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
+        .cfg_gpio = s5pc100_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 13,
+        .high_speed = 1,
+};
+
+struct platform_device s5pc100_device_spi1 = {
+        .name             = "s3c64xx-spi",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5pc100_spi1_resource),
+        .resource         = s5pc100_spi1_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_spi1_pdata,
+        },
+};
+
+static struct resource s5pc100_spi2_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_SPI2,
+                .end   = S5PC100_PA_SPI2 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI2_TX,
+                .end   = DMACH_SPI2_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI2_RX,
+                .end   = DMACH_SPI2_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI2,
+                .end   = IRQ_SPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
+        .cfg_gpio = s5pc100_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 13,
+        .high_speed = 1,
+};
+
+struct platform_device s5pc100_device_spi2 = {
+        .name             = "s3c64xx-spi",
+        .id               = 2,
+        .num_resources    = ARRAY_SIZE(s5pc100_spi2_resource),
+        .resource         = s5pc100_spi2_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_spi2_pdata,
+        },
+};
+
+void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        struct s3c64xx_spi_info *pd;
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                pd = &s5pc100_spi0_pdata;
+                break;
+        case 1:
+                pd = &s5pc100_spi1_pdata;
+                break;
+        case 2:
+                pd = &s5pc100_spi2_pdata;
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        pd->src_clk_name = spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
new file mode 100644
index 000000000000..0f5517571e2c
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource s5pc100_pdma0_resource[] = {
+        [0] = {
+                .start  = S5PC100_PA_PDMA0,
+                .end    = S5PC100_PA_PDMA0 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PDMA0,
+                .end    = IRQ_PDMA0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5pc100_pdma0_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_IRDA,
+                [9] = DMACH_I2S0_RX,
+                [10] = DMACH_I2S0_TX,
+                [11] = DMACH_I2S0S_TX,
+                [12] = DMACH_I2S1_RX,
+                [13] = DMACH_I2S1_TX,
+                [14] = DMACH_I2S2_RX,
+                [15] = DMACH_I2S2_TX,
+                [16] = DMACH_SPI0_RX,
+                [17] = DMACH_SPI0_TX,
+                [18] = DMACH_SPI1_RX,
+                [19] = DMACH_SPI1_TX,
+                [20] = DMACH_SPI2_RX,
+                [21] = DMACH_SPI2_TX,
+                [22] = DMACH_AC97_MICIN,
+                [23] = DMACH_AC97_PCMIN,
+                [24] = DMACH_AC97_PCMOUT,
+                [25] = DMACH_EXTERNAL,
+                [26] = DMACH_PWM,
+                [27] = DMACH_SPDIF,
+                [28] = DMACH_HSI_RX,
+                [29] = DMACH_HSI_TX,
+                [30] = DMACH_MAX,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct platform_device s5pc100_device_pdma0 = {
+        .name           = "s3c-pl330",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5pc100_pdma0_resource),
+        .resource       = s5pc100_pdma0_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_pdma0_pdata,
+        },
+};
+
+static struct resource s5pc100_pdma1_resource[] = {
+        [0] = {
+                .start  = S5PC100_PA_PDMA1,
+                .end    = S5PC100_PA_PDMA1 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PDMA1,
+                .end    = IRQ_PDMA1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5pc100_pdma1_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_IRDA,
+                [9] = DMACH_I2S0_RX,
+                [10] = DMACH_I2S0_TX,
+                [11] = DMACH_I2S0S_TX,
+                [12] = DMACH_I2S1_RX,
+                [13] = DMACH_I2S1_TX,
+                [14] = DMACH_I2S2_RX,
+                [15] = DMACH_I2S2_TX,
+                [16] = DMACH_SPI0_RX,
+                [17] = DMACH_SPI0_TX,
+                [18] = DMACH_SPI1_RX,
+                [19] = DMACH_SPI1_TX,
+                [20] = DMACH_SPI2_RX,
+                [21] = DMACH_SPI2_TX,
+                [22] = DMACH_PCM0_RX,
+                [23] = DMACH_PCM0_TX,
+                [24] = DMACH_PCM1_RX,
+                [25] = DMACH_PCM1_TX,
+                [26] = DMACH_MSM_REQ0,
+                [27] = DMACH_MSM_REQ1,
+                [28] = DMACH_MSM_REQ2,
+                [29] = DMACH_MSM_REQ3,
+                [30] = DMACH_MAX,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct platform_device s5pc100_device_pdma1 = {
+        .name           = "s3c-pl330",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s5pc100_pdma1_resource),
+        .resource       = s5pc100_pdma1_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_pdma1_pdata,
+        },
+};
+
+static struct platform_device *s5pc100_dmacs[] __initdata = {
+        &s5pc100_device_pdma0,
+        &s5pc100_device_pdma1,
+};
+
+static int __init s5pc100_dma_init(void)
+{
+        platform_add_devices(s5pc100_dmacs, ARRAY_SIZE(s5pc100_dmacs));
+
+        return 0;
+}
+arch_initcall(s5pc100_dma_init);
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index c8e8336a3a12..0fab7f2cd8bf 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -1,10 +1,10 @@
 /*
- * arch/arm/plat-s5pc1xx/gpiolib.c
+ * arch/arm/plat-s5pc100/gpiolib.c
  *
  *  Copyright 2009 Samsung Electronics Co
  *  Kyungmin Park <kyungmin.park@samsung.com>
  *
- * S5PC1XX - GPIOlib support
+ * S5PC100 - GPIOlib support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -61,13 +61,12 @@
  * L3   8       4Bit    None
  */
 
-#if 0
-static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
 {
         return S3C_IRQ_GPIO(chip->base + offset);
 }
 
-static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
+static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
 {
         int base;
 
@@ -85,7 +84,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
                 return IRQ_EINT(24 + offset);
         return -EINVAL;
 }
-#endif
+
 static struct s3c_gpio_cfg gpio_cfg = {
         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
         .set_pull       = s3c_gpio_setpull_updown,
@@ -382,31 +381,30 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 };
 
 /* FIXME move from irq-gpio.c */
-extern struct irq_chip s5pc1xx_gpioint;
-extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
+extern struct irq_chip s5pc100_gpioint;
+extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
 
 static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
 {
-#if 0
         /* Interrupt */
         if (chip->config == &gpio_cfg) {
                 int i, irq;
 
-                chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
+                chip->chip.to_irq = s5pc100_gpiolib_to_irq;
 
                 for (i = 0;  i < chip->chip.ngpio; i++) {
                         irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
-                        set_irq_chip(irq, &s5pc1xx_gpioint);
+                        set_irq_chip(irq, &s5pc100_gpioint);
                         set_irq_data(irq, &chip->chip);
                         set_irq_handler(irq, handle_level_irq);
                         set_irq_flags(irq, IRQF_VALID);
                 }
-        } else if (chip->config == &gpio_cfg_eint)
-                chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
-#endif
+        } else if (chip->config == &gpio_cfg_eint) {
+                chip->chip.to_irq = s5pc100_gpiolib_to_eint;
+        }
 }
 
-static __init int s5pc1xx_gpiolib_init(void)
+static __init int s5pc100_gpiolib_init(void)
 {
         struct s3c_gpio_chip *chip;
         int nr_chips;
@@ -419,10 +417,10 @@ static __init int s5pc1xx_gpiolib_init(void)
 
         samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
                                        ARRAY_SIZE(s5pc100_gpio_chips));
-#if 0
+
         /* Interrupt */
-        set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
-#endif
+        set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
+
         return 0;
 }
-core_initcall(s5pc1xx_gpiolib_init);
+core_initcall(s5pc100_gpiolib_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index e181f5789482..70e02e91ee3c 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,12 +22,14 @@
          * aligned and add in the offset when we load the value here.
          */
 
-        .macro addruart, rx, tmp
+        .macro addruart, rx, rtmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1
                 ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+                ldrne   \rx, = S3C_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
                 add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+#endif
         .endm
 
 /* include the reset of the code which will do the work, we're only
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index 67131939e626..ba76af052c81 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -20,7 +20,7 @@
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =S3C_VA_VIC0
+        ldr     \base, =VA_VIC0
         .endm
 
         .macro  arch_ret_to_user, tmp1, tmp2
@@ -29,18 +29,18 @@
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
         @ check the vic0
-        mov     \irqnr, # S3C_IRQ_OFFSET + 31
+        mov     \irqnr, # S5P_IRQ_OFFSET + 31
         ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
         teq     \irqstat, #0
 
         @ otherwise try vic1
-        addeq   \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
+        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
         addeq   \irqnr, \irqnr, #32
         ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
         teqeq   \irqstat, #0
 
         @ otherwise try vic2
-        addeq   \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0)
+        addeq   \tmp, \base, #(VA_VIC2 - VA_VIC0)
         addeq   \irqnr, \irqnr, #32
         ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
         teqeq   \irqstat, #0
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 29a8a12d9b4f..71ae1f52df1d 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,6 +146,13 @@ enum s5p_gpio_number {
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS           (S5PC100_GPIO_END + 1)
 
+#define EINT_MODE               S3C_GPIO_SFN(0x2)
+
+#define EINT_GPIO_0(x)          S5PC100_GPH0(x)
+#define EINT_GPIO_1(x)          S5PC100_GPH1(x)
+#define EINT_GPIO_2(x)          S5PC100_GPH2(x)
+#define EINT_GPIO_3(x)          S5PC100_GPH3(x)
+
 #include <asm-generic/gpio.h>
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index b53fa48a52c6..15066df3ced9 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,9 +11,107 @@
 
 #include <plat/irqs.h>
 
-/* LCD */
+/* VIC0: system, DMA, timer */
+#define IRQ_EINT16_31           S5P_IRQ_VIC0(16)
+#define IRQ_BATF                S5P_IRQ_VIC0(17)
+#define IRQ_MDMA                S5P_IRQ_VIC0(18)
+#define IRQ_PDMA0               S5P_IRQ_VIC0(19)
+#define IRQ_PDMA1               S5P_IRQ_VIC0(20)
+#define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(21)
+#define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(22)
+#define IRQ_TIMER2_VIC          S5P_IRQ_VIC0(23)
+#define IRQ_TIMER3_VIC          S5P_IRQ_VIC0(24)
+#define IRQ_TIMER4_VIC          S5P_IRQ_VIC0(25)
+#define IRQ_SYSTIMER            S5P_IRQ_VIC0(26)
+#define IRQ_WDT                 S5P_IRQ_VIC0(27)
+#define IRQ_RTC_ALARM           S5P_IRQ_VIC0(28)
+#define IRQ_RTC_TIC             S5P_IRQ_VIC0(29)
+#define IRQ_GPIOINT             S5P_IRQ_VIC0(30)
+
+/* VIC1: ARM, power, memory, connectivity */
+#define IRQ_CORTEX0             S5P_IRQ_VIC1(0)
+#define IRQ_CORTEX1             S5P_IRQ_VIC1(1)
+#define IRQ_CORTEX2             S5P_IRQ_VIC1(2)
+#define IRQ_CORTEX3             S5P_IRQ_VIC1(3)
+#define IRQ_CORTEX4             S5P_IRQ_VIC1(4)
+#define IRQ_IEMAPC              S5P_IRQ_VIC1(5)
+#define IRQ_IEMIEC              S5P_IRQ_VIC1(6)
+#define IRQ_ONENAND             S5P_IRQ_VIC1(7)
+#define IRQ_NFC                 S5P_IRQ_VIC1(8)
+#define IRQ_CFC                 S5P_IRQ_VIC1(9)
+#define IRQ_UART0               S5P_IRQ_VIC1(10)
+#define IRQ_UART1               S5P_IRQ_VIC1(11)
+#define IRQ_UART2               S5P_IRQ_VIC1(12)
+#define IRQ_UART3               S5P_IRQ_VIC1(13)
+#define IRQ_IIC                 S5P_IRQ_VIC1(14)
+#define IRQ_SPI0                S5P_IRQ_VIC1(15)
+#define IRQ_SPI1                S5P_IRQ_VIC1(16)
+#define IRQ_SPI2                S5P_IRQ_VIC1(17)
+#define IRQ_IRDA                S5P_IRQ_VIC1(18)
+#define IRQ_CAN0                S5P_IRQ_VIC1(19)
+#define IRQ_CAN1                S5P_IRQ_VIC1(20)
+#define IRQ_HSIRX               S5P_IRQ_VIC1(21)
+#define IRQ_HSITX               S5P_IRQ_VIC1(22)
+#define IRQ_UHOST               S5P_IRQ_VIC1(23)
+#define IRQ_OTG                 S5P_IRQ_VIC1(24)
+#define IRQ_MSM                 S5P_IRQ_VIC1(25)
+#define IRQ_HSMMC0              S5P_IRQ_VIC1(26)
+#define IRQ_HSMMC1              S5P_IRQ_VIC1(27)
+#define IRQ_HSMMC2              S5P_IRQ_VIC1(28)
+#define IRQ_MIPICSI             S5P_IRQ_VIC1(29)
+#define IRQ_MIPIDSI             S5P_IRQ_VIC1(30)
+
+/* VIC2: multimedia, audio, security */
+#define IRQ_LCD0                S5P_IRQ_VIC2(0)
+#define IRQ_LCD1                S5P_IRQ_VIC2(1)
+#define IRQ_LCD2                S5P_IRQ_VIC2(2)
+#define IRQ_LCD3                S5P_IRQ_VIC2(3)
+#define IRQ_ROTATOR             S5P_IRQ_VIC2(4)
+#define IRQ_FIMC0               S5P_IRQ_VIC2(5)
+#define IRQ_FIMC1               S5P_IRQ_VIC2(6)
+#define IRQ_FIMC2               S5P_IRQ_VIC2(7)
+#define IRQ_JPEG                S5P_IRQ_VIC2(8)
+#define IRQ_2D                  S5P_IRQ_VIC2(9)
+#define IRQ_3D                  S5P_IRQ_VIC2(10)
+#define IRQ_MIXER               S5P_IRQ_VIC2(11)
+#define IRQ_HDMI                S5P_IRQ_VIC2(12)
+#define IRQ_IIC1                S5P_IRQ_VIC2(13)
+#define IRQ_MFC                 S5P_IRQ_VIC2(14)
+#define IRQ_TVENC               S5P_IRQ_VIC2(15)
+#define IRQ_I2S0                S5P_IRQ_VIC2(16)
+#define IRQ_I2S1                S5P_IRQ_VIC2(17)
+#define IRQ_I2S2                S5P_IRQ_VIC2(18)
+#define IRQ_AC97                S5P_IRQ_VIC2(19)
+#define IRQ_PCM0                S5P_IRQ_VIC2(20)
+#define IRQ_PCM1                S5P_IRQ_VIC2(21)
+#define IRQ_SPDIF               S5P_IRQ_VIC2(22)
+#define IRQ_ADC                 S5P_IRQ_VIC2(23)
+#define IRQ_PENDN               S5P_IRQ_VIC2(24)
+#define IRQ_TC                  IRQ_PENDN
+#define IRQ_KEYPAD              S5P_IRQ_VIC2(25)
+#define IRQ_CG                  S5P_IRQ_VIC2(26)
+#define IRQ_SEC                 S5P_IRQ_VIC2(27)
+#define IRQ_SECRX               S5P_IRQ_VIC2(28)
+#define IRQ_SECTX               S5P_IRQ_VIC2(29)
+#define IRQ_SDMIRQ              S5P_IRQ_VIC2(30)
+#define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
+#define IRQ_VIC_END             S5P_IRQ_VIC2(31)
+
+#define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
+#define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
+
+#define IRQ_EINT(x)             ((x) < 16 ? S5P_IRQ_VIC0(x) : \
+                                 (S5P_EINT_BASE2 + (x) - 16))
+
+#define S3C_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
+#define S3C_IRQ_GPIO(x)         (S3C_IRQ_GPIO_BASE + (x))
+
+/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
+#define NR_IRQS         (S3C_IRQ_GPIO(320) + 1)
+
+/* Compatibility */
 #define IRQ_LCD_FIFO            IRQ_LCD0
 #define IRQ_LCD_VSYNC           IRQ_LCD1
 #define IRQ_LCD_SYSTEM          IRQ_LCD2
 
-#endif /* __ASM_ARCH_IRQ_H */
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 4681ebe8bef6..cadae4305688 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -3,9 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * Based on mach-s3c6400/include/mach/map.h
- *
- * S5PC1XX - Memory map definitions
+ * S5PC100 - Memory map definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -16,6 +14,7 @@
 #define __ASM_ARCH_MAP_H __FILE__
 
 #include <plat/map-base.h>
+#include <plat/map-s5p.h>
 
 /*
  * map-base.h has already defined virtual memory address
@@ -31,25 +30,21 @@
  *
  */
 
+#define S5PC100_PA_ONENAND_BUF  (0xB0000000)
+#define S5PC100_SZ_ONENAND_BUF  (SZ_256M - SZ_32M)
+
 /* Chip ID */
+
 #define S5PC100_PA_CHIPID       (0xE0000000)
-#define S5PC1XX_PA_CHIPID       S5PC100_PA_CHIPID
-#define S5PC1XX_VA_CHIPID       S3C_VA_SYS
-
-/* System */
-#define S5PC100_PA_CLK          (0xE0100000)
-#define S5PC100_PA_CLK_OTHER    (0xE0200000)
-#define S5PC100_PA_PWR          (0xE0108000)
-#define S5PC1XX_PA_CLK          S5PC100_PA_CLK
-#define S5PC1XX_PA_PWR          S5PC100_PA_PWR
-#define S5PC1XX_PA_CLK_OTHER    S5PC100_PA_CLK_OTHER
-#define S5PC1XX_VA_CLK          (S3C_VA_SYS + 0x10000)
-#define S5PC1XX_VA_PWR          (S3C_VA_SYS + 0x20000)
-#define S5PC1XX_VA_CLK_OTHER    (S3C_VA_SYS + 0x30000)
-
-/* GPIO */
-#define S5PC100_PA_GPIO         (0xE0300000)
-#define S5PC1XX_PA_GPIO         S5PC100_PA_GPIO
+#define S5P_PA_CHIPID           S5PC100_PA_CHIPID
+
+#define S5PC100_PA_SYSCON       (0xE0100000)
+#define S5P_PA_SYSCON           S5PC100_PA_SYSCON
+
+#define S5PC100_PA_OTHERS       (0xE0200000)
+#define S5PC100_VA_OTHERS       (S3C_VA_SYS + 0x10000)
+
+#define S5P_PA_GPIO             (0xE0300000)
 #define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
 
 /* Interrupt */
@@ -59,6 +54,12 @@
 #define S5PC100_VA_VIC_OFFSET   0x10000
 #define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+#define S5P_PA_VIC0             S5PC1XX_PA_VIC(0)
+#define S5P_PA_VIC1             S5PC1XX_PA_VIC(1)
+#define S5P_PA_VIC2             S5PC1XX_PA_VIC(2)
+
+
+#define S5PC100_PA_ONENAND      (0xE7100000)
 
 /* DMA */
 #define S5PC100_PA_MDMA         (0xE8100000)
@@ -67,84 +68,71 @@
 
 /* Timer */
 #define S5PC100_PA_TIMER        (0xEA000000)
-#define S5PC1XX_PA_TIMER        S5PC100_PA_TIMER
-#define S5PC1XX_VA_TIMER        S3C_VA_TIMER
+#define S5P_PA_TIMER            S5PC100_PA_TIMER
 
-/* RTC */
-#define S5PC100_PA_RTC          (0xEA300000)
+#define S5PC100_PA_SYSTIMER     (0xEA100000)
 
-/* UART */
 #define S5PC100_PA_UART         (0xEC000000)
-#define S5PC1XX_PA_UART         S5PC100_PA_UART
-#define S5PC1XX_VA_UART         S3C_VA_UART
 
-/* I2C */
-#define S5PC100_PA_I2C          (0xEC100000)
-#define S5PC100_PA_I2C1         (0xEC200000)
+#define S5P_PA_UART0            (S5PC100_PA_UART + 0x0)
+#define S5P_PA_UART1            (S5PC100_PA_UART + 0x400)
+#define S5P_PA_UART2            (S5PC100_PA_UART + 0x800)
+#define S5P_PA_UART3            (S5PC100_PA_UART + 0xC00)
+#define S5P_SZ_UART             SZ_256
+
+#define S5PC100_PA_IIC0         (0xEC100000)
+#define S5PC100_PA_IIC1         (0xEC200000)
+
+/* SPI */
+#define S5PC100_PA_SPI0         0xEC300000
+#define S5PC100_PA_SPI1         0xEC400000
+#define S5PC100_PA_SPI2         0xEC500000
 
 /* USB HS OTG */
 #define S5PC100_PA_USB_HSOTG    (0xED200000)
 #define S5PC100_PA_USB_HSPHY    (0xED300000)
 
-/* SD/MMC */
-#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
-#define S5PC100_PA_HSMMC0       S5PC100_PA_HSMMC(0)
-#define S5PC100_PA_HSMMC1       S5PC100_PA_HSMMC(1)
-#define S5PC100_PA_HSMMC2       S5PC100_PA_HSMMC(2)
-
-/* LCD */
 #define S5PC100_PA_FB           (0xEE000000)
 
-/* Multimedia */
-#define S5PC100_PA_G2D          (0xEE800000)
-#define S5PC100_PA_JPEG         (0xEE500000)
-#define S5PC100_PA_ROTATOR      (0xEE100000)
-#define S5PC100_PA_G3D          (0xEF000000)
-
-/* I2S */
 #define S5PC100_PA_I2S0         (0xF2000000)
 #define S5PC100_PA_I2S1         (0xF2100000)
 #define S5PC100_PA_I2S2         (0xF2200000)
 
+#define S5PC100_PA_AC97         0xF2300000
+
+/* PCM */
+#define S5PC100_PA_PCM0         0xF2400000
+#define S5PC100_PA_PCM1         0xF2500000
+
 /* KEYPAD */
 #define S5PC100_PA_KEYPAD       (0xF3100000)
 
-/* ADC & TouchScreen */
-#define S5PC100_PA_TSADC        (0xF3000000)
+#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
 
-/* ETC */
 #define S5PC100_PA_SDRAM        (0x20000000)
-#define S5PC1XX_PA_SDRAM        S5PC100_PA_SDRAM
+#define S5P_PA_SDRAM            S5PC100_PA_SDRAM
 
-/* compatibility defines. */
-#define S3C_PA_RTC              S5PC100_PA_RTC
+/* compatibiltiy defines. */
 #define S3C_PA_UART             S5PC100_PA_UART
-#define S3C_PA_UART0            (S5PC100_PA_UART + 0x0)
-#define S3C_PA_UART1            (S5PC100_PA_UART + 0x400)
-#define S3C_PA_UART2            (S5PC100_PA_UART + 0x800)
-#define S3C_PA_UART3            (S5PC100_PA_UART + 0xC00)
-#define S3C_VA_UART0            (S3C_VA_UART + 0x0)
-#define S3C_VA_UART1            (S3C_VA_UART + 0x400)
-#define S3C_VA_UART2            (S3C_VA_UART + 0x800)
-#define S3C_VA_UART3            (S3C_VA_UART + 0xC00)
-#define S3C_UART_OFFSET         0x400
-#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S3C_PA_IIC              S5PC100_PA_IIC0
+#define S3C_PA_IIC1             S5PC100_PA_IIC1
 #define S3C_PA_FB               S5PC100_PA_FB
 #define S3C_PA_G2D              S5PC100_PA_G2D
 #define S3C_PA_G3D              S5PC100_PA_G3D
 #define S3C_PA_JPEG             S5PC100_PA_JPEG
 #define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
-#define S3C_VA_VIC0             (S3C_VA_IRQ + 0x0)
-#define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
-#define S3C_VA_VIC2             (S3C_VA_IRQ + 0x20000)
-#define S3C_PA_IIC              S5PC100_PA_I2C
-#define S3C_PA_IIC1             S5PC100_PA_I2C1
+#define S5P_VA_VIC0             S5PC1XX_VA_VIC(0)
+#define S5P_VA_VIC1             S5PC1XX_VA_VIC(1)
+#define S5P_VA_VIC2             S5PC1XX_VA_VIC(2)
 #define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
 #define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
-#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC0
-#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC1
-#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC2
+#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC(0)
+#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC(1)
+#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC(2)
 #define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
 #define S3C_PA_TSADC            S5PC100_PA_TSADC
+#define S3C_PA_ONENAND          S5PC100_PA_ONENAND
+#define S3C_PA_ONENAND_BUF      S5PC100_PA_ONENAND_BUF
+#define S3C_SZ_ONENAND_BUF      S5PC100_SZ_ONENAND_BUF
 
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
index f2283bdc941e..5d27d286d504 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
@@ -17,6 +17,8 @@
 
 #define S5P_CLKREG(x)           (S3C_VA_SYS + (x))
 
+#define S5PC100_REG_OTHERS(x)   (S5PC100_VA_OTHERS + (x))
+
 #define S5P_APLL_LOCK           S5P_CLKREG(0x00)
 #define S5P_MPLL_LOCK           S5P_CLKREG(0x04)
 #define S5P_EPLL_LOCK           S5P_CLKREG(0x08)
@@ -68,4 +70,8 @@
 #define S5P_CLKDIV1_PCLKD1_MASK         (0x7<<16)
 #define S5P_CLKDIV1_PCLKD1_SHIFT        (16)
 
+#define S5PC100_SWRESET         S5PC100_REG_OTHERS(0x000)
+
+#define S5PC100_SWRESET_RESETVAL        0xc100
+
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index 68666913354c..763edebdd577 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
@@ -12,7 +12,7 @@
 #include <mach/map.h>
 
 /* S5PC100 */
-#define S5PC100_GPIO_BASE       S5PC1XX_VA_GPIO
+#define S5PC100_GPIO_BASE       S5P_VA_GPIO
 #define S5PC100_GPA0_BASE       (S5PC100_GPIO_BASE + 0x0000)
 #define S5PC100_GPA1_BASE       (S5PC100_GPIO_BASE + 0x0020)
 #define S5PC100_GPB_BASE        (S5PC100_GPIO_BASE + 0x0040)
@@ -47,24 +47,32 @@
 #define S5PC100_GPL2_BASE       (S5PC100_GPIO_BASE + 0x0360)
 #define S5PC100_GPL3_BASE       (S5PC100_GPIO_BASE + 0x0380)
 #define S5PC100_GPL4_BASE       (S5PC100_GPIO_BASE + 0x03A0)
-#define S5PC100_EINT_BASE       (S5PC100_GPIO_BASE + 0x0E00)
 
-#define S5PC100_UHOST           (S5PC100_GPIO_BASE + 0x0B68)
-#define S5PC100_PDNEN           (S5PC100_GPIO_BASE + 0x0F80)
+#define S5PC100EINT30CON                (S5P_VA_GPIO + 0xE00)
+#define S5P_EINT_CON(x)                 (S5PC100EINT30CON + ((x) * 0x4))
 
-/* PDNEN */
-#define S5PC100_PDNEN_CFG_PDNEN (1 << 1)
-#define S5PC100_PDNEN_CFG_AUTO  (0 << 1)
-#define S5PC100_PDNEN_POWERDOWN (1 << 0)
-#define S5PC100_PDNEN_NORMAL    (0 << 0)
+#define S5PC100EINT30FLTCON0            (S5P_VA_GPIO + 0xE80)
+#define S5P_EINT_FLTCON(x)              (S5PC100EINT30FLTCON0 + ((x) * 0x4))
 
-/* Common part */
-/* External interrupt base is same at both s5pc100 and s5pc110 */
-#define S5PC1XX_EINT_BASE       (S5PC100_EINT_BASE)
+#define S5PC100EINT30MASK               (S5P_VA_GPIO + 0xF00)
+#define S5P_EINT_MASK(x)                (S5PC100EINT30MASK + ((x) * 0x4))
 
-#define S5PC100_GPx_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
-#define S5PC100_GPx_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
-#define S5PC100_GPx_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#define S5PC100EINT30PEND               (S5P_VA_GPIO + 0xF40)
+#define S5P_EINT_PEND(x)                (S5PC100EINT30PEND + ((x) * 0x4))
+
+#define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) : \
+                          (((irq) - S5P_EINT_BASE2)))
+
+#define EINT_REG_NR(x)                  (eint_offset(x) >> 3)
+
+#define eint_irq_to_bit(irq)            (1 << (eint_offset(irq) & 0x7))
+
+/* values for S5P_EXTINT0 */
+#define S5P_EXTINT_LOWLEV               (0x00)
+#define S5P_EXTINT_HILEV                (0x01)
+#define S5P_EXTINT_FALLEDGE             (0x02)
+#define S5P_EXTINT_RISEEDGE             (0x03)
+#define S5P_EXTINT_BOTHEDGE             (0x04)
 
 #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
 
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
index 751ac15438c8..4d9036d0f288 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX - IRQ register definitions
+ * S5PC100 - IRQ register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -16,9 +16,4 @@
 #include <mach/map.h>
 #include <asm/hardware/vic.h>
 
-/* interrupt controller */
-#define S5PC1XX_VIC0REG(x)                      ((x) + S5PC1XX_VA_VIC(0))
-#define S5PC1XX_VIC1REG(x)                      ((x) + S5PC1XX_VA_VIC(1))
-#define S5PC1XX_VIC2REG(x)                      ((x) + S5PC1XX_VA_VIC(2))
-
 #endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..65e426370bb2
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S5PC100_PLAT_SPI_CLKS_H
+#define __S5PC100_PLAT_SPI_CLKS_H __FILE__
+
+#define S5PC100_SPI_SRCCLK_PCLK         0
+#define S5PC100_SPI_SRCCLK_48M          1
+#define S5PC100_SPI_SRCCLK_SPIBUS       2
+
+#endif /* __S5PC100_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index f0d31a2a598c..681f626a9ae1 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX - system implementation
+ * S5PC100 - system implementation
  *
  * Based on mach-s3c6400/include/mach/system.h
  */
@@ -13,14 +13,11 @@
 
 #include <linux/io.h>
 #include <mach/map.h>
-#include <plat/regs-clock.h>
-
-void (*s5pc1xx_idle)(void);
+#include <mach/regs-clock.h>
 
 static void arch_idle(void)
 {
-        if (s5pc1xx_idle)
-                s5pc1xx_idle();
+        /* nothing here yet */
 }
 
 static void arch_reset(char mode, const char *cmd)
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
index f338c9eec717..20f68730ed18 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -20,8 +20,8 @@
  */
 static inline u32 s3c24xx_ostimer_pending(void)
 {
-        u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
-        return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0));
+        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
+        return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
 }
 
 #define TICK_MAX        (0xffffffff)
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/mach-s5pc100/init.c
index c58710884ceb..19d7b523c137 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-init.c
+++ b/arch/arm/mach-s5pc100/init.c
@@ -1,9 +1,8 @@
-/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c
+/* linux/arch/arm/plat-s5pc100/s5pc100-init.c
  *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC100 - CPU initialisation (common with other S5PC1XX chips)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,9 +18,7 @@
 #include <plat/s5pc100.h>
 
 /* uart registration process */
-
 void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
-        /* The driver name is s3c6400-uart to reuse s3c6400_serial_drv  */
-        s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no);
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c
index fecca7a679b0..2bf86c18bc73 100644
--- a/arch/arm/plat-s5pc1xx/irq-gpio.c
+++ b/arch/arm/mach-s5pc100/irq-gpio.c
@@ -1,9 +1,9 @@
 /*
- * arch/arm/plat-s5pc1xx/irq-gpio.c
+ * arch/arm/mach-s5pc100/irq-gpio.c
  *
  * Copyright (C) 2009 Samsung Electronics
  *
- * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x)
+ * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,7 @@
 #include <mach/map.h>
 #include <plat/gpio-cfg.h>
 
-#define S5PC1XX_GPIOREG(x)              (S5PC1XX_VA_GPIO + (x))
+#define S5P_GPIOREG(x)          (S5P_VA_GPIO + (x))
 
 #define CON_OFFSET                      0x700
 #define MASK_OFFSET                     0x900
@@ -49,7 +49,7 @@ static int group_to_pend_offset(int group)
         return group << 2;
 }
 
-static int s5pc1xx_get_start(unsigned int group)
+static int s5pc100_get_start(unsigned int group)
 {
         switch (group) {
         case 0: return S5PC100_GPIO_A0_START;
@@ -80,7 +80,7 @@ static int s5pc1xx_get_start(unsigned int group)
         return -EINVAL;
 }
 
-static int s5pc1xx_get_group(unsigned int irq)
+static int s5pc100_get_group(unsigned int irq)
 {
         irq -= S3C_IRQ_GPIO(0);
 
@@ -134,67 +134,67 @@ static int s5pc1xx_get_group(unsigned int irq)
         return -EINVAL;
 }
 
-static int s5pc1xx_get_offset(unsigned int irq)
+static int s5pc100_get_offset(unsigned int irq)
 {
         struct gpio_chip *chip = get_irq_data(irq);
         return irq - S3C_IRQ_GPIO(chip->base);
 }
 
-static void s5pc1xx_gpioint_ack(unsigned int irq)
+static void s5pc100_gpioint_ack(unsigned int irq)
 {
         int group, offset, pend_offset;
         unsigned int value;
 
-        group = s5pc1xx_get_group(irq);
-        offset = s5pc1xx_get_offset(irq);
+        group = s5pc100_get_group(irq);
+        offset = s5pc100_get_offset(irq);
         pend_offset = group_to_pend_offset(group);
 
-        value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+        value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
         value |= 1 << offset;
-        __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+        __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
 }
 
-static void s5pc1xx_gpioint_mask(unsigned int irq)
+static void s5pc100_gpioint_mask(unsigned int irq)
 {
         int group, offset, mask_offset;
         unsigned int value;
 
-        group = s5pc1xx_get_group(irq);
-        offset = s5pc1xx_get_offset(irq);
+        group = s5pc100_get_group(irq);
+        offset = s5pc100_get_offset(irq);
         mask_offset = group_to_mask_offset(group);
 
-        value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+        value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
         value |= 1 << offset;
-        __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+        __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
 }
 
-static void s5pc1xx_gpioint_unmask(unsigned int irq)
+static void s5pc100_gpioint_unmask(unsigned int irq)
 {
         int group, offset, mask_offset;
         unsigned int value;
 
-        group = s5pc1xx_get_group(irq);
-        offset = s5pc1xx_get_offset(irq);
+        group = s5pc100_get_group(irq);
+        offset = s5pc100_get_offset(irq);
         mask_offset = group_to_mask_offset(group);
 
-        value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+        value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
         value &= ~(1 << offset);
-        __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+        __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
 }
 
-static void s5pc1xx_gpioint_mask_ack(unsigned int irq)
+static void s5pc100_gpioint_mask_ack(unsigned int irq)
 {
-        s5pc1xx_gpioint_mask(irq);
-        s5pc1xx_gpioint_ack(irq);
+        s5pc100_gpioint_mask(irq);
+        s5pc100_gpioint_ack(irq);
 }
 
-static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type)
+static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
 {
         int group, offset, con_offset;
         unsigned int value;
 
-        group = s5pc1xx_get_group(irq);
-        offset = s5pc1xx_get_offset(irq);
+        group = s5pc100_get_group(irq);
+        offset = s5pc100_get_offset(irq);
         con_offset = group_to_con_offset(group);
 
         switch (type) {
@@ -221,24 +221,24 @@ static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type)
         }
 
 
-        value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
+        value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
         value &= ~(0xf << (offset * 0x4));
         value |= (type << (offset * 0x4));
-        __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
+        __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
 
         return 0;
 }
 
-struct irq_chip s5pc1xx_gpioint = {
+struct irq_chip s5pc100_gpioint = {
         .name           = "GPIO",
-        .ack            = s5pc1xx_gpioint_ack,
-        .mask           = s5pc1xx_gpioint_mask,
-        .mask_ack       = s5pc1xx_gpioint_mask_ack,
-        .unmask         = s5pc1xx_gpioint_unmask,
-        .set_type       = s5pc1xx_gpioint_set_type,
+        .ack            = s5pc100_gpioint_ack,
+        .mask           = s5pc100_gpioint_mask,
+        .mask_ack       = s5pc100_gpioint_mask_ack,
+        .unmask         = s5pc100_gpioint_unmask,
+        .set_type       = s5pc100_gpioint_set_type,
 };
 
-void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 {
         int group, offset, pend_offset, mask_offset;
         int real_irq, group_end;
@@ -248,17 +248,17 @@ void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 
         for (group = 0; group < group_end; group++) {
                 pend_offset = group_to_pend_offset(group);
-                pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+                pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
                 if (!pend)
                         continue;
 
                 mask_offset = group_to_mask_offset(group);
-                mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+                mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
                 pend &= ~mask;
 
                 for (offset = 0; offset < 8; offset++) {
                         if (pend & (1 << offset)) {
-                                real_irq = s5pc1xx_get_start(group) + offset;
+                                real_irq = s5pc100_get_start(group) + offset;
                                 generic_handle_irq(S3C_IRQ_GPIO(real_irq));
                         }
                 }
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index bfe67db34f04..af22f8202a07 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -43,38 +43,48 @@
 #include <plat/fb.h>
 #include <plat/iic.h>
 
-#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
-#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
-#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define S5PC100_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define S5PC100_ULCON_DEFAULT   S3C2410_LCON_CS8
+
+#define S5PC100_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
+                                 S3C2440_UFCON_RXTRIG8 |        \
+                                 S3C2440_UFCON_TXTRIG16)
 
 static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
         [0] = {
                 .hwport      = 0,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = S5PC100_UCON_DEFAULT,
+                .ulcon       = S5PC100_ULCON_DEFAULT,
+                .ufcon       = S5PC100_UFCON_DEFAULT,
         },
         [1] = {
                 .hwport      = 1,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = S5PC100_UCON_DEFAULT,
+                .ulcon       = S5PC100_ULCON_DEFAULT,
+                .ufcon       = S5PC100_UFCON_DEFAULT,
         },
         [2] = {
                 .hwport      = 2,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = S5PC100_UCON_DEFAULT,
+                .ulcon       = S5PC100_ULCON_DEFAULT,
+                .ufcon       = S5PC100_UFCON_DEFAULT,
         },
         [3] = {
                 .hwport      = 3,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = S5PC100_UCON_DEFAULT,
+                .ulcon       = S5PC100_ULCON_DEFAULT,
+                .ufcon       = S5PC100_UFCON_DEFAULT,
         },
 };
 
@@ -118,8 +128,7 @@ static struct platform_device smdkc100_lcd_powerdev = {
 static struct s3c_fb_pd_win smdkc100_fb_win0 = {
         /* this is to ensure we use win0 */
         .win_mode       = {
-                .refresh        = 70,
-                .pixclock       = (8+13+3+800)*(7+5+1+480),
+                .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80),
                 .left_margin    = 8,
                 .right_margin   = 13,
                 .upper_margin   = 7,
@@ -140,8 +149,6 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
         .setup_gpio     = s5pc100_fb_gpio_setup_24bpp,
 };
 
-static struct map_desc smdkc100_iodesc[] = {};
-
 static struct platform_device *smdkc100_devices[] __initdata = {
         &s3c_device_i2c0,
         &s3c_device_i2c1,
@@ -150,11 +157,13 @@ static struct platform_device *smdkc100_devices[] __initdata = {
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
         &smdkc100_lcd_powerdev,
+        &s5pc100_device_iis0,
+        &s5pc100_device_ac97,
 };
 
 static void __init smdkc100_map_io(void)
 {
-        s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc));
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
 }
@@ -178,10 +187,9 @@ static void __init smdkc100_machine_init(void)
 
 MACHINE_START(SMDKC100, "SMDKC100")
         /* Maintainer: Byungho Min <bhmin@samsung.com> */
-        .phys_io        = S5PC100_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
-        .boot_params    = S5PC100_PA_SDRAM + 0x100,
-
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
         .init_machine   = smdkc100_machine_init,
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
index 185c8941e644..7769c760c9ef 100644
--- a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -1,8 +1,8 @@
-/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
+/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c
  *
  * Copyright 2009 Samsung Eletronics
  *
- * S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 7601c28e240b..0761eac9aaea 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -13,18 +13,68 @@ config CPU_S5PV210
         bool
         select PLAT_S5P
         select S3C_PL330_DMA
+        select S5P_EXT_INT
         help
           Enable S5PV210 CPU support
 
-choice
-        prompt "Select machine type"
-        depends on ARCH_S5PV210
-        default MACH_SMDKV210
+config S5PV210_SETUP_I2C1
+        bool
+        help
+          Common setup code for i2c bus 1.
+
+config S5PV210_SETUP_I2C2
+        bool
+        help
+          Common setup code for i2c bus 2.
+
+config S5PV210_SETUP_FB_24BPP
+        bool
+        help
+          Common setup code for S5PV210 with an 24bpp RGB display helper.
+
+config S5PV210_SETUP_SDHCI
+        bool
+        select S5PV210_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S5PV210 based SDHCI systems
+
+config S5PV210_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
+# machine support
+
+config MACH_AQUILA
+        bool "Samsung Aquila"
+        select CPU_S5PV210
+        select ARCH_SPARSEMEM_ENABLE
+        select S5PV210_SETUP_FB_24BPP
+        select S3C_DEV_FB
+        help
+          Machine support for the Samsung Aquila target based on S5PC110 SoC
+
+config MACH_GONI
+        bool "GONI"
+        select CPU_S5PV210
+        select ARCH_SPARSEMEM_ENABLE
+        help
+          Machine support for Samsung GONI board
+          S5PC110(MCP) is one of package option of S5PV210
+
+config S5PC110_DEV_ONENAND
+        bool
+        help
+          Compile in platform device definition for OneNAND1 controller
 
 config MACH_SMDKV210
         bool "SMDKV210"
         select CPU_S5PV210
         select ARCH_SPARSEMEM_ENABLE
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select S3C_DEV_WDT
+        select HAVE_S3C2410_WATCHDOG
         help
           Machine support for Samsung SMDKV210
 
@@ -32,10 +82,10 @@ config MACH_SMDKC110
         bool "SMDKC110"
         select CPU_S5PV210
         select ARCH_SPARSEMEM_ENABLE
+        select S3C_DEV_WDT
+        select HAVE_S3C2410_WATCHDOG
         help
           Machine support for Samsung SMDKC110
           S5PC110(MCP) is one of package option of S5PV210
 
-endchoice
-
 endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 99827813d293..30be9a6a4620 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -17,9 +17,19 @@ obj-$(CONFIG_CPU_S5PV210)	+= setup-i2c0.o
 
 # machine support
 
+obj-$(CONFIG_MACH_AQUILA)       += mach-aquila.o
 obj-$(CONFIG_MACH_SMDKV210)     += mach-smdkv210.o
 obj-$(CONFIG_MACH_SMDKC110)     += mach-smdkc110.o
+obj-$(CONFIG_MACH_GONI)         += mach-goni.o
 
 # device support
 
 obj-y                           += dev-audio.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
+obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
+
+obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)    += setup-fb-24bpp.o
+obj-$(CONFIG_S5PV210_SETUP_I2C1)        += setup-i2c1.o
+obj-$(CONFIG_S5PV210_SETUP_I2C2)        += setup-i2c2.o
+obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 2b776eb5d150..411a4a9cbfc7 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -32,6 +32,8 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 #include <plat/s5pv210.h>
+#include <plat/iic-core.h>
+#include <plat/sdhci.h>
 
 /* Initial IO mappings */
 
@@ -74,7 +76,21 @@ static void s5pv210_idle(void)
 
 void __init s5pv210_map_io(void)
 {
+#ifdef CONFIG_S3C_DEV_ADC
+        s3c_device_adc.name     = "s3c64xx-adc";
+#endif
+
         iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
+
+        /* initialise device information early */
+        s5pv210_default_sdhci0();
+        s5pv210_default_sdhci1();
+        s5pv210_default_sdhci2();
+
+        /* the i2c devices are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
+        s3c_i2c2_setname("s3c2440-i2c");
 }
 
 void __init s5pv210_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/mach-s5pv210/dev-onenand.c
new file mode 100644
index 000000000000..34997b752f93
--- /dev/null
+++ b/arch/arm/mach-s5pv210/dev-onenand.c
@@ -0,0 +1,50 @@
+/*
+ * linux/arch/arm/mach-s5pv210/dev-onenand.c
+ *
+ *  Copyright (c) 2008-2010 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S5PC110 series device definition for OneNAND devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+static struct resource s5pc110_onenand_resources[] = {
+        [0] = {
+                .start  = S5PC110_PA_ONENAND,
+                .end    = S5PC110_PA_ONENAND + SZ_128K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = S5PC110_PA_ONENAND_DMA,
+                .end    = S5PC110_PA_ONENAND_DMA + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device s5pc110_device_onenand = {
+        .name           = "s5pc110-onenand",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5pc110_onenand_resources),
+        .resource       = s5pc110_onenand_resources,
+};
+
+void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata)
+{
+        struct onenand_platform_data *pd;
+
+        pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
+        if (!pd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        s5pc110_device_onenand.dev.platform_data = pd;
+}
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
new file mode 100644
index 000000000000..337a62b57a0b
--- /dev/null
+++ b/arch/arm/mach-s5pv210/dev-spi.c
@@ -0,0 +1,178 @@
+/* linux/arch/arm/mach-s5pv210/dev-spi.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/spi-clocks.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+
+static char *spi_src_clks[] = {
+        [S5PV210_SPI_SRCCLK_PCLK] = "pclk",
+        [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PV210_GPB(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PV210_GPB(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PV210_GPB(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PV210_GPB(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PV210_GPB(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PV210_GPB(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PV210_GPB(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PV210_GPB(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s5pv210_spi0_resource[] = {
+        [0] = {
+                .start = S5PV210_PA_SPI0,
+                .end   = S5PV210_PA_SPI0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI0_TX,
+                .end   = DMACH_SPI0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI0_RX,
+                .end   = DMACH_SPI0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
+        .cfg_gpio = s5pv210_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x1ff,
+        .rx_lvl_offset = 15,
+        .high_speed = 1,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pv210_device_spi0 = {
+        .name             = "s3c64xx-spi",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5pv210_spi0_resource),
+        .resource         = s5pv210_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5pv210_spi0_pdata,
+        },
+};
+
+static struct resource s5pv210_spi1_resource[] = {
+        [0] = {
+                .start = S5PV210_PA_SPI1,
+                .end   = S5PV210_PA_SPI1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI1_TX,
+                .end   = DMACH_SPI1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI1_RX,
+                .end   = DMACH_SPI1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
+        .cfg_gpio = s5pv210_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 15,
+        .high_speed = 1,
+};
+
+struct platform_device s5pv210_device_spi1 = {
+        .name             = "s3c64xx-spi",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5pv210_spi1_resource),
+        .resource         = s5pv210_spi1_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5pv210_spi1_pdata,
+        },
+};
+
+void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        struct s3c64xx_spi_info *pd;
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                pd = &s5pv210_spi0_pdata;
+                break;
+        case 1:
+                pd = &s5pv210_spi1_pdata;
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        pd->src_clk_name = spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 62c5175ef291..92fc6c7fc064 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -17,22 +17,6 @@
 
 /* VIC0: System, DMA, Timer */
 
-#define IRQ_EINT0               S5P_IRQ_VIC0(0)
-#define IRQ_EINT1               S5P_IRQ_VIC0(1)
-#define IRQ_EINT2               S5P_IRQ_VIC0(2)
-#define IRQ_EINT3               S5P_IRQ_VIC0(3)
-#define IRQ_EINT4               S5P_IRQ_VIC0(4)
-#define IRQ_EINT5               S5P_IRQ_VIC0(5)
-#define IRQ_EINT6               S5P_IRQ_VIC0(6)
-#define IRQ_EINT7               S5P_IRQ_VIC0(7)
-#define IRQ_EINT8               S5P_IRQ_VIC0(8)
-#define IRQ_EINT9               S5P_IRQ_VIC0(9)
-#define IRQ_EINT10              S5P_IRQ_VIC0(10)
-#define IRQ_EINT11              S5P_IRQ_VIC0(11)
-#define IRQ_EINT12              S5P_IRQ_VIC0(12)
-#define IRQ_EINT13              S5P_IRQ_VIC0(13)
-#define IRQ_EINT14              S5P_IRQ_VIC0(14)
-#define IRQ_EINT15              S5P_IRQ_VIC0(15)
 #define IRQ_EINT16_31           S5P_IRQ_VIC0(16)
 #define IRQ_BATF                S5P_IRQ_VIC0(17)
 #define IRQ_MDMA                S5P_IRQ_VIC0(18)
@@ -134,13 +118,25 @@
 #define IRQ_MDNIE3              S5P_IRQ_VIC3(8)
 #define IRQ_VIC_END             S5P_IRQ_VIC3(31)
 
-#define S5P_IRQ_EINT_BASE       (IRQ_VIC_END + 1)
+#define S5P_EINT_16_31_BASE     (IRQ_VIC_END + 1)
 
-#define S5P_EINT(x)             ((x) + S5P_IRQ_EINT_BASE)
-#define IRQ_EINT(x)             S5P_EINT(x)
+#define EINT_MODE               S3C_GPIO_SFN(0xf)
+
+#define IRQ_EINT(x)             ((x) < 16 ? ((x) + S5P_IRQ_VIC0(0)) \
+                                        : ((x) + S5P_EINT_16_31_BASE))
 
 /* Set the default NR_IRQS */
 
-#define NR_IRQS                 (IRQ_EINT(31) + 1)
+#define NR_IRQS                 (IRQ_EINT(31) + 1)
+
+#define EINT_GPIO_0(x)          S5PV210_GPH0(x)
+#define EINT_GPIO_1(x)          S5PV210_GPH1(x)
+#define EINT_GPIO_2(x)          S5PV210_GPH2(x)
+#define EINT_GPIO_3(x)          S5PV210_GPH3(x)
+
+/* Compatibility */
+#define IRQ_LCD_FIFO            IRQ_LCD0
+#define IRQ_LCD_VSYNC           IRQ_LCD1
+#define IRQ_LCD_SYSTEM          IRQ_LCD2
 
 #endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 5adcb9f26e44..34eb168ec950 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -16,6 +16,9 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
+#define S5PC110_PA_ONENAND      (0xB0000000)
+#define S5PC110_PA_ONENAND_DMA  (0xB0600000)
+
 #define S5PV210_PA_CHIPID       (0xE0000000)
 #define S5P_PA_CHIPID           S5PV210_PA_CHIPID
 
@@ -25,13 +28,21 @@
 #define S5PV210_PA_GPIO         (0xE0200000)
 #define S5P_PA_GPIO             S5PV210_PA_GPIO
 
+/* SPI */
+#define S5PV210_PA_SPI0         0xE1300000
+#define S5PV210_PA_SPI1         0xE1400000
+
 #define S5PV210_PA_IIC0         (0xE1800000)
+#define S5PV210_PA_IIC1         (0xFAB00000)
+#define S5PV210_PA_IIC2         (0xE1A00000)
 
 #define S5PV210_PA_TIMER        (0xE2500000)
 #define S5P_PA_TIMER            S5PV210_PA_TIMER
 
 #define S5PV210_PA_SYSTIMER     (0xE2600000)
 
+#define S5PV210_PA_WATCHDOG     (0xE2700000)
+
 #define S5PV210_PA_UART         (0xE2900000)
 
 #define S5P_PA_UART0            (S5PV210_PA_UART + 0x0)
@@ -47,6 +58,10 @@
 #define S5PV210_PA_PDMA0        0xE0900000
 #define S5PV210_PA_PDMA1        0xE0A00000
 
+#define S5PV210_PA_FB           (0xF8000000)
+
+#define S5PV210_PA_HSMMC(x)     (0xEB000000 + ((x) * 0x100000))
+
 #define S5PV210_PA_VIC0         (0xF2000000)
 #define S5P_PA_VIC0             S5PV210_PA_VIC0
 
@@ -75,8 +90,19 @@
 /* AC97 */
 #define S5PV210_PA_AC97         0xE2200000
 
+#define S5PV210_PA_ADC          (0xE1700000)
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART             S5PV210_PA_UART
+#define S3C_PA_HSMMC0           S5PV210_PA_HSMMC(0)
+#define S3C_PA_HSMMC1           S5PV210_PA_HSMMC(1)
+#define S3C_PA_HSMMC2           S5PV210_PA_HSMMC(2)
 #define S3C_PA_IIC              S5PV210_PA_IIC0
+#define S3C_PA_IIC1             S5PV210_PA_IIC1
+#define S3C_PA_IIC2             S5PV210_PA_IIC2
+#define S3C_PA_FB               S5PV210_PA_FB
+#define S3C_PA_WDT              S5PV210_PA_WATCHDOG
+
+#define SAMSUNG_PA_ADC          S5PV210_PA_ADC
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index e56e0e4673ed..2a25ab40c863 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -126,6 +126,7 @@
 
 #define S5P_RST_STAT            S5P_CLKREG(0xA000)
 #define S5P_OSC_CON             S5P_CLKREG(0x8000)
+#define S5P_MDNIE_SEL           S5P_CLKREG(0x7008)
 #define S5P_MIPI_PHY_CON0       S5P_CLKREG(0x7200)
 #define S5P_MIPI_PHY_CON1       S5P_CLKREG(0x7204)
 #define S5P_MIPI_CONTROL        S5P_CLKREG(0xE814)
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h
new file mode 100644
index 000000000000..60d992989bdc
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/regs-fb.h
@@ -0,0 +1,21 @@
+/* 
+ * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * Dummy framebuffer to allow build for the moment.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MACH_REGS_FB_H
+#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
+
+#include <plat/regs-fb-v4.h>
+
+static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
+{
+        return 0x2400 + (window * 256 *4 ) + reg;
+}
+
+#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..6d068091c36c
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
@@ -0,0 +1,44 @@
+/* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV210 - GPIO (including EINT) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+
+#define S5PV210_EINT30CON               (S5P_VA_GPIO + 0xE00)
+#define S5P_EINT_CON(x)                 (S5PV210_EINT30CON + ((x) * 0x4))
+
+#define S5PV210_EINT30FLTCON0           (S5P_VA_GPIO + 0xE80)
+#define S5P_EINT_FLTCON(x)              (S5PV210_EINT30FLTCON0 + ((x) * 0x4))
+
+#define S5PV210_EINT30MASK              (S5P_VA_GPIO + 0xF00)
+#define S5P_EINT_MASK(x)                (S5PV210_EINT30MASK + ((x) * 0x4))
+
+#define S5PV210_EINT30PEND              (S5P_VA_GPIO + 0xF40)
+#define S5P_EINT_PEND(x)                (S5PV210_EINT30PEND + ((x) * 0x4))
+
+#define eint_offset(irq)        ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) \
+                                                : ((irq) - S5P_EINT_16_31_BASE))
+
+#define EINT_REG_NR(x)                  (eint_offset(x) >> 3)
+
+#define eint_irq_to_bit(irq)            (1 << (eint_offset(irq) & 0x7))
+
+/* values for S5P_EXTINT0 */
+#define S5P_EXTINT_LOWLEV               (0x00)
+#define S5P_EXTINT_HILEV                (0x01)
+#define S5P_EXTINT_FALLEDGE             (0x02)
+#define S5P_EXTINT_RISEEDGE             (0x03)
+#define S5P_EXTINT_BOTHEDGE             (0x04)
+
+#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..02acded5f73d
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S5PV210_PLAT_SPI_CLKS_H
+#define __S5PV210_PLAT_SPI_CLKS_H __FILE__
+
+#define S5PV210_SPI_SRCCLK_PCLK         0
+#define S5PV210_SPI_SRCCLK_SCLK         1
+
+#endif /* __S5PV210_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
new file mode 100644
index 000000000000..10bc76ec4025
--- /dev/null
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -0,0 +1,149 @@
+/* linux/arch/arm/mach-s5pv210/mach-aquila.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/fb.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-fb.h>
+
+#include <plat/regs-serial.h>
+#include <plat/s5pv210.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/fb.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define S5PV210_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define S5PV210_ULCON_DEFAULT   S3C2410_LCON_CS8
+
+#define S5PV210_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = S5PV210_UCON_DEFAULT,
+                .ulcon          = S5PV210_ULCON_DEFAULT,
+                .ufcon          = S5PV210_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = S5PV210_UCON_DEFAULT,
+                .ulcon          = S5PV210_ULCON_DEFAULT,
+                .ufcon          = S5PV210_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = S5PV210_UCON_DEFAULT,
+                .ulcon          = S5PV210_ULCON_DEFAULT,
+                .ufcon          = S5PV210_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = S5PV210_UCON_DEFAULT,
+                .ulcon          = S5PV210_ULCON_DEFAULT,
+                .ufcon          = S5PV210_UFCON_DEFAULT,
+        },
+};
+
+/* Frame Buffer */
+static struct s3c_fb_pd_win aquila_fb_win0 = {
+        .win_mode = {
+                .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60),
+                .left_margin = 16,
+                .right_margin = 16,
+                .upper_margin = 3,
+                .lower_margin = 28,
+                .hsync_len = 2,
+                .vsync_len = 2,
+                .xres = 480,
+                .yres = 800,
+        },
+        .max_bpp = 32,
+        .default_bpp = 16,
+};
+
+static struct s3c_fb_pd_win aquila_fb_win1 = {
+        .win_mode = {
+                .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60),
+                .left_margin = 16,
+                .right_margin = 16,
+                .upper_margin = 3,
+                .lower_margin = 28,
+                .hsync_len = 2,
+                .vsync_len = 2,
+                .xres = 480,
+                .yres = 800,
+        },
+        .max_bpp = 32,
+        .default_bpp = 16,
+};
+
+static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
+        .win[0]         = &aquila_fb_win0,
+        .win[1]         = &aquila_fb_win1,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
+                          VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
+        .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
+};
+
+static struct platform_device *aquila_devices[] __initdata = {
+        &s3c_device_fb,
+};
+
+static void __init aquila_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
+}
+
+static void __init aquila_machine_init(void)
+{
+        /* FB */
+        s3c_fb_set_platdata(&aquila_lcd_pdata);
+
+        platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices));
+}
+
+MACHINE_START(AQUILA, "Aquila")
+        /* Maintainers:
+           Marek Szyprowski <m.szyprowski@samsung.com>
+           Kyungmin Park <kyungmin.park@samsung.com> */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .init_irq       = s5pv210_init_irq,
+        .map_io         = aquila_map_io,
+        .init_machine   = aquila_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
new file mode 100644
index 000000000000..4863b13824e4
--- /dev/null
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -0,0 +1,98 @@
+/* linux/arch/arm/mach-s5pv210/mach-goni.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/regs-serial.h>
+#include <plat/s5pv210.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define S5PV210_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define S5PV210_ULCON_DEFAULT   S3C2410_LCON_CS8
+
+#define S5PV210_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = S5PV210_UCON_DEFAULT,
+                .ulcon          = S5PV210_ULCON_DEFAULT,
+                .ufcon          = S5PV210_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = S5PV210_UCON_DEFAULT,
+                .ulcon          = S5PV210_ULCON_DEFAULT,
+                .ufcon          = S5PV210_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = S5PV210_UCON_DEFAULT,
+                .ulcon          = S5PV210_ULCON_DEFAULT,
+                .ufcon          = S5PV210_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = S5PV210_UCON_DEFAULT,
+                .ulcon          = S5PV210_ULCON_DEFAULT,
+                .ufcon          = S5PV210_UFCON_DEFAULT,
+        },
+};
+
+static struct platform_device *goni_devices[] __initdata = {
+};
+
+static void __init goni_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
+}
+
+static void __init goni_machine_init(void)
+{
+        platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
+}
+
+MACHINE_START(GONI, "GONI")
+        /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .init_irq       = s5pv210_init_irq,
+        .map_io         = goni_map_io,
+        .init_machine   = goni_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 6f9fd3274e2e..4c8903c6d104 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -74,6 +74,7 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 static struct platform_device *smdkc110_devices[] __initdata = {
         &s5pv210_device_iis0,
         &s5pv210_device_ac97,
+        &s3c_device_wdt,
 };
 
 static void __init smdkc110_map_io(void)
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 3c29e18528a5..0d4627948040 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -25,6 +25,8 @@
 #include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PV210_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
@@ -74,6 +76,15 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 static struct platform_device *smdkv210_devices[] __initdata = {
         &s5pv210_device_iis0,
         &s5pv210_device_ac97,
+        &s3c_device_adc,
+        &s3c_device_ts,
+        &s3c_device_wdt,
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
 };
 
 static void __init smdkv210_map_io(void)
@@ -85,6 +96,7 @@ static void __init smdkv210_map_io(void)
 
 static void __init smdkv210_machine_init(void)
 {
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
         platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
 }
 
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
new file mode 100644
index 000000000000..a50cbac8720d
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
@@ -0,0 +1,62 @@
+/* linux/arch/arm/plat-s5pv210/setup-fb-24bpp.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Base s5pv210 setup information for 24bpp LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+
+#include <mach/regs-fb.h>
+#include <mach/gpio.h>
+#include <mach/map.h>
+#include <plat/fb.h>
+#include <mach/regs-clock.h>
+#include <plat/gpio-cfg.h>
+
+void s5pv210_fb_gpio_setup_24bpp(void)
+{
+        unsigned int gpio = 0;
+
+        for (gpio = S5PV210_GPF0(0); gpio <= S5PV210_GPF0(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        for (gpio = S5PV210_GPF1(0); gpio <= S5PV210_GPF1(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        for (gpio = S5PV210_GPF2(0); gpio <= S5PV210_GPF2(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        for (gpio = S5PV210_GPF3(0); gpio <= S5PV210_GPF3(3); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        /* Set DISPLAY_CONTROL register for Display path selection.
+         *
+         * ouput   |   RGB   |   I80   |   ITU
+         * -----------------------------------
+         *  00     |   MIE   |  FIMD   |  FIMD
+         *  01     | MDNIE   | MDNIE   |  FIMD
+         *  10     |  FIMD   |  FIMD   |  FIMD
+         *  11     |  FIMD   |  FIMD   |  FIMD
+         */
+        writel(0x2, S5P_MDNIE_SEL);
+}
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c
index 9ec6845840e5..c718253c70b8 100644
--- a/arch/arm/mach-s5pv210/setup-i2c0.c
+++ b/arch/arm/mach-s5pv210/setup-i2c0.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5pv210/setup-i2c0.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
  * I2C0 GPIO configuration.
@@ -17,9 +17,14 @@
 
 struct platform_device; /* don't need the contents */
 
+#include <mach/gpio.h>
 #include <plat/iic.h>
+#include <plat/gpio-cfg.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        /* Will be populated later */
+        s3c_gpio_cfgpin(S5PV210_GPD1(0), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPD1(0), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PV210_GPD1(1), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPD1(1), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c
new file mode 100644
index 000000000000..45e0e6ed2ed0
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-i2c1.c
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-s5pv210/setup-i2c1.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * I2C1 GPIO configuration.
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PV210_GPD1(2), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPD1(2), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PV210_GPD1(3), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPD1(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c
new file mode 100644
index 000000000000..b11b4bff69ac
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-i2c2.c
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-s5pv210/setup-i2c2.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * I2C2 GPIO configuration.
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c2_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PV210_GPD1(4), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPD1(4), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PV210_GPD1(5), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPD1(5), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..fe7d86dad14c
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -0,0 +1,104 @@
+/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5PV210 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+
+void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+
+        /* Set all the necessary GPG0/GPG1 pins to special-function 2 */
+        for (gpio = S5PV210_GPG0(0); gpio < S5PV210_GPG0(2); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        switch (width) {
+        case 8:
+                /* GPG1[3:6] special-funtion 3 */
+                for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) {
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                }
+        case 4:
+                /* GPG0[3:6] special-funtion 2 */
+                for (gpio = S5PV210_GPG0(3); gpio <= S5PV210_GPG0(6); gpio++) {
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                }
+        default:
+                break;
+        }
+
+        s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
+}
+
+void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+
+        /* Set all the necessary GPG1[0:1] pins to special-function 2 */
+        for (gpio = S5PV210_GPG1(0); gpio < S5PV210_GPG1(2); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        /* Data pin GPG1[3:6] to special-function 2 */
+        for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
+}
+
+void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+
+        /* Set all the necessary GPG2[0:1] pins to special-function 2 */
+        for (gpio = S5PV210_GPG2(0); gpio < S5PV210_GPG2(2); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        switch (width) {
+        case 8:
+                /* Data pin GPG3[3:6] to special-function 3 */
+                for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                }
+        case 4:
+                /* Data pin GPG2[3:6] to special-function 2 */
+                for (gpio = S5PV210_GPG2(3); gpio <= S5PV210_GPG2(6); gpio++) {
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                }
+        default:
+                break;
+        }
+
+        s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
+}
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
new file mode 100644
index 000000000000..51815ec60c2a
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-sdhci.c
@@ -0,0 +1,63 @@
+/* linux/arch/arm/mach-s5pv210/setup-sdhci.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s5pv210_hsmmc_clksrcs[4] = {
+        [0] = "hsmmc",          /* HCLK */
+        [1] = "hsmmc",          /* HCLK */
+        [2] = "sclk_mmc",       /* mmc_bus */
+        /*[4] = reserved */
+};
+
+void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
+                                    void __iomem *r,
+                                    struct mmc_ios *ios,
+                                    struct mmc_card *card)
+{
+        u32 ctrl2, ctrl3;
+
+        /* don't need to alter anything acording to card-type */
+
+        writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
+
+        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+                  S3C_SDHCI_CTRL2_ENFBCLKRX |
+                  S3C_SDHCI_CTRL2_DFCNT_NONE |
+                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+        if (ios->clock < 25 * 1000000)
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+                         S3C_SDHCI_CTRL3_FCSEL2 |
+                         S3C_SDHCI_CTRL3_FCSEL1 |
+                         S3C_SDHCI_CTRL3_FCSEL0);
+        else
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index cb0b63874482..2a8646173c2f 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -50,7 +51,26 @@
 #define MX35_H1_TLL_BIT         (1 << 5)
 #define MX35_H1_USBTE_BIT       (1 << 4)
 
-int mxc_set_usbcontrol(int port, unsigned int flags)
+#define MXC_OTG_OFFSET          0
+#define MXC_H1_OFFSET           0x200
+
+/* USB_CTRL */
+#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
+
+/* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT                       (1 << 5)        /* UH1 Disable Overcurrent Event */
+
+#define MXC_USBCMD_OFFSET                       0x140
+
+/* USBCMD */
+#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
+
+int mxc_initialize_usb_hw(int port, unsigned int flags)
 {
         unsigned int v;
 #ifdef CONFIG_ARCH_MX3
@@ -186,9 +206,85 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
                 return 0;
         }
 #endif /* CONFIG_MACH_MX27 */
+#ifdef CONFIG_ARCH_MX51
+        if (cpu_is_mx51()) {
+                void __iomem *usb_base;
+                u32 usbotg_base;
+                u32 usbother_base;
+                int ret = 0;
+
+                usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+
+                switch (port) {
+                case 0: /* OTG port */
+                        usbotg_base = usb_base + MXC_OTG_OFFSET;
+                        break;
+                case 1: /* Host 1 port */
+                        usbotg_base = usb_base + MXC_H1_OFFSET;
+                        break;
+                default:
+                        printk(KERN_ERR"%s no such port %d\n", __func__, port);
+                        ret = -ENOENT;
+                        goto error;
+                }
+                usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+                switch (port) {
+                case 0: /*OTG port */
+                        if (flags & MXC_EHCI_INTERNAL_PHY) {
+                                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                        v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
+                                else
+                                        v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
+                                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                                if (flags & MXC_EHCI_WAKEUP_ENABLED)
+                                        v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
+                                else
+                                        v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
+                                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+                        }
+                        break;
+                case 1: /* Host 1 */
+                        /*Host ULPI */
+                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                        if (flags & MXC_EHCI_WAKEUP_ENABLED)
+                                v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
+                        else
+                                v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
+
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                        else
+                                v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+
+                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
+                        else
+                                v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
+                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                        v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
+                        if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
+                                /* Interrupt Threshold Control:Immediate (no threshold) */
+                                v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
+                        __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
+                        break;
+                }
+
+error:
+                iounmap(usb_base);
+                return ret;
+        }
+#endif
         printk(KERN_WARNING
                 "%s() unable to setup USBCONTROL for this CPU\n", __func__);
         return -EINVAL;
 }
-EXPORT_SYMBOL(mxc_set_usbcontrol);
+EXPORT_SYMBOL(mxc_initialize_usb_hw);
 
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 70b23893f094..71437c61cfd7 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -3,7 +3,7 @@
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  *
  * Based on code from Freescale,
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -38,7 +38,6 @@ static int gpio_table_size;
 #define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
 #define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
 #define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
-#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
 
 #define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
 #define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
@@ -289,7 +288,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 /* its a serious configuration bug when it fails */
                 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 
-                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
+                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
                         /* setup one handler for each entry */
                         set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
                         set_irq_data(port[i].irq, &port[i]);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index fc5fec9b55f0..36ff3cedee1a 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -26,6 +26,7 @@ enum mx31moboard_boards {
         MX31DEVBOARD    = 1,
         MX31MARXBOT     = 2,
         MX31SMARTBOT    = 3,
+        MX31EYEBOT      = 4,
 };
 
 /*
@@ -35,7 +36,7 @@ enum mx31moboard_boards {
 
 extern void mx31moboard_devboard_init(void);
 extern void mx31moboard_marxbot_init(void);
-extern void mx31moboard_smartbot_init(void);
+extern void mx31moboard_smartbot_init(int board);
 
 #endif
 
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index e51465d7b224..cbaed295a2bf 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -719,6 +719,23 @@ enum iomux_pins {
 #define MX31_PIN_SRXD5__SRXD5           IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_SCK5__SCK5             IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_SFS5__SFS5             IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW0_KEY_ROW0      IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW1_KEY_ROW1      IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW2_KEY_ROW2      IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW3_KEY_ROW3      IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW4_KEY_ROW4      IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW5_KEY_ROW5      IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW6_KEY_ROW6      IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW7_KEY_ROW7      IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL0_KEY_COL0      IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL1_KEY_COL1      IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL2_KEY_COL2      IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL3_KEY_COL3      IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL4_KEY_COL4      IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL5_KEY_COL5      IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL6_KEY_COL6      IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL7_KEY_COL7      IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
+
 
 /*
  * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index b4f975e6a665..ab0f95d953d0 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -37,6 +38,11 @@ typedef enum iomux_config {
                                 PAD_CTL_SRE_FAST)
 #define MX51_UART3_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
                                 PAD_CTL_SRE_FAST)
+#define MX51_USBH1_PAD_CTRL     (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+                                PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+                                PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_GPIO_PAD_CTRL              (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
+                                PAD_CTL_SRE_FAST)
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -57,6 +63,7 @@ typedef enum iomux_config {
 #define MX51_PAD_GPIO_2_3__EIM_D19      IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_2_4__EIM_D20      IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_2_5__EIM_D21      IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5      IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_2_6__EIM_D22      IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_2_7__EIM_D23      IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
 
@@ -208,18 +215,19 @@ typedef enum iomux_config {
 #define MX51_PAD_KEY_COL3__KEY_COL3     IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_COL4__KEY_COL4     IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_COL5__KEY_COL5     IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_25__USBH1_CLK   IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_26__USBH1_DIR   IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_27__USBH1_STP   IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_28__USBH1_NXT   IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK   IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR   IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP   IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27   IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT   IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_GPIO_3_0__DI1_PIN11    IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_3_1__DI1_PIN12    IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_3_2__DI1_PIN13    IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
@@ -299,7 +307,7 @@ typedef enum iomux_config {
 #define MX51_PAD_GPIO_1_4__GPIO1_4      IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_5__GPIO1_5      IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_6__GPIO1_6      IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7      IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO1_7      IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_8__GPIO1_8      IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
                                                 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
 #define MX51_PAD_GPIO_1_9__GPIO1_9      IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 4b9b8368c0c0..7fc5f9946199 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -25,6 +25,18 @@
 #define MXC_EHCI_INTERNAL_PHY           (1 << 7)
 #define MXC_EHCI_IPPUE_DOWN             (1 << 8)
 #define MXC_EHCI_IPPUE_UP               (1 << 9)
+#define MXC_EHCI_WAKEUP_ENABLED (1 << 10)
+#define MXC_EHCI_ITC_NO_THRESHOLD       (1 << 11)
+
+#define MXC_USBCTRL_OFFSET              0
+#define MXC_USB_PHY_CTR_FUNC_OFFSET     0x8
+#define MXC_USB_PHY_CTR_FUNC2_OFFSET    0xc
+
+#define MX5_USBOTHER_REGS_OFFSET        0x800
+
+/* USB_PHY_CTRL_FUNC2*/
+#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK               0x3
+#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT              0
 
 struct mxc_usbh_platform_data {
         int (*init)(struct platform_device *pdev);
@@ -35,7 +47,7 @@ struct mxc_usbh_platform_data {
         struct otg_transceiver  *otg;
 };
 
-int mxc_set_usbcontrol(int port, unsigned int flags);
+int mxc_initialize_usb_hw(int port, unsigned int flags);
 
 #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
 
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index c1ce51abdba6..f9a1b059a76c 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -54,14 +54,14 @@
 #define MX2_TSTAT_COMP          (1 << 0)
 
 /* MX31, MX35, MX25, MXC91231, MX5 */
-#define MX3_TCTL_WAITEN         (1 << 3) /* Wait enable mode */
-#define MX3_TCTL_CLK_IPG        (1 << 6)
-#define MX3_TCTL_FRR            (1 << 9)
-#define MX3_IR                  0x0c
-#define MX3_TSTAT               0x08
-#define MX3_TSTAT_OF1           (1 << 0)
-#define MX3_TCN                 0x24
-#define MX3_TCMP                0x10
+#define V2_TCTL_WAITEN          (1 << 3) /* Wait enable mode */
+#define V2_TCTL_CLK_IPG         (1 << 6)
+#define V2_TCTL_FRR             (1 << 9)
+#define V2_IR                   0x0c
+#define V2_TSTAT                0x08
+#define V2_TSTAT_OF1            (1 << 0)
+#define V2_TCN                  0x24
+#define V2_TCMP                 0x10
 
 #define timer_is_v1()   (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 #define timer_is_v2()   (!timer_is_v1())
@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
         unsigned int tmp;
 
         if (timer_is_v2())
-                __raw_writel(0, timer_base + MX3_IR);
+                __raw_writel(0, timer_base + V2_IR);
         else {
                 tmp = __raw_readl(timer_base + MXC_TCTL);
                 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
@@ -86,7 +86,7 @@ static inline void gpt_irq_disable(void)
 static inline void gpt_irq_enable(void)
 {
         if (timer_is_v2())
-                __raw_writel(1<<0, timer_base + MX3_IR);
+                __raw_writel(1<<0, timer_base + V2_IR);
         else {
                 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
                         timer_base + MXC_TCTL);
@@ -102,7 +102,7 @@ static void gpt_irq_acknowledge(void)
                         __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
                                 timer_base + MX1_2_TSTAT);
         } else if (timer_is_v2())
-                __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
+                __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
 }
 
 static cycle_t mx1_2_get_cycles(struct clocksource *cs)
@@ -110,9 +110,9 @@ static cycle_t mx1_2_get_cycles(struct clocksource *cs)
         return __raw_readl(timer_base + MX1_2_TCN);
 }
 
-static cycle_t mx3_get_cycles(struct clocksource *cs)
+static cycle_t v2_get_cycles(struct clocksource *cs)
 {
-        return __raw_readl(timer_base + MX3_TCN);
+        return __raw_readl(timer_base + V2_TCN);
 }
 
 static struct clocksource clocksource_mxc = {
@@ -129,7 +129,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
         unsigned int c = clk_get_rate(timer_clk);
 
         if (timer_is_v2())
-                clocksource_mxc.read = mx3_get_cycles;
+                clocksource_mxc.read = v2_get_cycles;
 
         clocksource_mxc.mult = clocksource_hz2mult(c,
                                         clocksource_mxc.shift);
@@ -153,16 +153,16 @@ static int mx1_2_set_next_event(unsigned long evt,
                                 -ETIME : 0;
 }
 
-static int mx3_set_next_event(unsigned long evt,
+static int v2_set_next_event(unsigned long evt,
                               struct clock_event_device *unused)
 {
         unsigned long tcmp;
 
-        tcmp = __raw_readl(timer_base + MX3_TCN) + evt;
+        tcmp = __raw_readl(timer_base + V2_TCN) + evt;
 
-        __raw_writel(tcmp, timer_base + MX3_TCMP);
+        __raw_writel(tcmp, timer_base + V2_TCMP);
 
-        return (int)(tcmp - __raw_readl(timer_base + MX3_TCN)) < 0 ?
+        return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
                                 -ETIME : 0;
 }
 
@@ -192,8 +192,8 @@ static void mxc_set_mode(enum clock_event_mode mode,
         if (mode != clockevent_mode) {
                 /* Set event time into far-far future */
                 if (timer_is_v2())
-                        __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
-                                        timer_base + MX3_TCMP);
+                        __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
+                                        timer_base + V2_TCMP);
                 else
                         __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
                                         timer_base + MX1_2_TCMP);
@@ -245,7 +245,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
         uint32_t tstat;
 
         if (timer_is_v2())
-                tstat = __raw_readl(timer_base + MX3_TSTAT);
+                tstat = __raw_readl(timer_base + V2_TSTAT);
         else
                 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
 
@@ -276,7 +276,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
         unsigned int c = clk_get_rate(timer_clk);
 
         if (timer_is_v2())
-                clockevent_mxc.set_next_event = mx3_set_next_event;
+                clockevent_mxc.set_next_event = v2_set_next_event;
 
         clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
                                         clockevent_mxc.shift);
@@ -308,7 +308,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
         __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 
         if (timer_is_v2())
-                tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
+                tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
         else
                 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
 
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index afa6709db0b3..9b86d2a60d43 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -19,6 +19,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/common.h>
 
 /*
  *****************************************
@@ -144,6 +145,7 @@ void __init tzic_init_irq(void __iomem *irqbase)
                 set_irq_handler(i, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
+        mxc_register_gpios();
 
         pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 }
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 58583732b29a..452e18438b41 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -234,32 +234,6 @@ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
         }
 }
 
-
-/* Watchdog */
-
-static struct resource s3c_wdt_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_WATCHDOG,
-                .end   = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_WDT,
-                .end   = IRQ_WDT,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_wdt = {
-        .name             = "s3c2410-wdt",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(s3c_wdt_resource),
-        .resource         = s3c_wdt_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_wdt);
-
 /* IIS */
 
 static struct resource s3c_iis_resource[] = {
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 92bd75607b43..5cb2dd1da632 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
 
 config PLAT_S5P
         bool
-        depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210)
+        depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210)
         default y
         select ARM_VIC
         select NO_IOPORT
@@ -24,3 +24,8 @@ config PLAT_S5P
         select SAMSUNG_IRQ_UART
         help
           Base platform code for Samsung's S5P series SoC.
+
+config S5P_EXT_INT
+        bool
+        help
+          Use the external interrupts (other than GPIO interrupts.)
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 0ec09a9c36bd..39c242bb9d58 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -16,3 +16,5 @@ obj-y				+= dev-uart.o
 obj-y                           += cpu.o
 obj-y                           += clock.o
 obj-y                           += irq.o
+obj-$(CONFIG_S5P_EXT_INT)       += irq-eint.o
+
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index f92e5de3a755..75cb8c37ca2c 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -19,12 +19,14 @@
 #include <plat/cpu.h>
 #include <plat/s5p6440.h>
 #include <plat/s5p6442.h>
+#include <plat/s5pc100.h>
 #include <plat/s5pv210.h>
 
 /* table of supported CPUs */
 
 static const char name_s5p6440[] = "S5P6440";
 static const char name_s5p6442[] = "S5P6442";
+static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
 
 static struct cpu_table cpu_ids[] __initdata = {
@@ -45,6 +47,14 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init           = s5p6442_init,
                 .name           = name_s5p6442,
         }, {
+                .idcode         = 0x43100000,
+                .idmask         = 0xfffff000,
+                .map_io         = s5pc100_map_io,
+                .init_clocks    = s5pc100_init_clocks,
+                .init_uarts     = s5pc100_init_uarts,
+                .init           = s5pc100_init,
+                .name           = name_s5pc100,
+        }, {
                 .idcode         = 0x43110000,
                 .idmask         = 0xfffff000,
                 .map_io         = s5pv210_map_io,
diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-s5p/include/plat/s5pc100.h
new file mode 100644
index 000000000000..5f6099dd7cad
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5pc100.h
@@ -0,0 +1,33 @@
+/* arch/arm/plat-s5p/include/plat/s5pc100.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for s5pc100 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PC100 related SoCs */
+
+extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pc100_register_clocks(void);
+extern void s5pc100_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S5PC100
+
+extern  int s5pc100_init(void);
+extern void s5pc100_init_irq(void);
+extern void s5pc100_map_io(void);
+extern void s5pc100_init_clocks(int xtal);
+
+#define s5pc100_init_uarts s5pc100_common_init_uarts
+
+#else
+#define s5pc100_init_clocks NULL
+#define s5pc100_init_uarts NULL
+#define s5pc100_map_io NULL
+#define s5pc100_init NULL
+#endif
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
new file mode 100644
index 000000000000..eaa70aa0127b
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -0,0 +1,213 @@
+/* linux/arch/arm/plat-s5p/irq-eint.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P - IRQ EINT support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware/vic.h>
+
+#include <plat/regs-irqtype.h>
+
+#include <mach/map.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+
+static inline void s5p_irq_eint_mask(unsigned int irq)
+{
+        u32 mask;
+
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
+        mask |= eint_irq_to_bit(irq);
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+}
+
+static void s5p_irq_eint_unmask(unsigned int irq)
+{
+        u32 mask;
+
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
+        mask &= ~(eint_irq_to_bit(irq));
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+}
+
+static inline void s5p_irq_eint_ack(unsigned int irq)
+{
+        __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
+}
+
+static void s5p_irq_eint_maskack(unsigned int irq)
+{
+        /* compiler should in-line these */
+        s5p_irq_eint_mask(irq);
+        s5p_irq_eint_ack(irq);
+}
+
+static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
+{
+        int offs = eint_offset(irq);
+        int shift;
+        u32 ctrl, mask;
+        u32 newvalue = 0;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                newvalue = S5P_EXTINT_RISEEDGE;
+                break;
+
+        case IRQ_TYPE_EDGE_FALLING:
+                newvalue = S5P_EXTINT_RISEEDGE;
+                break;
+
+        case IRQ_TYPE_EDGE_BOTH:
+                newvalue = S5P_EXTINT_BOTHEDGE;
+                break;
+
+        case IRQ_TYPE_LEVEL_LOW:
+                newvalue = S5P_EXTINT_LOWLEV;
+                break;
+
+        case IRQ_TYPE_LEVEL_HIGH:
+                newvalue = S5P_EXTINT_HILEV;
+                break;
+
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -EINVAL;
+        }
+
+        shift = (offs & 0x7) * 4;
+        mask = 0x7 << shift;
+
+        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
+        ctrl &= ~mask;
+        ctrl |= newvalue << shift;
+        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
+
+        if ((0 <= offs) && (offs < 8))
+                s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+
+        else if ((8 <= offs) && (offs < 16))
+                s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+
+        else if ((16 <= offs) && (offs < 24))
+                s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+
+        else if ((24 <= offs) && (offs < 32))
+                s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+
+        else
+                printk(KERN_ERR "No such irq number %d", offs);
+
+        return 0;
+}
+
+static struct irq_chip s5p_irq_eint = {
+        .name           = "s5p-eint",
+        .mask           = s5p_irq_eint_mask,
+        .unmask         = s5p_irq_eint_unmask,
+        .mask_ack       = s5p_irq_eint_maskack,
+        .ack            = s5p_irq_eint_ack,
+        .set_type       = s5p_irq_eint_set_type,
+#ifdef CONFIG_PM
+        .set_wake       = s3c_irqext_wake,
+#endif
+};
+
+/* s5p_irq_demux_eint
+ *
+ * This function demuxes the IRQ from the group0 external interrupts,
+ * from EINTs 16 to 31. It is designed to be inlined into the specific
+ * handler s5p_irq_demux_eintX_Y.
+ *
+ * Each EINT pend/mask registers handle eight of them.
+ */
+static inline void s5p_irq_demux_eint(unsigned int start)
+{
+        u32 status;
+        u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+        unsigned int irq;
+
+        status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+        status &= ~mask;
+        status &= 0xff;
+
+        while (status) {
+                irq = fls(status);
+                generic_handle_irq(irq - 1 + start);
+                status &= ~(1 << irq);
+        }
+}
+
+static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+        s5p_irq_demux_eint(IRQ_EINT(16));
+        s5p_irq_demux_eint(IRQ_EINT(24));
+}
+
+static inline void s5p_irq_vic_eint_mask(unsigned int irq)
+{
+        s5p_irq_eint_mask(irq);
+}
+
+static void s5p_irq_vic_eint_unmask(unsigned int irq)
+{
+        s5p_irq_eint_unmask(irq);
+}
+
+static inline void s5p_irq_vic_eint_ack(unsigned int irq)
+{
+        __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
+}
+
+static void s5p_irq_vic_eint_maskack(unsigned int irq)
+{
+        s5p_irq_vic_eint_mask(irq);
+        s5p_irq_vic_eint_ack(irq);
+}
+
+static struct irq_chip s5p_irq_vic_eint = {
+        .name           = "s5p_vic_eint",
+        .mask           = s5p_irq_vic_eint_mask,
+        .unmask         = s5p_irq_vic_eint_unmask,
+        .mask_ack       = s5p_irq_vic_eint_maskack,
+        .ack            = s5p_irq_vic_eint_ack,
+        .set_type       = s5p_irq_eint_set_type,
+#ifdef CONFIG_PM
+        .set_wake       = s3c_irqext_wake,
+#endif
+};
+
+int __init s5p_init_irq_eint(void)
+{
+        int irq;
+
+        for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
+                set_irq_chip(irq, &s5p_irq_vic_eint);
+
+        for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
+                set_irq_chip(irq, &s5p_irq_eint);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+
+        set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
+        return 0;
+}
+
+arch_initcall(s5p_init_irq_eint);
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
deleted file mode 100644
index c7bd2bbda239..000000000000
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-# Copyright 2009 Samsung Electronics Co.
-#       Byungho Min <bhmin@samsung.com>
-#
-# Licensed under GPLv2
-
-config PLAT_S5PC1XX
-        bool
-        depends on ARCH_S5PC1XX
-        default y
-        select PLAT_S3C
-        select ARM_VIC
-        select NO_IOPORT
-        select ARCH_REQUIRE_GPIOLIB
-        select SAMSUNG_CLKSRC
-        select SAMSUNG_IRQ_UART
-        select SAMSUNG_IRQ_VIC_TIMER
-        select S3C_GPIO_TRACK
-        select S3C_GPIO_PULL_UPDOWN
-        select S5P_GPIO_DRVSTR
-        select S3C_GPIO_CFG_S3C24XX
-        select S3C_GPIO_CFG_S3C64XX
-        select SAMSUNG_GPIOLIB_4BIT
-        help
-          Base platform code for any Samsung S5PC1XX device
-
-if PLAT_S5PC1XX
-
-# Configuration options shared by all S3C64XX implementations
-
-config CPU_S5PC100_INIT
-        bool
-        help
-          Common initialisation code for the S5PC1XX
-
-config CPU_S5PC100_CLOCK
-        bool
-        help
-          Common clock support code for the S5PC1XX
-
-# platform specific device setup
-
-config S5PC1XX_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
deleted file mode 100644
index 9ce6409a9e02..000000000000
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-# arch/arm/plat-s5pc1xx/Makefile
-#
-# Copyright 2009 Samsung Electronics Co.
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           := dummy.o
-obj-                            :=
-
-# Core files
-
-obj-y                           += dev-uart.o
-obj-y                           += cpu.o
-obj-y                           += irq.o
-obj-y                           += clock.o
-
-# CPU support
-
-obj-$(CONFIG_CPU_S5PC100_INIT)  += s5pc100-init.o
-obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o
-
-# Device setup
-
-obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
deleted file mode 100644
index 387f23190c3c..000000000000
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ /dev/null
@@ -1,709 +0,0 @@
-/* linux/arch/arm/plat-s5pc1xx/clock.c
- *
- * Copyright 2009 Samsung Electronics Co.
- *
- * S5PC1XX Base clock support
- *
- * Based on plat-s3c64xx/clock.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-
-#include <plat/regs-clock.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-
-struct clk clk_27m = {
-        .name           = "clk_27m",
-        .id             = -1,
-        .rate           = 27000000,
-};
-
-static int clk_48m_ctrl(struct clk *clk, int enable)
-{
-        unsigned long flags;
-        u32 val;
-
-        /* can't rely on clock lock, this register has other usages */
-        local_irq_save(flags);
-
-        val = __raw_readl(S5PC100_CLKSRC1);
-        if (enable)
-                val |= S5PC100_CLKSRC1_CLK48M_MASK;
-        else
-                val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
-
-        __raw_writel(val, S5PC100_CLKSRC1);
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-struct clk clk_48m = {
-        .name           = "clk_48m",
-        .id             = -1,
-        .rate           = 48000000,
-        .enable         = clk_48m_ctrl,
-};
-
-struct clk clk_54m = {
-        .name           = "clk_54m",
-        .id             = -1,
-        .rate           = 54000000,
-};
-
-struct clk clk_hd0 = {
-        .name           = "hclkd0",
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .ops            = &clk_ops_def_setrate,
-};
-
-struct clk clk_pd0 = {
-        .name           = "pclkd0",
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .ops            = &clk_ops_def_setrate,
-};
-
-static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
-{
-        unsigned int ctrlbit = clk->ctrlbit;
-        u32 con;
-
-        con = __raw_readl(reg);
-        if (enable)
-                con |= ctrlbit;
-        else
-                con &= ~ctrlbit;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-
-static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
-}
-
-static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
-}
-
-static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
-}
-
-static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
-}
-
-static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
-}
-
-static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
-}
-
-static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
-}
-
-static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
-}
-
-static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
-}
-
-static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
-}
-
-int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
-}
-
-int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
-{
-        return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
-}
-
-static struct clk s5pc100_init_clocks_disable[] = {
-        {
-                .name           = "dsi",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_DSI,
-        }, {
-                .name           = "csi",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_CSI,
-        }, {
-                .name           = "ccan",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN0,
-        }, {
-                .name           = "ccan",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN1,
-        }, {
-                .name           = "keypad",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
-        }, {
-                .name           = "hclkd2",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc100_clk_d20_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D20_HCLKD2,
-        }, {
-                .name           = "iis-d2",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc100_clk_d20_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D20_I2SD2,
-        },
-};
-
-static struct clk s5pc100_init_clocks[] = {
-        /* System1 (D0_0) devices */
-        {
-                .name           = "intc",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_INTC,
-        }, {
-                .name           = "tzic",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_TZIC,
-        }, {
-                .name           = "cf-ata",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_CFCON,
-        }, {
-                .name           = "mdma",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_MDMA,
-        }, {
-                .name           = "g2d",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_G2D,
-        }, {
-                .name           = "secss",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_SECSS,
-        }, {
-                .name           = "cssys",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_CSSYS,
-        },
-
-        /* Memory (D0_1) devices */
-        {
-                .name           = "dmc",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_DMC,
-        }, {
-                .name           = "sromc",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_SROMC,
-        }, {
-                .name           = "onenand",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_ONENAND,
-        }, {
-                .name           = "nand",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_NFCON,
-        }, {
-                .name           = "intmem",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_INTMEM,
-        }, {
-                .name           = "ebi",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_EBI,
-        },
-
-        /* System2 (D0_2) devices */
-        {
-                .name           = "seckey",
-                .id             = -1,
-                .parent         = &clk_pd0,
-                .enable         = s5pc100_clk_d02_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D02_SECKEY,
-        }, {
-                .name           = "sdm",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc100_clk_d02_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D02_SDM,
-        },
-
-        /* File (D1_0) devices */
-        {
-                .name           = "pdma",
-                .id             = 0,
-                .parent         = &clk_h,
-                .enable         = s5pc100_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA0,
-        }, {
-                .name           = "pdma",
-                .id             = 1,
-                .parent         = &clk_h,
-                .enable         = s5pc100_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA1,
-        }, {
-                .name           = "usb-host",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc100_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_USBHOST,
-        }, {
-                .name           = "otg",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc100_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_USBOTG,
-        }, {
-                .name           = "modem",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc100_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_MODEMIF,
-        }, {
-                .name           = "hsmmc",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC2,
-        },
-
-        /* Multimedia1 (D1_1) devices */
-        {
-                .name           = "lcd",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_LCD,
-        }, {
-                .name           = "rotator",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_ROTATOR,
-        }, {
-                .name           = "fimc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC0,
-        }, {
-                .name           = "fimc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC1,
-        }, {
-                .name           = "fimc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC2,
-        }, {
-                .name           = "jpeg",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_JPEG,
-        }, {
-                .name           = "g3d",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_G3D,
-        },
-
-        /* Multimedia2 (D1_2) devices */
-        {
-                .name           = "tv",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_TV,
-        }, {
-                .name           = "vp",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_VP,
-        }, {
-                .name           = "mixer",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_MIXER,
-        }, {
-                .name           = "hdmi",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_HDMI,
-        }, {
-                .name           = "mfc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_MFC,
-        },
-
-        /* System (D1_3) devices */
-        {
-                .name           = "chipid",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_CHIPID,
-        }, {
-                .name           = "gpio",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_GPIO,
-        }, {
-                .name           = "apc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_APC,
-        }, {
-                .name           = "iec",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_IEC,
-        }, {
-                .name           = "timers",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_PWM,
-        }, {
-                .name           = "systimer",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_SYSTIMER,
-        }, {
-                .name           = "watchdog",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_WDT,
-        }, {
-                .name           = "rtc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_RTC,
-        },
-
-        /* Connectivity (D1_4) devices */
-        {
-                .name           = "uart",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART0,
-        }, {
-                .name           = "uart",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART1,
-        }, {
-                .name           = "uart",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART2,
-        }, {
-                .name           = "uart",
-                .id             = 3,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART3,
-        }, {
-                .name           = "i2c",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_IIC,
-        }, {
-                .name           = "hdmi-i2c",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HDMI_IIC,
-        }, {
-                .name           = "spi",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI0,
-        }, {
-                .name           = "spi",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI1,
-        }, {
-                .name           = "spi",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI2,
-        }, {
-                .name           = "irda",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_IRDA,
-        }, {
-                .name           = "hsitx",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HSITX,
-        }, {
-                .name           = "hsirx",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HSIRX,
-        },
-
-        /* Audio (D1_5) devices */
-        {
-                .name           = "iis",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS0,
-        }, {
-                .name           = "iis",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS1,
-        }, {
-                .name           = "iis",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS2,
-        }, {
-                .name           = "ac97",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_AC97,
-        }, {
-                .name           = "pcm",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_PCM0,
-        }, {
-                .name           = "pcm",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_PCM1,
-        }, {
-                .name           = "spdif",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_SPDIF,
-        }, {
-                .name           = "adc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_TSADC,
-        }, {
-                .name           = "cg",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc100_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_CG,
-        },
-
-        /* Audio (D2_0) devices: all disabled */
-
-        /* Special Clocks 0 */
-        {
-                .name           = "sclk_hpm",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_HPM,
-        }, {
-                .name           = "sclk_onenand",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_ONENAND,
-        }, {
-                .name           = "spi_48",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0_48,
-        }, {
-                .name           = "spi_48",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1_48,
-        }, {
-                .name           = "spi_48",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2_48,
-        }, {
-                .name           = "mmc_48",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0_48,
-        }, {
-                .name           = "mmc_48",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1_48,
-        }, {
-                .name           = "mmc_48",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2_48,
-        },
-        /* Special Clocks 1 */
-};
-
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_epll,
-        &clk_pd0,
-        &clk_hd0,
-        &clk_27m,
-        &clk_48m,
-        &clk_54m,
-};
-
-void __init s5pc1xx_register_clocks(void)
-{
-        struct clk *clkp;
-        int ret;
-        int ptr;
-        int size;
-
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        s3c_register_clocks(s5pc100_init_clocks,
-                            ARRAY_SIZE(s5pc100_init_clocks));
-
-        clkp = s5pc100_init_clocks_disable;
-        size = ARRAY_SIZE(s5pc100_init_clocks_disable);
-
-        for (ptr = 0; ptr < size; ptr++, clkp++) {
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-
-                (clkp->enable)(clkp, 0);
-        }
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
deleted file mode 100644
index 02baeaa2a121..000000000000
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* linux/arch/arm/plat-s5pc1xx/cpu.c
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC1XX CPU Support
- *
- * Based on plat-s3c64xx/cpu.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-
-#include <asm/mach/map.h>
-
-#include <plat/regs-serial.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-
-#include <plat/s5pc100.h>
-
-/* table of supported CPUs */
-
-static const char name_s5pc100[] = "S5PC100";
-
-static struct cpu_table cpu_ids[] __initdata = {
-        {
-                .idcode         = 0x43100000,
-                .idmask         = 0xfffff000,
-                .map_io         = s5pc100_map_io,
-                .init_clocks    = s5pc100_init_clocks,
-                .init_uarts     = s5pc100_init_uarts,
-                .init           = s5pc100_init,
-                .name           = name_s5pc100,
-        },
-};
-/* minimal IO mapping */
-
-/* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */
-#define UART_OFFS (S3C_PA_UART & 0xffff)
-
-static struct map_desc s5pc1xx_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5PC1XX_VA_CLK_OTHER,
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC1XX_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC1XX_VA_CHIPID,
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_CHIPID),
-                .length         = SZ_16,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC1XX_VA_CLK,
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_CLK),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC1XX_VA_PWR,
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_PWR),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)(S5PC1XX_VA_UART),
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_UART),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC1XX_VA_VIC(0),
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(0)),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC1XX_VA_VIC(1),
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(1)),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC1XX_VA_VIC(2),
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(2)),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC1XX_VA_TIMER,
-                .pfn            = __phys_to_pfn(S5PC1XX_PA_TIMER),
-                .length         = SZ_256,
-                .type           = MT_DEVICE,
-        },
-};
-
-/* read cpu identification code */
-
-void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size)
-{
-        unsigned long idcode;
-
-        /* initialise the io descriptors we need for initialisation */
-        iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc));
-        iotable_init(mach_desc, size);
-
-        idcode = __raw_readl(S5PC1XX_VA_CHIPID);
-        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
-}
diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c
deleted file mode 100644
index 586c95c60bfe..000000000000
--- a/arch/arm/plat-s5pc1xx/dev-uart.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* linux/arch/arm/plat-s5pc1xx/dev-uart.c
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * Based on plat-s3c64xx/dev-uart.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-
-#include <plat/devs.h>
-
-/* Serial port registrations */
-
-/* 64xx uarts are closer together */
-
-static struct resource s5pc1xx_uart0_resource[] = {
-        [0] = {
-                .start  = S3C_PA_UART0,
-                .end    = S3C_PA_UART0 + 0x100,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_S3CUART_RX0,
-                .end    = IRQ_S3CUART_RX0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = IRQ_S3CUART_TX0,
-                .end    = IRQ_S3CUART_TX0,
-                .flags  = IORESOURCE_IRQ,
-
-        },
-        [3] = {
-                .start  = IRQ_S3CUART_ERR0,
-                .end    = IRQ_S3CUART_ERR0,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct resource s5pc1xx_uart1_resource[] = {
-        [0] = {
-                .start = S3C_PA_UART1,
-                .end   = S3C_PA_UART1 + 0x100,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_S3CUART_RX1,
-                .end    = IRQ_S3CUART_RX1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = IRQ_S3CUART_TX1,
-                .end    = IRQ_S3CUART_TX1,
-                .flags  = IORESOURCE_IRQ,
-
-        },
-        [3] = {
-                .start  = IRQ_S3CUART_ERR1,
-                .end    = IRQ_S3CUART_ERR1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource s5pc1xx_uart2_resource[] = {
-        [0] = {
-                .start = S3C_PA_UART2,
-                .end   = S3C_PA_UART2 + 0x100,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_S3CUART_RX2,
-                .end    = IRQ_S3CUART_RX2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = IRQ_S3CUART_TX2,
-                .end    = IRQ_S3CUART_TX2,
-                .flags  = IORESOURCE_IRQ,
-
-        },
-        [3] = {
-                .start  = IRQ_S3CUART_ERR2,
-                .end    = IRQ_S3CUART_ERR2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource s5pc1xx_uart3_resource[] = {
-        [0] = {
-                .start = S3C_PA_UART3,
-                .end   = S3C_PA_UART3 + 0x100,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_S3CUART_RX3,
-                .end    = IRQ_S3CUART_RX3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = IRQ_S3CUART_TX3,
-                .end    = IRQ_S3CUART_TX3,
-                .flags  = IORESOURCE_IRQ,
-
-        },
-        [3] = {
-                .start  = IRQ_S3CUART_ERR3,
-                .end    = IRQ_S3CUART_ERR3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-
-struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = {
-        [0] = {
-                .resources      = s5pc1xx_uart0_resource,
-                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart0_resource),
-        },
-        [1] = {
-                .resources      = s5pc1xx_uart1_resource,
-                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart1_resource),
-        },
-        [2] = {
-                .resources      = s5pc1xx_uart2_resource,
-                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart2_resource),
-        },
-        [3] = {
-                .resources      = s5pc1xx_uart3_resource,
-                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart3_resource),
-        },
-};
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
deleted file mode 100644
index 33ad267e8477..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *
- * External Interrupt (GPH0 ~ GPH3) control register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S5PC1XX_WKUP_INT_CON0_7         (S5PC1XX_EINT_BASE + 0x0)
-#define S5PC1XX_WKUP_INT_CON8_15        (S5PC1XX_EINT_BASE + 0x4)
-#define S5PC1XX_WKUP_INT_CON16_23       (S5PC1XX_EINT_BASE + 0x8)
-#define S5PC1XX_WKUP_INT_CON24_31       (S5PC1XX_EINT_BASE + 0xC)
-#define S5PC1XX_WKUP_INT_CON(x)         (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4))
-
-#define S5PC1XX_WKUP_INT_FLTCON0_3      (S5PC1XX_EINT_BASE + 0x80)
-#define S5PC1XX_WKUP_INT_FLTCON4_7      (S5PC1XX_EINT_BASE + 0x84)
-#define S5PC1XX_WKUP_INT_FLTCON8_11     (S5PC1XX_EINT_BASE + 0x88)
-#define S5PC1XX_WKUP_INT_FLTCON12_15    (S5PC1XX_EINT_BASE + 0x8C)
-#define S5PC1XX_WKUP_INT_FLTCON16_19    (S5PC1XX_EINT_BASE + 0x90)
-#define S5PC1XX_WKUP_INT_FLTCON20_23    (S5PC1XX_EINT_BASE + 0x94)
-#define S5PC1XX_WKUP_INT_FLTCON24_27    (S5PC1XX_EINT_BASE + 0x98)
-#define S5PC1XX_WKUP_INT_FLTCON28_31    (S5PC1XX_EINT_BASE + 0x9C)
-#define S5PC1XX_WKUP_INT_FLTCON(x)      (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4))
-
-#define S5PC1XX_WKUP_INT_MASK0_7        (S5PC1XX_EINT_BASE + 0x100)
-#define S5PC1XX_WKUP_INT_MASK8_15       (S5PC1XX_EINT_BASE + 0x104)
-#define S5PC1XX_WKUP_INT_MASK16_23      (S5PC1XX_EINT_BASE + 0x108)
-#define S5PC1XX_WKUP_INT_MASK24_31      (S5PC1XX_EINT_BASE + 0x10C)
-#define S5PC1XX_WKUP_INT_MASK(x)        (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4))
-
-#define S5PC1XX_WKUP_INT_PEND0_7        (S5PC1XX_EINT_BASE + 0x140)
-#define S5PC1XX_WKUP_INT_PEND8_15       (S5PC1XX_EINT_BASE + 0x144)
-#define S5PC1XX_WKUP_INT_PEND16_23      (S5PC1XX_EINT_BASE + 0x148)
-#define S5PC1XX_WKUP_INT_PEND24_31      (S5PC1XX_EINT_BASE + 0x14C)
-#define S5PC1XX_WKUP_INT_PEND(x)        (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4))
-
-#define S5PC1XX_WKUP_INT_LOWLEV         (0x00)
-#define S5PC1XX_WKUP_INT_HILEV          (0x01)
-#define S5PC1XX_WKUP_INT_FALLEDGE       (0x02)
-#define S5PC1XX_WKUP_INT_RISEEDGE       (0x03)
-#define S5PC1XX_WKUP_INT_BOTHEDGE       (0x04)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
deleted file mode 100644
index 409c804315e8..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC1XX - Common IRQ support
- *
- * Based on plat-s3c64xx/include/plat/irqs.h
- */
-
-#ifndef __ASM_PLAT_S5PC1XX_IRQS_H
-#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__
-
-/* we keep the first set of CPU IRQs out of the range of
- * the ISA space, so that the PC104 has them to itself
- * and we don't end up having to do horrible things to the
- * standard ISA drivers....
- *
- * note, since we're using the VICs, our start must be a
- * mulitple of 32 to allow the common code to work
- */
-
-#define S3C_IRQ_OFFSET          (32)
-
-#define S3C_IRQ(x)              ((x) + S3C_IRQ_OFFSET)
-
-#define S3C_VIC0_BASE           S3C_IRQ(0)
-#define S3C_VIC1_BASE           S3C_IRQ(32)
-#define S3C_VIC2_BASE           S3C_IRQ(64)
-
-/* UART interrupts, each UART has 4 intterupts per channel so
- * use the space between the ISA and S3C main interrupts. Note, these
- * are not in the same order as the S3C24XX series! */
-
-#define IRQ_S3CUART_BASE0       (16)
-#define IRQ_S3CUART_BASE1       (20)
-#define IRQ_S3CUART_BASE2       (24)
-#define IRQ_S3CUART_BASE3       (28)
-
-#define UART_IRQ_RXD            (0)
-#define UART_IRQ_ERR            (1)
-#define UART_IRQ_TXD            (2)
-#define UART_IRQ_MODEM          (3)
-
-#define IRQ_S3CUART_RX0         (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
-#define IRQ_S3CUART_TX0         (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
-#define IRQ_S3CUART_ERR0        (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
-
-#define IRQ_S3CUART_RX1         (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
-#define IRQ_S3CUART_TX1         (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
-#define IRQ_S3CUART_ERR1        (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
-
-#define IRQ_S3CUART_RX2         (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
-#define IRQ_S3CUART_TX2         (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
-#define IRQ_S3CUART_ERR2        (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
-
-#define IRQ_S3CUART_RX3         (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
-#define IRQ_S3CUART_TX3         (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
-#define IRQ_S3CUART_ERR3        (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
-
-/* VIC based IRQs */
-
-#define S5PC1XX_IRQ_VIC0(x)     (S3C_VIC0_BASE + (x))
-#define S5PC1XX_IRQ_VIC1(x)     (S3C_VIC1_BASE + (x))
-#define S5PC1XX_IRQ_VIC2(x)     (S3C_VIC2_BASE + (x))
-
-/*
- * VIC0: system, DMA, timer
- */
-#define IRQ_EINT0               S5PC1XX_IRQ_VIC0(0)
-#define IRQ_EINT1               S5PC1XX_IRQ_VIC0(1)
-#define IRQ_EINT2               S5PC1XX_IRQ_VIC0(2)
-#define IRQ_EINT3               S5PC1XX_IRQ_VIC0(3)
-#define IRQ_EINT4               S5PC1XX_IRQ_VIC0(4)
-#define IRQ_EINT5               S5PC1XX_IRQ_VIC0(5)
-#define IRQ_EINT6               S5PC1XX_IRQ_VIC0(6)
-#define IRQ_EINT7               S5PC1XX_IRQ_VIC0(7)
-#define IRQ_EINT8               S5PC1XX_IRQ_VIC0(8)
-#define IRQ_EINT9               S5PC1XX_IRQ_VIC0(9)
-#define IRQ_EINT10              S5PC1XX_IRQ_VIC0(10)
-#define IRQ_EINT11              S5PC1XX_IRQ_VIC0(11)
-#define IRQ_EINT12              S5PC1XX_IRQ_VIC0(12)
-#define IRQ_EINT13              S5PC1XX_IRQ_VIC0(13)
-#define IRQ_EINT14              S5PC1XX_IRQ_VIC0(14)
-#define IRQ_EINT15              S5PC1XX_IRQ_VIC0(15)
-#define IRQ_EINT16_31           S5PC1XX_IRQ_VIC0(16)
-#define IRQ_BATF                S5PC1XX_IRQ_VIC0(17)
-#define IRQ_MDMA                S5PC1XX_IRQ_VIC0(18)
-#define IRQ_PDMA0               S5PC1XX_IRQ_VIC0(19)
-#define IRQ_PDMA1               S5PC1XX_IRQ_VIC0(20)
-#define IRQ_TIMER0_VIC          S5PC1XX_IRQ_VIC0(21)
-#define IRQ_TIMER1_VIC          S5PC1XX_IRQ_VIC0(22)
-#define IRQ_TIMER2_VIC          S5PC1XX_IRQ_VIC0(23)
-#define IRQ_TIMER3_VIC          S5PC1XX_IRQ_VIC0(24)
-#define IRQ_TIMER4_VIC          S5PC1XX_IRQ_VIC0(25)
-#define IRQ_SYSTIMER            S5PC1XX_IRQ_VIC0(26)
-#define IRQ_WDT                 S5PC1XX_IRQ_VIC0(27)
-#define IRQ_RTC_ALARM           S5PC1XX_IRQ_VIC0(28)
-#define IRQ_RTC_TIC             S5PC1XX_IRQ_VIC0(29)
-#define IRQ_GPIOINT             S5PC1XX_IRQ_VIC0(30)
-
-/*
- * VIC1: ARM, power, memory, connectivity
- */
-#define IRQ_CORTEX0             S5PC1XX_IRQ_VIC1(0)
-#define IRQ_CORTEX1             S5PC1XX_IRQ_VIC1(1)
-#define IRQ_CORTEX2             S5PC1XX_IRQ_VIC1(2)
-#define IRQ_CORTEX3             S5PC1XX_IRQ_VIC1(3)
-#define IRQ_CORTEX4             S5PC1XX_IRQ_VIC1(4)
-#define IRQ_IEMAPC              S5PC1XX_IRQ_VIC1(5)
-#define IRQ_IEMIEC              S5PC1XX_IRQ_VIC1(6)
-#define IRQ_ONENAND             S5PC1XX_IRQ_VIC1(7)
-#define IRQ_NFC                 S5PC1XX_IRQ_VIC1(8)
-#define IRQ_CFC                 S5PC1XX_IRQ_VIC1(9)
-#define IRQ_UART0               S5PC1XX_IRQ_VIC1(10)
-#define IRQ_UART1               S5PC1XX_IRQ_VIC1(11)
-#define IRQ_UART2               S5PC1XX_IRQ_VIC1(12)
-#define IRQ_UART3               S5PC1XX_IRQ_VIC1(13)
-#define IRQ_IIC                 S5PC1XX_IRQ_VIC1(14)
-#define IRQ_SPI0                S5PC1XX_IRQ_VIC1(15)
-#define IRQ_SPI1                S5PC1XX_IRQ_VIC1(16)
-#define IRQ_SPI2                S5PC1XX_IRQ_VIC1(17)
-#define IRQ_IRDA                S5PC1XX_IRQ_VIC1(18)
-#define IRQ_CAN0                S5PC1XX_IRQ_VIC1(19)
-#define IRQ_CAN1                S5PC1XX_IRQ_VIC1(20)
-#define IRQ_HSIRX               S5PC1XX_IRQ_VIC1(21)
-#define IRQ_HSITX               S5PC1XX_IRQ_VIC1(22)
-#define IRQ_UHOST               S5PC1XX_IRQ_VIC1(23)
-#define IRQ_OTG                 S5PC1XX_IRQ_VIC1(24)
-#define IRQ_MSM                 S5PC1XX_IRQ_VIC1(25)
-#define IRQ_HSMMC0              S5PC1XX_IRQ_VIC1(26)
-#define IRQ_HSMMC1              S5PC1XX_IRQ_VIC1(27)
-#define IRQ_HSMMC2              S5PC1XX_IRQ_VIC1(28)
-#define IRQ_MIPICSI             S5PC1XX_IRQ_VIC1(29)
-#define IRQ_MIPIDSI             S5PC1XX_IRQ_VIC1(30)
-
-/*
- * VIC2: multimedia, audio, security
- */
-#define IRQ_LCD0                S5PC1XX_IRQ_VIC2(0)
-#define IRQ_LCD1                S5PC1XX_IRQ_VIC2(1)
-#define IRQ_LCD2                S5PC1XX_IRQ_VIC2(2)
-#define IRQ_LCD3                S5PC1XX_IRQ_VIC2(3)
-#define IRQ_ROTATOR             S5PC1XX_IRQ_VIC2(4)
-#define IRQ_FIMC0               S5PC1XX_IRQ_VIC2(5)
-#define IRQ_FIMC1               S5PC1XX_IRQ_VIC2(6)
-#define IRQ_FIMC2               S5PC1XX_IRQ_VIC2(7)
-#define IRQ_JPEG                S5PC1XX_IRQ_VIC2(8)
-#define IRQ_2D                  S5PC1XX_IRQ_VIC2(9)
-#define IRQ_3D                  S5PC1XX_IRQ_VIC2(10)
-#define IRQ_MIXER               S5PC1XX_IRQ_VIC2(11)
-#define IRQ_HDMI                S5PC1XX_IRQ_VIC2(12)
-#define IRQ_IIC1                S5PC1XX_IRQ_VIC2(13)
-#define IRQ_MFC                 S5PC1XX_IRQ_VIC2(14)
-#define IRQ_TVENC               S5PC1XX_IRQ_VIC2(15)
-#define IRQ_I2S0                S5PC1XX_IRQ_VIC2(16)
-#define IRQ_I2S1                S5PC1XX_IRQ_VIC2(17)
-#define IRQ_I2S2                S5PC1XX_IRQ_VIC2(18)
-#define IRQ_AC97                S5PC1XX_IRQ_VIC2(19)
-#define IRQ_PCM0                S5PC1XX_IRQ_VIC2(20)
-#define IRQ_PCM1                S5PC1XX_IRQ_VIC2(21)
-#define IRQ_SPDIF               S5PC1XX_IRQ_VIC2(22)
-#define IRQ_ADC                 S5PC1XX_IRQ_VIC2(23)
-#define IRQ_PENDN               S5PC1XX_IRQ_VIC2(24)
-#define IRQ_TC                  IRQ_PENDN
-#define IRQ_KEYPAD              S5PC1XX_IRQ_VIC2(25)
-#define IRQ_CG                  S5PC1XX_IRQ_VIC2(26)
-#define IRQ_SEC                 S5PC1XX_IRQ_VIC2(27)
-#define IRQ_SECRX               S5PC1XX_IRQ_VIC2(28)
-#define IRQ_SECTX               S5PC1XX_IRQ_VIC2(29)
-#define IRQ_SDMIRQ              S5PC1XX_IRQ_VIC2(30)
-#define IRQ_SDMFIQ              S5PC1XX_IRQ_VIC2(31)
-
-#define IRQ_TIMER(x)            (IRQ_SDMFIQ + 1 + (x))
-#define IRQ_TIMER0              IRQ_TIMER(0)
-#define IRQ_TIMER1              IRQ_TIMER(1)
-#define IRQ_TIMER2              IRQ_TIMER(2)
-#define IRQ_TIMER3              IRQ_TIMER(3)
-#define IRQ_TIMER4              IRQ_TIMER(4)
-
-/* External interrupt */
-#define S3C_IRQ_EINT_BASE       (IRQ_SDMFIQ + 6)
-
-#define S3C_EINT(x)             (S3C_IRQ_EINT_BASE + (x - 16))
-#define IRQ_EINT(x)             (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
-#define IRQ_EINT_BIT(x)         (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
-
-/* GPIO interrupt */
-#define S3C_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
-#define S3C_IRQ_GPIO(x)         (S3C_IRQ_GPIO_BASE + (x))
-
-/*
- * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
- */
-#define NR_IRQS                 (S3C_IRQ_GPIO(320) + 1)
-
-#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
-
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
deleted file mode 100644
index 21afef1573e7..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/pll.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/plat-s5pc1xx/include/plat/pll.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC1XX PLL code
- *
- * Based on plat-s3c64xx/include/plat/pll.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S5P_PLL_MDIV_MASK       ((1 << (25-16+1)) - 1)
-#define S5P_PLL_PDIV_MASK       ((1 << (13-8+1)) - 1)
-#define S5P_PLL_SDIV_MASK       ((1 << (2-0+1)) - 1)
-#define S5P_PLL_MDIV_SHIFT      (16)
-#define S5P_PLL_PDIV_SHIFT      (8)
-#define S5P_PLL_SDIV_SHIFT      (0)
-
-#include <asm/div64.h>
-
-static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
-                                            u32 pllcon)
-{
-        u32 mdiv, pdiv, sdiv;
-        u64 fvco = baseclk;
-
-        mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK;
-        pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK;
-        sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
-
-        fvco *= mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned long)fvco;
-}
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
deleted file mode 100644
index 24dec4e52538..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC1XX clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_REGS_CLOCK_H
-#define __PLAT_REGS_CLOCK_H __FILE__
-
-#define S5PC100_CLKREG(x)               (S5PC1XX_VA_CLK + (x))
-#define S5PC100_CLKREG_OTHER(x)         (S5PC1XX_VA_CLK_OTHER + (x))
-
-/* s5pc100 register for clock */
-#define S5PC100_APLL_LOCK               S5PC100_CLKREG(0x00)
-#define S5PC100_MPLL_LOCK               S5PC100_CLKREG(0x04)
-#define S5PC100_EPLL_LOCK               S5PC100_CLKREG(0x08)
-#define S5PC100_HPLL_LOCK               S5PC100_CLKREG(0x0C)
-
-#define S5PC100_APLL_CON                S5PC100_CLKREG(0x100)
-#define S5PC100_MPLL_CON                S5PC100_CLKREG(0x104)
-#define S5PC100_EPLL_CON                S5PC100_CLKREG(0x108)
-#define S5PC100_HPLL_CON                S5PC100_CLKREG(0x10C)
-
-#define S5PC100_CLKSRC0                 S5PC100_CLKREG(0x200)
-#define S5PC100_CLKSRC1                 S5PC100_CLKREG(0x204)
-#define S5PC100_CLKSRC2                 S5PC100_CLKREG(0x208)
-#define S5PC100_CLKSRC3                 S5PC100_CLKREG(0x20C)
-
-#define S5PC100_CLKDIV0                 S5PC100_CLKREG(0x300)
-#define S5PC100_CLKDIV1                 S5PC100_CLKREG(0x304)
-#define S5PC100_CLKDIV2                 S5PC100_CLKREG(0x308)
-#define S5PC100_CLKDIV3                 S5PC100_CLKREG(0x30C)
-#define S5PC100_CLKDIV4                 S5PC100_CLKREG(0x310)
-
-#define S5PC100_CLK_OUT                 S5PC100_CLKREG(0x400)
-
-#define S5PC100_CLKGATE_D00             S5PC100_CLKREG(0x500)
-#define S5PC100_CLKGATE_D01             S5PC100_CLKREG(0x504)
-#define S5PC100_CLKGATE_D02             S5PC100_CLKREG(0x508)
-
-#define S5PC100_CLKGATE_D10             S5PC100_CLKREG(0x520)
-#define S5PC100_CLKGATE_D11             S5PC100_CLKREG(0x524)
-#define S5PC100_CLKGATE_D12             S5PC100_CLKREG(0x528)
-#define S5PC100_CLKGATE_D13             S5PC100_CLKREG(0x52C)
-#define S5PC100_CLKGATE_D14             S5PC100_CLKREG(0x530)
-#define S5PC100_CLKGATE_D15             S5PC100_CLKREG(0x534)
-
-#define S5PC100_CLKGATE_D20             S5PC100_CLKREG(0x540)
-
-#define S5PC100_SCLKGATE0               S5PC100_CLKREG(0x560)
-#define S5PC100_SCLKGATE1               S5PC100_CLKREG(0x564)
-
-/* EPLL_CON */
-#define S5PC100_EPLL_EN                 (1<<31)
-#define S5PC100_EPLL_MASK               0xffffffff
-#define S5PC100_EPLLVAL(_m, _p, _s)     ((_m) << 16 | ((_p) << 8) | ((_s)))
-
-/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */
-#define S5PC100_CLKSRC1_CLK48M_MASK     (0x1<<24)
-#define S5PC100_CLKSRC1_CLK48M_SHIFT    (24)
-
-/* CLKDIV0 */
-#define S5PC100_CLKDIV0_APLL_MASK               (0x1<<0)
-#define S5PC100_CLKDIV0_APLL_SHIFT              (0)
-#define S5PC100_CLKDIV0_ARM_MASK                (0x7<<4)
-#define S5PC100_CLKDIV0_ARM_SHIFT               (4)
-#define S5PC100_CLKDIV0_D0_MASK         (0x7<<8)
-#define S5PC100_CLKDIV0_D0_SHIFT                (8)
-#define S5PC100_CLKDIV0_PCLKD0_MASK             (0x7<<12)
-#define S5PC100_CLKDIV0_PCLKD0_SHIFT    (12)
-#define S5PC100_CLKDIV0_SECSS_MASK              (0x7<<16)
-#define S5PC100_CLKDIV0_SECSS_SHIFT             (16)
-
-/* CLKDIV1 (OneNAND clock only used in one place, removed) */
-#define S5PC100_CLKDIV1_APLL2_MASK              (0x7<<0)
-#define S5PC100_CLKDIV1_APLL2_SHIFT             (0)
-#define S5PC100_CLKDIV1_MPLL_MASK               (0x3<<4)
-#define S5PC100_CLKDIV1_MPLL_SHIFT              (4)
-#define S5PC100_CLKDIV1_MPLL2_MASK              (0x1<<8)
-#define S5PC100_CLKDIV1_MPLL2_SHIFT             (8)
-#define S5PC100_CLKDIV1_D1_MASK         (0x7<<12)
-#define S5PC100_CLKDIV1_D1_SHIFT                (12)
-#define S5PC100_CLKDIV1_PCLKD1_MASK             (0x7<<16)
-#define S5PC100_CLKDIV1_PCLKD1_SHIFT    (16)
-#define S5PC100_CLKDIV1_CAM_MASK                (0x1F<<24)
-#define S5PC100_CLKDIV1_CAM_SHIFT               (24)
-
-/* CLKDIV2 => removed in clksrc update */
-/* CLKDIV3 => removed in clksrc update, or not needed */
-/* CLKDIV4 => removed in clksrc update, or not needed */
-
-/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
-#define S5PC100_CLKGATE_D00_INTC                (1<<0)
-#define S5PC100_CLKGATE_D00_TZIC                (1<<1)
-#define S5PC100_CLKGATE_D00_CFCON               (1<<2)
-#define S5PC100_CLKGATE_D00_MDMA                (1<<3)
-#define S5PC100_CLKGATE_D00_G2D         (1<<4)
-#define S5PC100_CLKGATE_D00_SECSS               (1<<5)
-#define S5PC100_CLKGATE_D00_CSSYS               (1<<6)
-
-/* HCLKD0/PCLKD0 Clock Gate 1 Registers */
-#define S5PC100_CLKGATE_D01_DMC         (1<<0)
-#define S5PC100_CLKGATE_D01_SROMC               (1<<1)
-#define S5PC100_CLKGATE_D01_ONENAND             (1<<2)
-#define S5PC100_CLKGATE_D01_NFCON               (1<<3)
-#define S5PC100_CLKGATE_D01_INTMEM              (1<<4)
-#define S5PC100_CLKGATE_D01_EBI         (1<<5)
-
-/* PCLKD0 Clock Gate 2 Registers */
-#define S5PC100_CLKGATE_D02_SECKEY              (1<<1)
-#define S5PC100_CLKGATE_D02_SDM         (1<<2)
-
-/* HCLKD1/PCLKD1 Clock Gate 0 Registers */
-#define S5PC100_CLKGATE_D10_PDMA0               (1<<0)
-#define S5PC100_CLKGATE_D10_PDMA1               (1<<1)
-#define S5PC100_CLKGATE_D10_USBHOST             (1<<2)
-#define S5PC100_CLKGATE_D10_USBOTG              (1<<3)
-#define S5PC100_CLKGATE_D10_MODEMIF             (1<<4)
-#define S5PC100_CLKGATE_D10_HSMMC0              (1<<5)
-#define S5PC100_CLKGATE_D10_HSMMC1              (1<<6)
-#define S5PC100_CLKGATE_D10_HSMMC2              (1<<7)
-
-/* HCLKD1/PCLKD1 Clock Gate 1 Registers */
-#define S5PC100_CLKGATE_D11_LCD         (1<<0)
-#define S5PC100_CLKGATE_D11_ROTATOR             (1<<1)
-#define S5PC100_CLKGATE_D11_FIMC0               (1<<2)
-#define S5PC100_CLKGATE_D11_FIMC1               (1<<3)
-#define S5PC100_CLKGATE_D11_FIMC2               (1<<4)
-#define S5PC100_CLKGATE_D11_JPEG                (1<<5)
-#define S5PC100_CLKGATE_D11_DSI         (1<<6)
-#define S5PC100_CLKGATE_D11_CSI         (1<<7)
-#define S5PC100_CLKGATE_D11_G3D         (1<<8)
-
-/* HCLKD1/PCLKD1 Clock Gate 2 Registers */
-#define S5PC100_CLKGATE_D12_TV          (1<<0)
-#define S5PC100_CLKGATE_D12_VP          (1<<1)
-#define S5PC100_CLKGATE_D12_MIXER               (1<<2)
-#define S5PC100_CLKGATE_D12_HDMI                (1<<3)
-#define S5PC100_CLKGATE_D12_MFC         (1<<4)
-
-/* HCLKD1/PCLKD1 Clock Gate 3 Registers */
-#define S5PC100_CLKGATE_D13_CHIPID              (1<<0)
-#define S5PC100_CLKGATE_D13_GPIO                (1<<1)
-#define S5PC100_CLKGATE_D13_APC         (1<<2)
-#define S5PC100_CLKGATE_D13_IEC         (1<<3)
-#define S5PC100_CLKGATE_D13_PWM         (1<<6)
-#define S5PC100_CLKGATE_D13_SYSTIMER    (1<<7)
-#define S5PC100_CLKGATE_D13_WDT         (1<<8)
-#define S5PC100_CLKGATE_D13_RTC         (1<<9)
-
-/* HCLKD1/PCLKD1 Clock Gate 4 Registers */
-#define S5PC100_CLKGATE_D14_UART0               (1<<0)
-#define S5PC100_CLKGATE_D14_UART1               (1<<1)
-#define S5PC100_CLKGATE_D14_UART2               (1<<2)
-#define S5PC100_CLKGATE_D14_UART3               (1<<3)
-#define S5PC100_CLKGATE_D14_IIC         (1<<4)
-#define S5PC100_CLKGATE_D14_HDMI_IIC    (1<<5)
-#define S5PC100_CLKGATE_D14_SPI0                (1<<6)
-#define S5PC100_CLKGATE_D14_SPI1                (1<<7)
-#define S5PC100_CLKGATE_D14_SPI2                (1<<8)
-#define S5PC100_CLKGATE_D14_IRDA                (1<<9)
-#define S5PC100_CLKGATE_D14_CCAN0               (1<<10)
-#define S5PC100_CLKGATE_D14_CCAN1               (1<<11)
-#define S5PC100_CLKGATE_D14_HSITX               (1<<12)
-#define S5PC100_CLKGATE_D14_HSIRX               (1<<13)
-
-/* HCLKD1/PCLKD1 Clock Gate 5 Registers */
-#define S5PC100_CLKGATE_D15_IIS0                (1<<0)
-#define S5PC100_CLKGATE_D15_IIS1                (1<<1)
-#define S5PC100_CLKGATE_D15_IIS2                (1<<2)
-#define S5PC100_CLKGATE_D15_AC97                (1<<3)
-#define S5PC100_CLKGATE_D15_PCM0                (1<<4)
-#define S5PC100_CLKGATE_D15_PCM1                (1<<5)
-#define S5PC100_CLKGATE_D15_SPDIF               (1<<6)
-#define S5PC100_CLKGATE_D15_TSADC               (1<<7)
-#define S5PC100_CLKGATE_D15_KEYIF               (1<<8)
-#define S5PC100_CLKGATE_D15_CG          (1<<9)
-
-/* HCLKD2 Clock Gate 0 Registers */
-#define S5PC100_CLKGATE_D20_HCLKD2              (1<<0)
-#define S5PC100_CLKGATE_D20_I2SD2               (1<<1)
-
-/* Special Clock Gate 0 Registers */
-#define S5PC100_CLKGATE_SCLK0_HPM               (1<<0)
-#define S5PC100_CLKGATE_SCLK0_PWI               (1<<1)
-#define S5PC100_CLKGATE_SCLK0_ONENAND   (1<<2)
-#define S5PC100_CLKGATE_SCLK0_UART              (1<<3)
-#define S5PC100_CLKGATE_SCLK0_SPI0              (1<<4)
-#define S5PC100_CLKGATE_SCLK0_SPI1              (1<<5)
-#define S5PC100_CLKGATE_SCLK0_SPI2              (1<<6)
-#define S5PC100_CLKGATE_SCLK0_SPI0_48   (1<<7)
-#define S5PC100_CLKGATE_SCLK0_SPI1_48   (1<<8)
-#define S5PC100_CLKGATE_SCLK0_SPI2_48   (1<<9)
-#define S5PC100_CLKGATE_SCLK0_IRDA              (1<<10)
-#define S5PC100_CLKGATE_SCLK0_USBHOST   (1<<11)
-#define S5PC100_CLKGATE_SCLK0_MMC0              (1<<12)
-#define S5PC100_CLKGATE_SCLK0_MMC1              (1<<13)
-#define S5PC100_CLKGATE_SCLK0_MMC2              (1<<14)
-#define S5PC100_CLKGATE_SCLK0_MMC0_48   (1<<15)
-#define S5PC100_CLKGATE_SCLK0_MMC1_48   (1<<16)
-#define S5PC100_CLKGATE_SCLK0_MMC2_48   (1<<17)
-
-/* Special Clock Gate 1 Registers */
-#define S5PC100_CLKGATE_SCLK1_LCD               (1<<0)
-#define S5PC100_CLKGATE_SCLK1_FIMC0             (1<<1)
-#define S5PC100_CLKGATE_SCLK1_FIMC1             (1<<2)
-#define S5PC100_CLKGATE_SCLK1_FIMC2             (1<<3)
-#define S5PC100_CLKGATE_SCLK1_TV54              (1<<4)
-#define S5PC100_CLKGATE_SCLK1_VDAC54    (1<<5)
-#define S5PC100_CLKGATE_SCLK1_MIXER             (1<<6)
-#define S5PC100_CLKGATE_SCLK1_HDMI              (1<<7)
-#define S5PC100_CLKGATE_SCLK1_AUDIO0    (1<<8)
-#define S5PC100_CLKGATE_SCLK1_AUDIO1    (1<<9)
-#define S5PC100_CLKGATE_SCLK1_AUDIO2    (1<<10)
-#define S5PC100_CLKGATE_SCLK1_SPDIF             (1<<11)
-#define S5PC100_CLKGATE_SCLK1_CAM               (1<<12)
-
-#define S5PC100_SWRESET         S5PC100_CLKREG_OTHER(0x000)
-#define S5PC100_OND_SWRESET     S5PC100_CLKREG_OTHER(0x008)
-#define S5PC100_GEN_CTRL        S5PC100_CLKREG_OTHER(0x100)
-#define S5PC100_GEN_STATUS      S5PC100_CLKREG_OTHER(0x104)
-#define S5PC100_MEM_SYS_CFG     S5PC100_CLKREG_OTHER(0x200)
-#define S5PC100_CAM_MUX_SEL     S5PC100_CLKREG_OTHER(0x300)
-#define S5PC100_MIXER_OUT_SEL   S5PC100_CLKREG_OTHER(0x304)
-#define S5PC100_LPMP_MODE_SEL   S5PC100_CLKREG_OTHER(0x308)
-#define S5PC100_MIPI_PHY_CON0   S5PC100_CLKREG_OTHER(0x400)
-#define S5PC100_MIPI_PHY_CON1   S5PC100_CLKREG_OTHER(0x414)
-#define S5PC100_HDMI_PHY_CON0   S5PC100_CLKREG_OTHER(0x420)
-
-#define S5PC100_SWRESET_RESETVAL        0xc100
-#define S5PC100_OTHER_SYS_INT   24
-#define S5PC100_OTHER_STA_TYPE  23
-#define STA_TYPE_EXPON          0
-#define STA_TYPE_SFR            1
-
-#define S5PC100_SLEEP_CFG_OSC_EN        0
-
-/* OTHERS Resgister */
-#define S5PC100_OTHERS_USB_SIG_MASK     (1 << 16)
-#define S5PC100_OTHERS_MIPI_DPHY_EN             (1 << 28)
-
-/* MIPI D-PHY Control Register 0 */
-#define S5PC100_MIPI_PHY_CON0_M_RESETN  (1 << 1)
-#define S5PC100_MIPI_PHY_CON0_S_RESETN  (1 << 0)
-
-#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
deleted file mode 100644
index 02ffa491b53a..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Jongse Won <jongse.won@samsung.com>
- *
- * S5PC1XX clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_REGS_PWR
-#define __ASM_ARM_REGS_PWR __FILE__
-
-#define S5PC1XX_PWRREG(x)                       (S5PC1XX_VA_PWR + (x))
-
-/* s5pc100 (0xE0108000) register for power management */
-#define S5PC100_PWR_CFG                         S5PC1XX_PWRREG(0x0)
-#define S5PC100_EINT_WAKEUP_MASK                S5PC1XX_PWRREG(0x4)
-#define S5PC100_NORMAL_CFG                      S5PC1XX_PWRREG(0x10)
-#define S5PC100_STOP_CFG                        S5PC1XX_PWRREG(0x14)
-#define S5PC100_SLEEP_CFG                       S5PC1XX_PWRREG(0x18)
-#define S5PC100_STOP_MEM_CFG                    S5PC1XX_PWRREG(0x1C)
-#define S5PC100_OSC_FREQ                        S5PC1XX_PWRREG(0x100)
-#define S5PC100_OSC_STABLE                      S5PC1XX_PWRREG(0x104)
-#define S5PC100_PWR_STABLE                      S5PC1XX_PWRREG(0x108)
-#define S5PC100_MTC_STABLE                      S5PC1XX_PWRREG(0x110)
-#define S5PC100_CLAMP_STABLE                    S5PC1XX_PWRREG(0x114)
-#define S5PC100_OTHERS                          S5PC1XX_PWRREG(0x200)
-#define S5PC100_RST_STAT                        S5PC1XX_PWRREG(0x300)
-#define S5PC100_WAKEUP_STAT                     S5PC1XX_PWRREG(0x304)
-#define S5PC100_BLK_PWR_STAT                    S5PC1XX_PWRREG(0x308)
-#define S5PC100_INFORM0                         S5PC1XX_PWRREG(0x400)
-#define S5PC100_INFORM1                         S5PC1XX_PWRREG(0x404)
-#define S5PC100_INFORM2                         S5PC1XX_PWRREG(0x408)
-#define S5PC100_INFORM3                         S5PC1XX_PWRREG(0x40C)
-#define S5PC100_INFORM4                         S5PC1XX_PWRREG(0x410)
-#define S5PC100_INFORM5                         S5PC1XX_PWRREG(0x414)
-#define S5PC100_INFORM6                         S5PC1XX_PWRREG(0x418)
-#define S5PC100_INFORM7                         S5PC1XX_PWRREG(0x41C)
-#define S5PC100_DCGIDX_MAP0                     S5PC1XX_PWRREG(0x500)
-#define S5PC100_DCGIDX_MAP1                     S5PC1XX_PWRREG(0x504)
-#define S5PC100_DCGIDX_MAP2                     S5PC1XX_PWRREG(0x508)
-#define S5PC100_DCGPERF_MAP0                    S5PC1XX_PWRREG(0x50C)
-#define S5PC100_DCGPERF_MAP1                    S5PC1XX_PWRREG(0x510)
-#define S5PC100_DVCIDX_MAP                      S5PC1XX_PWRREG(0x514)
-#define S5PC100_FREQ_CPU                        S5PC1XX_PWRREG(0x518)
-#define S5PC100_FREQ_DPM                        S5PC1XX_PWRREG(0x51C)
-#define S5PC100_DVSEMCLK_EN                     S5PC1XX_PWRREG(0x520)
-#define S5PC100_APLL_CON_L8                     S5PC1XX_PWRREG(0x600)
-#define S5PC100_APLL_CON_L7                     S5PC1XX_PWRREG(0x604)
-#define S5PC100_APLL_CON_L6                     S5PC1XX_PWRREG(0x608)
-#define S5PC100_APLL_CON_L5                     S5PC1XX_PWRREG(0x60C)
-#define S5PC100_APLL_CON_L4                     S5PC1XX_PWRREG(0x610)
-#define S5PC100_APLL_CON_L3                     S5PC1XX_PWRREG(0x614)
-#define S5PC100_APLL_CON_L2                     S5PC1XX_PWRREG(0x618)
-#define S5PC100_APLL_CON_L1                     S5PC1XX_PWRREG(0x61C)
-#define S5PC100_IEM_CONTROL                     S5PC1XX_PWRREG(0x620)
-#define S5PC100_CLKDIV_IEM_L8                   S5PC1XX_PWRREG(0x700)
-#define S5PC100_CLKDIV_IEM_L7                   S5PC1XX_PWRREG(0x704)
-#define S5PC100_CLKDIV_IEM_L6                   S5PC1XX_PWRREG(0x708)
-#define S5PC100_CLKDIV_IEM_L5                   S5PC1XX_PWRREG(0x70C)
-#define S5PC100_CLKDIV_IEM_L4                   S5PC1XX_PWRREG(0x710)
-#define S5PC100_CLKDIV_IEM_L3                   S5PC1XX_PWRREG(0x714)
-#define S5PC100_CLKDIV_IEM_L2                   S5PC1XX_PWRREG(0x718)
-#define S5PC100_CLKDIV_IEM_L1                   S5PC1XX_PWRREG(0x71C)
-#define S5PC100_IEM_HPMCLK_DIV                  S5PC1XX_PWRREG(0x724)
-
-/* PWR_CFG */
-#define S5PC100_PWRCFG_CFG_DEEP_IDLE            (1 << 31)
-#define S5PC100_PWRCFG_CFG_WFI_MASK             (3 << 5)
-#define S5PC100_PWRCFG_CFG_WFI_IDLE             (0 << 5)
-#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE        (1 << 5)
-#define S5PC100_PWRCFG_CFG_WFI_STOP             (2 << 5)
-#define S5PC100_PWRCFG_CFG_WFI_SLEEP            (3 << 5)
-
-/* SLEEP_CFG */
-#define S5PC100_SLEEP_OSC_EN_SLEEP              (1 << 0)
-
-/* OTHERS */
-#define S5PC100_PMU_INT_DISABLE                 (1 << 24)
-
-#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
deleted file mode 100644
index 2531f34a56f3..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * Header file for s5pc100 cpu support
- *
- * Based on plat-s3c64xx/include/plat/s3c6400.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* Common init code for S5PC100 related SoCs */
-extern  int s5pc100_init(void);
-extern void s5pc100_map_io(void);
-extern void s5pc100_init_clocks(int xtal);
-extern  int s5pc100_register_baseclocks(unsigned long xtal);
-extern void s5pc100_init_irq(void);
-extern void s5pc100_init_io(struct map_desc *mach_desc, int size);
-extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-extern void s5pc100_register_clocks(void);
-extern void s5pc100_setup_clocks(void);
-extern struct sysdev_class s5pc100_sysclass;
-
-#define s5pc100_init_uarts s5pc100_common_init_uarts
-
-/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */
-extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
-extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
-
-/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */
-extern struct clk clk_hpll;
-extern struct clk clk_hd0;
-extern struct clk clk_pd0;
-extern struct clk clk_54m;
-extern void s5pc1xx_register_clocks(void);
-extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
-extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
-
-/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
-extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
-extern struct platform_device s3c_device_g2d;
-extern struct platform_device s3c_device_g3d;
-extern struct platform_device s3c_device_vpp;
-extern struct platform_device s3c_device_tvenc;
-extern struct platform_device s3c_device_tvscaler;
-extern struct platform_device s3c_device_rotator;
-extern struct platform_device s3c_device_jpeg;
-extern struct platform_device s3c_device_onenand;
-extern struct platform_device s3c_device_usb_otghcd;
-extern struct platform_device s3c_device_keypad;
-extern struct platform_device s3c_device_ts;
-extern struct platform_device s3c_device_g3d;
-extern struct platform_device s3c_device_smc911x;
-extern struct platform_device s3c_device_fimc0;
-extern struct platform_device s3c_device_fimc1;
-extern struct platform_device s3c_device_mfc;
-extern struct platform_device s3c_device_ac97;
-extern struct platform_device s3c_device_fimc0;
-extern struct platform_device s3c_device_fimc1;
-extern struct platform_device s3c_device_fimc2;
-
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c
deleted file mode 100644
index 373122f57d56..000000000000
--- a/arch/arm/plat-s5pc1xx/irq-eint.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * linux/arch/arm/plat-s5pc1xx/irq-eint.c
- *
- *  Copyright 2009 Samsung Electronics Co.
- *  Byungho Min <bhmin@samsung.com>
- *  Kyungin Park <kyungmin.park@samsung.com>
- *
- * Based on plat-s3c64xx/irq-eint.c
- *
- * S5PC1XX - Interrupt handling for IRQ_EINT(x)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/pm.h>
-#include <linux/gpio.h>
-
-#include <asm/hardware/vic.h>
-
-#include <mach/map.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-ext.h>
-#include <plat/pm.h>
-#include <plat/regs-gpio.h>
-#include <plat/regs-irqtype.h>
-
-/*
- * bank is a group of external interrupt
- * bank0 means EINT0 ... EINT7
- * bank1 means EINT8 ... EINT15
- * bank2 means EINT16 ... EINT23
- * bank3 means EINT24 ... EINT31
- */
-
-static inline int s3c_get_eint(unsigned int irq)
-{
-        int real;
-
-        if (irq < IRQ_EINT16_31)
-                real = (irq - IRQ_EINT0);
-        else
-                real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0;
-
-        return real;
-}
-
-static inline int s3c_get_bank(unsigned int irq)
-{
-        return s3c_get_eint(irq) >> 3;
-}
-
-static inline int s3c_eint_to_bit(unsigned int irq)
-{
-        int real, bit;
-
-        real = s3c_get_eint(irq);
-        bit = 1 << (real & (8 - 1));
-
-        return bit;
-}
-
-static inline void s3c_irq_eint_mask(unsigned int irq)
-{
-        u32 mask;
-        u32 bank = s3c_get_bank(irq);
-
-        mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
-        mask |= s3c_eint_to_bit(irq);
-        __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
-}
-
-static void s3c_irq_eint_unmask(unsigned int irq)
-{
-        u32 mask;
-        u32 bank = s3c_get_bank(irq);
-
-        mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
-        mask &= ~(s3c_eint_to_bit(irq));
-        __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
-}
-
-static inline void s3c_irq_eint_ack(unsigned int irq)
-{
-        u32 bank = s3c_get_bank(irq);
-
-        __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank));
-}
-
-static void s3c_irq_eint_maskack(unsigned int irq)
-{
-        /* compiler should in-line these */
-        s3c_irq_eint_mask(irq);
-        s3c_irq_eint_ack(irq);
-}
-
-static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
-{
-        u32 bank = s3c_get_bank(irq);
-        int real = s3c_get_eint(irq);
-        int gpio, shift, sfn;
-        u32 ctrl, con = 0;
-
-        switch (type) {
-        case IRQ_TYPE_NONE:
-                printk(KERN_WARNING "No edge setting!\n");
-                break;
-
-        case IRQ_TYPE_EDGE_RISING:
-                con = S5PC1XX_WKUP_INT_RISEEDGE;
-                break;
-
-        case IRQ_TYPE_EDGE_FALLING:
-                con = S5PC1XX_WKUP_INT_FALLEDGE;
-                break;
-
-        case IRQ_TYPE_EDGE_BOTH:
-                con = S5PC1XX_WKUP_INT_BOTHEDGE;
-                break;
-
-        case IRQ_TYPE_LEVEL_LOW:
-                con = S5PC1XX_WKUP_INT_LOWLEV;
-                break;
-
-        case IRQ_TYPE_LEVEL_HIGH:
-                con = S5PC1XX_WKUP_INT_HILEV;
-                break;
-
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -EINVAL;
-        }
-
-        gpio = real & (8 - 1);
-        shift = gpio << 2;
-
-        ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank));
-        ctrl &= ~(0x7 << shift);
-        ctrl |= con << shift;
-        __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank));
-
-        switch (real) {
-        case 0 ... 7:
-                        gpio = S5PC100_GPH0(gpio);
-                break;
-        case 8 ... 15:
-                        gpio = S5PC100_GPH1(gpio);
-                break;
-        case 16 ... 23:
-                        gpio = S5PC100_GPH2(gpio);
-                break;
-        case 24 ... 31:
-                        gpio = S5PC100_GPH3(gpio);
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        sfn = S3C_GPIO_SFN(0x2);
-        s3c_gpio_cfgpin(gpio, sfn);
-
-        return 0;
-}
-
-static struct irq_chip s3c_irq_eint = {
-        .name           = "EINT",
-        .mask           = s3c_irq_eint_mask,
-        .unmask         = s3c_irq_eint_unmask,
-        .mask_ack       = s3c_irq_eint_maskack,
-        .ack            = s3c_irq_eint_ack,
-        .set_type       = s3c_irq_eint_set_type,
-        .set_wake       = s3c_irqext_wake,
-};
-
-/* s3c_irq_demux_eint
- *
- * This function demuxes the IRQ from external interrupts,
- * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into
- * the specific handlers s3c_irq_demux_eintX_Y.
- */
-static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
-{
-        u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3)));
-        u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3)));
-        unsigned int irq;
-
-        status &= ~mask;
-        status &= (1 << (end - start + 1)) - 1;
-
-        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
-                if (status & 1)
-                        generic_handle_irq(irq);
-
-                status >>= 1;
-        }
-}
-
-static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
-{
-        s3c_irq_demux_eint(16, 23);
-        s3c_irq_demux_eint(24, 31);
-}
-
-/*
- * Handle EINT0 ... EINT15 at VIC directly
- */
-static void s3c_irq_vic_eint_mask(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        unsigned int real;
-
-        s3c_irq_eint_mask(irq);
-        real = s3c_get_eint(irq);
-        writel(1 << real, base + VIC_INT_ENABLE_CLEAR);
-}
-
-static void s3c_irq_vic_eint_unmask(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        unsigned int real;
-
-        s3c_irq_eint_unmask(irq);
-        real = s3c_get_eint(irq);
-        writel(1 << real, base + VIC_INT_ENABLE);
-}
-
-static inline void s3c_irq_vic_eint_ack(unsigned int irq)
-{
-        u32 bit;
-        u32 bank = s3c_get_bank(irq);
-
-        bit = s3c_eint_to_bit(irq);
-        __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank));
-}
-
-static void s3c_irq_vic_eint_maskack(unsigned int irq)
-{
-        /* compiler should in-line these */
-        s3c_irq_vic_eint_mask(irq);
-        s3c_irq_vic_eint_ack(irq);
-}
-
-static struct irq_chip s3c_irq_vic_eint = {
-        .name           = "EINT",
-        .mask           = s3c_irq_vic_eint_mask,
-        .unmask         = s3c_irq_vic_eint_unmask,
-        .mask_ack       = s3c_irq_vic_eint_maskack,
-        .ack            = s3c_irq_vic_eint_ack,
-        .set_type       = s3c_irq_eint_set_type,
-        .set_wake       = s3c_irqext_wake,
-};
-
-static int __init s5pc1xx_init_irq_eint(void)
-{
-        int irq;
-
-        for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) {
-                set_irq_chip(irq, &s3c_irq_vic_eint);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-
-        for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
-                set_irq_chip(irq, &s3c_irq_eint);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-
-        set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31);
-
-        return 0;
-}
-
-arch_initcall(s5pc1xx_init_irq_eint);
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
deleted file mode 100644
index bfc524827819..000000000000
--- a/arch/arm/plat-s5pc1xx/irq.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* arch/arm/plat-s5pc1xx/irq.c
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC1XX - Interrupt handling
- *
- * Based on plat-s3c64xx/irq.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/hardware/vic.h>
-
-#include <mach/map.h>
-#include <plat/irq-vic-timer.h>
-#include <plat/irq-uart.h>
-#include <plat/cpu.h>
-
-/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
- * are consecutive when looking up the interrupt in the demux routines.
- */
-static struct s3c_uart_irq uart_irqs[] = {
-        [0] = {
-                .regs           = (void *)S3C_VA_UART0,
-                .base_irq       = IRQ_S3CUART_BASE0,
-                .parent_irq     = IRQ_UART0,
-        },
-        [1] = {
-                .regs           = (void *)S3C_VA_UART1,
-                .base_irq       = IRQ_S3CUART_BASE1,
-                .parent_irq     = IRQ_UART1,
-        },
-        [2] = {
-                .regs           = (void *)S3C_VA_UART2,
-                .base_irq       = IRQ_S3CUART_BASE2,
-                .parent_irq     = IRQ_UART2,
-        },
-        [3] = {
-                .regs           = (void *)S3C_VA_UART3,
-                .base_irq       = IRQ_S3CUART_BASE3,
-                .parent_irq     = IRQ_UART3,
-        },
-};
-
-void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
-{
-        int i;
-
-        printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
-
-        /* initialise the pair of VICs */
-        for (i = 0; i < num; i++)
-                vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET),
-                                vic_valid[i], 0);
-
-        /* add the timer sub-irqs */
-
-        s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
-        s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
-        s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
-        s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
-        s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
-
-        s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
-}
-
-
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
deleted file mode 100644
index 2bf6c57a96a2..000000000000
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ /dev/null
@@ -1,876 +0,0 @@
-/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c
- *
- * Copyright 2009 Samsung Electronics, Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 based common clock support
- *
- * Based on plat-s3c64xx/s3c6400-clock.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/sysdev.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-
-#include <plat/cpu-freq.h>
-
-#include <plat/regs-clock.h>
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/devs.h>
-#include <plat/s5pc100.h>
-
-/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
- * ext_xtal_mux for want of an actual name from the manual.
-*/
-
-static struct clk clk_ext_xtal_mux = {
-        .name           = "ext_xtal",
-        .id             = -1,
-};
-
-#define clk_fin_apll clk_ext_xtal_mux
-#define clk_fin_mpll clk_ext_xtal_mux
-#define clk_fin_epll clk_ext_xtal_mux
-#define clk_fin_hpll clk_ext_xtal_mux
-
-#define clk_fout_mpll   clk_mpll
-#define clk_vclk_54m    clk_54m
-
-/* APLL */
-static struct clk clk_fout_apll = {
-        .name           = "fout_apll",
-        .id             = -1,
-        .rate           = 27000000,
-};
-
-static struct clk *clk_src_apll_list[] = {
-        [0] = &clk_fin_apll,
-        [1] = &clk_fout_apll,
-};
-
-static struct clksrc_sources clk_src_apll = {
-        .sources        = clk_src_apll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
-};
-
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_apll,
-        .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, },
-};
-
-static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK;
-        ratio >>= S5PC100_CLKDIV0_APLL_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_apll = {
-        .name           = "dout_apll",
-        .id             = -1,
-        .parent         = &clk_mout_apll.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_apll_get_rate,
-        },
-};
-
-static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK;
-        ratio >>= S5PC100_CLKDIV0_ARM_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk,
-                                                unsigned long rate)
-{
-        unsigned long parent = clk_get_rate(clk->parent);
-        u32 div;
-
-        if (parent < rate)
-                return rate;
-
-        div = (parent / rate) - 1;
-        if (div > S5PC100_CLKDIV0_ARM_MASK)
-                div = S5PC100_CLKDIV0_ARM_MASK;
-
-        return parent / (div + 1);
-}
-
-static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent = clk_get_rate(clk->parent);
-        u32 div;
-        u32 val;
-
-        if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1))
-                return -EINVAL;
-
-        rate = clk_round_rate(clk, rate);
-        div = clk_get_rate(clk->parent) / rate;
-
-        val = __raw_readl(S5PC100_CLKDIV0);
-        val &= S5PC100_CLKDIV0_ARM_MASK;
-        val |= (div - 1);
-        __raw_writel(val, S5PC100_CLKDIV0);
-
-        return 0;
-}
-
-static struct clk clk_arm = {
-        .name           = "armclk",
-        .id             = -1,
-        .parent         = &clk_dout_apll,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_arm_get_rate,
-                .set_rate       = s5pc100_clk_arm_set_rate,
-                .round_rate     = s5pc100_clk_arm_round_rate,
-        },
-};
-
-static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK;
-        ratio >>= S5PC100_CLKDIV0_D0_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_d0_bus = {
-        .name           = "dout_d0_bus",
-        .id             = -1,
-        .parent         = &clk_arm,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_d0_bus_get_rate,
-        },
-};
-
-static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK;
-        ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_pclkd0 = {
-        .name           = "dout_pclkd0",
-        .id             = -1,
-        .parent         = &clk_dout_d0_bus,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_pclkd0_get_rate,
-        },
-};
-
-static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK;
-        ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_apll2 = {
-        .name           = "dout_apll2",
-        .id             = -1,
-        .parent         = &clk_mout_apll.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_apll2_get_rate,
-        },
-};
-
-/* MPLL */
-static struct clk *clk_src_mpll_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &clk_fout_mpll,
-};
-
-static struct clksrc_sources clk_src_mpll = {
-        .sources        = clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
-};
-
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_mpll,
-        .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, },
-};
-
-static struct clk *clkset_am_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_dout_apll2,
-};
-
-static struct clksrc_sources clk_src_am = {
-        .sources        = clkset_am_list,
-        .nr_sources     = ARRAY_SIZE(clkset_am_list),
-};
-
-static struct clksrc_clk clk_mout_am = {
-        .clk = {
-                .name           = "mout_am",
-                .id             = -1,
-        },
-        .sources        = &clk_src_am,
-        .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, },
-};
-
-static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-
-        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK;
-        ratio >>= S5PC100_CLKDIV1_D1_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_d1_bus = {
-        .name           = "dout_d1_bus",
-        .id             = -1,
-        .parent         = &clk_mout_am.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_d1_bus_get_rate,
-        },
-};
-
-static struct clk *clkset_onenand_list[] = {
-        [0] = &clk_dout_d0_bus,
-        [1] = &clk_dout_d1_bus,
-};
-
-static struct clksrc_sources clk_src_onenand = {
-        .sources        = clkset_onenand_list,
-        .nr_sources     = ARRAY_SIZE(clkset_onenand_list),
-};
-
-static struct clksrc_clk clk_mout_onenand = {
-        .clk = {
-                .name           = "mout_onenand",
-                .id             = -1,
-        },
-        .sources        = &clk_src_onenand,
-        .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, },
-};
-
-static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-
-        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK;
-        ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_pclkd1 = {
-        .name           = "dout_pclkd1",
-        .id             = -1,
-        .parent         = &clk_dout_d1_bus,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_pclkd1_get_rate,
-        },
-};
-
-static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-
-        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
-        ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_mpll2 = {
-        .name           = "dout_mpll2",
-        .id             = -1,
-        .parent         = &clk_mout_am.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_mpll2_get_rate,
-        },
-};
-
-static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-
-        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK;
-        ratio >>= S5PC100_CLKDIV1_CAM_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_cam = {
-        .name           = "dout_cam",
-        .id             = -1,
-        .parent         = &clk_dout_mpll2,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_cam_get_rate,
-        },
-};
-
-static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned int ratio;
-
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-
-        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK;
-        ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT;
-
-        return rate / (ratio + 1);
-}
-
-static struct clk clk_dout_mpll = {
-        .name           = "dout_mpll",
-        .id             = -1,
-        .parent         = &clk_mout_am.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5pc100_clk_dout_mpll_get_rate,
-        },
-};
-
-/* EPLL */
-static struct clk clk_fout_epll = {
-        .name           = "fout_epll",
-        .id             = -1,
-};
-
-static struct clk *clk_src_epll_list[] = {
-        [0] = &clk_fin_epll,
-        [1] = &clk_fout_epll,
-};
-
-static struct clksrc_sources clk_src_epll = {
-        .sources        = clk_src_epll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
-};
-
-static struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-                .id             = -1,
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, },
-};
-
-/* HPLL */
-static struct clk clk_fout_hpll = {
-        .name           = "fout_hpll",
-        .id             = -1,
-};
-
-static struct clk *clk_src_hpll_list[] = {
-        [0] = &clk_27m,
-        [1] = &clk_fout_hpll,
-};
-
-static struct clksrc_sources clk_src_hpll = {
-        .sources        = clk_src_hpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_hpll_list),
-};
-
-static struct clksrc_clk clk_mout_hpll = {
-        .clk    = {
-                .name           = "mout_hpll",
-                .id             = -1,
-        },
-        .sources = &clk_src_hpll,
-        .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, },
-};
-
-/* Peripherals */
-/*
- * The peripheral clocks are all controlled via clocksource followed
- * by an optional divider and gate stage. We currently roll this into
- * one clock which hides the intermediate clock from the mux.
- *
- * Note, the JPEG clock can only be an even divider...
- *
- * The scaler and LCD clocks depend on the S5PC100 version, and also
- * have a common parent divisor so are not included here.
- */
-
-static struct clk clk_iis_cd0 = {
-        .name           = "iis_cdclk0",
-        .id             = -1,
-};
-
-static struct clk clk_iis_cd1 = {
-        .name           = "iis_cdclk1",
-        .id             = -1,
-};
-
-static struct clk clk_iis_cd2 = {
-        .name           = "iis_cdclk2",
-        .id             = -1,
-};
-
-static struct clk clk_pcm_cd0 = {
-        .name           = "pcm_cdclk0",
-        .id             = -1,
-};
-
-static struct clk clk_pcm_cd1 = {
-        .name           = "pcm_cdclk1",
-        .id             = -1,
-};
-
-static struct clk *clkset_audio0_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        &clk_fin_epll,
-        &clk_iis_cd0,
-        &clk_pcm_cd0,
-        &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clkset_audio0 = {
-        .sources        = clkset_audio0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
-};
-
-static struct clk *clkset_spi_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll2,
-        &clk_fin_epll,
-        &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clkset_spi = {
-        .sources        = clkset_spi_list,
-        .nr_sources     = ARRAY_SIZE(clkset_spi_list),
-};
-
-static struct clk *clkset_uart_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-};
-
-static struct clksrc_sources clkset_uart = {
-        .sources        = clkset_uart_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
-};
-
-static struct clk *clkset_audio1_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        &clk_fin_epll,
-        &clk_iis_cd1,
-        &clk_pcm_cd1,
-        &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clkset_audio1 = {
-        .sources        = clkset_audio1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
-};
-
-static struct clk *clkset_audio2_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        &clk_fin_epll,
-        &clk_iis_cd2,
-        &clk_mout_hpll.clk,
-};
-
-static struct clksrc_sources clkset_audio2 = {
-        .sources        = clkset_audio2_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
-};
-
-static struct clksrc_clk clksrc_audio[] = {
-        {
-                .clk    = {
-                        .name           = "audio-bus",
-                        .id             = 0,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO0,
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clkset_audio0,
-                .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, },
-        }, {
-                .clk    = {
-                        .name           = "audio-bus",
-                        .id             = 1,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO1,
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clkset_audio1,
-                .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, },
-        }, {
-                .clk    = {
-                        .name           = "audio-bus",
-                        .id             = 2,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO2,
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clkset_audio2,
-                .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, },
-        },
-};
-
-static struct clk *clkset_spdif_list[] = {
-        &clksrc_audio[0].clk,
-        &clksrc_audio[1].clk,
-        &clksrc_audio[2].clk,
-};
-
-static struct clksrc_sources clkset_spdif = {
-        .sources        = clkset_spdif_list,
-        .nr_sources     = ARRAY_SIZE(clkset_spdif_list),
-};
-
-static struct clk *clkset_lcd_fimc_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        &clk_mout_hpll.clk,
-        &clk_vclk_54m,
-};
-
-static struct clksrc_sources clkset_lcd_fimc = {
-        .sources        = clkset_lcd_fimc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_lcd_fimc_list),
-};
-
-static struct clk *clkset_mmc_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        &clk_fin_epll,
-        &clk_mout_hpll.clk ,
-};
-
-static struct clksrc_sources clkset_mmc = {
-        .sources        = clkset_mmc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mmc_list),
-};
-
-static struct clk *clkset_usbhost_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        &clk_mout_hpll.clk,
-        &clk_48m,
-};
-
-static struct clksrc_sources clkset_usbhost = {
-        .sources        = clkset_usbhost_list,
-        .nr_sources     = ARRAY_SIZE(clkset_usbhost_list),
-};
-
-static struct clksrc_clk clksrc_clks[] = {
-        {
-                .clk    = {
-                        .name           = "spi_bus",
-                        .id             = 0,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0,
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clkset_spi,
-                .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "spi_bus",
-                        .id             = 1,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1,
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clkset_spi,
-                .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "spi_bus",
-                        .id             = 2,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2,
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clkset_spi,
-                .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .id             = -1,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK0_UART,
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clkset_uart,
-                .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, },
-                .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, },
-        }, {
-                .clk    = {
-                        .name           = "spdif",
-                        .id             = -1,
-                },
-                .sources        = &clkset_spdif,
-                .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "lcd",
-                        .id             = -1,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK1_LCD,
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clkset_lcd_fimc,
-                .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "fimc",
-                        .id             = 0,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC0,
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clkset_lcd_fimc,
-                .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "fimc",
-                        .id             = 1,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC1,
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources        = &clkset_lcd_fimc,
-                .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "fimc",
-                        .id             = 2,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC2,
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clkset_lcd_fimc,
-                .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 0,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0,
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clkset_mmc,
-                .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 1,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1,
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clkset_mmc,
-                .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 2,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2,
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources        = &clkset_mmc,
-                .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
-        }, {
-                .clk    = {
-                        .name           = "usbhost",
-                        .id             = -1,
-                        .ctrlbit        = S5PC100_CLKGATE_SCLK0_USBHOST,
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clkset_usbhost,
-                .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
-                .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
-        }
-};
-
-/* Clock initialisation code */
-
-static struct clksrc_clk *init_parents[] = {
-        &clk_mout_apll,
-        &clk_mout_mpll,
-        &clk_mout_am,
-        &clk_mout_onenand,
-        &clk_mout_epll,
-        &clk_mout_hpll,
-};
-
-#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
-
-void __init_or_cpufreq s5pc100_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long hclkd0;
-        unsigned long hclk;
-        unsigned long pclkd0;
-        unsigned long pclk;
-        unsigned long apll, mpll, epll, hpll;
-        unsigned int ptr;
-        u32 clkdiv0, clkdiv1;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        clkdiv0 = __raw_readl(S5PC100_CLKDIV0);
-        clkdiv1 = __raw_readl(S5PC100_CLKDIV1);
-
-        printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
-        mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
-        epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
-        hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
-
-        printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
-                ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
-                print_mhz(apll), print_mhz(mpll),
-                print_mhz(epll), print_mhz(hpll));
-
-        armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL);
-        armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
-        hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
-        pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
-        hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
-        pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
-
-        printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz,"
-                " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz,"
-                " PCLK=%ld.%03ld MHz\n",
-                print_mhz(armclk), print_mhz(hclkd0),
-                print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk));
-
-        clk_fout_apll.rate = apll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_hpll.rate = hpll;
-
-        clk_h.rate = hclk;
-        clk_p.rate = pclk;
-        clk_f.rate = armclk;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
-                s3c_set_clksrc(init_parents[ptr], true);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
-                s3c_set_clksrc(clksrc_audio + ptr, true);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
-                s3c_set_clksrc(clksrc_clks + ptr, true);
-}
-
-static struct clk *clks[] __initdata = {
-        &clk_ext_xtal_mux,
-        &clk_dout_apll,
-        &clk_dout_d0_bus,
-        &clk_dout_pclkd0,
-        &clk_dout_apll2,
-        &clk_mout_apll.clk,
-        &clk_mout_mpll.clk,
-        &clk_mout_epll.clk,
-        &clk_mout_hpll.clk,
-        &clk_mout_am.clk,
-        &clk_dout_d1_bus,
-        &clk_mout_onenand.clk,
-        &clk_dout_pclkd1,
-        &clk_dout_mpll2,
-        &clk_dout_cam,
-        &clk_dout_mpll,
-        &clk_fout_epll,
-        &clk_iis_cd0,
-        &clk_iis_cd1,
-        &clk_iis_cd2,
-        &clk_pcm_cd0,
-        &clk_pcm_cd1,
-        &clk_arm,
-};
-
-void __init s5pc100_register_clocks(void)
-{
-        struct clk *clkp;
-        int ret;
-        int ptr;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
-                clkp = clks[ptr];
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-
-        s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio));
-        s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
-}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 229919e9744c..2753fb3e4f73 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,7 +6,7 @@
 
 config PLAT_SAMSUNG
         bool
-        depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX
+        depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX
         select NO_IOPORT
         default y
         help
@@ -170,6 +170,11 @@ config S3C_DEV_I2C1
         help
           Compile in platform device definitions for I2C channel 1
 
+config S3C_DEV_I2C2
+        bool
+        help
+          Compile in platform device definitions for I2C channel 2
+
 config S3C_DEV_FB
         bool
         help
@@ -185,11 +190,22 @@ config S3C_DEV_USB_HSOTG
         help
           Compile in platform device definition for USB high-speed OtG
 
+config S3C_DEV_WDT
+        bool
+        default y if ARCH_S3C2410
+        help
+          Complie in platform device definition for Watchdog Timer
+
 config S3C_DEV_NAND
         bool
         help
           Compile in platform device definition for NAND controller
 
+config S3C_DEV_ONENAND
+        bool
+        help
+          Compile in platform device definition for OneNAND controller
+
 config S3C_DEV_RTC
         bool
         help
@@ -269,4 +285,12 @@ config SAMSUNG_PM_CHECK_CHUNKSIZE
 
           See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
 
+config SAMSUNG_WAKEMASK
+        bool
+        depends on PM
+        help
+          Compile support for wakeup-mask controls found on the S3C6400
+          and above. This code allows a set of interrupt to wakeup-mask
+          mappings. See <plat/wakeup-mask.h>
+
 endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 48288499a3b9..b1d82cc5e716 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -36,11 +36,14 @@ obj-$(CONFIG_S3C_DEV_HSMMC2)	+= dev-hsmmc2.o
 obj-$(CONFIG_S3C_DEV_HWMON)     += dev-hwmon.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
+obj-$(CONFIG_S3C_DEV_I2C2)      += dev-i2c2.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
 obj-y                           += dev-uart.o
 obj-$(CONFIG_S3C_DEV_USB_HOST)  += dev-usb.o
 obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
+obj-$(CONFIG_S3C_DEV_WDT)       += dev-wdt.o
 obj-$(CONFIG_S3C_DEV_NAND)      += dev-nand.o
+obj-$(CONFIG_S3C_DEV_ONENAND)   += dev-onenand.o
 obj-$(CONFIG_S3C_DEV_RTC)       += dev-rtc.o
 
 obj-$(CONFIG_SAMSUNG_DEV_ADC)   += dev-adc.o
@@ -58,6 +61,8 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)                += pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)  += pm-check.o
 
+obj-$(CONFIG_SAMSUNG_WAKEMASK)  += wakeup-mask.o
+
 # PWM support
 
 obj-$(CONFIG_HAVE_PWM)          += pwm.o
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 210030d5cfe1..04d9521ddc9f 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -66,6 +66,7 @@ struct adc_device {
         struct s3c_adc_client   *cur;
         struct s3c_adc_client   *ts_pend;
         void __iomem            *regs;
+        spinlock_t               lock;
 
         unsigned int             prescale;
 
@@ -74,7 +75,7 @@ struct adc_device {
 
 static struct adc_device *adc_dev;
 
-static LIST_HEAD(adc_pending);
+static LIST_HEAD(adc_pending);  /* protected by adc_device.lock */
 
 #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
 
@@ -145,7 +146,7 @@ int s3c_adc_start(struct s3c_adc_client *client,
         if (client->is_ts && adc->ts_pend)
                 return -EAGAIN;
 
-        local_irq_save(flags);
+        spin_lock_irqsave(&adc->lock, flags);
 
         client->channel = channel;
         client->nr_samples = nr_samples;
@@ -157,7 +158,8 @@ int s3c_adc_start(struct s3c_adc_client *client,
 
         if (!adc->cur)
                 s3c_adc_try(adc);
-        local_irq_restore(flags);
+
+        spin_unlock_irqrestore(&adc->lock, flags);
 
         return 0;
 }
@@ -237,6 +239,10 @@ EXPORT_SYMBOL_GPL(s3c_adc_register);
 
 void s3c_adc_release(struct s3c_adc_client *client)
 {
+        unsigned long flags;
+
+        spin_lock_irqsave(&adc_dev->lock, flags);
+
         /* We should really check that nothing is in progress. */
         if (adc_dev->cur == client)
                 adc_dev->cur = NULL;
@@ -255,6 +261,8 @@ void s3c_adc_release(struct s3c_adc_client *client)
 
         if (adc_dev->cur == NULL)
                 s3c_adc_try(adc_dev);
+
+        spin_unlock_irqrestore(&adc_dev->lock, flags);
         kfree(client);
 }
 EXPORT_SYMBOL_GPL(s3c_adc_release);
@@ -264,7 +272,6 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
         struct adc_device *adc = pw;
         struct s3c_adc_client *client = adc->cur;
         enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
-        unsigned long flags;
         unsigned data0, data1;
 
         if (!client) {
@@ -296,12 +303,12 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
                 client->select_cb(client, 1);
                 s3c_adc_convert(adc);
         } else {
-                local_irq_save(flags);
+                spin_lock(&adc->lock);
                 (client->select_cb)(client, 0);
                 adc->cur = NULL;
 
                 s3c_adc_try(adc);
-                local_irq_restore(flags);
+                spin_unlock(&adc->lock);
         }
 
 exit:
@@ -326,6 +333,8 @@ static int s3c_adc_probe(struct platform_device *pdev)
                 return -ENOMEM;
         }
 
+        spin_lock_init(&adc->lock);
+
         adc->pdev = pdev;
         adc->prescale = S3C2410_ADCCON_PRSCVL(49);
 
@@ -407,13 +416,17 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
 static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
 {
         struct adc_device *adc = platform_get_drvdata(pdev);
+        unsigned long flags;
         u32 con;
 
+        spin_lock_irqsave(&adc->lock, flags);
+
         con = readl(adc->regs + S3C2410_ADCCON);
         con |= S3C2410_ADCCON_STDBM;
         writel(con, adc->regs + S3C2410_ADCCON);
 
         disable_irq(adc->irq);
+        spin_unlock_irqrestore(&adc->lock, flags);
         clk_disable(adc->clk);
 
         return 0;
@@ -422,6 +435,7 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
 static int s3c_adc_resume(struct platform_device *pdev)
 {
         struct adc_device *adc = platform_get_drvdata(pdev);
+        unsigned long flags;
 
         clk_enable(adc->clk);
         enable_irq(adc->irq);
diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c
new file mode 100644
index 000000000000..07036dee09e7
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-i2c2.c
@@ -0,0 +1,70 @@
+/* linux/arch/arm/plat-s3c/dev-i2c2.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S3C series device definition for i2c device 2
+ *
+ * Based on plat-samsung/dev-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+        [0] = {
+                .start = S3C_PA_IIC2,
+                .end   = S3C_PA_IIC2 + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_CAN0,
+                .end   = IRQ_CAN0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_i2c2 = {
+        .name             = "s3c2410-i2c",
+        .id               = 2,
+        .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
+        .resource         = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data2 __initdata = {
+        .flags          = 0,
+        .bus_num        = 2,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+};
+
+void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd)
+                pd = &default_i2c_data2;
+
+        npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        else if (!npd->cfg_gpio)
+                npd->cfg_gpio = s3c_i2c2_cfg_gpio;
+
+        s3c_device_i2c2.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dev-onenand.c b/arch/arm/plat-samsung/dev-onenand.c
new file mode 100644
index 000000000000..45ec73287d8c
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-onenand.c
@@ -0,0 +1,55 @@
+/*
+ * linux/arch/arm/plat-samsung/dev-onenand.c
+ *
+ *  Copyright (c) 2008-2010 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S3C64XX/S5PC100 series device definition for OneNAND devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+static struct resource s3c_onenand_resources[] = {
+        [0] = {
+                .start  = S3C_PA_ONENAND,
+                .end    = S3C_PA_ONENAND + 0x400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = S3C_PA_ONENAND_BUF,
+                .end    = S3C_PA_ONENAND_BUF + S3C_SZ_ONENAND_BUF - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = IRQ_ONENAND,
+                .end    = IRQ_ONENAND,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_onenand = {
+        .name           = "samsung-onenand",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s3c_onenand_resources),
+        .resource       = s3c_onenand_resources,
+};
+
+void s3c_onenand_set_platdata(struct onenand_platform_data *pdata)
+{
+        struct onenand_platform_data *pd;
+
+        pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
+        if (!pd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        s3c_device_onenand.dev.platform_data = pd;
+}
diff --git a/arch/arm/plat-samsung/dev-wdt.c b/arch/arm/plat-samsung/dev-wdt.c
new file mode 100644
index 000000000000..5efca87cddbd
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-wdt.c
@@ -0,0 +1,40 @@
+/* linux/arch/arm/plat-samsung/dev-wdt.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C series device definition for the watchdog timer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+static struct resource s3c_wdt_resource[] = {
+        [0] = {
+                .start  = S3C_PA_WDT,
+                .end    = S3C_PA_WDT + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_WDT,
+                .end    = IRQ_WDT,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device s3c_device_wdt = {
+        .name           = "s3c2410-wdt",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s3c_wdt_resource),
+        .resource       = s3c_wdt_resource,
+};
+EXPORT_SYMBOL(s3c_device_wdt);
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index ef69e56b2885..e6144e4b9118 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -45,6 +45,7 @@ extern struct platform_device s3c_device_lcd;
 extern struct platform_device s3c_device_wdt;
 extern struct platform_device s3c_device_i2c0;
 extern struct platform_device s3c_device_i2c1;
+extern struct platform_device s3c_device_i2c2;
 extern struct platform_device s3c_device_rtc;
 extern struct platform_device s3c_device_adc;
 extern struct platform_device s3c_device_sdi;
@@ -57,9 +58,20 @@ extern struct platform_device s3c_device_hsmmc2;
 extern struct platform_device s3c_device_spi0;
 extern struct platform_device s3c_device_spi1;
 
+extern struct platform_device s5pc100_device_spi0;
+extern struct platform_device s5pc100_device_spi1;
+extern struct platform_device s5pc100_device_spi2;
+extern struct platform_device s5pv210_device_spi0;
+extern struct platform_device s5pv210_device_spi1;
+extern struct platform_device s5p6440_device_spi0;
+extern struct platform_device s5p6440_device_spi1;
+
 extern struct platform_device s3c_device_hwmon;
 
 extern struct platform_device s3c_device_nand;
+extern struct platform_device s3c_device_onenand;
+extern struct platform_device s3c64xx_device_onenand1;
+extern struct platform_device s5pc110_device_onenand;
 
 extern struct platform_device s3c_device_usbgadget;
 extern struct platform_device s3c_device_usb_hsotg;
@@ -76,10 +88,18 @@ extern struct platform_device s5p6442_device_pcm0;
 extern struct platform_device s5p6442_device_pcm1;
 extern struct platform_device s5p6442_device_iis0;
 extern struct platform_device s5p6442_device_iis1;
+extern struct platform_device s5p6442_device_spi;
 
 extern struct platform_device s5p6440_device_pcm;
 extern struct platform_device s5p6440_device_iis;
 
+extern struct platform_device s5pc100_device_ac97;
+extern struct platform_device s5pc100_device_pcm0;
+extern struct platform_device s5pc100_device_pcm1;
+extern struct platform_device s5pc100_device_iis0;
+extern struct platform_device s5pc100_device_iis1;
+extern struct platform_device s5pc100_device_iis2;
+
 /* s3c2440 specific devices */
 
 #ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 1f85649d8c18..27d3b497b55b 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -84,4 +84,11 @@ extern void s3c64xx_fb_gpio_setup_24bpp(void);
  */
 extern void s5pc100_fb_gpio_setup_24bpp(void);
 
+/**
+ * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s5pv210_fb_gpio_setup_24bpp(void);
+
 #endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h
index 36397ca20962..f182669b8e8e 100644
--- a/arch/arm/plat-samsung/include/plat/iic-core.h
+++ b/arch/arm/plat-samsung/include/plat/iic-core.h
@@ -32,4 +32,11 @@ static inline void s3c_i2c1_setname(char *name)
 #endif
 }
 
+static inline void s3c_i2c2_setname(char *name)
+{
+#ifdef CONFIG_S3C_DEV_I2C2
+        s3c_device_i2c2.name = name;
+#endif
+}
+
 #endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
index 3083df00dee6..133308bf595d 100644
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -54,9 +54,11 @@ struct s3c2410_platform_i2c {
  */
 extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
 extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c);
 
 /* defined by architecture to configure gpio */
 extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
 extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c2_cfg_gpio(struct platform_device *dev);
 
 #endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/onenand-core.h b/arch/arm/plat-samsung/include/plat/onenand-core.h
new file mode 100644
index 000000000000..7701cb7020c8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/onenand-core.h
@@ -0,0 +1,37 @@
+/*
+ * linux/arch/arm/plat-samsung/onenand-core.h
+ *
+ *  Copyright (c) 2010 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *  Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * Samsung OneNAD Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_ONENAND_CORE_H
+#define __ASM_ARCH_ONENAND_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_onenand_setname(char *name)
+{
+#ifdef CONFIG_S3C_DEV_ONENAND
+        s3c_device_onenand.name = name;
+#endif
+}
+
+static inline void s3c64xx_onenand1_setname(char *name)
+{
+#ifdef CONFIG_S3C64XX_DEV_ONENAND1
+        s3c64xx_device_onenand1.name = name;
+#endif
+}
+
+#endif /* __ASM_ARCH_ONENAND_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-onenand.h b/arch/arm/plat-samsung/include/plat/regs-onenand.h
new file mode 100644
index 000000000000..930ea8b88ed3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-onenand.h
@@ -0,0 +1,63 @@
+/*
+ * linux/arch/arm/plat-s3c/include/plat/regs-onenand.h
+ *
+ *  Copyright (C) 2008-2010 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __SAMSUNG_ONENAND_H__
+#define __SAMSUNG_ONENAND_H__
+
+#include <mach/hardware.h>
+
+/*
+ * OneNAND Controller
+ */
+#define MEM_CFG_OFFSET          0x0000
+#define BURST_LEN_OFFSET        0x0010
+#define MEM_RESET_OFFSET        0x0020
+#define INT_ERR_STAT_OFFSET     0x0030
+#define INT_ERR_MASK_OFFSET     0x0040
+#define INT_ERR_ACK_OFFSET      0x0050
+#define ECC_ERR_STAT_OFFSET     0x0060
+#define MANUFACT_ID_OFFSET      0x0070
+#define DEVICE_ID_OFFSET        0x0080
+#define DATA_BUF_SIZE_OFFSET    0x0090
+#define BOOT_BUF_SIZE_OFFSET    0x00A0
+#define BUF_AMOUNT_OFFSET       0x00B0
+#define TECH_OFFSET             0x00C0
+#define FBA_WIDTH_OFFSET        0x00D0
+#define FPA_WIDTH_OFFSET        0x00E0
+#define FSA_WIDTH_OFFSET        0x00F0
+#define TRANS_SPARE_OFFSET      0x0140
+#define DBS_DFS_WIDTH_OFFSET    0x0160
+#define INT_PIN_ENABLE_OFFSET   0x01A0
+#define ACC_CLOCK_OFFSET        0x01C0
+#define FLASH_VER_ID_OFFSET     0x01F0
+#define FLASH_AUX_CNTRL_OFFSET  0x0300          /* s3c64xx only */
+
+#define ONENAND_MEM_RESET_HOT   0x3
+#define ONENAND_MEM_RESET_COLD  0x2
+#define ONENAND_MEM_RESET_WARM  0x1
+
+#define CACHE_OP_ERR            (1 << 13)
+#define RST_CMP                 (1 << 12)
+#define RDY_ACT                 (1 << 11)
+#define INT_ACT                 (1 << 10)
+#define UNSUP_CMD               (1 << 9)
+#define LOCKED_BLK              (1 << 8)
+#define BLK_RW_CMP              (1 << 7)
+#define ERS_CMP                 (1 << 6)
+#define PGM_CMP                 (1 << 5)
+#define LOAD_CMP                (1 << 4)
+#define ERS_FAIL                (1 << 3)
+#define PGM_FAIL                (1 << 2)
+#define INT_TO                  (1 << 1)
+#define LD_FAIL_ECC_ERR         (1 << 0)
+
+#define TSRF                    (1 << 0)
+
+#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index d17724149315..e5aba8f95b79 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -63,5 +63,9 @@ struct s3c64xx_spi_info {
  * has some chips attached to it.
  */
 extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+extern void s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 
 #endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 7d07cd7aa4f2..13f9fb20900a 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -75,6 +75,9 @@ extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 
 /* S3C6400 SDHCI setup */
 
@@ -218,4 +221,56 @@ static inline void s5pc100_default_sdhci1(void) { }
 static inline void s5pc100_default_sdhci2(void) { }
 #endif /* CONFIG_S5PC100_SETUP_SDHCI */
 
+
+/* S5PC110 SDHCI setup */
+#ifdef CONFIG_S5PV210_SETUP_SDHCI
+extern char *s5pv210_hsmmc_clksrcs[4];
+
+extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
+                                           void __iomem *r,
+                                           struct mmc_ios *ios,
+                                           struct mmc_card *card);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s5pv210_default_sdhci0(void)
+{
+        s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s5pv210_default_sdhci1(void)
+{
+        s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pv210_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s5pv210_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pv210_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
+
+#else
+static inline void s5pv210_default_sdhci0(void) { }
+static inline void s5pv210_default_sdhci1(void) { }
+static inline void s5pv210_default_sdhci2(void) { }
+#endif /* CONFIG_S5PC100_SETUP_SDHCI */
+
+
+
+
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/wakeup-mask.h b/arch/arm/plat-samsung/include/plat/wakeup-mask.h
new file mode 100644
index 000000000000..43e4acd2e1c6
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/wakeup-mask.h
@@ -0,0 +1,44 @@
+/* arch/arm/plat-samsung/include/plat/wakeup-mask.h
+ *
+ * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * Support for wakeup mask interrupts on newer SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#ifndef __PLAT_WAKEUP_MASK_H
+#define __PLAT_WAKEUP_MASK_H __file__
+
+/* if no irq yet defined, but still want to mask */
+#define NO_WAKEUP_IRQ (0x90000000)
+
+/**
+ * struct samsung_wakeup_mask - wakeup mask information
+ * @irq: The interrupt associated with this wakeup.
+ * @bit: The bit, as a (1 << bitno) controlling this source.
+ */ 
+struct samsung_wakeup_mask {
+        unsigned int    irq;
+        u32             bit;
+};
+
+/**
+ * samsung_sync_wakemask - sync wakeup mask information for pm
+ * @reg: The register that is used.
+ * @masks: The list of masks to use.
+ * @nr_masks: The number of entries pointed to buy @masks.
+ *
+ * Synchronise the wakeup mask information at suspend time from the list
+ * of interrupts and control bits in @masks. We do this at suspend time
+ * as overriding the relevant irq chips is harder and the register is only
+ * required to be correct before we enter sleep.
+ */
+extern void samsung_sync_wakemask(void __iomem *reg,
+                                  struct samsung_wakeup_mask *masks,
+                                  int nr_masks);
+
+#endif /* __PLAT_WAKEUP_MASK_H */
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index d50ab9d2af53..7df03f87fbfa 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -331,8 +331,10 @@ void s3c_pm_save_gpios(void)
 
         for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
                 ourchip = s3c_gpiolib_getchip(gpio_nr);
-                if (!ourchip)
+                if (!ourchip) {
+                        gpio_nr++;
                         continue;
+                }
 
                 s3c_pm_save_gpio(ourchip);
 
@@ -369,8 +371,10 @@ void s3c_pm_restore_gpios(void)
 
         for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
                 ourchip = s3c_gpiolib_getchip(gpio_nr);
-                if (!ourchip)
+                if (!ourchip) {
+                        gpio_nr++;
                         continue;
+                }
 
                 s3c_pm_resume_gpio(ourchip);
 
diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c
new file mode 100644
index 000000000000..2e09b6ad84ca
--- /dev/null
+++ b/arch/arm/plat-samsung/wakeup-mask.c
@@ -0,0 +1,47 @@
+/* arch/arm/plat-samsung/wakeup-mask.c
+ *
+ * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * Support for wakeup mask interrupts on newer SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/sysdev.h>
+#include <linux/types.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <plat/wakeup-mask.h>
+#include <plat/pm.h>
+
+void samsung_sync_wakemask(void __iomem *reg,
+                           struct samsung_wakeup_mask *mask, int nr_mask)
+{
+        struct irq_desc *desc;
+        u32 val;
+
+        val = __raw_readl(reg);
+
+        for (; nr_mask > 0; nr_mask--, mask++) {
+                if (mask->irq == NO_WAKEUP_IRQ) {
+                        val |= mask->bit;
+                        continue;
+                }
+
+                desc = irq_to_desc(mask->irq);
+
+                /* bit of a liberty to read this directly from irq_desc. */
+                if (desc->wake_depth > 0)
+                        val &= ~mask->bit;
+                else
+                        val |= mask->bit;
+        }
+
+        printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val);
+        __raw_writel(val, reg);
+}
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index 2dd4cfe7ca17..b9dee28ee7d0 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -296,6 +296,12 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr,
         card->type = MMC_TYPE_SDIO;
 
         /*
+         * Call the optional HC's init_card function to handle quirks.
+         */
+        if (host->ops->init_card)
+                host->ops->init_card(host, card);
+
+        /*
          * For native busses:  set card RCA and quit open drain mode.
          */
         if (!powered_resume && !mmc_host_is_spi(host)) {
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 2df90412abb5..ec18e3b60342 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -119,6 +119,7 @@ struct mxcmci_host {
         int                     detect_irq;
         int                     dma;
         int                     do_dma;
+        int                     use_sdio;
         unsigned int            power_mode;
         struct imxmmc_platform_data *pdata;
 
@@ -138,6 +139,7 @@ struct mxcmci_host {
         int                     clock;
 
         struct work_struct      datawork;
+        spinlock_t              lock;
 };
 
 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
@@ -151,6 +153,8 @@ static void mxcmci_softreset(struct mxcmci_host *host)
 {
         int i;
 
+        dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
+
         /* reset sequence */
         writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
         writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
@@ -224,6 +228,9 @@ static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
                 unsigned int cmdat)
 {
+        u32 int_cntr;
+        unsigned long flags;
+
         WARN_ON(host->cmd != NULL);
         host->cmd = cmd;
 
@@ -247,12 +254,16 @@ static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
                 return -EINVAL;
         }
 
+        int_cntr = INT_END_CMD_RES_EN;
+
         if (mxcmci_use_dma(host))
-                writel(INT_READ_OP_EN | INT_WRITE_OP_DONE_EN |
-                                INT_END_CMD_RES_EN,
-                                host->base + MMC_REG_INT_CNTR);
-        else
-                writel(INT_END_CMD_RES_EN, host->base + MMC_REG_INT_CNTR);
+                int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN;
+
+        spin_lock_irqsave(&host->lock, flags);
+        if (host->use_sdio)
+                int_cntr |= INT_SDIO_IRQ_EN;
+        writel(int_cntr, host->base + MMC_REG_INT_CNTR);
+        spin_unlock_irqrestore(&host->lock, flags);
 
         writew(cmd->opcode, host->base + MMC_REG_CMD);
         writel(cmd->arg, host->base + MMC_REG_ARG);
@@ -264,7 +275,14 @@ static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
 static void mxcmci_finish_request(struct mxcmci_host *host,
                 struct mmc_request *req)
 {
-        writel(0, host->base + MMC_REG_INT_CNTR);
+        u32 int_cntr = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->lock, flags);
+        if (host->use_sdio)
+                int_cntr |= INT_SDIO_IRQ_EN;
+        writel(int_cntr, host->base + MMC_REG_INT_CNTR);
+        spin_unlock_irqrestore(&host->lock, flags);
 
         host->req = NULL;
         host->cmd = NULL;
@@ -290,16 +308,25 @@ static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
                 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
                                 stat);
                 if (stat & STATUS_CRC_READ_ERR) {
+                        dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
                         data->error = -EILSEQ;
                 } else if (stat & STATUS_CRC_WRITE_ERR) {
                         u32 err_code = (stat >> 9) & 0x3;
-                        if (err_code == 2) /* No CRC response */
+                        if (err_code == 2) { /* No CRC response */
+                                dev_err(mmc_dev(host->mmc),
+                                        "%s: No CRC -ETIMEDOUT\n", __func__);
                                 data->error = -ETIMEDOUT;
-                        else
+                        } else {
+                                dev_err(mmc_dev(host->mmc),
+                                        "%s: -EILSEQ\n", __func__);
                                 data->error = -EILSEQ;
+                        }
                 } else if (stat & STATUS_TIME_OUT_READ) {
+                        dev_err(mmc_dev(host->mmc),
+                                "%s: read -ETIMEDOUT\n", __func__);
                         data->error = -ETIMEDOUT;
                 } else {
+                        dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
                         data->error = -EIO;
                 }
         } else {
@@ -433,8 +460,6 @@ static int mxcmci_transfer_data(struct mxcmci_host *host)
         struct scatterlist *sg;
         int stat, i;
 
-        host->datasize = 0;
-
         host->data = data;
         host->datasize = 0;
 
@@ -464,6 +489,9 @@ static void mxcmci_datawork(struct work_struct *work)
         struct mxcmci_host *host = container_of(work, struct mxcmci_host,
                                                   datawork);
         int datastat = mxcmci_transfer_data(host);
+
+        writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
+                host->base + MMC_REG_STATUS);
         mxcmci_finish_data(host, datastat);
 
         if (host->req->stop) {
@@ -523,15 +551,35 @@ static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
 static irqreturn_t mxcmci_irq(int irq, void *devid)
 {
         struct mxcmci_host *host = devid;
+        unsigned long flags;
+        bool sdio_irq;
         u32 stat;
 
         stat = readl(host->base + MMC_REG_STATUS);
-        writel(stat, host->base + MMC_REG_STATUS);
+        writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
+                        STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
 
         dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
 
+        spin_lock_irqsave(&host->lock, flags);
+        sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
+        spin_unlock_irqrestore(&host->lock, flags);
+
+#ifdef HAS_DMA
+        if (mxcmci_use_dma(host) &&
+            (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
+                writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
+                        host->base + MMC_REG_STATUS);
+#endif
+
+        if (sdio_irq) {
+                writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
+                mmc_signal_sdio_irq(host->mmc);
+        }
+
         if (stat & STATUS_END_CMD_RESP)
                 mxcmci_cmd_done(host, stat);
+
 #ifdef HAS_DMA
         if (mxcmci_use_dma(host) &&
                   (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
@@ -668,11 +716,46 @@ static int mxcmci_get_ro(struct mmc_host *mmc)
         return -ENOSYS;
 }
 
+static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+        struct mxcmci_host *host = mmc_priv(mmc);
+        unsigned long flags;
+        u32 int_cntr;
+
+        spin_lock_irqsave(&host->lock, flags);
+        host->use_sdio = enable;
+        int_cntr = readl(host->base + MMC_REG_INT_CNTR);
+
+        if (enable)
+                int_cntr |= INT_SDIO_IRQ_EN;
+        else
+                int_cntr &= ~INT_SDIO_IRQ_EN;
+
+        writel(int_cntr, host->base + MMC_REG_INT_CNTR);
+        spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
+{
+        /*
+         * MX3 SoCs have a silicon bug which corrupts CRC calculation of
+         * multi-block transfers when connected SDIO peripheral doesn't
+         * drive the BUSY line as required by the specs.
+         * One way to prevent this is to only allow 1-bit transfers.
+         */
+
+        if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO)
+                host->caps &= ~MMC_CAP_4_BIT_DATA;
+        else
+                host->caps |= MMC_CAP_4_BIT_DATA;
+}
 
 static const struct mmc_host_ops mxcmci_ops = {
-        .request        = mxcmci_request,
-        .set_ios        = mxcmci_set_ios,
-        .get_ro         = mxcmci_get_ro,
+        .request                = mxcmci_request,
+        .set_ios                = mxcmci_set_ios,
+        .get_ro                 = mxcmci_get_ro,
+        .enable_sdio_irq        = mxcmci_enable_sdio_irq,
+        .init_card              = mxcmci_init_card,
 };
 
 static int mxcmci_probe(struct platform_device *pdev)
@@ -700,7 +783,7 @@ static int mxcmci_probe(struct platform_device *pdev)
         }
 
         mmc->ops = &mxcmci_ops;
-        mmc->caps = MMC_CAP_4_BIT_DATA;
+        mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
 
         /* MMC core transfer sizes tunable parameters */
         mmc->max_hw_segs = 64;
@@ -719,6 +802,7 @@ static int mxcmci_probe(struct platform_device *pdev)
 
         host->mmc = mmc;
         host->pdata = pdev->dev.platform_data;
+        spin_lock_init(&host->lock);
 
         if (host->pdata && host->pdata->ocr_avail)
                 mmc->ocr_avail = host->pdata->ocr_avail;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index b2900d8406d3..fb03aff8e83a 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -38,7 +38,7 @@
 #define DRIVER_NAME "mxc_nand"
 
 #define nfc_is_v21()            (cpu_is_mx25() || cpu_is_mx35())
-#define nfc_is_v1()             (cpu_is_mx31() || cpu_is_mx27())
+#define nfc_is_v1()             (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
 
 /* Addresses for NFC registers */
 #define NFC_BUF_SIZE            0xE00
@@ -168,11 +168,7 @@ static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 {
         struct mxc_nand_host *host = dev_id;
 
-        uint16_t tmp;
-
-        tmp = readw(host->regs + NFC_CONFIG1);
-        tmp |= NFC_INT_MSK; /* Disable interrupt */
-        writew(tmp, host->regs + NFC_CONFIG1);
+        disable_irq_nosync(irq);
 
         wake_up(&host->irq_waitq);
 
@@ -184,15 +180,13 @@ static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
  */
 static void wait_op_done(struct mxc_nand_host *host, int useirq)
 {
-        uint32_t tmp;
-        int max_retries = 2000;
+        uint16_t tmp;
+        int max_retries = 8000;
 
         if (useirq) {
                 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
 
-                        tmp = readw(host->regs + NFC_CONFIG1);
-                        tmp  &= ~NFC_INT_MSK;   /* Enable interrupt */
-                        writew(tmp, host->regs + NFC_CONFIG1);
+                        enable_irq(host->irq);
 
                         wait_event(host->irq_waitq,
                                 readw(host->regs + NFC_CONFIG2) & NFC_INT);
@@ -226,8 +220,23 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
         writew(cmd, host->regs + NFC_FLASH_CMD);
         writew(NFC_CMD, host->regs + NFC_CONFIG2);
 
-        /* Wait for operation to complete */
-        wait_op_done(host, useirq);
+        if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
+                int max_retries = 100;
+                /* Reset completion is indicated by NFC_CONFIG2 */
+                /* being set to 0 */
+                while (max_retries-- > 0) {
+                        if (readw(host->regs + NFC_CONFIG2) == 0) {
+                                break;
+                        }
+                        udelay(1);
+                }
+                if (max_retries < 0)
+                        DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
+                              __func__);
+        } else {
+                /* Wait for operation to complete */
+                wait_op_done(host, useirq);
+        }
 }
 
 /* This function sends an address (or partial address) to the
@@ -542,6 +551,41 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
         }
 }
 
+static void preset(struct mtd_info *mtd)
+{
+        struct nand_chip *nand_chip = mtd->priv;
+        struct mxc_nand_host *host = nand_chip->priv;
+        uint16_t tmp;
+
+        /* enable interrupt, disable spare enable */
+        tmp = readw(host->regs + NFC_CONFIG1);
+        tmp &= ~NFC_INT_MSK;
+        tmp &= ~NFC_SP_EN;
+        if (nand_chip->ecc.mode == NAND_ECC_HW) {
+                tmp |= NFC_ECC_EN;
+        } else {
+                tmp &= ~NFC_ECC_EN;
+        }
+        writew(tmp, host->regs + NFC_CONFIG1);
+        /* preset operation */
+
+        /* Unlock the internal RAM Buffer */
+        writew(0x2, host->regs + NFC_CONFIG);
+
+        /* Blocks to be unlocked */
+        if (nfc_is_v21()) {
+                writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
+                writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
+        } else if (nfc_is_v1()) {
+                writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
+                writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
+        } else
+                BUG();
+
+        /* Unlock Block Command for given address range */
+        writew(0x4, host->regs + NFC_WRPROT);
+}
+
 /* Used by the upper layer to write command to NAND Flash for
  * different operations to be carried out on NAND Flash */
 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
@@ -559,6 +603,10 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 
         /* Command pre-processing step */
         switch (command) {
+        case NAND_CMD_RESET:
+                send_cmd(host, command, false);
+                preset(mtd);
+                break;
 
         case NAND_CMD_STATUS:
                 host->buf_start = 0;
@@ -679,7 +727,6 @@ static int __init mxcnd_probe(struct platform_device *pdev)
         struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
         struct mxc_nand_host *host;
         struct resource *res;
-        uint16_t tmp;
         int err = 0, nr_parts = 0;
         struct nand_ecclayout *oob_smallpage, *oob_largepage;
 
@@ -743,51 +790,17 @@ static int __init mxcnd_probe(struct platform_device *pdev)
                 host->spare_len = 64;
                 oob_smallpage = &nandv2_hw_eccoob_smallpage;
                 oob_largepage = &nandv2_hw_eccoob_largepage;
+                this->ecc.bytes = 9;
         } else if (nfc_is_v1()) {
                 host->regs = host->base;
                 host->spare0 = host->base + 0x800;
                 host->spare_len = 16;
                 oob_smallpage = &nandv1_hw_eccoob_smallpage;
                 oob_largepage = &nandv1_hw_eccoob_largepage;
-        } else
-                BUG();
-
-        /* disable interrupt and spare enable */
-        tmp = readw(host->regs + NFC_CONFIG1);
-        tmp |= NFC_INT_MSK;
-        tmp &= ~NFC_SP_EN;
-        writew(tmp, host->regs + NFC_CONFIG1);
-
-        init_waitqueue_head(&host->irq_waitq);
-
-        host->irq = platform_get_irq(pdev, 0);
-
-        err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
-        if (err)
-                goto eirq;
-
-        /* Reset NAND */
-        this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
-
-        /* preset operation */
-        /* Unlock the internal RAM Buffer */
-        writew(0x2, host->regs + NFC_CONFIG);
-
-        /* Blocks to be unlocked */
-        if (nfc_is_v21()) {
-                writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
-                writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
-                this->ecc.bytes = 9;
-        } else if (nfc_is_v1()) {
-                writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
-                writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
                 this->ecc.bytes = 3;
         } else
                 BUG();
 
-        /* Unlock Block Command for given address range */
-        writew(0x4, host->regs + NFC_WRPROT);
-
         this->ecc.size = 512;
         this->ecc.layout = oob_smallpage;
 
@@ -796,14 +809,8 @@ static int __init mxcnd_probe(struct platform_device *pdev)
                 this->ecc.hwctl = mxc_nand_enable_hwecc;
                 this->ecc.correct = mxc_nand_correct_data;
                 this->ecc.mode = NAND_ECC_HW;
-                tmp = readw(host->regs + NFC_CONFIG1);
-                tmp |= NFC_ECC_EN;
-                writew(tmp, host->regs + NFC_CONFIG1);
         } else {
                 this->ecc.mode = NAND_ECC_SOFT;
-                tmp = readw(host->regs + NFC_CONFIG1);
-                tmp &= ~NFC_ECC_EN;
-                writew(tmp, host->regs + NFC_CONFIG1);
         }
 
         /* NAND bus width determines access funtions used by upper layer */
@@ -817,6 +824,14 @@ static int __init mxcnd_probe(struct platform_device *pdev)
                 this->options |= NAND_USE_FLASH_BBT;
         }
 
+        init_waitqueue_head(&host->irq_waitq);
+
+        host->irq = platform_get_irq(pdev, 0);
+
+        err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
+        if (err)
+                goto eirq;
+
         /* first scan to find the device and get the page size */
         if (nand_scan_ident(mtd, 1)) {
                 err = -ENXIO;
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index ead59f42e69b..544ccfd7056e 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -199,8 +199,8 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
         writel(pdata->portsc, hcd->regs + PORTSC_OFFSET);
         mdelay(10);
 
-        /* setup USBCONTROL. */
-        ret = mxc_set_usbcontrol(pdev->id, pdata->flags);
+        /* setup specific usb hw */
+        ret = mxc_initialize_usb_hw(pdev->id, pdata->flags);
         if (ret < 0)
                 goto err_init;
 
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 43eaf5ca5848..3196c84cc630 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -108,6 +108,9 @@ struct mmc_host_ops {
         int     (*get_cd)(struct mmc_host *host);
 
         void    (*enable_sdio_irq)(struct mmc_host *host, int enable);
+
+        /* optional callback for HC quirks */
+        void    (*init_card)(struct mmc_host *host, struct mmc_card *card);
 };
 
 struct mmc_card;