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-rw-r--r--drivers/ssb/main.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index ee2937c41424..f8a13f863217 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1332,21 +1332,27 @@ EXPORT_SYMBOL(ssb_bus_powerup);
1332static void ssb_broadcast_value(struct ssb_device *dev, 1332static void ssb_broadcast_value(struct ssb_device *dev,
1333 u32 address, u32 data) 1333 u32 address, u32 data)
1334{ 1334{
1335#ifdef CONFIG_SSB_DRIVER_PCICORE
1335 /* This is used for both, PCI and ChipCommon core, so be careful. */ 1336 /* This is used for both, PCI and ChipCommon core, so be careful. */
1336 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 1337 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1337 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 1338 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1339#endif
1338 1340
1339 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); 1341 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1340 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ 1342 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1341 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); 1343 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1342 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ 1344 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1343} 1345}
1344 1346
1345void ssb_commit_settings(struct ssb_bus *bus) 1347void ssb_commit_settings(struct ssb_bus *bus)
1346{ 1348{
1347 struct ssb_device *dev; 1349 struct ssb_device *dev;
1348 1350
1351#ifdef CONFIG_SSB_DRIVER_PCICORE
1349 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 1352 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1353#else
1354 dev = bus->chipco.dev;
1355#endif
1350 if (WARN_ON(!dev)) 1356 if (WARN_ON(!dev))
1351 return; 1357 return;
1352 /* This forces an update of the cached registers. */ 1358 /* This forces an update of the cached registers. */