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-rw-r--r--drivers/gpu/drm/radeon/ni.c16
-rw-r--r--drivers/gpu/drm/radeon/nid.h1
2 files changed, 8 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index af45b23675ee..647b1d0fa62c 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1331,13 +1331,12 @@ void cayman_fence_ring_emit(struct radeon_device *rdev,
1331{ 1331{
1332 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1332 struct radeon_ring *ring = &rdev->ring[fence->ring];
1333 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1333 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1334 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1335 PACKET3_SH_ACTION_ENA;
1334 1336
1335 /* flush read cache over gart for this vmid */ 1337 /* flush read cache over gart for this vmid */
1336 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1337 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1338 radeon_ring_write(ring, 0);
1339 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1338 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1340 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); 1339 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1341 radeon_ring_write(ring, 0xFFFFFFFF); 1340 radeon_ring_write(ring, 0xFFFFFFFF);
1342 radeon_ring_write(ring, 0); 1341 radeon_ring_write(ring, 0);
1343 radeon_ring_write(ring, 10); /* poll interval */ 1342 radeon_ring_write(ring, 10); /* poll interval */
@@ -1353,6 +1352,8 @@ void cayman_fence_ring_emit(struct radeon_device *rdev,
1353void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1352void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1354{ 1353{
1355 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1354 struct radeon_ring *ring = &rdev->ring[ib->ring];
1355 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1356 PACKET3_SH_ACTION_ENA;
1356 1357
1357 /* set to DX10/11 mode */ 1358 /* set to DX10/11 mode */
1358 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1359 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
@@ -1377,14 +1378,11 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1377 (ib->vm ? (ib->vm->id << 24) : 0)); 1378 (ib->vm ? (ib->vm->id << 24) : 0));
1378 1379
1379 /* flush read cache over gart for this vmid */ 1380 /* flush read cache over gart for this vmid */
1380 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1381 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1382 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
1383 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1381 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1384 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); 1382 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1385 radeon_ring_write(ring, 0xFFFFFFFF); 1383 radeon_ring_write(ring, 0xFFFFFFFF);
1386 radeon_ring_write(ring, 0); 1384 radeon_ring_write(ring, 0);
1387 radeon_ring_write(ring, 10); /* poll interval */ 1385 radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */
1388} 1386}
1389 1387
1390static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1388static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 22421bc80c0d..d996033c243e 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -1154,6 +1154,7 @@
1154# define PACKET3_DB_ACTION_ENA (1 << 26) 1154# define PACKET3_DB_ACTION_ENA (1 << 26)
1155# define PACKET3_SH_ACTION_ENA (1 << 27) 1155# define PACKET3_SH_ACTION_ENA (1 << 27)
1156# define PACKET3_SX_ACTION_ENA (1 << 28) 1156# define PACKET3_SX_ACTION_ENA (1 << 28)
1157# define PACKET3_ENGINE_ME (1 << 31)
1157#define PACKET3_ME_INITIALIZE 0x44 1158#define PACKET3_ME_INITIALIZE 0x44
1158#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1159#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1159#define PACKET3_COND_WRITE 0x45 1160#define PACKET3_COND_WRITE 0x45