aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/vic.txt12
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/s3c6400.dtsi41
-rw-r--r--arch/arm/boot/dts/s3c6410-mini6410.dts228
-rw-r--r--arch/arm/boot/dts/s3c6410-smdk6410.dts103
-rw-r--r--arch/arm/boot/dts/s3c6410.dtsi57
-rw-r--r--arch/arm/boot/dts/s3c64xx-pinctrl.dtsi687
-rw-r--r--arch/arm/boot/dts/s3c64xx.dtsi199
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig16
-rw-r--r--arch/arm/mach-s3c64xx/Makefile3
-rw-r--r--arch/arm/mach-s3c64xx/clock.c1007
-rw-r--r--arch/arm/mach-s3c64xx/common.c33
-rw-r--r--arch/arm/mach-s3c64xx/common.h12
-rw-r--r--arch/arm/mach-s3c64xx/dma.c13
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-clock.h132
-rw-r--r--arch/arm/mach-s3c64xx/irq-pm.c9
-rw-r--r--arch/arm/mach-s3c64xx/mach-anw6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-hmt.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-mini6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-ncp.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c85
-rw-r--r--arch/arm/mach-s3c64xx/mach-smartq.c11
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6400.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/pm.c21
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c15
-rw-r--r--arch/arm/mach-s3c64xx/s3c6410.c16
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h4
-rw-r--r--arch/arm/plat-samsung/init.c12
-rw-r--r--drivers/clk/samsung/Makefile2
-rw-r--r--drivers/gpio/gpio-samsung.c34
-rw-r--r--drivers/irqchip/irq-vic.c7
-rw-r--r--drivers/usb/host/ohci-s3c2410.c8
35 files changed, 1550 insertions, 1235 deletions
diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
index 266716b23437..dd527216c5fb 100644
--- a/Documentation/devicetree/bindings/arm/vic.txt
+++ b/Documentation/devicetree/bindings/arm/vic.txt
@@ -18,6 +18,15 @@ Required properties:
18Optional properties: 18Optional properties:
19 19
20- interrupts : Interrupt source for parent controllers if the VIC is nested. 20- interrupts : Interrupt source for parent controllers if the VIC is nested.
21- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
22 represents single interrupt source, starting from source 0 at LSb and ending
23 at source 31 at MSb. A bit that is set means that the source is wired and
24 clear means otherwise. If unspecified, defaults to all valid.
25- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be
26 configured as wake up source for the system. Order of bits is the same as for
27 valid-mask property. A set bit means that this interrupt source can be
28 configured as a wake up source for the system. If unspecied, defaults to all
29 interrupt sources configurable as wake up sources.
21 30
22Example: 31Example:
23 32
@@ -26,4 +35,7 @@ Example:
26 interrupt-controller; 35 interrupt-controller;
27 #interrupt-cells = <1>; 36 #interrupt-cells = <1>;
28 reg = <0x60000 0x1000>; 37 reg = <0x60000 0x1000>;
38
39 valid-mask = <0xffffff7f>;
40 valid-wakeup-mask = <0x0000ff7f>;
29 }; 41 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f7714d8d2d2..76b025e3a74a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -727,6 +727,7 @@ config ARCH_S3C64XX
727 select ARM_VIC 727 select ARM_VIC
728 select CLKDEV_LOOKUP 728 select CLKDEV_LOOKUP
729 select CLKSRC_SAMSUNG_PWM 729 select CLKSRC_SAMSUNG_PWM
730 select COMMON_CLK
730 select CPU_V6 731 select CPU_V6
731 select GENERIC_CLOCKEVENTS 732 select GENERIC_CLOCKEVENTS
732 select GPIO_SAMSUNG 733 select GPIO_SAMSUNG
@@ -740,7 +741,6 @@ config ARCH_S3C64XX
740 select S3C_DEV_NAND 741 select S3C_DEV_NAND
741 select S3C_GPIO_TRACK 742 select S3C_GPIO_TRACK
742 select SAMSUNG_ATAGS 743 select SAMSUNG_ATAGS
743 select SAMSUNG_CLKSRC
744 select SAMSUNG_GPIOLIB_4BIT 744 select SAMSUNG_GPIOLIB_4BIT
745 select SAMSUNG_WDT_RESET 745 select SAMSUNG_WDT_RESET
746 select USB_ARCH_HAS_OHCI 746 select USB_ARCH_HAS_OHCI
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e95af3f5433b..7ec6985a5315 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -195,6 +195,8 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
195 ste-ccu8540.dtb \ 195 ste-ccu8540.dtb \
196 ste-ccu9540.dtb 196 ste-ccu9540.dtb
197dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 197dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
198dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
199 s3c6410-smdk6410.dtb
198dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 200dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
199 emev2-kzm9d-reference.dtb \ 201 emev2-kzm9d-reference.dtb \
200 r8a7740-armadillo800eva.dtb \ 202 r8a7740-armadillo800eva.dtb \
diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi
new file mode 100644
index 000000000000..a7d1c8ec150d
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6400.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Samsung's S3C6400 SoC device tree source
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
7 * based board files can include this file and provide values for board specfic
8 * bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
12 * nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17*/
18
19#include "s3c64xx.dtsi"
20
21/ {
22 compatible = "samsung,s3c6400";
23};
24
25&vic0 {
26 valid-mask = <0xfffffe1f>;
27 valid-wakeup-mask = <0x00200004>;
28};
29
30&vic1 {
31 valid-mask = <0xffffffff>;
32 valid-wakeup-mask = <0x53020000>;
33};
34
35&soc {
36 clocks: clock-controller@7e00f000 {
37 compatible = "samsung,s3c6400-clock";
38 reg = <0x7e00f000 0x1000>;
39 #clock-cells = <1>;
40 };
41};
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts
new file mode 100644
index 000000000000..57e00f9bce99
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -0,0 +1,228 @@
1/*
2 * Samsung's S3C6410 based Mini6410 board device tree source
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Device tree source file for FriendlyARM Mini6410 board which is based on
7 * Samsung's S3C6410 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/dts-v1/;
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19#include "s3c6410.dtsi"
20
21/ {
22 model = "FriendlyARM Mini6410 board based on S3C6410";
23 compatible = "friendlyarm,mini6410", "samsung,s3c6410";
24
25 memory {
26 reg = <0x50000000 0x10000000>;
27 };
28
29 chosen {
30 bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
31 };
32
33 clocks {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 fin_pll: oscillator@0 {
39 compatible = "fixed-clock";
40 reg = <0>;
41 clock-frequency = <12000000>;
42 clock-output-names = "fin_pll";
43 #clock-cells = <0>;
44 };
45
46 xusbxti: oscillator@1 {
47 compatible = "fixed-clock";
48 reg = <1>;
49 clock-output-names = "xusbxti";
50 clock-frequency = <48000000>;
51 #clock-cells = <0>;
52 };
53 };
54
55 srom-cs1@18000000 {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 reg = <0x18000000 0x8000000>;
60 ranges;
61
62 ethernet@18000000 {
63 compatible = "davicom,dm9000";
64 reg = <0x18000000 0x2 0x18000004 0x2>;
65 interrupt-parent = <&gpn>;
66 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
67 davicom,no-eeprom;
68 };
69 };
70
71 gpio-keys {
72 compatible = "gpio-keys";
73 pinctrl-names = "default";
74 pinctrl-0 = <&gpio_keys>;
75 autorepeat;
76
77 button-k1 {
78 label = "K1";
79 gpios = <&gpn 0 GPIO_ACTIVE_LOW>;
80 linux,code = <2>;
81 debounce-interval = <20>;
82 };
83
84 button-k2 {
85 label = "K2";
86 gpios = <&gpn 1 GPIO_ACTIVE_LOW>;
87 linux,code = <3>;
88 debounce-interval = <20>;
89 };
90
91 button-k3 {
92 label = "K3";
93 gpios = <&gpn 2 GPIO_ACTIVE_LOW>;
94 linux,code = <4>;
95 debounce-interval = <20>;
96 };
97
98 button-k4 {
99 label = "K4";
100 gpios = <&gpn 3 GPIO_ACTIVE_LOW>;
101 linux,code = <5>;
102 debounce-interval = <20>;
103 };
104
105 button-k5 {
106 label = "K5";
107 gpios = <&gpn 4 GPIO_ACTIVE_LOW>;
108 linux,code = <6>;
109 debounce-interval = <20>;
110 };
111
112 button-k6 {
113 label = "K6";
114 gpios = <&gpn 5 GPIO_ACTIVE_LOW>;
115 linux,code = <7>;
116 debounce-interval = <20>;
117 };
118
119 button-k7 {
120 label = "K7";
121 gpios = <&gpl 11 GPIO_ACTIVE_LOW>;
122 linux,code = <8>;
123 debounce-interval = <20>;
124 };
125
126 button-k8 {
127 label = "K8";
128 gpios = <&gpl 12 GPIO_ACTIVE_LOW>;
129 linux,code = <9>;
130 debounce-interval = <20>;
131 };
132 };
133
134 leds {
135 compatible = "gpio-leds";
136 pinctrl-names = "default";
137 pinctrl-0 = <&gpio_leds>;
138
139 led-1 {
140 label = "LED1";
141 gpios = <&gpk 4 GPIO_ACTIVE_LOW>;
142 linux,default-trigger = "heartbeat";
143 };
144
145 led-2 {
146 label = "LED2";
147 gpios = <&gpk 5 GPIO_ACTIVE_LOW>;
148 linux,default-trigger = "mmc0";
149 };
150
151 led-3 {
152 label = "LED3";
153 gpios = <&gpk 6 GPIO_ACTIVE_LOW>;
154 };
155
156 led-4 {
157 label = "LED4";
158 gpios = <&gpk 7 GPIO_ACTIVE_LOW>;
159 };
160 };
161
162 buzzer {
163 compatible = "pwm-beeper";
164 pwms = <&pwm 0 1000000 0>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pwm0_out>;
167 };
168};
169
170&sdhci0 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
173 bus-width = <4>;
174 status = "okay";
175};
176
177&uart0 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&uart0_data>;
180 status = "okay";
181};
182
183&uart1 {
184 pinctrl-names = "default";
185 pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
186 status = "okay";
187};
188
189&uart2 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&uart2_data>;
192 status = "okay";
193};
194
195&uart3 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&uart3_data>;
198 status = "okay";
199};
200
201&pwm {
202 status = "okay";
203};
204
205&pinctrl0 {
206 gpio_leds: gpio-leds {
207 samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7";
208 samsung,pin-pud = <PIN_PULL_NONE>;
209 };
210
211 gpio_keys: gpio-keys {
212 samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3",
213 "gpn-4", "gpn-5", "gpl-11", "gpl-12";
214 samsung,pin-pud = <PIN_PULL_NONE>;
215 };
216};
217
218&i2c0 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c0_bus>;
221 status = "okay";
222
223 eeprom@50 {
224 compatible = "atmel,24c08";
225 reg = <0x50>;
226 pagesize = <16>;
227 };
228};
diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts
new file mode 100644
index 000000000000..ecf35ec466f7
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts
@@ -0,0 +1,103 @@
1/*
2 * Samsung S3C6410 based SMDK6410 board device tree source.
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Device tree source file for SAMSUNG SMDK6410 board which is based on
7 * Samsung's S3C6410 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/dts-v1/;
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19#include "s3c6410.dtsi"
20
21/ {
22 model = "SAMSUNG SMDK6410 board based on S3C6410";
23 compatible = "samsung,mini6410", "samsung,s3c6410";
24
25 memory {
26 reg = <0x50000000 0x8000000>;
27 };
28
29 chosen {
30 bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
31 };
32
33 clocks {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 fin_pll: oscillator@0 {
39 compatible = "fixed-clock";
40 reg = <0>;
41 clock-frequency = <12000000>;
42 clock-output-names = "fin_pll";
43 #clock-cells = <0>;
44 };
45
46 xusbxti: oscillator@1 {
47 compatible = "fixed-clock";
48 reg = <1>;
49 clock-output-names = "xusbxti";
50 clock-frequency = <48000000>;
51 #clock-cells = <0>;
52 };
53 };
54
55 srom-cs1@18000000 {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 reg = <0x18000000 0x8000000>;
60 ranges;
61
62 ethernet@18000000 {
63 compatible = "smsc,lan9115";
64 reg = <0x18000000 0x10000>;
65 interrupt-parent = <&gpn>;
66 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
67 phy-mode = "mii";
68 reg-io-width = <4>;
69 smsc,force-internal-phy;
70 };
71 };
72};
73
74&sdhci0 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
77 bus-width = <4>;
78 status = "okay";
79};
80
81&uart0 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
84 status = "okay";
85};
86
87&uart1 {
88 pinctrl-names = "default";
89 pinctrl-0 = <&uart1_data>;
90 status = "okay";
91};
92
93&uart2 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&uart2_data>;
96 status = "okay";
97};
98
99&uart3 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&uart3_data>;
102 status = "okay";
103};
diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi
new file mode 100644
index 000000000000..eb4226b3407c
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410.dtsi
@@ -0,0 +1,57 @@
1/*
2 * Samsung's S3C6410 SoC device tree source
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410
7 * based board files can include this file and provide values for board specfic
8 * bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional
12 * nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17*/
18
19#include "s3c64xx.dtsi"
20
21/ {
22 compatible = "samsung,s3c6410";
23
24 aliases {
25 i2c1 = &i2c1;
26 };
27};
28
29&vic0 {
30 valid-mask = <0xffffff7f>;
31 valid-wakeup-mask = <0x00200004>;
32};
33
34&vic1 {
35 valid-mask = <0xffffffff>;
36 valid-wakeup-mask = <0x53020000>;
37};
38
39&soc {
40 clocks: clock-controller@7e00f000 {
41 compatible = "samsung,s3c6410-clock";
42 reg = <0x7e00f000 0x1000>;
43 #clock-cells = <1>;
44 };
45
46 i2c1: i2c@7f00f000 {
47 compatible = "samsung,s3c2440-i2c";
48 reg = <0x7f00f000 0x1000>;
49 interrupt-parent = <&vic0>;
50 interrupts = <5>;
51 clock-names = "i2c";
52 clocks = <&clocks PCLK_IIC1>;
53 status = "disabled";
54 #address-cells = <1>;
55 #size-cells = <0>;
56 };
57};
diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
new file mode 100644
index 000000000000..b1197d8b04de
--- /dev/null
+++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
@@ -0,0 +1,687 @@
1/*
2 * Samsung's S3C64xx SoC series common device tree source
3 * - pin control-related definitions
4 *
5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6 *
7 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
8 * listed as device tree nodes in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define PIN_PULL_NONE 0
16#define PIN_PULL_DOWN 1
17#define PIN_PULL_UP 2
18
19&pinctrl0 {
20 /*
21 * Pin banks
22 */
23
24 gpa: gpa {
25 gpio-controller;
26 #gpio-cells = <2>;
27 interrupt-controller;
28 #interrupt-cells = <2>;
29 };
30
31 gpb: gpb {
32 gpio-controller;
33 #gpio-cells = <2>;
34 interrupt-controller;
35 #interrupt-cells = <2>;
36 };
37
38 gpc: gpc {
39 gpio-controller;
40 #gpio-cells = <2>;
41 interrupt-controller;
42 #interrupt-cells = <2>;
43 };
44
45 gpd: gpd {
46 gpio-controller;
47 #gpio-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
50 };
51
52 gpe: gpe {
53 gpio-controller;
54 #gpio-cells = <2>;
55 };
56
57 gpf: gpf {
58 gpio-controller;
59 #gpio-cells = <2>;
60 interrupt-controller;
61 #interrupt-cells = <2>;
62 };
63
64 gpg: gpg {
65 gpio-controller;
66 #gpio-cells = <2>;
67 interrupt-controller;
68 #interrupt-cells = <2>;
69 };
70
71 gph: gph {
72 gpio-controller;
73 #gpio-cells = <2>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
76 };
77
78 gpi: gpi {
79 gpio-controller;
80 #gpio-cells = <2>;
81 };
82
83 gpj: gpj {
84 gpio-controller;
85 #gpio-cells = <2>;
86 };
87
88 gpk: gpk {
89 gpio-controller;
90 #gpio-cells = <2>;
91 };
92
93 gpl: gpl {
94 gpio-controller;
95 #gpio-cells = <2>;
96 interrupt-controller;
97 #interrupt-cells = <2>;
98 };
99
100 gpm: gpm {
101 gpio-controller;
102 #gpio-cells = <2>;
103 interrupt-controller;
104 #interrupt-cells = <2>;
105 };
106
107 gpn: gpn {
108 gpio-controller;
109 #gpio-cells = <2>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 };
113
114 gpo: gpo {
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
121 gpp: gpp {
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 };
127
128 gpq: gpq {
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 /*
136 * Pin groups
137 */
138
139 uart0_data: uart0-data {
140 samsung,pins = "gpa-0", "gpa-1";
141 samsung,pin-function = <2>;
142 samsung,pin-pud = <PIN_PULL_NONE>;
143 };
144
145 uart0_fctl: uart0-fctl {
146 samsung,pins = "gpa-2", "gpa-3";
147 samsung,pin-function = <2>;
148 samsung,pin-pud = <PIN_PULL_NONE>;
149 };
150
151 uart1_data: uart1-data {
152 samsung,pins = "gpa-4", "gpa-5";
153 samsung,pin-function = <2>;
154 samsung,pin-pud = <PIN_PULL_NONE>;
155 };
156
157 uart1_fctl: uart1-fctl {
158 samsung,pins = "gpa-6", "gpa-7";
159 samsung,pin-function = <2>;
160 samsung,pin-pud = <PIN_PULL_NONE>;
161 };
162
163 uart2_data: uart2-data {
164 samsung,pins = "gpb-0", "gpb-1";
165 samsung,pin-function = <2>;
166 samsung,pin-pud = <PIN_PULL_NONE>;
167 };
168
169 uart3_data: uart3-data {
170 samsung,pins = "gpb-2", "gpb-3";
171 samsung,pin-function = <2>;
172 samsung,pin-pud = <PIN_PULL_NONE>;
173 };
174
175 ext_dma_0: ext-dma-0 {
176 samsung,pins = "gpb-0", "gpb-1";
177 samsung,pin-function = <3>;
178 samsung,pin-pud = <PIN_PULL_NONE>;
179 };
180
181 ext_dma_1: ext-dma-1 {
182 samsung,pins = "gpb-2", "gpb-3";
183 samsung,pin-function = <4>;
184 samsung,pin-pud = <PIN_PULL_NONE>;
185 };
186
187 irda_data_0: irda-data-0 {
188 samsung,pins = "gpb-0", "gpb-1";
189 samsung,pin-function = <4>;
190 samsung,pin-pud = <PIN_PULL_NONE>;
191 };
192
193 irda_data_1: irda-data-1 {
194 samsung,pins = "gpb-2", "gpb-3";
195 samsung,pin-function = <3>;
196 samsung,pin-pud = <PIN_PULL_NONE>;
197 };
198
199 irda_sdbw: irda-sdbw {
200 samsung,pins = "gpb-4";
201 samsung,pin-function = <2>;
202 samsung,pin-pud = <PIN_PULL_NONE>;
203 };
204
205 i2c0_bus: i2c0-bus {
206 samsung,pins = "gpb-5", "gpb-6";
207 samsung,pin-function = <2>;
208 samsung,pin-pud = <PIN_PULL_UP>;
209 };
210
211 i2c1_bus: i2c1-bus {
212 /* S3C6410-only */
213 samsung,pins = "gpb-2", "gpb-3";
214 samsung,pin-function = <6>;
215 samsung,pin-pud = <PIN_PULL_UP>;
216 };
217
218 spi0_bus: spi0-bus {
219 samsung,pins = "gpc-0", "gpc-1", "gpc-2";
220 samsung,pin-function = <2>;
221 samsung,pin-pud = <PIN_PULL_UP>;
222 };
223
224 spi0_cs: spi0-cs {
225 samsung,pins = "gpc-3";
226 samsung,pin-function = <2>;
227 samsung,pin-pud = <PIN_PULL_NONE>;
228 };
229
230 spi1_bus: spi1-bus {
231 samsung,pins = "gpc-4", "gpc-5", "gpc-6";
232 samsung,pin-function = <2>;
233 samsung,pin-pud = <PIN_PULL_UP>;
234 };
235
236 spi1_cs: spi1-cs {
237 samsung,pins = "gpc-7";
238 samsung,pin-function = <2>;
239 samsung,pin-pud = <PIN_PULL_NONE>;
240 };
241
242 sd0_cmd: sd0-cmd {
243 samsung,pins = "gpg-1";
244 samsung,pin-function = <2>;
245 samsung,pin-pud = <PIN_PULL_NONE>;
246 };
247
248 sd0_clk: sd0-clk {
249 samsung,pins = "gpg-0";
250 samsung,pin-function = <2>;
251 samsung,pin-pud = <PIN_PULL_NONE>;
252 };
253
254 sd0_bus1: sd0-bus1 {
255 samsung,pins = "gpg-2";
256 samsung,pin-function = <2>;
257 samsung,pin-pud = <PIN_PULL_NONE>;
258 };
259
260 sd0_bus4: sd0-bus4 {
261 samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5";
262 samsung,pin-function = <2>;
263 samsung,pin-pud = <PIN_PULL_NONE>;
264 };
265
266 sd0_cd: sd0-cd {
267 samsung,pins = "gpg-6";
268 samsung,pin-function = <2>;
269 samsung,pin-pud = <PIN_PULL_UP>;
270 };
271
272 sd1_cmd: sd1-cmd {
273 samsung,pins = "gph-1";
274 samsung,pin-function = <2>;
275 samsung,pin-pud = <PIN_PULL_NONE>;
276 };
277
278 sd1_clk: sd1-clk {
279 samsung,pins = "gph-0";
280 samsung,pin-function = <2>;
281 samsung,pin-pud = <PIN_PULL_NONE>;
282 };
283
284 sd1_bus1: sd1-bus1 {
285 samsung,pins = "gph-2";
286 samsung,pin-function = <2>;
287 samsung,pin-pud = <PIN_PULL_NONE>;
288 };
289
290 sd1_bus4: sd1-bus4 {
291 samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5";
292 samsung,pin-function = <2>;
293 samsung,pin-pud = <PIN_PULL_NONE>;
294 };
295
296 sd1_bus8: sd1-bus8 {
297 samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5",
298 "gph-6", "gph-7", "gph-8", "gph-9";
299 samsung,pin-function = <2>;
300 samsung,pin-pud = <PIN_PULL_NONE>;
301 };
302
303 sd1_cd: sd1-cd {
304 samsung,pins = "gpg-6";
305 samsung,pin-function = <3>;
306 samsung,pin-pud = <PIN_PULL_UP>;
307 };
308
309 sd2_cmd: sd2-cmd {
310 samsung,pins = "gpc-4";
311 samsung,pin-function = <3>;
312 samsung,pin-pud = <PIN_PULL_NONE>;
313 };
314
315 sd2_clk: sd2-clk {
316 samsung,pins = "gpc-5";
317 samsung,pin-function = <3>;
318 samsung,pin-pud = <PIN_PULL_NONE>;
319 };
320
321 sd2_bus1: sd2-bus1 {
322 samsung,pins = "gph-6";
323 samsung,pin-function = <3>;
324 samsung,pin-pud = <PIN_PULL_NONE>;
325 };
326
327 sd2_bus4: sd2-bus4 {
328 samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9";
329 samsung,pin-function = <3>;
330 samsung,pin-pud = <PIN_PULL_NONE>;
331 };
332
333 i2s0_bus: i2s0-bus {
334 samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
335 samsung,pin-function = <3>;
336 samsung,pin-pud = <PIN_PULL_NONE>;
337 };
338
339 i2s0_cdclk: i2s0-cdclk {
340 samsung,pins = "gpd-1";
341 samsung,pin-function = <3>;
342 samsung,pin-pud = <PIN_PULL_NONE>;
343 };
344
345 i2s1_bus: i2s1-bus {
346 samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
347 samsung,pin-function = <3>;
348 samsung,pin-pud = <PIN_PULL_NONE>;
349 };
350
351 i2s1_cdclk: i2s1-cdclk {
352 samsung,pins = "gpe-1";
353 samsung,pin-function = <3>;
354 samsung,pin-pud = <PIN_PULL_NONE>;
355 };
356
357 i2s2_bus: i2s2-bus {
358 /* S3C6410-only */
359 samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
360 "gph-8", "gph-9";
361 samsung,pin-function = <5>;
362 samsung,pin-pud = <PIN_PULL_NONE>;
363 };
364
365 i2s2_cdclk: i2s2-cdclk {
366 /* S3C6410-only */
367 samsung,pins = "gph-7";
368 samsung,pin-function = <5>;
369 samsung,pin-pud = <PIN_PULL_NONE>;
370 };
371
372 pcm0_bus: pcm0-bus {
373 samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
374 samsung,pin-function = <2>;
375 samsung,pin-pud = <PIN_PULL_NONE>;
376 };
377
378 pcm0_extclk: pcm0-extclk {
379 samsung,pins = "gpd-1";
380 samsung,pin-function = <2>;
381 samsung,pin-pud = <PIN_PULL_NONE>;
382 };
383
384 pcm1_bus: pcm1-bus {
385 samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
386 samsung,pin-function = <2>;
387 samsung,pin-pud = <PIN_PULL_NONE>;
388 };
389
390 pcm1_extclk: pcm1-extclk {
391 samsung,pins = "gpe-1";
392 samsung,pin-function = <2>;
393 samsung,pin-pud = <PIN_PULL_NONE>;
394 };
395
396 ac97_bus_0: ac97-bus-0 {
397 samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4";
398 samsung,pin-function = <4>;
399 samsung,pin-pud = <PIN_PULL_NONE>;
400 };
401
402 ac97_bus_1: ac97-bus-1 {
403 samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4";
404 samsung,pin-function = <4>;
405 samsung,pin-pud = <PIN_PULL_NONE>;
406 };
407
408 cam_port: cam-port {
409 samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4",
410 "gpf-5", "gpf-6", "gpf-7", "gpf-8",
411 "gpf-9", "gpf-10", "gpf-11", "gpf-12";
412 samsung,pin-function = <2>;
413 samsung,pin-pud = <PIN_PULL_NONE>;
414 };
415
416 cam_rst: cam-rst {
417 samsung,pins = "gpf-3";
418 samsung,pin-function = <2>;
419 samsung,pin-pud = <PIN_PULL_NONE>;
420 };
421
422 cam_field: cam-field {
423 /* S3C6410-only */
424 samsung,pins = "gpb-4";
425 samsung,pin-function = <3>;
426 samsung,pin-pud = <PIN_PULL_NONE>;
427 };
428
429 pwm_extclk: pwm-extclk {
430 samsung,pins = "gpf-13";
431 samsung,pin-function = <2>;
432 samsung,pin-pud = <PIN_PULL_NONE>;
433 };
434
435 pwm0_out: pwm0-out {
436 samsung,pins = "gpf-14";
437 samsung,pin-function = <2>;
438 samsung,pin-pud = <PIN_PULL_NONE>;
439 };
440
441 pwm1_out: pwm1-out {
442 samsung,pins = "gpf-15";
443 samsung,pin-function = <2>;
444 samsung,pin-pud = <PIN_PULL_NONE>;
445 };
446
447 clkout0: clkout-0 {
448 samsung,pins = "gpf-14";
449 samsung,pin-function = <3>;
450 samsung,pin-pud = <PIN_PULL_NONE>;
451 };
452
453 keypad_col0_0: keypad-col0-0 {
454 samsung,pins = "gph-0";
455 samsung,pin-function = <4>;
456 samsung,pin-pud = <PIN_PULL_NONE>;
457 };
458
459 keypad_col1_0: keypad-col1-0 {
460 samsung,pins = "gph-1";
461 samsung,pin-function = <4>;
462 samsung,pin-pud = <PIN_PULL_NONE>;
463 };
464
465 keypad_col2_0: keypad-col2-0 {
466 samsung,pins = "gph-2";
467 samsung,pin-function = <4>;
468 samsung,pin-pud = <PIN_PULL_NONE>;
469 };
470
471 keypad_col3_0: keypad-col3-0 {
472 samsung,pins = "gph-3";
473 samsung,pin-function = <4>;
474 samsung,pin-pud = <PIN_PULL_NONE>;
475 };
476
477 keypad_col4_0: keypad-col4-0 {
478 samsung,pins = "gph-4";
479 samsung,pin-function = <4>;
480 samsung,pin-pud = <PIN_PULL_NONE>;
481 };
482
483 keypad_col5_0: keypad-col5-0 {
484 samsung,pins = "gph-5";
485 samsung,pin-function = <4>;
486 samsung,pin-pud = <PIN_PULL_NONE>;
487 };
488
489 keypad_col6_0: keypad-col6-0 {
490 samsung,pins = "gph-6";
491 samsung,pin-function = <4>;
492 samsung,pin-pud = <PIN_PULL_NONE>;
493 };
494
495 keypad_col7_0: keypad-col7-0 {
496 samsung,pins = "gph-7";
497 samsung,pin-function = <4>;
498 samsung,pin-pud = <PIN_PULL_NONE>;
499 };
500
501 keypad_col0_1: keypad-col0-1 {
502 samsung,pins = "gpl-0";
503 samsung,pin-function = <3>;
504 samsung,pin-pud = <PIN_PULL_NONE>;
505 };
506
507 keypad_col1_1: keypad-col1-1 {
508 samsung,pins = "gpl-1";
509 samsung,pin-function = <3>;
510 samsung,pin-pud = <PIN_PULL_NONE>;
511 };
512
513 keypad_col2_1: keypad-col2-1 {
514 samsung,pins = "gpl-2";
515 samsung,pin-function = <3>;
516 samsung,pin-pud = <PIN_PULL_NONE>;
517 };
518
519 keypad_col3_1: keypad-col3-1 {
520 samsung,pins = "gpl-3";
521 samsung,pin-function = <3>;
522 samsung,pin-pud = <PIN_PULL_NONE>;
523 };
524
525 keypad_col4_1: keypad-col4-1 {
526 samsung,pins = "gpl-4";
527 samsung,pin-function = <3>;
528 samsung,pin-pud = <PIN_PULL_NONE>;
529 };
530
531 keypad_col5_1: keypad-col5-1 {
532 samsung,pins = "gpl-5";
533 samsung,pin-function = <3>;
534 samsung,pin-pud = <PIN_PULL_NONE>;
535 };
536
537 keypad_col6_1: keypad-col6-1 {
538 samsung,pins = "gpl-6";
539 samsung,pin-function = <3>;
540 samsung,pin-pud = <PIN_PULL_NONE>;
541 };
542
543 keypad_col7_1: keypad-col7-1 {
544 samsung,pins = "gpl-7";
545 samsung,pin-function = <3>;
546 samsung,pin-pud = <PIN_PULL_NONE>;
547 };
548
549 keypad_row0_0: keypad-row0-0 {
550 samsung,pins = "gpk-8";
551 samsung,pin-function = <3>;
552 samsung,pin-pud = <PIN_PULL_NONE>;
553 };
554
555 keypad_row1_0: keypad-row1-0 {
556 samsung,pins = "gpk-9";
557 samsung,pin-function = <3>;
558 samsung,pin-pud = <PIN_PULL_NONE>;
559 };
560
561 keypad_row2_0: keypad-row2-0 {
562 samsung,pins = "gpk-10";
563 samsung,pin-function = <3>;
564 samsung,pin-pud = <PIN_PULL_NONE>;
565 };
566
567 keypad_row3_0: keypad-row3-0 {
568 samsung,pins = "gpk-11";
569 samsung,pin-function = <3>;
570 samsung,pin-pud = <PIN_PULL_NONE>;
571 };
572
573 keypad_row4_0: keypad-row4-0 {
574 samsung,pins = "gpk-12";
575 samsung,pin-function = <3>;
576 samsung,pin-pud = <PIN_PULL_NONE>;
577 };
578
579 keypad_row5_0: keypad-row5-0 {
580 samsung,pins = "gpk-13";
581 samsung,pin-function = <3>;
582 samsung,pin-pud = <PIN_PULL_NONE>;
583 };
584
585 keypad_row6_0: keypad-row6-0 {
586 samsung,pins = "gpk-14";
587 samsung,pin-function = <3>;
588 samsung,pin-pud = <PIN_PULL_NONE>;
589 };
590
591 keypad_row7_0: keypad-row7-0 {
592 samsung,pins = "gpk-15";
593 samsung,pin-function = <3>;
594 samsung,pin-pud = <PIN_PULL_NONE>;
595 };
596
597 keypad_row0_1: keypad-row0-1 {
598 samsung,pins = "gpn-0";
599 samsung,pin-function = <3>;
600 samsung,pin-pud = <PIN_PULL_NONE>;
601 };
602
603 keypad_row1_1: keypad-row1-1 {
604 samsung,pins = "gpn-1";
605 samsung,pin-function = <3>;
606 samsung,pin-pud = <PIN_PULL_NONE>;
607 };
608
609 keypad_row2_1: keypad-row2-1 {
610 samsung,pins = "gpn-2";
611 samsung,pin-function = <3>;
612 samsung,pin-pud = <PIN_PULL_NONE>;
613 };
614
615 keypad_row3_1: keypad-row3-1 {
616 samsung,pins = "gpn-3";
617 samsung,pin-function = <3>;
618 samsung,pin-pud = <PIN_PULL_NONE>;
619 };
620
621 keypad_row4_1: keypad-row4-1 {
622 samsung,pins = "gpn-4";
623 samsung,pin-function = <3>;
624 samsung,pin-pud = <PIN_PULL_NONE>;
625 };
626
627 keypad_row5_1: keypad-row5-1 {
628 samsung,pins = "gpn-5";
629 samsung,pin-function = <3>;
630 samsung,pin-pud = <PIN_PULL_NONE>;
631 };
632
633 keypad_row6_1: keypad-row6-1 {
634 samsung,pins = "gpn-6";
635 samsung,pin-function = <3>;
636 samsung,pin-pud = <PIN_PULL_NONE>;
637 };
638
639 keypad_row7_1: keypad-row7-1 {
640 samsung,pins = "gpn-7";
641 samsung,pin-function = <3>;
642 samsung,pin-pud = <PIN_PULL_NONE>;
643 };
644
645 lcd_ctrl: lcd-ctrl {
646 samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11";
647 samsung,pin-function = <2>;
648 samsung,pin-pud = <PIN_PULL_NONE>;
649 };
650
651 lcd_data16: lcd-data-width16 {
652 samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6",
653 "gpi-7", "gpi-10", "gpi-11", "gpi-12",
654 "gpi-13", "gpi-14", "gpi-15", "gpj-3",
655 "gpj-4", "gpj-5", "gpj-6", "gpj-7";
656 samsung,pin-function = <2>;
657 samsung,pin-pud = <PIN_PULL_NONE>;
658 };
659
660 lcd_data18: lcd-data-width18 {
661 samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5",
662 "gpi-6", "gpi-7", "gpi-10", "gpi-11",
663 "gpi-12", "gpi-13", "gpi-14", "gpi-15",
664 "gpj-2", "gpj-3", "gpj-4", "gpj-5",
665 "gpj-6", "gpj-7";
666 samsung,pin-function = <2>;
667 samsung,pin-pud = <PIN_PULL_NONE>;
668 };
669
670 lcd_data24: lcd-data-width24 {
671 samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
672 "gpi-4", "gpi-5", "gpi-6", "gpi-7",
673 "gpi-8", "gpi-9", "gpi-10", "gpi-11",
674 "gpi-12", "gpi-13", "gpi-14", "gpi-15",
675 "gpj-0", "gpj-1", "gpj-2", "gpj-3",
676 "gpj-4", "gpj-5", "gpj-6", "gpj-7";
677 samsung,pin-function = <2>;
678 samsung,pin-pud = <PIN_PULL_NONE>;
679 };
680
681 hsi_bus: hsi-bus {
682 samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3",
683 "gpk-4", "gpk-5", "gpk-6", "gpk-7";
684 samsung,pin-function = <3>;
685 samsung,pin-pud = <PIN_PULL_NONE>;
686 };
687};
diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
new file mode 100644
index 000000000000..4e3be4d3493d
--- /dev/null
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -0,0 +1,199 @@
1/*
2 * Samsung's S3C64xx SoC series common device tree source
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Samsung's S3C64xx SoC series device nodes are listed in this file.
7 * Particular SoCs from S3C64xx series can include this file and provide
8 * values for SoCs specfic bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
12 * nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include "skeleton.dtsi"
20#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
21
22/ {
23 aliases {
24 i2c0 = &i2c0;
25 pinctrl0 = &pinctrl0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,arm1176jzf-s", "arm,arm1176";
35 reg = <0x0>;
36 };
37 };
38
39 soc: soc {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44
45 vic0: interrupt-controller@71200000 {
46 compatible = "arm,pl192-vic";
47 interrupt-controller;
48 reg = <0x71200000 0x1000>;
49 #interrupt-cells = <1>;
50 };
51
52 vic1: interrupt-controller@71300000 {
53 compatible = "arm,pl192-vic";
54 interrupt-controller;
55 reg = <0x71300000 0x1000>;
56 #interrupt-cells = <1>;
57 };
58
59 sdhci0: sdhci@7c200000 {
60 compatible = "samsung,s3c6410-sdhci";
61 reg = <0x7c200000 0x100>;
62 interrupt-parent = <&vic1>;
63 interrupts = <24>;
64 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
65 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
66 <&clocks SCLK_MMC0>;
67 status = "disabled";
68 };
69
70 sdhci1: sdhci@7c300000 {
71 compatible = "samsung,s3c6410-sdhci";
72 reg = <0x7c300000 0x100>;
73 interrupt-parent = <&vic1>;
74 interrupts = <25>;
75 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
76 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
77 <&clocks SCLK_MMC1>;
78 status = "disabled";
79 };
80
81 sdhci2: sdhci@7c400000 {
82 compatible = "samsung,s3c6410-sdhci";
83 reg = <0x7c400000 0x100>;
84 interrupt-parent = <&vic1>;
85 interrupts = <17>;
86 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
87 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
88 <&clocks SCLK_MMC2>;
89 status = "disabled";
90 };
91
92 watchdog: watchdog@7e004000 {
93 compatible = "samsung,s3c2410-wdt";
94 reg = <0x7e004000 0x1000>;
95 interrupt-parent = <&vic0>;
96 interrupts = <26>;
97 clock-names = "watchdog";
98 clocks = <&clocks PCLK_WDT>;
99 status = "disabled";
100 };
101
102 i2c0: i2c@7f004000 {
103 compatible = "samsung,s3c2440-i2c";
104 reg = <0x7f004000 0x1000>;
105 interrupt-parent = <&vic1>;
106 interrupts = <18>;
107 clock-names = "i2c";
108 clocks = <&clocks PCLK_IIC0>;
109 status = "disabled";
110 #address-cells = <1>;
111 #size-cells = <0>;
112 };
113
114 uart0: serial@7f005000 {
115 compatible = "samsung,s3c6400-uart";
116 reg = <0x7f005000 0x100>;
117 interrupt-parent = <&vic1>;
118 interrupts = <5>;
119 clock-names = "uart", "clk_uart_baud2",
120 "clk_uart_baud3";
121 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
122 <&clocks SCLK_UART>;
123 status = "disabled";
124 };
125
126 uart1: serial@7f005400 {
127 compatible = "samsung,s3c6400-uart";
128 reg = <0x7f005400 0x100>;
129 interrupt-parent = <&vic1>;
130 interrupts = <6>;
131 clock-names = "uart", "clk_uart_baud2",
132 "clk_uart_baud3";
133 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
134 <&clocks SCLK_UART>;
135 status = "disabled";
136 };
137
138 uart2: serial@7f005800 {
139 compatible = "samsung,s3c6400-uart";
140 reg = <0x7f005800 0x100>;
141 interrupt-parent = <&vic1>;
142 interrupts = <7>;
143 clock-names = "uart", "clk_uart_baud2",
144 "clk_uart_baud3";
145 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
146 <&clocks SCLK_UART>;
147 status = "disabled";
148 };
149
150 uart3: serial@7f005c00 {
151 compatible = "samsung,s3c6400-uart";
152 reg = <0x7f005c00 0x100>;
153 interrupt-parent = <&vic1>;
154 interrupts = <8>;
155 clock-names = "uart", "clk_uart_baud2",
156 "clk_uart_baud3";
157 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
158 <&clocks SCLK_UART>;
159 status = "disabled";
160 };
161
162 pwm: pwm@7f006000 {
163 compatible = "samsung,s3c6400-pwm";
164 reg = <0x7f006000 0x1000>;
165 interrupt-parent = <&vic0>;
166 interrupts = <23>, <24>, <25>, <27>, <28>;
167 clock-names = "timers";
168 clocks = <&clocks PCLK_PWM>;
169 samsung,pwm-outputs = <0>, <1>;
170 #pwm-cells = <3>;
171 status = "disabled";
172 };
173
174 pinctrl0: pinctrl@7f008000 {
175 compatible = "samsung,s3c64xx-pinctrl";
176 reg = <0x7f008000 0x1000>;
177 interrupt-parent = <&vic1>;
178 interrupts = <21>;
179
180 pctrl_int_map: pinctrl-interrupt-map {
181 interrupt-map = <0 &vic0 0>,
182 <1 &vic0 1>,
183 <2 &vic1 0>,
184 <3 &vic1 1>;
185 #address-cells = <0>;
186 #size-cells = <0>;
187 #interrupt-cells = <1>;
188 };
189
190 wakeup-interrupt-controller {
191 compatible = "samsung,s3c64xx-wakeup-eint";
192 interrupts = <0>, <1>, <2>, <3>;
193 interrupt-parent = <&pctrl_int_map>;
194 };
195 };
196 };
197};
198
199#include "s3c64xx-pinctrl.dtsi"
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 041da5172423..bd14e3a37128 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -306,3 +306,19 @@ config MACH_WLF_CRAGG_6410
306 select SAMSUNG_GPIO_EXTRA128 306 select SAMSUNG_GPIO_EXTRA128
307 help 307 help
308 Machine support for the Wolfson Cragganmore S3C6410 variant. 308 Machine support for the Wolfson Cragganmore S3C6410 variant.
309
310config MACH_S3C64XX_DT
311 bool "Samsung S3C6400/S3C6410 machine using Device Tree"
312 select CLKSRC_OF
313 select CPU_S3C6400
314 select CPU_S3C6410
315 select PINCTRL
316 select PINCTRL_S3C64XX
317 select USE_OF
318 help
319 Machine support for Samsung S3C6400/S3C6410 machines with Device Tree
320 enabled.
321 Select this if a fdt blob is available for your S3C64XX SoC based
322 board.
323 Note: This is under development and not all peripherals can be
324 supported with this machine file.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 31d0c9101272..6faedcffce04 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -12,7 +12,7 @@ obj- :=
12 12
13# Core 13# Core
14 14
15obj-y += common.o clock.o 15obj-y += common.o
16 16
17# Core support 17# Core support
18 18
@@ -57,3 +57,4 @@ obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
57obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o 57obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
58obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o 58obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
59obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o 59obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
60obj-$(CONFIG_MACH_S3C64XX_DT) += mach-s3c64xx-dt.o
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
deleted file mode 100644
index c1bcc4a6d3a8..000000000000
--- a/arch/arm/mach-s3c64xx/clock.c
+++ /dev/null
@@ -1,1007 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/clock.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX Base clock support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25
26#include <mach/regs-clock.h>
27
28#include <plat/cpu.h>
29#include <plat/devs.h>
30#include <plat/cpu-freq.h>
31#include <plat/clock.h>
32#include <plat/clock-clksrc.h>
33#include <plat/pll.h>
34
35#include "regs-sys.h"
36
37/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
38 * ext_xtal_mux for want of an actual name from the manual.
39*/
40
41static struct clk clk_ext_xtal_mux = {
42 .name = "ext_xtal",
43};
44
45#define clk_fin_apll clk_ext_xtal_mux
46#define clk_fin_mpll clk_ext_xtal_mux
47#define clk_fin_epll clk_ext_xtal_mux
48
49#define clk_fout_mpll clk_mpll
50#define clk_fout_epll clk_epll
51
52struct clk clk_h2 = {
53 .name = "hclk2",
54 .rate = 0,
55};
56
57struct clk clk_27m = {
58 .name = "clk_27m",
59 .rate = 27000000,
60};
61
62static int clk_48m_ctrl(struct clk *clk, int enable)
63{
64 unsigned long flags;
65 u32 val;
66
67 /* can't rely on clock lock, this register has other usages */
68 local_irq_save(flags);
69
70 val = __raw_readl(S3C64XX_OTHERS);
71 if (enable)
72 val |= S3C64XX_OTHERS_USBMASK;
73 else
74 val &= ~S3C64XX_OTHERS_USBMASK;
75
76 __raw_writel(val, S3C64XX_OTHERS);
77 local_irq_restore(flags);
78
79 return 0;
80}
81
82struct clk clk_48m = {
83 .name = "clk_48m",
84 .rate = 48000000,
85 .enable = clk_48m_ctrl,
86};
87
88struct clk clk_xusbxti = {
89 .name = "xusbxti",
90 .rate = 48000000,
91};
92
93static int inline s3c64xx_gate(void __iomem *reg,
94 struct clk *clk,
95 int enable)
96{
97 unsigned int ctrlbit = clk->ctrlbit;
98 u32 con;
99
100 con = __raw_readl(reg);
101
102 if (enable)
103 con |= ctrlbit;
104 else
105 con &= ~ctrlbit;
106
107 __raw_writel(con, reg);
108 return 0;
109}
110
111static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
112{
113 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
114}
115
116static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
117{
118 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
119}
120
121int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
122{
123 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
124}
125
126static struct clk init_clocks_off[] = {
127 {
128 .name = "nand",
129 .parent = &clk_h,
130 }, {
131 .name = "rtc",
132 .parent = &clk_p,
133 .enable = s3c64xx_pclk_ctrl,
134 .ctrlbit = S3C_CLKCON_PCLK_RTC,
135 }, {
136 .name = "adc",
137 .parent = &clk_p,
138 .enable = s3c64xx_pclk_ctrl,
139 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
140 }, {
141 .name = "i2c",
142 .devname = "s3c2440-i2c.0",
143 .parent = &clk_p,
144 .enable = s3c64xx_pclk_ctrl,
145 .ctrlbit = S3C_CLKCON_PCLK_IIC,
146 }, {
147 .name = "i2c",
148 .devname = "s3c2440-i2c.1",
149 .parent = &clk_p,
150 .enable = s3c64xx_pclk_ctrl,
151 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
152 }, {
153 .name = "keypad",
154 .parent = &clk_p,
155 .enable = s3c64xx_pclk_ctrl,
156 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
157 }, {
158 .name = "spi",
159 .devname = "s3c6410-spi.0",
160 .parent = &clk_p,
161 .enable = s3c64xx_pclk_ctrl,
162 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
163 }, {
164 .name = "spi",
165 .devname = "s3c6410-spi.1",
166 .parent = &clk_p,
167 .enable = s3c64xx_pclk_ctrl,
168 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
169 }, {
170 .name = "48m",
171 .devname = "s3c-sdhci.0",
172 .parent = &clk_48m,
173 .enable = s3c64xx_sclk_ctrl,
174 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
175 }, {
176 .name = "48m",
177 .devname = "s3c-sdhci.1",
178 .parent = &clk_48m,
179 .enable = s3c64xx_sclk_ctrl,
180 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
181 }, {
182 .name = "48m",
183 .devname = "s3c-sdhci.2",
184 .parent = &clk_48m,
185 .enable = s3c64xx_sclk_ctrl,
186 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
187 }, {
188 .name = "ac97",
189 .parent = &clk_p,
190 .ctrlbit = S3C_CLKCON_PCLK_AC97,
191 }, {
192 .name = "cfcon",
193 .parent = &clk_h,
194 .enable = s3c64xx_hclk_ctrl,
195 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
196 }, {
197 .name = "dma0",
198 .parent = &clk_h,
199 .enable = s3c64xx_hclk_ctrl,
200 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
201 }, {
202 .name = "dma1",
203 .parent = &clk_h,
204 .enable = s3c64xx_hclk_ctrl,
205 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
206 }, {
207 .name = "3dse",
208 .parent = &clk_h,
209 .enable = s3c64xx_hclk_ctrl,
210 .ctrlbit = S3C_CLKCON_HCLK_3DSE,
211 }, {
212 .name = "hclk_secur",
213 .parent = &clk_h,
214 .enable = s3c64xx_hclk_ctrl,
215 .ctrlbit = S3C_CLKCON_HCLK_SECUR,
216 }, {
217 .name = "sdma1",
218 .parent = &clk_h,
219 .enable = s3c64xx_hclk_ctrl,
220 .ctrlbit = S3C_CLKCON_HCLK_SDMA1,
221 }, {
222 .name = "sdma0",
223 .parent = &clk_h,
224 .enable = s3c64xx_hclk_ctrl,
225 .ctrlbit = S3C_CLKCON_HCLK_SDMA0,
226 }, {
227 .name = "hclk_jpeg",
228 .parent = &clk_h,
229 .enable = s3c64xx_hclk_ctrl,
230 .ctrlbit = S3C_CLKCON_HCLK_JPEG,
231 }, {
232 .name = "camif",
233 .parent = &clk_h,
234 .enable = s3c64xx_hclk_ctrl,
235 .ctrlbit = S3C_CLKCON_HCLK_CAMIF,
236 }, {
237 .name = "hclk_scaler",
238 .parent = &clk_h,
239 .enable = s3c64xx_hclk_ctrl,
240 .ctrlbit = S3C_CLKCON_HCLK_SCALER,
241 }, {
242 .name = "2d",
243 .parent = &clk_h,
244 .enable = s3c64xx_hclk_ctrl,
245 .ctrlbit = S3C_CLKCON_HCLK_2D,
246 }, {
247 .name = "tv",
248 .parent = &clk_h,
249 .enable = s3c64xx_hclk_ctrl,
250 .ctrlbit = S3C_CLKCON_HCLK_TV,
251 }, {
252 .name = "post0",
253 .parent = &clk_h,
254 .enable = s3c64xx_hclk_ctrl,
255 .ctrlbit = S3C_CLKCON_HCLK_POST0,
256 }, {
257 .name = "rot",
258 .parent = &clk_h,
259 .enable = s3c64xx_hclk_ctrl,
260 .ctrlbit = S3C_CLKCON_HCLK_ROT,
261 }, {
262 .name = "hclk_mfc",
263 .parent = &clk_h,
264 .enable = s3c64xx_hclk_ctrl,
265 .ctrlbit = S3C_CLKCON_HCLK_MFC,
266 }, {
267 .name = "pclk_mfc",
268 .parent = &clk_p,
269 .enable = s3c64xx_pclk_ctrl,
270 .ctrlbit = S3C_CLKCON_PCLK_MFC,
271 }, {
272 .name = "dac27",
273 .enable = s3c64xx_sclk_ctrl,
274 .ctrlbit = S3C_CLKCON_SCLK_DAC27,
275 }, {
276 .name = "tv27",
277 .enable = s3c64xx_sclk_ctrl,
278 .ctrlbit = S3C_CLKCON_SCLK_TV27,
279 }, {
280 .name = "scaler27",
281 .enable = s3c64xx_sclk_ctrl,
282 .ctrlbit = S3C_CLKCON_SCLK_SCALER27,
283 }, {
284 .name = "sclk_scaler",
285 .enable = s3c64xx_sclk_ctrl,
286 .ctrlbit = S3C_CLKCON_SCLK_SCALER,
287 }, {
288 .name = "post0_27",
289 .enable = s3c64xx_sclk_ctrl,
290 .ctrlbit = S3C_CLKCON_SCLK_POST0_27,
291 }, {
292 .name = "secur",
293 .enable = s3c64xx_sclk_ctrl,
294 .ctrlbit = S3C_CLKCON_SCLK_SECUR,
295 }, {
296 .name = "sclk_mfc",
297 .enable = s3c64xx_sclk_ctrl,
298 .ctrlbit = S3C_CLKCON_SCLK_MFC,
299 }, {
300 .name = "sclk_jpeg",
301 .enable = s3c64xx_sclk_ctrl,
302 .ctrlbit = S3C_CLKCON_SCLK_JPEG,
303 },
304};
305
306static struct clk clk_48m_spi0 = {
307 .name = "spi_48m",
308 .devname = "s3c6410-spi.0",
309 .parent = &clk_48m,
310 .enable = s3c64xx_sclk_ctrl,
311 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
312};
313
314static struct clk clk_48m_spi1 = {
315 .name = "spi_48m",
316 .devname = "s3c6410-spi.1",
317 .parent = &clk_48m,
318 .enable = s3c64xx_sclk_ctrl,
319 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
320};
321
322static struct clk clk_i2s0 = {
323 .name = "iis",
324 .devname = "samsung-i2s.0",
325 .parent = &clk_p,
326 .enable = s3c64xx_pclk_ctrl,
327 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
328};
329
330static struct clk clk_i2s1 = {
331 .name = "iis",
332 .devname = "samsung-i2s.1",
333 .parent = &clk_p,
334 .enable = s3c64xx_pclk_ctrl,
335 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
336};
337
338#ifdef CONFIG_CPU_S3C6410
339static struct clk clk_i2s2 = {
340 .name = "iis",
341 .devname = "samsung-i2s.2",
342 .parent = &clk_p,
343 .enable = s3c64xx_pclk_ctrl,
344 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
345};
346#endif
347
348static struct clk init_clocks[] = {
349 {
350 .name = "lcd",
351 .parent = &clk_h,
352 .enable = s3c64xx_hclk_ctrl,
353 .ctrlbit = S3C_CLKCON_HCLK_LCD,
354 }, {
355 .name = "gpio",
356 .parent = &clk_p,
357 .enable = s3c64xx_pclk_ctrl,
358 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
359 }, {
360 .name = "usb-host",
361 .parent = &clk_h,
362 .enable = s3c64xx_hclk_ctrl,
363 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
364 }, {
365 .name = "otg",
366 .parent = &clk_h,
367 .enable = s3c64xx_hclk_ctrl,
368 .ctrlbit = S3C_CLKCON_HCLK_USB,
369 }, {
370 .name = "timers",
371 .parent = &clk_p,
372 .enable = s3c64xx_pclk_ctrl,
373 .ctrlbit = S3C_CLKCON_PCLK_PWM,
374 }, {
375 .name = "uart",
376 .devname = "s3c6400-uart.0",
377 .parent = &clk_p,
378 .enable = s3c64xx_pclk_ctrl,
379 .ctrlbit = S3C_CLKCON_PCLK_UART0,
380 }, {
381 .name = "uart",
382 .devname = "s3c6400-uart.1",
383 .parent = &clk_p,
384 .enable = s3c64xx_pclk_ctrl,
385 .ctrlbit = S3C_CLKCON_PCLK_UART1,
386 }, {
387 .name = "uart",
388 .devname = "s3c6400-uart.2",
389 .parent = &clk_p,
390 .enable = s3c64xx_pclk_ctrl,
391 .ctrlbit = S3C_CLKCON_PCLK_UART2,
392 }, {
393 .name = "uart",
394 .devname = "s3c6400-uart.3",
395 .parent = &clk_p,
396 .enable = s3c64xx_pclk_ctrl,
397 .ctrlbit = S3C_CLKCON_PCLK_UART3,
398 }, {
399 .name = "watchdog",
400 .parent = &clk_p,
401 .ctrlbit = S3C_CLKCON_PCLK_WDT,
402 },
403};
404
405static struct clk clk_hsmmc0 = {
406 .name = "hsmmc",
407 .devname = "s3c-sdhci.0",
408 .parent = &clk_h,
409 .enable = s3c64xx_hclk_ctrl,
410 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
411};
412
413static struct clk clk_hsmmc1 = {
414 .name = "hsmmc",
415 .devname = "s3c-sdhci.1",
416 .parent = &clk_h,
417 .enable = s3c64xx_hclk_ctrl,
418 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
419};
420
421static struct clk clk_hsmmc2 = {
422 .name = "hsmmc",
423 .devname = "s3c-sdhci.2",
424 .parent = &clk_h,
425 .enable = s3c64xx_hclk_ctrl,
426 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
427};
428
429static struct clk clk_fout_apll = {
430 .name = "fout_apll",
431};
432
433static struct clk *clk_src_apll_list[] = {
434 [0] = &clk_fin_apll,
435 [1] = &clk_fout_apll,
436};
437
438static struct clksrc_sources clk_src_apll = {
439 .sources = clk_src_apll_list,
440 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
441};
442
443static struct clksrc_clk clk_mout_apll = {
444 .clk = {
445 .name = "mout_apll",
446 },
447 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
448 .sources = &clk_src_apll,
449};
450
451static struct clk *clk_src_epll_list[] = {
452 [0] = &clk_fin_epll,
453 [1] = &clk_fout_epll,
454};
455
456static struct clksrc_sources clk_src_epll = {
457 .sources = clk_src_epll_list,
458 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
459};
460
461static struct clksrc_clk clk_mout_epll = {
462 .clk = {
463 .name = "mout_epll",
464 },
465 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
466 .sources = &clk_src_epll,
467};
468
469static struct clk *clk_src_mpll_list[] = {
470 [0] = &clk_fin_mpll,
471 [1] = &clk_fout_mpll,
472};
473
474static struct clksrc_sources clk_src_mpll = {
475 .sources = clk_src_mpll_list,
476 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
477};
478
479static struct clksrc_clk clk_mout_mpll = {
480 .clk = {
481 .name = "mout_mpll",
482 },
483 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
484 .sources = &clk_src_mpll,
485};
486
487static unsigned int armclk_mask;
488
489static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
490{
491 unsigned long rate = clk_get_rate(clk->parent);
492 u32 clkdiv;
493
494 /* divisor mask starts at bit0, so no need to shift */
495 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
496
497 return rate / (clkdiv + 1);
498}
499
500static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
501 unsigned long rate)
502{
503 unsigned long parent = clk_get_rate(clk->parent);
504 u32 div;
505
506 if (parent < rate)
507 return parent;
508
509 div = (parent / rate) - 1;
510 if (div > armclk_mask)
511 div = armclk_mask;
512
513 return parent / (div + 1);
514}
515
516static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
517{
518 unsigned long parent = clk_get_rate(clk->parent);
519 u32 div;
520 u32 val;
521
522 if (rate < parent / (armclk_mask + 1))
523 return -EINVAL;
524
525 rate = clk_round_rate(clk, rate);
526 div = clk_get_rate(clk->parent) / rate;
527
528 val = __raw_readl(S3C_CLK_DIV0);
529 val &= ~armclk_mask;
530 val |= (div - 1);
531 __raw_writel(val, S3C_CLK_DIV0);
532
533 return 0;
534
535}
536
537static struct clk clk_arm = {
538 .name = "armclk",
539 .parent = &clk_mout_apll.clk,
540 .ops = &(struct clk_ops) {
541 .get_rate = s3c64xx_clk_arm_get_rate,
542 .set_rate = s3c64xx_clk_arm_set_rate,
543 .round_rate = s3c64xx_clk_arm_round_rate,
544 },
545};
546
547static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
548{
549 unsigned long rate = clk_get_rate(clk->parent);
550
551 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
552
553 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
554 rate /= 2;
555
556 return rate;
557}
558
559static struct clk_ops clk_dout_ops = {
560 .get_rate = s3c64xx_clk_doutmpll_get_rate,
561};
562
563static struct clk clk_dout_mpll = {
564 .name = "dout_mpll",
565 .parent = &clk_mout_mpll.clk,
566 .ops = &clk_dout_ops,
567};
568
569static struct clk *clkset_spi_mmc_list[] = {
570 &clk_mout_epll.clk,
571 &clk_dout_mpll,
572 &clk_fin_epll,
573 &clk_27m,
574};
575
576static struct clksrc_sources clkset_spi_mmc = {
577 .sources = clkset_spi_mmc_list,
578 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
579};
580
581static struct clk *clkset_irda_list[] = {
582 &clk_mout_epll.clk,
583 &clk_dout_mpll,
584 NULL,
585 &clk_27m,
586};
587
588static struct clksrc_sources clkset_irda = {
589 .sources = clkset_irda_list,
590 .nr_sources = ARRAY_SIZE(clkset_irda_list),
591};
592
593static struct clk *clkset_uart_list[] = {
594 &clk_mout_epll.clk,
595 &clk_dout_mpll,
596 NULL,
597 NULL
598};
599
600static struct clksrc_sources clkset_uart = {
601 .sources = clkset_uart_list,
602 .nr_sources = ARRAY_SIZE(clkset_uart_list),
603};
604
605static struct clk *clkset_uhost_list[] = {
606 &clk_48m,
607 &clk_mout_epll.clk,
608 &clk_dout_mpll,
609 &clk_fin_epll,
610};
611
612static struct clksrc_sources clkset_uhost = {
613 .sources = clkset_uhost_list,
614 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
615};
616
617/* The peripheral clocks are all controlled via clocksource followed
618 * by an optional divider and gate stage. We currently roll this into
619 * one clock which hides the intermediate clock from the mux.
620 *
621 * Note, the JPEG clock can only be an even divider...
622 *
623 * The scaler and LCD clocks depend on the S3C64XX version, and also
624 * have a common parent divisor so are not included here.
625 */
626
627/* clocks that feed other parts of the clock source tree */
628
629static struct clk clk_iis_cd0 = {
630 .name = "iis_cdclk0",
631};
632
633static struct clk clk_iis_cd1 = {
634 .name = "iis_cdclk1",
635};
636
637static struct clk clk_iisv4_cd = {
638 .name = "iis_cdclk_v4",
639};
640
641static struct clk clk_pcm_cd = {
642 .name = "pcm_cdclk",
643};
644
645static struct clk *clkset_audio0_list[] = {
646 [0] = &clk_mout_epll.clk,
647 [1] = &clk_dout_mpll,
648 [2] = &clk_fin_epll,
649 [3] = &clk_iis_cd0,
650 [4] = &clk_pcm_cd,
651};
652
653static struct clksrc_sources clkset_audio0 = {
654 .sources = clkset_audio0_list,
655 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
656};
657
658static struct clk *clkset_audio1_list[] = {
659 [0] = &clk_mout_epll.clk,
660 [1] = &clk_dout_mpll,
661 [2] = &clk_fin_epll,
662 [3] = &clk_iis_cd1,
663 [4] = &clk_pcm_cd,
664};
665
666static struct clksrc_sources clkset_audio1 = {
667 .sources = clkset_audio1_list,
668 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
669};
670
671#ifdef CONFIG_CPU_S3C6410
672static struct clk *clkset_audio2_list[] = {
673 [0] = &clk_mout_epll.clk,
674 [1] = &clk_dout_mpll,
675 [2] = &clk_fin_epll,
676 [3] = &clk_iisv4_cd,
677 [4] = &clk_pcm_cd,
678};
679
680static struct clksrc_sources clkset_audio2 = {
681 .sources = clkset_audio2_list,
682 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
683};
684#endif
685
686static struct clksrc_clk clksrcs[] = {
687 {
688 .clk = {
689 .name = "usb-bus-host",
690 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
691 .enable = s3c64xx_sclk_ctrl,
692 },
693 .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
694 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
695 .sources = &clkset_uhost,
696 }, {
697 .clk = {
698 .name = "irda-bus",
699 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
700 .enable = s3c64xx_sclk_ctrl,
701 },
702 .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
703 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
704 .sources = &clkset_irda,
705 }, {
706 .clk = {
707 .name = "camera",
708 .ctrlbit = S3C_CLKCON_SCLK_CAM,
709 .enable = s3c64xx_sclk_ctrl,
710 .parent = &clk_h2,
711 },
712 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
713 },
714};
715
716/* Where does UCLK0 come from? */
717static struct clksrc_clk clk_sclk_uclk = {
718 .clk = {
719 .name = "uclk1",
720 .ctrlbit = S3C_CLKCON_SCLK_UART,
721 .enable = s3c64xx_sclk_ctrl,
722 },
723 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
724 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
725 .sources = &clkset_uart,
726};
727
728static struct clksrc_clk clk_sclk_mmc0 = {
729 .clk = {
730 .name = "mmc_bus",
731 .devname = "s3c-sdhci.0",
732 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
733 .enable = s3c64xx_sclk_ctrl,
734 },
735 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
736 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
737 .sources = &clkset_spi_mmc,
738};
739
740static struct clksrc_clk clk_sclk_mmc1 = {
741 .clk = {
742 .name = "mmc_bus",
743 .devname = "s3c-sdhci.1",
744 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
745 .enable = s3c64xx_sclk_ctrl,
746 },
747 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
748 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
749 .sources = &clkset_spi_mmc,
750};
751
752static struct clksrc_clk clk_sclk_mmc2 = {
753 .clk = {
754 .name = "mmc_bus",
755 .devname = "s3c-sdhci.2",
756 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
757 .enable = s3c64xx_sclk_ctrl,
758 },
759 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
760 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
761 .sources = &clkset_spi_mmc,
762};
763
764static struct clksrc_clk clk_sclk_spi0 = {
765 .clk = {
766 .name = "spi-bus",
767 .devname = "s3c6410-spi.0",
768 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
769 .enable = s3c64xx_sclk_ctrl,
770 },
771 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
772 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
773 .sources = &clkset_spi_mmc,
774};
775
776static struct clksrc_clk clk_sclk_spi1 = {
777 .clk = {
778 .name = "spi-bus",
779 .devname = "s3c6410-spi.1",
780 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
781 .enable = s3c64xx_sclk_ctrl,
782 },
783 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
784 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
785 .sources = &clkset_spi_mmc,
786};
787
788static struct clksrc_clk clk_audio_bus0 = {
789 .clk = {
790 .name = "audio-bus",
791 .devname = "samsung-i2s.0",
792 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
793 .enable = s3c64xx_sclk_ctrl,
794 },
795 .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
796 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
797 .sources = &clkset_audio0,
798};
799
800static struct clksrc_clk clk_audio_bus1 = {
801 .clk = {
802 .name = "audio-bus",
803 .devname = "samsung-i2s.1",
804 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
805 .enable = s3c64xx_sclk_ctrl,
806 },
807 .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
808 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
809 .sources = &clkset_audio1,
810};
811
812#ifdef CONFIG_CPU_S3C6410
813static struct clksrc_clk clk_audio_bus2 = {
814 .clk = {
815 .name = "audio-bus",
816 .devname = "samsung-i2s.2",
817 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
818 .enable = s3c64xx_sclk_ctrl,
819 },
820 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
821 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
822 .sources = &clkset_audio2,
823};
824#endif
825/* Clock initialisation code */
826
827static struct clksrc_clk *init_parents[] = {
828 &clk_mout_apll,
829 &clk_mout_epll,
830 &clk_mout_mpll,
831};
832
833static struct clksrc_clk *clksrc_cdev[] = {
834 &clk_sclk_uclk,
835 &clk_sclk_mmc0,
836 &clk_sclk_mmc1,
837 &clk_sclk_mmc2,
838 &clk_sclk_spi0,
839 &clk_sclk_spi1,
840 &clk_audio_bus0,
841 &clk_audio_bus1,
842};
843
844static struct clk *clk_cdev[] = {
845 &clk_hsmmc0,
846 &clk_hsmmc1,
847 &clk_hsmmc2,
848 &clk_48m_spi0,
849 &clk_48m_spi1,
850 &clk_i2s0,
851 &clk_i2s1,
852};
853
854static struct clk_lookup s3c64xx_clk_lookup[] = {
855 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
856 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
857 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
858 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
859 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
860 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
861 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
862 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
863 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
864 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
865 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
866 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
867 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
868 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
869 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk),
870 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
871 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk),
872#ifdef CONFIG_CPU_S3C6410
873 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
874 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk),
875#endif
876};
877
878#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
879
880void __init_or_cpufreq s3c64xx_setup_clocks(void)
881{
882 struct clk *xtal_clk;
883 unsigned long xtal;
884 unsigned long fclk;
885 unsigned long hclk;
886 unsigned long hclk2;
887 unsigned long pclk;
888 unsigned long epll;
889 unsigned long apll;
890 unsigned long mpll;
891 unsigned int ptr;
892 u32 clkdiv0;
893
894 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
895
896 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
897 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
898
899 xtal_clk = clk_get(NULL, "xtal");
900 BUG_ON(IS_ERR(xtal_clk));
901
902 xtal = clk_get_rate(xtal_clk);
903 clk_put(xtal_clk);
904
905 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
906
907 /* For now assume the mux always selects the crystal */
908 clk_ext_xtal_mux.parent = xtal_clk;
909
910 epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
911 __raw_readl(S3C_EPLL_CON1));
912 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
913 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
914
915 fclk = mpll;
916
917 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
918 apll, mpll, epll);
919
920 if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
921 /* Synchronous mode */
922 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
923 else
924 /* Asynchronous mode */
925 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
926
927 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
928 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
929
930 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
931 hclk2, hclk, pclk);
932
933 clk_fout_mpll.rate = mpll;
934 clk_fout_epll.rate = epll;
935 clk_fout_apll.rate = apll;
936
937 clk_h2.rate = hclk2;
938 clk_h.rate = hclk;
939 clk_p.rate = pclk;
940 clk_f.rate = fclk;
941
942 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
943 s3c_set_clksrc(init_parents[ptr], true);
944
945 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
946 s3c_set_clksrc(&clksrcs[ptr], true);
947}
948
949static struct clk *clks1[] __initdata = {
950 &clk_ext_xtal_mux,
951 &clk_iis_cd0,
952 &clk_iis_cd1,
953 &clk_iisv4_cd,
954 &clk_pcm_cd,
955 &clk_mout_epll.clk,
956 &clk_mout_mpll.clk,
957 &clk_dout_mpll,
958 &clk_arm,
959};
960
961static struct clk *clks[] __initdata = {
962 &clk_ext,
963 &clk_epll,
964 &clk_27m,
965 &clk_48m,
966 &clk_h2,
967 &clk_xusbxti,
968};
969
970/**
971 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
972 * @xtal: The rate for the clock crystal feeding the PLLs.
973 * @armclk_divlimit: Divisor mask for ARMCLK.
974 *
975 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
976 * as ARMCLK as well as the necessary parent clocks.
977 *
978 * This call does not setup the clocks, which is left to the
979 * s3c64xx_setup_clocks() call which may be needed by the cpufreq
980 * or resume code to re-set the clocks if the bootloader has changed
981 * them.
982 */
983void __init s3c64xx_register_clocks(unsigned long xtal,
984 unsigned armclk_divlimit)
985{
986 unsigned int cnt;
987
988 armclk_mask = armclk_divlimit;
989
990 s3c24xx_register_baseclocks(xtal);
991 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
992
993 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
994
995 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
996 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
997
998 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
999 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
1000 s3c_disable_clocks(clk_cdev[cnt], 1);
1001
1002 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
1003 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1004 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
1005 s3c_register_clksrc(clksrc_cdev[cnt], 1);
1006 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
1007}
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 73d79cf5e141..7a3ce4c39e5f 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -14,9 +14,14 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17/*
18 * NOTE: Code in this file is not used when booting with Device Tree support.
19 */
20
17#include <linux/kernel.h> 21#include <linux/kernel.h>
18#include <linux/init.h> 22#include <linux/init.h>
19#include <linux/module.h> 23#include <linux/module.h>
24#include <linux/clk-provider.h>
20#include <linux/interrupt.h> 25#include <linux/interrupt.h>
21#include <linux/ioport.h> 26#include <linux/ioport.h>
22#include <linux/serial_core.h> 27#include <linux/serial_core.h>
@@ -38,7 +43,6 @@
38#include <mach/regs-gpio.h> 43#include <mach/regs-gpio.h>
39 44
40#include <plat/cpu.h> 45#include <plat/cpu.h>
41#include <plat/clock.h>
42#include <plat/devs.h> 46#include <plat/devs.h>
43#include <plat/pm.h> 47#include <plat/pm.h>
44#include <plat/gpio-cfg.h> 48#include <plat/gpio-cfg.h>
@@ -50,6 +54,19 @@
50 54
51#include "common.h" 55#include "common.h"
52 56
57/* External clock frequency */
58static unsigned long xtal_f = 12000000, xusbxti_f = 48000000;
59
60void __init s3c64xx_set_xtal_freq(unsigned long freq)
61{
62 xtal_f = freq;
63}
64
65void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
66{
67 xusbxti_f = freq;
68}
69
53/* uart registration process */ 70/* uart registration process */
54 71
55static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) 72static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
@@ -67,7 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
67 .idcode = S3C6400_CPU_ID, 84 .idcode = S3C6400_CPU_ID,
68 .idmask = S3C64XX_CPU_MASK, 85 .idmask = S3C64XX_CPU_MASK,
69 .map_io = s3c6400_map_io, 86 .map_io = s3c6400_map_io,
70 .init_clocks = s3c6400_init_clocks,
71 .init_uarts = s3c64xx_init_uarts, 87 .init_uarts = s3c64xx_init_uarts,
72 .init = s3c6400_init, 88 .init = s3c6400_init,
73 .name = name_s3c6400, 89 .name = name_s3c6400,
@@ -75,7 +91,6 @@ static struct cpu_table cpu_ids[] __initdata = {
75 .idcode = S3C6410_CPU_ID, 91 .idcode = S3C6410_CPU_ID,
76 .idmask = S3C64XX_CPU_MASK, 92 .idmask = S3C64XX_CPU_MASK,
77 .map_io = s3c6410_map_io, 93 .map_io = s3c6410_map_io,
78 .init_clocks = s3c6410_init_clocks,
79 .init_uarts = s3c64xx_init_uarts, 94 .init_uarts = s3c64xx_init_uarts,
80 .init = s3c6410_init, 95 .init = s3c6410_init,
81 .name = name_s3c6410, 96 .name = name_s3c6410,
@@ -192,6 +207,10 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
192 207
193static __init int s3c64xx_dev_init(void) 208static __init int s3c64xx_dev_init(void)
194{ 209{
210 /* Not applicable when using DT. */
211 if (of_have_populated_dt())
212 return 0;
213
195 subsys_system_register(&s3c64xx_subsys, NULL); 214 subsys_system_register(&s3c64xx_subsys, NULL);
196 return device_register(&s3c64xx_dev); 215 return device_register(&s3c64xx_dev);
197} 216}
@@ -213,8 +232,10 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
213{ 232{
214 /* 233 /*
215 * FIXME: there is no better place to put this at the moment 234 * FIXME: there is no better place to put this at the moment
216 * (samsung_wdt_reset_init needs clocks) 235 * (s3c64xx_clk_init needs ioremap and must happen before init_time
236 * samsung_wdt_reset_init needs clocks)
217 */ 237 */
238 s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
218 samsung_wdt_reset_init(S3C_VA_WATCHDOG); 239 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
219 240
220 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 241 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
@@ -391,6 +412,10 @@ static int __init s3c64xx_init_irq_eint(void)
391{ 412{
392 int irq; 413 int irq;
393 414
415 /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
416 if (of_have_populated_dt())
417 return -ENODEV;
418
394 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { 419 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
395 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); 420 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
396 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); 421 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index e8f990b37665..bd3bd562011e 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -22,21 +22,21 @@
22void s3c64xx_init_irq(u32 vic0, u32 vic1); 22void s3c64xx_init_irq(u32 vic0, u32 vic1);
23void s3c64xx_init_io(struct map_desc *mach_desc, int size); 23void s3c64xx_init_io(struct map_desc *mach_desc, int size);
24 24
25void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
26void s3c64xx_setup_clocks(void);
27
28void s3c64xx_restart(enum reboot_mode mode, const char *cmd); 25void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
29void s3c64xx_init_late(void); 26void s3c64xx_init_late(void);
30 27
28void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
29 unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
30void s3c64xx_set_xtal_freq(unsigned long freq);
31void s3c64xx_set_xusbxti_freq(unsigned long freq);
32
31#ifdef CONFIG_CPU_S3C6400 33#ifdef CONFIG_CPU_S3C6400
32 34
33extern int s3c6400_init(void); 35extern int s3c6400_init(void);
34extern void s3c6400_init_irq(void); 36extern void s3c6400_init_irq(void);
35extern void s3c6400_map_io(void); 37extern void s3c6400_map_io(void);
36extern void s3c6400_init_clocks(int xtal);
37 38
38#else 39#else
39#define s3c6400_init_clocks NULL
40#define s3c6400_map_io NULL 40#define s3c6400_map_io NULL
41#define s3c6400_init NULL 41#define s3c6400_init NULL
42#endif 42#endif
@@ -46,10 +46,8 @@ extern void s3c6400_init_clocks(int xtal);
46extern int s3c6410_init(void); 46extern int s3c6410_init(void);
47extern void s3c6410_init_irq(void); 47extern void s3c6410_init_irq(void);
48extern void s3c6410_map_io(void); 48extern void s3c6410_map_io(void);
49extern void s3c6410_init_clocks(int xtal);
50 49
51#else 50#else
52#define s3c6410_init_clocks NULL
53#define s3c6410_map_io NULL 51#define s3c6410_map_io NULL
54#define s3c6410_init NULL 52#define s3c6410_init NULL
55#endif 53#endif
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 759846c28d12..7e22c2113816 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -12,6 +12,10 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15/*
16 * NOTE: Code in this file is not used when booting with Device Tree support.
17 */
18
15#include <linux/kernel.h> 19#include <linux/kernel.h>
16#include <linux/module.h> 20#include <linux/module.h>
17#include <linux/interrupt.h> 21#include <linux/interrupt.h>
@@ -24,6 +28,7 @@
24#include <linux/err.h> 28#include <linux/err.h>
25#include <linux/io.h> 29#include <linux/io.h>
26#include <linux/amba/pl080.h> 30#include <linux/amba/pl080.h>
31#include <linux/of.h>
27 32
28#include <mach/dma.h> 33#include <mach/dma.h>
29#include <mach/map.h> 34#include <mach/map.h>
@@ -677,7 +682,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
677 goto err_map; 682 goto err_map;
678 } 683 }
679 684
680 clk_enable(dmac->clk); 685 clk_prepare_enable(dmac->clk);
681 686
682 dmac->regs = regs; 687 dmac->regs = regs;
683 dmac->chanbase = chbase; 688 dmac->chanbase = chbase;
@@ -711,7 +716,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
711 return 0; 716 return 0;
712 717
713err_clk: 718err_clk:
714 clk_disable(dmac->clk); 719 clk_disable_unprepare(dmac->clk);
715 clk_put(dmac->clk); 720 clk_put(dmac->clk);
716err_map: 721err_map:
717 iounmap(regs); 722 iounmap(regs);
@@ -726,6 +731,10 @@ static int __init s3c64xx_dma_init(void)
726{ 731{
727 int ret; 732 int ret;
728 733
734 /* This driver is not supported when booting with device tree. */
735 if (of_have_populated_dt())
736 return -ENODEV;
737
729 printk(KERN_INFO "%s: Registering DMA channels\n", __func__); 738 printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
730 739
731 dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0); 740 dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0);
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
index 05332b998ec0..4f44aac77092 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -15,145 +15,21 @@
15#ifndef __PLAT_REGS_CLOCK_H 15#ifndef __PLAT_REGS_CLOCK_H
16#define __PLAT_REGS_CLOCK_H __FILE__ 16#define __PLAT_REGS_CLOCK_H __FILE__
17 17
18/*
19 * FIXME: Remove remaining definitions
20 */
21
18#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) 22#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
19 23
20#define S3C_APLL_LOCK S3C_CLKREG(0x00)
21#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
22#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
23#define S3C_APLL_CON S3C_CLKREG(0x0C)
24#define S3C_MPLL_CON S3C_CLKREG(0x10)
25#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
26#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
27#define S3C_CLK_SRC S3C_CLKREG(0x1C)
28#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
29#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
30#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
31#define S3C_CLK_OUT S3C_CLKREG(0x2C)
32#define S3C_HCLK_GATE S3C_CLKREG(0x30)
33#define S3C_PCLK_GATE S3C_CLKREG(0x34) 24#define S3C_PCLK_GATE S3C_CLKREG(0x34)
34#define S3C_SCLK_GATE S3C_CLKREG(0x38)
35#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
36#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) 25#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
37#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) 26#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
38 27
39/* CLKDIV0 */
40#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
41#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
42#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
43#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
44#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
45#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
46#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
47#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
48
49#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
50#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
51#define S3C6400_CLKDIV0_ARM_SHIFT (0)
52
53/* HCLK GATE Registers */
54#define S3C_CLKCON_HCLK_3DSE (1<<31)
55#define S3C_CLKCON_HCLK_UHOST (1<<29)
56#define S3C_CLKCON_HCLK_SECUR (1<<28)
57#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
58#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
59#define S3C_CLKCON_HCLK_IROM (1<<25)
60#define S3C_CLKCON_HCLK_DDR1 (1<<24)
61#define S3C_CLKCON_HCLK_DDR0 (1<<23)
62#define S3C_CLKCON_HCLK_MEM1 (1<<22)
63#define S3C_CLKCON_HCLK_MEM0 (1<<21)
64#define S3C_CLKCON_HCLK_USB (1<<20)
65#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
66#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
67#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
68#define S3C_CLKCON_HCLK_MDP (1<<16)
69#define S3C_CLKCON_HCLK_DHOST (1<<15)
70#define S3C_CLKCON_HCLK_IHOST (1<<14)
71#define S3C_CLKCON_HCLK_DMA1 (1<<13)
72#define S3C_CLKCON_HCLK_DMA0 (1<<12)
73#define S3C_CLKCON_HCLK_JPEG (1<<11)
74#define S3C_CLKCON_HCLK_CAMIF (1<<10)
75#define S3C_CLKCON_HCLK_SCALER (1<<9)
76#define S3C_CLKCON_HCLK_2D (1<<8)
77#define S3C_CLKCON_HCLK_TV (1<<7)
78#define S3C_CLKCON_HCLK_POST0 (1<<5)
79#define S3C_CLKCON_HCLK_ROT (1<<4)
80#define S3C_CLKCON_HCLK_LCD (1<<3)
81#define S3C_CLKCON_HCLK_TZIC (1<<2)
82#define S3C_CLKCON_HCLK_INTC (1<<1)
83#define S3C_CLKCON_HCLK_MFC (1<<0)
84
85/* PCLK GATE Registers */ 28/* PCLK GATE Registers */
86#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
87#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
88#define S3C_CLKCON_PCLK_SKEY (1<<24)
89#define S3C_CLKCON_PCLK_CHIPID (1<<23)
90#define S3C_CLKCON_PCLK_SPI1 (1<<22)
91#define S3C_CLKCON_PCLK_SPI0 (1<<21)
92#define S3C_CLKCON_PCLK_HSIRX (1<<20)
93#define S3C_CLKCON_PCLK_HSITX (1<<19)
94#define S3C_CLKCON_PCLK_GPIO (1<<18)
95#define S3C_CLKCON_PCLK_IIC (1<<17)
96#define S3C_CLKCON_PCLK_IIS1 (1<<16)
97#define S3C_CLKCON_PCLK_IIS0 (1<<15)
98#define S3C_CLKCON_PCLK_AC97 (1<<14)
99#define S3C_CLKCON_PCLK_TZPC (1<<13)
100#define S3C_CLKCON_PCLK_TSADC (1<<12)
101#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
102#define S3C_CLKCON_PCLK_IRDA (1<<10)
103#define S3C_CLKCON_PCLK_PCM1 (1<<9)
104#define S3C_CLKCON_PCLK_PCM0 (1<<8)
105#define S3C_CLKCON_PCLK_PWM (1<<7)
106#define S3C_CLKCON_PCLK_RTC (1<<6)
107#define S3C_CLKCON_PCLK_WDT (1<<5)
108#define S3C_CLKCON_PCLK_UART3 (1<<4) 29#define S3C_CLKCON_PCLK_UART3 (1<<4)
109#define S3C_CLKCON_PCLK_UART2 (1<<3) 30#define S3C_CLKCON_PCLK_UART2 (1<<3)
110#define S3C_CLKCON_PCLK_UART1 (1<<2) 31#define S3C_CLKCON_PCLK_UART1 (1<<2)
111#define S3C_CLKCON_PCLK_UART0 (1<<1) 32#define S3C_CLKCON_PCLK_UART0 (1<<1)
112#define S3C_CLKCON_PCLK_MFC (1<<0)
113
114/* SCLK GATE Registers */
115#define S3C_CLKCON_SCLK_UHOST (1<<30)
116#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
117#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
118#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
119#define S3C_CLKCON_SCLK_MMC2 (1<<26)
120#define S3C_CLKCON_SCLK_MMC1 (1<<25)
121#define S3C_CLKCON_SCLK_MMC0 (1<<24)
122#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
123#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
124#define S3C_CLKCON_SCLK_SPI1 (1<<21)
125#define S3C_CLKCON_SCLK_SPI0 (1<<20)
126#define S3C_CLKCON_SCLK_DAC27 (1<<19)
127#define S3C_CLKCON_SCLK_TV27 (1<<18)
128#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
129#define S3C_CLKCON_SCLK_SCALER (1<<16)
130#define S3C_CLKCON_SCLK_LCD27 (1<<15)
131#define S3C_CLKCON_SCLK_LCD (1<<14)
132#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
133#define S3C6410_CLKCON_FIMC (1<<13)
134#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
135#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
136#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
137#define S3C_CLKCON_SCLK_POST0 (1<<10)
138#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
139#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
140#define S3C_CLKCON_SCLK_SECUR (1<<7)
141#define S3C_CLKCON_SCLK_IRDA (1<<6)
142#define S3C_CLKCON_SCLK_UART (1<<5)
143#define S3C_CLKCON_SCLK_ONENAND (1<<4)
144#define S3C_CLKCON_SCLK_MFC (1<<3)
145#define S3C_CLKCON_SCLK_CAM (1<<2)
146#define S3C_CLKCON_SCLK_JPEG (1<<1)
147
148/* CLKSRC */
149
150#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
151#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
152#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
153#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
154#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
155#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
156#define S3C6400_CLKSRC_MFC (1 << 4)
157 33
158/* MEM_SYS_CFG */ 34/* MEM_SYS_CFG */
159#define MEM_SYS_CFG_INDEP_CF 0x4000 35#define MEM_SYS_CFG_INDEP_CF 0x4000
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index c3da1b68d03e..1649c0d1c1b8 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -12,12 +12,17 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15/*
16 * NOTE: Code in this file is not used when booting with Device Tree support.
17 */
18
15#include <linux/kernel.h> 19#include <linux/kernel.h>
16#include <linux/syscore_ops.h> 20#include <linux/syscore_ops.h>
17#include <linux/interrupt.h> 21#include <linux/interrupt.h>
18#include <linux/serial_core.h> 22#include <linux/serial_core.h>
19#include <linux/irq.h> 23#include <linux/irq.h>
20#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/of.h>
21 26
22#include <mach/map.h> 27#include <mach/map.h>
23 28
@@ -101,6 +106,10 @@ static struct syscore_ops s3c64xx_irq_syscore_ops = {
101 106
102static __init int s3c64xx_syscore_init(void) 107static __init int s3c64xx_syscore_init(void)
103{ 108{
109 /* Appropriate drivers (pinctrl, uart) handle this when using DT. */
110 if (of_have_populated_dt())
111 return 0;
112
104 register_syscore_ops(&s3c64xx_irq_syscore_ops); 113 register_syscore_ops(&s3c64xx_irq_syscore_ops);
105 114
106 return 0; 115 return 0;
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 35e3f54574ef..d266dd5f7060 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = {
207static void __init anw6410_map_io(void) 207static void __init anw6410_map_io(void)
208{ 208{
209 s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc)); 209 s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
210 s3c24xx_init_clocks(12000000); 210 s3c64xx_set_xtal_freq(12000000);
211 s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs)); 211 s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
212 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 212 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
213 213
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index eb8e5a1aca42..1a911df9e451 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -743,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = {
743static void __init crag6410_map_io(void) 743static void __init crag6410_map_io(void)
744{ 744{
745 s3c64xx_init_io(NULL, 0); 745 s3c64xx_init_io(NULL, 0);
746 s3c24xx_init_clocks(12000000); 746 s3c64xx_set_xtal_freq(12000000);
747 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); 747 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
748 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 748 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
749 749
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index f39569e0f2e6..e8064044ef79 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -247,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = {
247static void __init hmt_map_io(void) 247static void __init hmt_map_io(void)
248{ 248{
249 s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); 249 s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
250 s3c24xx_init_clocks(12000000); 250 s3c64xx_set_xtal_freq(12000000);
251 s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); 251 s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
252 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 252 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
253} 253}
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index fc043e3ecdf8..58d46a3d7b78 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -231,7 +231,7 @@ static void __init mini6410_map_io(void)
231 u32 tmp; 231 u32 tmp;
232 232
233 s3c64xx_init_io(NULL, 0); 233 s3c64xx_init_io(NULL, 0);
234 s3c24xx_init_clocks(12000000); 234 s3c64xx_set_xtal_freq(12000000);
235 s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs)); 235 s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
236 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 236 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
237 237
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 7e2c3908f1f8..2067b0bf55b4 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {};
86static void __init ncp_map_io(void) 86static void __init ncp_map_io(void)
87{ 87{
88 s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc)); 88 s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
89 s3c24xx_init_clocks(12000000); 89 s3c64xx_set_xtal_freq(12000000);
90 s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs)); 90 s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
91 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 91 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
92} 92}
diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
new file mode 100644
index 000000000000..7eb9a10fc1af
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
@@ -0,0 +1,85 @@
1/*
2 * Samsung's S3C64XX flattened device tree enabled machine
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/clk-provider.h>
12#include <linux/irqchip.h>
13#include <linux/of_platform.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/system_misc.h>
18
19#include <plat/cpu.h>
20#include <plat/watchdog-reset.h>
21
22#include <mach/map.h>
23
24#include "common.h"
25
26/*
27 * IO mapping for shared system controller IP.
28 *
29 * FIXME: Make remaining drivers use dynamic mapping.
30 */
31static struct map_desc s3c64xx_dt_iodesc[] __initdata = {
32 {
33 .virtual = (unsigned long)S3C_VA_SYS,
34 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
35 .length = SZ_4K,
36 .type = MT_DEVICE,
37 },
38};
39
40static void __init s3c64xx_dt_map_io(void)
41{
42 debug_ll_io_init();
43 iotable_init(s3c64xx_dt_iodesc, ARRAY_SIZE(s3c64xx_dt_iodesc));
44
45 s3c64xx_init_cpu();
46
47 if (!soc_is_s3c64xx())
48 panic("SoC is not S3C64xx!");
49}
50
51static void __init s3c64xx_dt_init_irq(void)
52{
53 of_clk_init(NULL);
54 samsung_wdt_reset_of_init();
55 irqchip_init();
56};
57
58static void __init s3c64xx_dt_init_machine(void)
59{
60 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
61}
62
63static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd)
64{
65 if (mode != REBOOT_SOFT)
66 samsung_wdt_reset();
67
68 /* if all else fails, or mode was for soft, jump to 0 */
69 soft_restart(0);
70}
71
72static char const *s3c64xx_dt_compat[] __initdata = {
73 "samsung,s3c6400",
74 "samsung,s3c6410",
75 NULL
76};
77
78DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened Device Tree)")
79 /* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */
80 .dt_compat = s3c64xx_dt_compat,
81 .map_io = s3c64xx_dt_map_io,
82 .init_irq = s3c64xx_dt_init_irq,
83 .init_machine = s3c64xx_dt_init_machine,
84 .restart = s3c64xx_dt_restart,
85MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 86d980b448fd..0f47237be3b2 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -337,13 +337,6 @@ err:
337 return ret; 337 return ret;
338} 338}
339 339
340static int __init smartq_usb_otg_init(void)
341{
342 clk_xusbxti.rate = 12000000;
343
344 return 0;
345}
346
347static int __init smartq_wifi_init(void) 340static int __init smartq_wifi_init(void)
348{ 341{
349 int ret; 342 int ret;
@@ -377,7 +370,8 @@ static struct map_desc smartq_iodesc[] __initdata = {};
377void __init smartq_map_io(void) 370void __init smartq_map_io(void)
378{ 371{
379 s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc)); 372 s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
380 s3c24xx_init_clocks(12000000); 373 s3c64xx_set_xtal_freq(12000000);
374 s3c64xx_set_xusbxti_freq(12000000);
381 s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs)); 375 s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
382 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 376 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
383 377
@@ -399,7 +393,6 @@ void __init smartq_machine_init(void)
399 WARN_ON(smartq_lcd_setup_gpio()); 393 WARN_ON(smartq_lcd_setup_gpio());
400 WARN_ON(smartq_power_off_init()); 394 WARN_ON(smartq_power_off_init());
401 WARN_ON(smartq_usb_host_init()); 395 WARN_ON(smartq_usb_host_init());
402 WARN_ON(smartq_usb_otg_init());
403 WARN_ON(smartq_wifi_init()); 396 WARN_ON(smartq_wifi_init());
404 397
405 platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices)); 398 platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index d70c0843aea2..27381cfcabbe 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {};
65static void __init smdk6400_map_io(void) 65static void __init smdk6400_map_io(void)
66{ 66{
67 s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); 67 s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
68 s3c24xx_init_clocks(12000000); 68 s3c64xx_set_xtal_freq(12000000);
69 s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); 69 s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
70 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 70 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
71} 71}
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d90b450c5645..2a7b32ca5c96 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -634,7 +634,7 @@ static void __init smdk6410_map_io(void)
634 u32 tmp; 634 u32 tmp;
635 635
636 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); 636 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
637 s3c24xx_init_clocks(12000000); 637 s3c64xx_set_xtal_freq(12000000);
638 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); 638 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
639 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 639 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
640 640
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 6a1f91fea678..8cdb824a3b43 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -194,29 +194,8 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear)
194#endif 194#endif
195 195
196static struct sleep_save core_save[] = { 196static struct sleep_save core_save[] = {
197 SAVE_ITEM(S3C_APLL_LOCK),
198 SAVE_ITEM(S3C_MPLL_LOCK),
199 SAVE_ITEM(S3C_EPLL_LOCK),
200 SAVE_ITEM(S3C_CLK_SRC),
201 SAVE_ITEM(S3C_CLK_DIV0),
202 SAVE_ITEM(S3C_CLK_DIV1),
203 SAVE_ITEM(S3C_CLK_DIV2),
204 SAVE_ITEM(S3C_CLK_OUT),
205 SAVE_ITEM(S3C_HCLK_GATE),
206 SAVE_ITEM(S3C_PCLK_GATE),
207 SAVE_ITEM(S3C_SCLK_GATE),
208 SAVE_ITEM(S3C_MEM0_GATE),
209
210 SAVE_ITEM(S3C_EPLL_CON1),
211 SAVE_ITEM(S3C_EPLL_CON0),
212
213 SAVE_ITEM(S3C64XX_MEM0DRVCON), 197 SAVE_ITEM(S3C64XX_MEM0DRVCON),
214 SAVE_ITEM(S3C64XX_MEM1DRVCON), 198 SAVE_ITEM(S3C64XX_MEM1DRVCON),
215
216#ifndef CONFIG_CPU_FREQ
217 SAVE_ITEM(S3C_APLL_CON),
218 SAVE_ITEM(S3C_MPLL_CON),
219#endif
220}; 199};
221 200
222static struct sleep_save misc_save[] = { 201static struct sleep_save misc_save[] = {
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 4869714c6f1b..3db0c98222f7 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -9,6 +9,10 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12/*
13 * NOTE: Code in this file is not used when booting with Device Tree support.
14 */
15
12#include <linux/kernel.h> 16#include <linux/kernel.h>
13#include <linux/types.h> 17#include <linux/types.h>
14#include <linux/interrupt.h> 18#include <linux/interrupt.h>
@@ -20,6 +24,7 @@
20#include <linux/device.h> 24#include <linux/device.h>
21#include <linux/serial_core.h> 25#include <linux/serial_core.h>
22#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/of.h>
23 28
24#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 30#include <asm/mach/map.h>
@@ -58,12 +63,6 @@ void __init s3c6400_map_io(void)
58 s3c64xx_onenand1_setname("s3c6400-onenand"); 63 s3c64xx_onenand1_setname("s3c6400-onenand");
59} 64}
60 65
61void __init s3c6400_init_clocks(int xtal)
62{
63 s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
64 s3c64xx_setup_clocks();
65}
66
67void __init s3c6400_init_irq(void) 66void __init s3c6400_init_irq(void)
68{ 67{
69 /* VIC0 does not have IRQS 5..7, 68 /* VIC0 does not have IRQS 5..7,
@@ -82,6 +81,10 @@ static struct device s3c6400_dev = {
82 81
83static int __init s3c6400_core_init(void) 82static int __init s3c6400_core_init(void)
84{ 83{
84 /* Not applicable when using DT. */
85 if (of_have_populated_dt())
86 return 0;
87
85 return subsys_system_register(&s3c6400_subsys, NULL); 88 return subsys_system_register(&s3c6400_subsys, NULL);
86} 89}
87 90
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 31c29fdf1800..72b2278953a8 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -10,6 +10,10 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13/*
14 * NOTE: Code in this file is not used when booting with Device Tree support.
15 */
16
13#include <linux/kernel.h> 17#include <linux/kernel.h>
14#include <linux/types.h> 18#include <linux/types.h>
15#include <linux/interrupt.h> 19#include <linux/interrupt.h>
@@ -21,6 +25,7 @@
21#include <linux/device.h> 25#include <linux/device.h>
22#include <linux/serial_core.h> 26#include <linux/serial_core.h>
23#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/of.h>
24 29
25#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 31#include <asm/mach/map.h>
@@ -62,13 +67,6 @@ void __init s3c6410_map_io(void)
62 s3c_cfcon_setname("s3c64xx-pata"); 67 s3c_cfcon_setname("s3c64xx-pata");
63} 68}
64 69
65void __init s3c6410_init_clocks(int xtal)
66{
67 printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
68 s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
69 s3c64xx_setup_clocks();
70}
71
72void __init s3c6410_init_irq(void) 70void __init s3c6410_init_irq(void)
73{ 71{
74 /* VIC0 is missing IRQ7, VIC1 is fully populated. */ 72 /* VIC0 is missing IRQ7, VIC1 is fully populated. */
@@ -86,6 +84,10 @@ static struct device s3c6410_dev = {
86 84
87static int __init s3c6410_core_init(void) 85static int __init s3c6410_core_init(void)
88{ 86{
87 /* Not applicable when using DT. */
88 if (of_have_populated_dt())
89 return 0;
90
89 return subsys_system_register(&s3c6410_subsys, NULL); 91 return subsys_system_register(&s3c6410_subsys, NULL);
90} 92}
91 93
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03a10d1..335beb341355 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -87,8 +87,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
87#endif 87#endif
88 88
89#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 89#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
90# define soc_is_s3c6400() is_samsung_s3c6400()
91# define soc_is_s3c6410() is_samsung_s3c6410()
90# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) 92# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410())
91#else 93#else
94# define soc_is_s3c6400() 0
95# define soc_is_s3c6410() 0
92# define soc_is_s3c64xx() 0 96# define soc_is_s3c64xx() 0
93#endif 97#endif
94 98
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 50a3ea0037db..aa9511b6914a 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -11,12 +11,18 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12*/ 12*/
13 13
14/*
15 * NOTE: Code in this file is not used on S3C64xx when booting with
16 * Device Tree support.
17 */
18
14#include <linux/init.h> 19#include <linux/init.h>
15#include <linux/module.h> 20#include <linux/module.h>
16#include <linux/interrupt.h> 21#include <linux/interrupt.h>
17#include <linux/ioport.h> 22#include <linux/ioport.h>
18#include <linux/serial_core.h> 23#include <linux/serial_core.h>
19#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/of.h>
20 26
21#include <mach/hardware.h> 27#include <mach/hardware.h>
22 28
@@ -148,8 +154,12 @@ static int __init s3c_arch_init(void)
148 154
149 // do the correct init for cpu 155 // do the correct init for cpu
150 156
151 if (cpu == NULL) 157 if (cpu == NULL) {
158 /* Not needed when booting with device tree. */
159 if (of_have_populated_dt())
160 return 0;
152 panic("s3c_arch_init: NULL cpu\n"); 161 panic("s3c_arch_init: NULL cpu\n");
162 }
153 163
154 ret = (cpu->init)(); 164 ret = (cpu->init)();
155 if (ret != 0) 165 if (ret != 0)
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380086d5..8eb4799237f0 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
8obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o 8obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
9obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 9obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
10obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 10obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
11ifdef CONFIG_COMMON_CLK
12obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o 11obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
13endif
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 358a21c2d811..29b5d6777dc5 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2082,34 +2082,14 @@ static __init int samsung_gpiolib_init(void)
2082 int i, nr_chips; 2082 int i, nr_chips;
2083 int group = 0; 2083 int group = 0;
2084 2084
2085#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
2086 /* 2085 /*
2087 * This gpio driver includes support for device tree support and there 2086 * Currently there are two drivers that can provide GPIO support for
2088 * are platforms using it. In order to maintain compatibility with those 2087 * Samsung SoCs. For device tree enabled platforms, the new
2089 * platforms, and to allow non-dt Exynos4210 platforms to use this 2088 * pinctrl-samsung driver is used, providing both GPIO and pin control
2090 * gpiolib support, a check is added to find out if there is a active 2089 * interfaces. For legacy (non-DT) platforms this driver is used.
2091 * pin-controller driver support available. If it is available, this 2090 */
2092 * gpiolib support is ignored and the gpiolib support available in 2091 if (of_have_populated_dt())
2093 * pin-controller driver is used. This is a temporary check and will go 2092 return -ENODEV;
2094 * away when all of the Exynos4210 platforms have switched to using
2095 * device tree and the pin-ctrl driver.
2096 */
2097 struct device_node *pctrl_np;
2098 static const struct of_device_id exynos_pinctrl_ids[] = {
2099 { .compatible = "samsung,s3c2412-pinctrl", },
2100 { .compatible = "samsung,s3c2416-pinctrl", },
2101 { .compatible = "samsung,s3c2440-pinctrl", },
2102 { .compatible = "samsung,s3c2450-pinctrl", },
2103 { .compatible = "samsung,exynos4210-pinctrl", },
2104 { .compatible = "samsung,exynos4x12-pinctrl", },
2105 { .compatible = "samsung,exynos5250-pinctrl", },
2106 { .compatible = "samsung,exynos5440-pinctrl", },
2107 { }
2108 };
2109 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
2110 if (pctrl_np && of_device_is_available(pctrl_np))
2111 return -ENODEV;
2112#endif
2113 2093
2114 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); 2094 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2115 2095
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 2bbb00404cf5..8e21ae0bab46 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -469,6 +469,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
469int __init vic_of_init(struct device_node *node, struct device_node *parent) 469int __init vic_of_init(struct device_node *node, struct device_node *parent)
470{ 470{
471 void __iomem *regs; 471 void __iomem *regs;
472 u32 interrupt_mask = ~0;
473 u32 wakeup_mask = ~0;
472 474
473 if (WARN(parent, "non-root VICs are not supported")) 475 if (WARN(parent, "non-root VICs are not supported"))
474 return -EINVAL; 476 return -EINVAL;
@@ -477,10 +479,13 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
477 if (WARN_ON(!regs)) 479 if (WARN_ON(!regs))
478 return -EIO; 480 return -EIO;
479 481
482 of_property_read_u32(node, "valid-mask", &interrupt_mask);
483 of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
484
480 /* 485 /*
481 * Passing 0 as first IRQ makes the simple domain allocate descriptors 486 * Passing 0 as first IRQ makes the simple domain allocate descriptors
482 */ 487 */
483 __vic_init(regs, 0, ~0, ~0, node); 488 __vic_init(regs, 0, interrupt_mask, wakeup_mask, node);
484 489
485 return 0; 490 return 0;
486} 491}
diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
index 4919afa4125e..1adff32e40e2 100644
--- a/drivers/usb/host/ohci-s3c2410.c
+++ b/drivers/usb/host/ohci-s3c2410.c
@@ -47,10 +47,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)
47 47
48 dev_dbg(&dev->dev, "s3c2410_start_hc:\n"); 48 dev_dbg(&dev->dev, "s3c2410_start_hc:\n");
49 49
50 clk_enable(usb_clk); 50 clk_prepare_enable(usb_clk);
51 mdelay(2); /* let the bus clock stabilise */ 51 mdelay(2); /* let the bus clock stabilise */
52 52
53 clk_enable(clk); 53 clk_prepare_enable(clk);
54 54
55 if (info != NULL) { 55 if (info != NULL) {
56 info->hcd = hcd; 56 info->hcd = hcd;
@@ -75,8 +75,8 @@ static void s3c2410_stop_hc(struct platform_device *dev)
75 (info->enable_oc)(info, 0); 75 (info->enable_oc)(info, 0);
76 } 76 }
77 77
78 clk_disable(clk); 78 clk_disable_unprepare(clk);
79 clk_disable(usb_clk); 79 clk_disable_unprepare(usb_clk);
80} 80}
81 81
82/* ohci_s3c2410_hub_status_data 82/* ohci_s3c2410_hub_status_data
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-18 22:26:27 -0400