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-rw-r--r--Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt14
-rw-r--r--drivers/mmc/host/dw_mmc-k3.c41
2 files changed, 2 insertions, 53 deletions
diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
index d7e2d7f159bb..b8653ea97957 100644
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
@@ -14,18 +14,6 @@ Required Properties:
14* compatible: should be one of the following. 14* compatible: should be one of the following.
15 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extentions. 15 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extentions.
16 16
17* clock-freq-table: should be the frequency (in Hz) array of the ciu clock
18 in each supported mode.
19 0. CIU clock rate in Hz for DS mode
20 1. CIU clock rate in Hz for MMC HS mode
21 2. CIU clock rate in Hz for SD HS mode
22 3. CIU clock rate in Hz for SDR12 mode
23 4. CIU clock rate in Hz for SDR25 mode
24 5. CIU clock rate in Hz for SDR50 mode
25 6. CIU clock rate in Hz for SDR104 mode
26 7. CIU clock rate in Hz for DDR50 mode
27 8. CIU clock rate in Hz for HS200 mode
28
29Example: 17Example:
30 18
31 /* for Hi3620 */ 19 /* for Hi3620 */
@@ -39,8 +27,6 @@ Example:
39 #size-cells = <0>; 27 #size-cells = <0>;
40 clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>; 28 clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>;
41 clock-names = "ciu", "biu"; 29 clock-names = "ciu", "biu";
42 clock-freq-table =
43 <25000000 0 50000000 25000000 50000000 100000000 0 50000000>;
44 }; 30 };
45 31
46 /* Board portion */ 32 /* Board portion */
diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index 3542a03e9f99..f567c219cff4 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -18,56 +18,19 @@
18#include "dw_mmc.h" 18#include "dw_mmc.h"
19#include "dw_mmc-pltfm.h" 19#include "dw_mmc-pltfm.h"
20 20
21#define MAX_NUMS 10
22struct dw_mci_k3_priv_data {
23 u32 clk_table[MAX_NUMS];
24};
25
26static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios) 21static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
27{ 22{
28 struct dw_mci_k3_priv_data *priv = host->priv;
29 u32 rate = priv->clk_table[ios->timing];
30 int ret; 23 int ret;
31 24
32 if (!rate) { 25 ret = clk_set_rate(host->ciu_clk, ios->clock);
33 dev_warn(host->dev,
34 "no specified rate in timing %u\n", ios->timing);
35 return;
36 }
37
38 ret = clk_set_rate(host->ciu_clk, rate);
39 if (ret) 26 if (ret)
40 dev_warn(host->dev, "failed to set clock rate %uHz\n", rate); 27 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
41 28
42 host->bus_hz = clk_get_rate(host->ciu_clk); 29 host->bus_hz = clk_get_rate(host->ciu_clk);
43} 30}
44 31
45static int dw_mci_k3_parse_dt(struct dw_mci *host)
46{
47 struct dw_mci_k3_priv_data *priv;
48 struct device_node *node = host->dev->of_node;
49 struct property *prop;
50 const __be32 *cur;
51 u32 val, num = 0;
52
53 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
54 if (!priv) {
55 dev_err(host->dev, "mem alloc failed for private data\n");
56 return -ENOMEM;
57 }
58 host->priv = priv;
59
60 of_property_for_each_u32(node, "clock-freq-table", prop, cur, val) {
61 if (num >= MAX_NUMS)
62 break;
63 priv->clk_table[num++] = val;
64 }
65 return 0;
66}
67
68static const struct dw_mci_drv_data k3_drv_data = { 32static const struct dw_mci_drv_data k3_drv_data = {
69 .set_ios = dw_mci_k3_set_ios, 33 .set_ios = dw_mci_k3_set_ios,
70 .parse_dt = dw_mci_k3_parse_dt,
71}; 34};
72 35
73static const struct of_device_id dw_mci_k3_match[] = { 36static const struct of_device_id dw_mci_k3_match[] = {