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-rw-r--r--Documentation/thermal/nouveau_thermal7
-rw-r--r--drivers/gpu/drm/drm_modeset_lock.c1
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c47
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c9
-rw-r--r--drivers/gpu/drm/i915/i915_gpu_error.c3
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c18
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c5
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c9
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h2
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c4
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c3
-rw-r--r--drivers/gpu/drm/nouveau/Makefile1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nvc0.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/base.c6
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/dport.c7
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc18
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h460
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h460
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h188
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h188
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h170
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h170
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc6
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv50.c9
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c41
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h2
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/i2c.h1
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c8
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c76
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c39
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c19
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c7
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c118
-rw-r--r--drivers/gpu/drm/radeon/evergreen_reg.h2
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c35
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c22
-rw-r--r--drivers/tty/vt/vt.c24
-rw-r--r--drivers/video/console/dummycon.c1
-rw-r--r--drivers/video/console/vgacon.c1
48 files changed, 1373 insertions, 832 deletions
diff --git a/Documentation/thermal/nouveau_thermal b/Documentation/thermal/nouveau_thermal
index efceb7828f54..60bc29357ac3 100644
--- a/Documentation/thermal/nouveau_thermal
+++ b/Documentation/thermal/nouveau_thermal
@@ -4,7 +4,7 @@ Kernel driver nouveau
4Supported chips: 4Supported chips:
5* NV43+ 5* NV43+
6 6
7Authors: Martin Peres (mupuf) <martin.peres@labri.fr> 7Authors: Martin Peres (mupuf) <martin.peres@free.fr>
8 8
9Description 9Description
10--------- 10---------
@@ -68,8 +68,9 @@ Your fan can be driven in different modes:
68 68
69NOTE: Be sure to use the manual mode if you want to drive the fan speed manually 69NOTE: Be sure to use the manual mode if you want to drive the fan speed manually
70 70
71NOTE2: Not all fan management modes may be supported on all chipsets. We are 71NOTE2: When operating in manual mode outside the vbios-defined
72working on it. 72[PWM_min, PWM_max] range, the reported fan speed (RPM) may not be accurate
73depending on your hardware.
73 74
74Bug reports 75Bug reports
75--------- 76---------
diff --git a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c
index 7c2497dea1e9..0dc57d5ecd10 100644
--- a/drivers/gpu/drm/drm_modeset_lock.c
+++ b/drivers/gpu/drm/drm_modeset_lock.c
@@ -64,6 +64,7 @@
64void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx, 64void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx,
65 uint32_t flags) 65 uint32_t flags)
66{ 66{
67 memset(ctx, 0, sizeof(*ctx));
67 ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class); 68 ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class);
68 INIT_LIST_HEAD(&ctx->locked); 69 INIT_LIST_HEAD(&ctx->locked);
69} 70}
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4c22a5b7f4c5..6c656392d67d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -36,6 +36,8 @@
36#include "i915_drv.h" 36#include "i915_drv.h"
37#include "i915_trace.h" 37#include "i915_trace.h"
38#include <linux/pci.h> 38#include <linux/pci.h>
39#include <linux/console.h>
40#include <linux/vt.h>
39#include <linux/vgaarb.h> 41#include <linux/vgaarb.h>
40#include <linux/acpi.h> 42#include <linux/acpi.h>
41#include <linux/pnp.h> 43#include <linux/pnp.h>
@@ -1386,7 +1388,6 @@ cleanup_gem:
1386 i915_gem_context_fini(dev); 1388 i915_gem_context_fini(dev);
1387 mutex_unlock(&dev->struct_mutex); 1389 mutex_unlock(&dev->struct_mutex);
1388 WARN_ON(dev_priv->mm.aliasing_ppgtt); 1390 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1389 drm_mm_takedown(&dev_priv->gtt.base.mm);
1390cleanup_irq: 1391cleanup_irq:
1391 drm_irq_uninstall(dev); 1392 drm_irq_uninstall(dev);
1392cleanup_gem_stolen: 1393cleanup_gem_stolen:
@@ -1450,6 +1451,38 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1450} 1451}
1451#endif 1452#endif
1452 1453
1454#if !defined(CONFIG_VGA_CONSOLE)
1455static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1456{
1457 return 0;
1458}
1459#elif !defined(CONFIG_DUMMY_CONSOLE)
1460static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1461{
1462 return -ENODEV;
1463}
1464#else
1465static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1466{
1467 int ret;
1468
1469 DRM_INFO("Replacing VGA console driver\n");
1470
1471 console_lock();
1472 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1473 if (ret == 0) {
1474 ret = do_unregister_con_driver(&vga_con);
1475
1476 /* Ignore "already unregistered". */
1477 if (ret == -ENODEV)
1478 ret = 0;
1479 }
1480 console_unlock();
1481
1482 return ret;
1483}
1484#endif
1485
1453static void i915_dump_device_info(struct drm_i915_private *dev_priv) 1486static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1454{ 1487{
1455 const struct intel_device_info *info = &dev_priv->info; 1488 const struct intel_device_info *info = &dev_priv->info;
@@ -1623,8 +1656,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1623 if (ret) 1656 if (ret)
1624 goto out_regs; 1657 goto out_regs;
1625 1658
1626 if (drm_core_check_feature(dev, DRIVER_MODESET)) 1659 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1660 ret = i915_kick_out_vgacon(dev_priv);
1661 if (ret) {
1662 DRM_ERROR("failed to remove conflicting VGA console\n");
1663 goto out_gtt;
1664 }
1665
1627 i915_kick_out_firmware_fb(dev_priv); 1666 i915_kick_out_firmware_fb(dev_priv);
1667 }
1628 1668
1629 pci_set_master(dev->pdev); 1669 pci_set_master(dev->pdev);
1630 1670
@@ -1756,8 +1796,6 @@ out_mtrrfree:
1756 arch_phys_wc_del(dev_priv->gtt.mtrr); 1796 arch_phys_wc_del(dev_priv->gtt.mtrr);
1757 io_mapping_free(dev_priv->gtt.mappable); 1797 io_mapping_free(dev_priv->gtt.mappable);
1758out_gtt: 1798out_gtt:
1759 list_del(&dev_priv->gtt.base.global_link);
1760 drm_mm_takedown(&dev_priv->gtt.base.mm);
1761 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); 1799 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1762out_regs: 1800out_regs:
1763 intel_uncore_fini(dev); 1801 intel_uncore_fini(dev);
@@ -1846,7 +1884,6 @@ int i915_driver_unload(struct drm_device *dev)
1846 i915_free_hws(dev); 1884 i915_free_hws(dev);
1847 } 1885 }
1848 1886
1849 list_del(&dev_priv->gtt.base.global_link);
1850 WARN_ON(!list_empty(&dev_priv->vm_list)); 1887 WARN_ON(!list_empty(&dev_priv->vm_list));
1851 1888
1852 drm_vblank_cleanup(dev); 1889 drm_vblank_cleanup(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eec820aec022..8b3cde703364 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1992,7 +1992,10 @@ static void gen6_gmch_remove(struct i915_address_space *vm)
1992 1992
1993 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); 1993 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1994 1994
1995 drm_mm_takedown(&vm->mm); 1995 if (drm_mm_initialized(&vm->mm)) {
1996 drm_mm_takedown(&vm->mm);
1997 list_del(&vm->global_link);
1998 }
1996 iounmap(gtt->gsm); 1999 iounmap(gtt->gsm);
1997 teardown_scratch_page(vm->dev); 2000 teardown_scratch_page(vm->dev);
1998} 2001}
@@ -2025,6 +2028,10 @@ static int i915_gmch_probe(struct drm_device *dev,
2025 2028
2026static void i915_gmch_remove(struct i915_address_space *vm) 2029static void i915_gmch_remove(struct i915_address_space *vm)
2027{ 2030{
2031 if (drm_mm_initialized(&vm->mm)) {
2032 drm_mm_takedown(&vm->mm);
2033 list_del(&vm->global_link);
2034 }
2028 intel_gmch_remove(); 2035 intel_gmch_remove();
2029} 2036}
2030 2037
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 87ec60e181a7..66cf41765bf9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -888,6 +888,8 @@ static void i915_gem_record_rings(struct drm_device *dev,
888 for (i = 0; i < I915_NUM_RINGS; i++) { 888 for (i = 0; i < I915_NUM_RINGS; i++) {
889 struct intel_engine_cs *ring = &dev_priv->ring[i]; 889 struct intel_engine_cs *ring = &dev_priv->ring[i];
890 890
891 error->ring[i].pid = -1;
892
891 if (ring->dev == NULL) 893 if (ring->dev == NULL)
892 continue; 894 continue;
893 895
@@ -895,7 +897,6 @@ static void i915_gem_record_rings(struct drm_device *dev,
895 897
896 i915_record_ring_state(dev, ring, &error->ring[i]); 898 i915_record_ring_state(dev, ring, &error->ring[i]);
897 899
898 error->ring[i].pid = -1;
899 request = i915_gem_find_active_request(ring); 900 request = i915_gem_find_active_request(ring);
900 if (request) { 901 if (request) {
901 /* We need to copy these to an anonymous buffer 902 /* We need to copy these to an anonymous buffer
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6f8017a7e937..267f069765ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2847,10 +2847,14 @@ static int semaphore_passed(struct intel_engine_cs *ring)
2847 struct intel_engine_cs *signaller; 2847 struct intel_engine_cs *signaller;
2848 u32 seqno, ctl; 2848 u32 seqno, ctl;
2849 2849
2850 ring->hangcheck.deadlock = true; 2850 ring->hangcheck.deadlock++;
2851 2851
2852 signaller = semaphore_waits_for(ring, &seqno); 2852 signaller = semaphore_waits_for(ring, &seqno);
2853 if (signaller == NULL || signaller->hangcheck.deadlock) 2853 if (signaller == NULL)
2854 return -1;
2855
2856 /* Prevent pathological recursion due to driver bugs */
2857 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2854 return -1; 2858 return -1;
2855 2859
2856 /* cursory check for an unkickable deadlock */ 2860 /* cursory check for an unkickable deadlock */
@@ -2858,7 +2862,13 @@ static int semaphore_passed(struct intel_engine_cs *ring)
2858 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) 2862 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2859 return -1; 2863 return -1;
2860 2864
2861 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); 2865 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2866 return 1;
2867
2868 if (signaller->hangcheck.deadlock)
2869 return -1;
2870
2871 return 0;
2862} 2872}
2863 2873
2864static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) 2874static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
@@ -2867,7 +2877,7 @@ static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2867 int i; 2877 int i;
2868 2878
2869 for_each_ring(ring, dev_priv, i) 2879 for_each_ring(ring, dev_priv, i)
2870 ring->hangcheck.deadlock = false; 2880 ring->hangcheck.deadlock = 0;
2871} 2881}
2872 2882
2873static enum intel_ring_hangcheck_action 2883static enum intel_ring_hangcheck_action
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 5e6c888b4928..38a98570d10c 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -798,9 +798,6 @@ static void i965_enable_backlight(struct intel_connector *connector)
798 ctl = freq << 16; 798 ctl = freq << 16;
799 I915_WRITE(BLC_PWM_CTL, ctl); 799 I915_WRITE(BLC_PWM_CTL, ctl);
800 800
801 /* XXX: combine this into above write? */
802 intel_panel_actually_set_backlight(connector, panel->backlight.level);
803
804 ctl2 = BLM_PIPE(pipe); 801 ctl2 = BLM_PIPE(pipe);
805 if (panel->backlight.combination_mode) 802 if (panel->backlight.combination_mode)
806 ctl2 |= BLM_COMBINATION_MODE; 803 ctl2 |= BLM_COMBINATION_MODE;
@@ -809,6 +806,8 @@ static void i965_enable_backlight(struct intel_connector *connector)
809 I915_WRITE(BLC_PWM_CTL2, ctl2); 806 I915_WRITE(BLC_PWM_CTL2, ctl2);
810 POSTING_READ(BLC_PWM_CTL2); 807 POSTING_READ(BLC_PWM_CTL2);
811 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); 808 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
809
810 intel_panel_actually_set_backlight(connector, panel->backlight.level);
812} 811}
813 812
814static void vlv_enable_backlight(struct intel_connector *connector) 813static void vlv_enable_backlight(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1e53abec1b5..769caea97c21 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -511,8 +511,7 @@ void intel_update_fbc(struct drm_device *dev)
511 obj = intel_fb->obj; 511 obj = intel_fb->obj;
512 adjusted_mode = &intel_crtc->config.adjusted_mode; 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
513 513
514 if (i915.enable_fbc < 0 && 514 if (i915.enable_fbc < 0) {
515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) 515 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n"); 516 DRM_DEBUG_KMS("disabled per chip default\n");
518 goto out_disable; 517 goto out_disable;
@@ -3506,15 +3505,11 @@ static void gen8_enable_rps(struct drm_device *dev)
3506 3505
3507 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 3506 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3508 3507
3509 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
3510 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
3511 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
3512
3513 /* 5: Enable RPS */ 3508 /* 5: Enable RPS */
3514 I915_WRITE(GEN6_RP_CONTROL, 3509 I915_WRITE(GEN6_RP_CONTROL,
3515 GEN6_RP_MEDIA_TURBO | 3510 GEN6_RP_MEDIA_TURBO |
3516 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3511 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3517 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ 3512 GEN6_RP_MEDIA_IS_GFX |
3518 GEN6_RP_ENABLE | 3513 GEN6_RP_ENABLE |
3519 GEN6_RP_UP_BUSY_AVG | 3514 GEN6_RP_UP_BUSY_AVG |
3520 GEN6_RP_DOWN_IDLE_AVG); 3515 GEN6_RP_DOWN_IDLE_AVG);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 910c83cf7d44..e72017bdcd7f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -55,7 +55,7 @@ struct intel_ring_hangcheck {
55 u32 seqno; 55 u32 seqno;
56 int score; 56 int score;
57 enum intel_ring_hangcheck_action action; 57 enum intel_ring_hangcheck_action action;
58 bool deadlock; 58 int deadlock;
59}; 59};
60 60
61struct intel_ringbuffer { 61struct intel_ringbuffer {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 6a4d5bc17697..20375cc7f82d 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1385,7 +1385,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
1385 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1385 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1386 } 1386 }
1387 1387
1388 dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier; 1388 dotclock = pipe_config->port_clock;
1389 if (pipe_config->pixel_multiplier)
1390 dotclock /= pipe_config->pixel_multiplier;
1389 1391
1390 if (HAS_PCH_SPLIT(dev)) 1392 if (HAS_PCH_SPLIT(dev))
1391 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1393 ironlake_check_encoder_dotclock(pipe_config, dotclock);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 79cba593df0d..4f6fef7ac069 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -320,7 +320,8 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
320 struct drm_i915_private *dev_priv = dev->dev_private; 320 struct drm_i915_private *dev_priv = dev->dev_private;
321 unsigned long irqflags; 321 unsigned long irqflags;
322 322
323 del_timer_sync(&dev_priv->uncore.force_wake_timer); 323 if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
324 gen6_force_wake_timer((unsigned long)dev_priv);
324 325
325 /* Hold uncore.lock across reset to prevent any register access 326 /* Hold uncore.lock across reset to prevent any register access
326 * with forcewake not set correctly 327 * with forcewake not set correctly
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 2b6156d0e4b5..8b307e143632 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -140,6 +140,7 @@ nouveau-y += core/subdev/i2c/nv4e.o
140nouveau-y += core/subdev/i2c/nv50.o 140nouveau-y += core/subdev/i2c/nv50.o
141nouveau-y += core/subdev/i2c/nv94.o 141nouveau-y += core/subdev/i2c/nv94.o
142nouveau-y += core/subdev/i2c/nvd0.o 142nouveau-y += core/subdev/i2c/nvd0.o
143nouveau-y += core/subdev/i2c/gf117.o
143nouveau-y += core/subdev/i2c/nve0.o 144nouveau-y += core/subdev/i2c/nve0.o
144nouveau-y += core/subdev/ibus/nvc0.o 145nouveau-y += core/subdev/ibus/nvc0.o
145nouveau-y += core/subdev/ibus/nve0.o 146nouveau-y += core/subdev/ibus/nve0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index f199957995fa..8d55ed633b19 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device)
314 device->cname = "GF117"; 314 device->cname = "GF117";
315 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 315 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
316 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; 316 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
317 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; 317 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
318 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 318 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
319 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 319 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
320 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 320 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
index c41f656abe64..9c38c5e40500 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
@@ -99,8 +99,10 @@ _nouveau_disp_dtor(struct nouveau_object *object)
99 99
100 nouveau_event_destroy(&disp->vblank); 100 nouveau_event_destroy(&disp->vblank);
101 101
102 list_for_each_entry_safe(outp, outt, &disp->outp, head) { 102 if (disp->outp.next) {
103 nouveau_object_ref(NULL, (struct nouveau_object **)&outp); 103 list_for_each_entry_safe(outp, outt, &disp->outp, head) {
104 nouveau_object_ref(NULL, (struct nouveau_object **)&outp);
105 }
104 } 106 }
105 107
106 nouveau_engine_destroy(&disp->base); 108 nouveau_engine_destroy(&disp->base);
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
index 39562d48101d..5a5b59b21130 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
@@ -241,7 +241,9 @@ dp_link_train_eq(struct dp_state *dp)
241 dp_set_training_pattern(dp, 2); 241 dp_set_training_pattern(dp, 2);
242 242
243 do { 243 do {
244 if (dp_link_train_update(dp, dp->pc2, 400)) 244 if ((tries &&
245 dp_link_train_commit(dp, dp->pc2)) ||
246 dp_link_train_update(dp, dp->pc2, 400))
245 break; 247 break;
246 248
247 eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); 249 eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
@@ -253,9 +255,6 @@ dp_link_train_eq(struct dp_state *dp)
253 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) 255 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
254 eq_done = false; 256 eq_done = false;
255 } 257 }
256
257 if (dp_link_train_commit(dp, dp->pc2))
258 break;
259 } while (!eq_done && cr_done && ++tries <= 5); 258 } while (!eq_done && cr_done && ++tries <= 5);
260 259
261 return eq_done ? 0 : -1; 260 return eq_done ? 0 : -1;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 1e85f36c705f..26e962b7e702 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -1270,7 +1270,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
1270 i--; 1270 i--;
1271 1271
1272 outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); 1272 outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
1273 if (!data) 1273 if (!outp)
1274 return NULL; 1274 return NULL;
1275 1275
1276 if (outp->info.location == 0) { 1276 if (outp->info.location == 0) {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
index 2f7345f7fe07..7445f12b1d9e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
@@ -54,7 +54,7 @@ mmio_list_base:
54#ifdef INCLUDE_CODE 54#ifdef INCLUDE_CODE
55// reports an exception to the host 55// reports an exception to the host
56// 56//
57// In: $r15 error code (see nvc0.fuc) 57// In: $r15 error code (see os.h)
58// 58//
59error: 59error:
60 push $r14 60 push $r14
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
index c8ddb8d71b91..b4ad18bf5a26 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
@@ -49,7 +49,7 @@ hub_mmio_list_next:
49#ifdef INCLUDE_CODE 49#ifdef INCLUDE_CODE
50// reports an exception to the host 50// reports an exception to the host
51// 51//
52// In: $r15 error code (see nvc0.fuc) 52// In: $r15 error code (see os.h)
53// 53//
54error: 54error:
55 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) 55 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
@@ -343,13 +343,25 @@ ih:
343 ih_no_ctxsw: 343 ih_no_ctxsw:
344 and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD 344 and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD
345 bra e #ih_no_fwmthd 345 bra e #ih_no_fwmthd
346 // none we handle, ack, and fall-through to unhandled 346 // none we handle; report to host and ack
347 nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO)
348 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15)
349 nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR)
350 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15)
351 extr $r14 $r15 16:18
352 shl b32 $r14 $r14 2
353 imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0))
354 add b32 $r14 $r15
355 call(nv_rd32)
356 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15)
357 mov $r15 E_BAD_FWMTHD
358 call(error)
347 mov $r11 0x100 359 mov $r11 0x100
348 nv_wr32(0x400144, $r11) 360 nv_wr32(0x400144, $r11)
349 361
350 // anything we didn't handle, bring it to the host's attention 362 // anything we didn't handle, bring it to the host's attention
351 ih_no_fwmthd: 363 ih_no_fwmthd:
352 mov $r11 0x104 // FIFO | CHSW 364 mov $r11 0x504 // FIFO | CHSW | FWMTHD
353 not b32 $r11 365 not b32 $r11
354 and $r11 $r10 $r11 366 and $r11 $r10 $r11
355 bra e #ih_no_other 367 bra e #ih_no_other
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
index 214dd16ec566..5f953c5c20b7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
@@ -478,10 +478,10 @@ uint32_t gm107_grhub_code[] = {
478 0x01040080, 478 0x01040080,
479 0xbd0001f6, 479 0xbd0001f6,
480 0x01004104, 480 0x01004104,
481 0x627e020f, 481 0xa87e020f,
482 0x717e0006, 482 0xb77e0006,
483 0x100f0006, 483 0x100f0006,
484 0x0006b37e, 484 0x0006f97e,
485 0x98000e98, 485 0x98000e98,
486 0x207e010f, 486 0x207e010f,
487 0x14950001, 487 0x14950001,
@@ -523,8 +523,8 @@ uint32_t gm107_grhub_code[] = {
523 0x800040b7, 523 0x800040b7,
524 0xf40132b6, 524 0xf40132b6,
525 0x000fb41b, 525 0x000fb41b,
526 0x0006b37e, 526 0x0006f97e,
527 0x627e000f, 527 0xa87e000f,
528 0x00800006, 528 0x00800006,
529 0x01f60201, 529 0x01f60201,
530 0xbd04bd00, 530 0xbd04bd00,
@@ -554,7 +554,7 @@ uint32_t gm107_grhub_code[] = {
554 0x0009f602, 554 0x0009f602,
555 0x32f404bd, 555 0x32f404bd,
556 0x0231f401, 556 0x0231f401,
557 0x0008367e, 557 0x00087c7e,
558 0x99f094bd, 558 0x99f094bd,
559 0x17008007, 559 0x17008007,
560 0x0009f602, 560 0x0009f602,
@@ -563,7 +563,7 @@ uint32_t gm107_grhub_code[] = {
563 0x37008006, 563 0x37008006,
564 0x0009f602, 564 0x0009f602,
565 0x31f404bd, 565 0x31f404bd,
566 0x08367e01, 566 0x087c7e01,
567 0xf094bd00, 567 0xf094bd00,
568 0x00800699, 568 0x00800699,
569 0x09f60217, 569 0x09f60217,
@@ -572,7 +572,7 @@ uint32_t gm107_grhub_code[] = {
572 0x20f92f0e, 572 0x20f92f0e,
573 0x32f412b2, 573 0x32f412b2,
574 0x0232f401, 574 0x0232f401,
575 0x0008367e, 575 0x00087c7e,
576 0x008020fc, 576 0x008020fc,
577 0x02f602c0, 577 0x02f602c0,
578 0xf404bd00, 578 0xf404bd00,
@@ -580,7 +580,7 @@ uint32_t gm107_grhub_code[] = {
580 0x23c8130e, 580 0x23c8130e,
581 0x0d0bf41f, 581 0x0d0bf41f,
582 0xf40131f4, 582 0xf40131f4,
583 0x367e0232, 583 0x7c7e0232,
584/* 0x054e: chsw_done */ 584/* 0x054e: chsw_done */
585 0x01020008, 585 0x01020008,
586 0x02c30080, 586 0x02c30080,
@@ -593,7 +593,7 @@ uint32_t gm107_grhub_code[] = {
593 0xb0ff2a0e, 593 0xb0ff2a0e,
594 0x1bf401e4, 594 0x1bf401e4,
595 0x7ef2b20c, 595 0x7ef2b20c,
596 0xf40007d6, 596 0xf400081c,
597/* 0x057a: main_not_ctx_chan */ 597/* 0x057a: main_not_ctx_chan */
598 0xe4b0400e, 598 0xe4b0400e,
599 0x2c1bf402, 599 0x2c1bf402,
@@ -602,7 +602,7 @@ uint32_t gm107_grhub_code[] = {
602 0x0009f602, 602 0x0009f602,
603 0x32f404bd, 603 0x32f404bd,
604 0x0232f401, 604 0x0232f401,
605 0x0008367e, 605 0x00087c7e,
606 0x99f094bd, 606 0x99f094bd,
607 0x17008007, 607 0x17008007,
608 0x0009f602, 608 0x0009f602,
@@ -642,238 +642,238 @@ uint32_t gm107_grhub_code[] = {
642/* 0x061a: ih_no_ctxsw */ 642/* 0x061a: ih_no_ctxsw */
643 0xabe40000, 643 0xabe40000,
644 0x0bf40400, 644 0x0bf40400,
645 0x01004b10, 645 0x07088e56,
646 0x448ebfb2,
647 0x8f7e4001,
648/* 0x062e: ih_no_fwmthd */
649 0x044b0000,
650 0xffb0bd01,
651 0x0bf4b4ab,
652 0x0700800c,
653 0x000bf603,
654/* 0x0642: ih_no_other */
655 0x004004bd,
656 0x000af601,
657 0xf0fc04bd,
658 0xd0fce0fc,
659 0xa0fcb0fc,
660 0x80fc90fc,
661 0xfc0088fe,
662 0x0032f480,
663/* 0x0662: ctx_4170s */
664 0xf5f001f8,
665 0x8effb210,
666 0x7e404170,
667 0xf800008f,
668/* 0x0671: ctx_4170w */
669 0x41708e00,
670 0x00657e40, 646 0x00657e40,
671 0xf0ffb200, 647 0x80ffb200,
672 0x1bf410f4, 648 0xf6020400,
673/* 0x0683: ctx_redswitch */
674 0x4e00f8f3,
675 0xe5f00200,
676 0x20e5f040,
677 0x8010e5f0,
678 0xf6018500,
679 0x04bd000e,
680/* 0x069a: ctx_redswitch_delay */
681 0xf2b6080f,
682 0xfd1bf401,
683 0x0400e5f1,
684 0x0100e5f1,
685 0x01850080,
686 0xbd000ef6,
687/* 0x06b3: ctx_86c */
688 0x8000f804,
689 0xf6022300,
690 0x04bd000f, 649 0x04bd000f,
691 0x148effb2, 650 0x4007048e,
692 0x8f7e408a, 651 0x0000657e,
693 0xffb20000, 652 0x0080ffb2,
694 0x41a88c8e, 653 0x0ff60203,
654 0xc704bd00,
655 0xee9450fe,
656 0x07008f02,
657 0x00efbb40,
658 0x0000657e,
659 0x02020080,
660 0xbd000ff6,
661 0x7e030f04,
662 0x4b0002f8,
663 0xbfb20100,
664 0x4001448e,
695 0x00008f7e, 665 0x00008f7e,
696/* 0x06d2: ctx_mem */ 666/* 0x0674: ih_no_fwmthd */
697 0x008000f8, 667 0xbd05044b,
698 0x0ff60284, 668 0xb4abffb0,
699/* 0x06db: ctx_mem_wait */ 669 0x800c0bf4,
700 0x8f04bd00, 670 0xf6030700,
701 0xcf028400, 671 0x04bd000b,
702 0xfffd00ff, 672/* 0x0688: ih_no_other */
703 0xf61bf405, 673 0xf6010040,
704/* 0x06ea: ctx_load */ 674 0x04bd000a,
705 0x94bd00f8, 675 0xe0fcf0fc,
706 0x800599f0, 676 0xb0fcd0fc,
707 0xf6023700, 677 0x90fca0fc,
708 0x04bd0009, 678 0x88fe80fc,
709 0xb87e0c0a, 679 0xf480fc00,
710 0xf4bd0000, 680 0x01f80032,
711 0x02890080, 681/* 0x06a8: ctx_4170s */
682 0xb210f5f0,
683 0x41708eff,
684 0x008f7e40,
685/* 0x06b7: ctx_4170w */
686 0x8e00f800,
687 0x7e404170,
688 0xb2000065,
689 0x10f4f0ff,
690 0xf8f31bf4,
691/* 0x06c9: ctx_redswitch */
692 0x02004e00,
693 0xf040e5f0,
694 0xe5f020e5,
695 0x85008010,
696 0x000ef601,
697 0x080f04bd,
698/* 0x06e0: ctx_redswitch_delay */
699 0xf401f2b6,
700 0xe5f1fd1b,
701 0xe5f10400,
702 0x00800100,
703 0x0ef60185,
704 0xf804bd00,
705/* 0x06f9: ctx_86c */
706 0x23008000,
707 0x000ff602,
708 0xffb204bd,
709 0x408a148e,
710 0x00008f7e,
711 0x8c8effb2,
712 0x8f7e41a8,
713 0x00f80000,
714/* 0x0718: ctx_mem */
715 0x02840080,
712 0xbd000ff6, 716 0xbd000ff6,
713 0xc1008004, 717/* 0x0721: ctx_mem_wait */
714 0x0002f602, 718 0x84008f04,
715 0x008004bd, 719 0x00ffcf02,
716 0x02f60283, 720 0xf405fffd,
717 0x0f04bd00, 721 0x00f8f61b,
718 0x06d27e07, 722/* 0x0730: ctx_load */
719 0xc0008000, 723 0x99f094bd,
720 0x0002f602, 724 0x37008005,
721 0x0bfe04bd, 725 0x0009f602,
722 0x1f2af000, 726 0x0c0a04bd,
723 0xb60424b6, 727 0x0000b87e,
724 0x94bd0220, 728 0x0080f4bd,
725 0x800899f0, 729 0x0ff60289,
726 0xf6023700, 730 0x8004bd00,
727 0x04bd0009, 731 0xf602c100,
728 0x02810080, 732 0x04bd0002,
729 0xbd0002f6, 733 0x02830080,
730 0x0000d204,
731 0x25f08000,
732 0x88008002,
733 0x0002f602,
734 0x100104bd,
735 0xf0020042,
736 0x12fa0223,
737 0xbd03f805,
738 0x0899f094,
739 0x02170080,
740 0xbd0009f6,
741 0x81019804,
742 0x981814b6,
743 0x25b68002,
744 0x0512fd08,
745 0xbd1601b5,
746 0x0999f094,
747 0x02370080,
748 0xbd0009f6,
749 0x81008004,
750 0x0001f602,
751 0x010204bd,
752 0x02880080,
753 0xbd0002f6, 734 0xbd0002f6,
754 0x01004104, 735 0x7e070f04,
755 0xfa0613f0, 736 0x80000718,
756 0x03f80501, 737 0xf602c000,
738 0x04bd0002,
739 0xf0000bfe,
740 0x24b61f2a,
741 0x0220b604,
757 0x99f094bd, 742 0x99f094bd,
758 0x17008009, 743 0x37008008,
759 0x0009f602, 744 0x0009f602,
760 0x94bd04bd, 745 0x008004bd,
761 0x800599f0, 746 0x02f60281,
747 0xd204bd00,
748 0x80000000,
749 0x800225f0,
750 0xf6028800,
751 0x04bd0002,
752 0x00421001,
753 0x0223f002,
754 0xf80512fa,
755 0xf094bd03,
756 0x00800899,
757 0x09f60217,
758 0x9804bd00,
759 0x14b68101,
760 0x80029818,
761 0xfd0825b6,
762 0x01b50512,
763 0xf094bd16,
764 0x00800999,
765 0x09f60237,
766 0x8004bd00,
767 0xf6028100,
768 0x04bd0001,
769 0x00800102,
770 0x02f60288,
771 0x4104bd00,
772 0x13f00100,
773 0x0501fa06,
774 0x94bd03f8,
775 0x800999f0,
762 0xf6021700, 776 0xf6021700,
763 0x04bd0009, 777 0x04bd0009,
764/* 0x07d6: ctx_chan */ 778 0x99f094bd,
765 0xea7e00f8, 779 0x17008005,
766 0x0c0a0006, 780 0x0009f602,
767 0x0000b87e, 781 0x00f804bd,
768 0xd27e050f, 782/* 0x081c: ctx_chan */
769 0x00f80006, 783 0x0007307e,
770/* 0x07e8: ctx_mmio_exec */ 784 0xb87e0c0a,
771 0x80410398, 785 0x050f0000,
786 0x0007187e,
787/* 0x082e: ctx_mmio_exec */
788 0x039800f8,
789 0x81008041,
790 0x0003f602,
791 0x34bd04bd,
792/* 0x083c: ctx_mmio_loop */
793 0xf4ff34c4,
794 0x00450e1b,
795 0x0653f002,
796 0xf80535fa,
797/* 0x084d: ctx_mmio_pull */
798 0x804e9803,
799 0x7e814f98,
800 0xb600008f,
801 0x12b60830,
802 0xdf1bf401,
803/* 0x0860: ctx_mmio_done */
804 0x80160398,
772 0xf6028100, 805 0xf6028100,
773 0x04bd0003, 806 0x04bd0003,
774/* 0x07f6: ctx_mmio_loop */ 807 0x414000b5,
775 0x34c434bd, 808 0x13f00100,
776 0x0e1bf4ff, 809 0x0601fa06,
777 0xf0020045, 810 0x00f803f8,
778 0x35fa0653, 811/* 0x087c: ctx_xfer */
779/* 0x0807: ctx_mmio_pull */ 812 0x0080040e,
780 0x9803f805, 813 0x0ef60302,
781 0x4f98804e, 814/* 0x0887: ctx_xfer_idle */
782 0x008f7e81, 815 0x8e04bd00,
783 0x0830b600, 816 0xcf030000,
784 0xf40112b6, 817 0xe4f100ee,
785/* 0x081a: ctx_mmio_done */ 818 0x1bf42000,
786 0x0398df1b, 819 0x0611f4f5,
787 0x81008016, 820/* 0x089b: ctx_xfer_pre */
788 0x0003f602, 821 0x0f0c02f4,
789 0x00b504bd, 822 0x06f97e10,
790 0x01004140, 823 0x1b11f400,
791 0xfa0613f0, 824/* 0x08a4: ctx_xfer_pre_load */
792 0x03f80601, 825 0xa87e020f,
793/* 0x0836: ctx_xfer */ 826 0xb77e0006,
794 0x040e00f8, 827 0xc97e0006,
795 0x03020080, 828 0xf4bd0006,
796 0xbd000ef6, 829 0x0006a87e,
797/* 0x0841: ctx_xfer_idle */ 830 0x0007307e,
798 0x00008e04, 831/* 0x08bc: ctx_xfer_exec */
799 0x00eecf03, 832 0xbd160198,
800 0x2000e4f1, 833 0x05008024,
801 0xf4f51bf4, 834 0x0002f601,
802 0x02f40611, 835 0x1fb204bd,
803/* 0x0855: ctx_xfer_pre */ 836 0x41a5008e,
804 0x7e100f0c,
805 0xf40006b3,
806/* 0x085e: ctx_xfer_pre_load */
807 0x020f1b11,
808 0x0006627e,
809 0x0006717e,
810 0x0006837e,
811 0x627ef4bd,
812 0xea7e0006,
813/* 0x0876: ctx_xfer_exec */
814 0x01980006,
815 0x8024bd16,
816 0xf6010500,
817 0x04bd0002,
818 0x008e1fb2,
819 0x8f7e41a5,
820 0xfcf00000,
821 0x022cf001,
822 0xfd0124b6,
823 0xffb205f2,
824 0x41a5048e,
825 0x00008f7e, 837 0x00008f7e,
826 0x0002167e, 838 0xf001fcf0,
827 0xfc8024bd, 839 0x24b6022c,
828 0x02f60247, 840 0x05f2fd01,
829 0xf004bd00, 841 0x048effb2,
830 0x20b6012c, 842 0x8f7e41a5,
831 0x4afc8003, 843 0x167e0000,
832 0x0002f602, 844 0x24bd0002,
833 0xacf004bd, 845 0x0247fc80,
834 0x06a5f001, 846 0xbd0002f6,
835 0x0c98000b, 847 0x012cf004,
836 0x010d9800, 848 0x800320b6,
837 0x3d7e000e, 849 0xf6024afc,
838 0x080a0001, 850 0x04bd0002,
839 0x0000ec7e, 851 0xf001acf0,
840 0x00020a7e, 852 0x000b06a5,
841 0x0a1201f4, 853 0x98000c98,
842 0x00b87e0c, 854 0x000e010d,
843 0x7e050f00, 855 0x00013d7e,
844 0xf40006d2, 856 0xec7e080a,
845/* 0x08f2: ctx_xfer_post */ 857 0x0a7e0000,
846 0x020f2d02, 858 0x01f40002,
847 0x0006627e, 859 0x7e0c0a12,
848 0xb37ef4bd, 860 0x0f0000b8,
849 0x277e0006, 861 0x07187e05,
850 0x717e0002, 862 0x2d02f400,
863/* 0x0938: ctx_xfer_post */
864 0xa87e020f,
851 0xf4bd0006, 865 0xf4bd0006,
852 0x0006627e, 866 0x0006f97e,
853 0x981011f4, 867 0x0002277e,
854 0x11fd4001, 868 0x0006b77e,
855 0x070bf405, 869 0xa87ef4bd,
856 0x0007e87e, 870 0x11f40006,
857/* 0x091c: ctx_xfer_no_post_mmio */ 871 0x40019810,
858/* 0x091c: ctx_xfer_done */ 872 0xf40511fd,
859 0x000000f8, 873 0x2e7e070b,
860 0x00000000, 874/* 0x0962: ctx_xfer_no_post_mmio */
861 0x00000000, 875/* 0x0962: ctx_xfer_done */
862 0x00000000, 876 0x00f80008,
863 0x00000000,
864 0x00000000,
865 0x00000000,
866 0x00000000,
867 0x00000000,
868 0x00000000,
869 0x00000000,
870 0x00000000,
871 0x00000000,
872 0x00000000,
873 0x00000000,
874 0x00000000,
875 0x00000000,
876 0x00000000,
877 0x00000000, 877 0x00000000,
878 0x00000000, 878 0x00000000,
879 0x00000000, 879 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
index 64dfd75192bf..e49b5a877ae4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
@@ -478,10 +478,10 @@ uint32_t nv108_grhub_code[] = {
478 0x01040080, 478 0x01040080,
479 0xbd0001f6, 479 0xbd0001f6,
480 0x01004104, 480 0x01004104,
481 0x627e020f, 481 0xa87e020f,
482 0x717e0006, 482 0xb77e0006,
483 0x100f0006, 483 0x100f0006,
484 0x0006b37e, 484 0x0006f97e,
485 0x98000e98, 485 0x98000e98,
486 0x207e010f, 486 0x207e010f,
487 0x14950001, 487 0x14950001,
@@ -523,8 +523,8 @@ uint32_t nv108_grhub_code[] = {
523 0x800040b7, 523 0x800040b7,
524 0xf40132b6, 524 0xf40132b6,
525 0x000fb41b, 525 0x000fb41b,
526 0x0006b37e, 526 0x0006f97e,
527 0x627e000f, 527 0xa87e000f,
528 0x00800006, 528 0x00800006,
529 0x01f60201, 529 0x01f60201,
530 0xbd04bd00, 530 0xbd04bd00,
@@ -554,7 +554,7 @@ uint32_t nv108_grhub_code[] = {
554 0x0009f602, 554 0x0009f602,
555 0x32f404bd, 555 0x32f404bd,
556 0x0231f401, 556 0x0231f401,
557 0x0008367e, 557 0x00087c7e,
558 0x99f094bd, 558 0x99f094bd,
559 0x17008007, 559 0x17008007,
560 0x0009f602, 560 0x0009f602,
@@ -563,7 +563,7 @@ uint32_t nv108_grhub_code[] = {
563 0x37008006, 563 0x37008006,
564 0x0009f602, 564 0x0009f602,
565 0x31f404bd, 565 0x31f404bd,
566 0x08367e01, 566 0x087c7e01,
567 0xf094bd00, 567 0xf094bd00,
568 0x00800699, 568 0x00800699,
569 0x09f60217, 569 0x09f60217,
@@ -572,7 +572,7 @@ uint32_t nv108_grhub_code[] = {
572 0x20f92f0e, 572 0x20f92f0e,
573 0x32f412b2, 573 0x32f412b2,
574 0x0232f401, 574 0x0232f401,
575 0x0008367e, 575 0x00087c7e,
576 0x008020fc, 576 0x008020fc,
577 0x02f602c0, 577 0x02f602c0,
578 0xf404bd00, 578 0xf404bd00,
@@ -580,7 +580,7 @@ uint32_t nv108_grhub_code[] = {
580 0x23c8130e, 580 0x23c8130e,
581 0x0d0bf41f, 581 0x0d0bf41f,
582 0xf40131f4, 582 0xf40131f4,
583 0x367e0232, 583 0x7c7e0232,
584/* 0x054e: chsw_done */ 584/* 0x054e: chsw_done */
585 0x01020008, 585 0x01020008,
586 0x02c30080, 586 0x02c30080,
@@ -593,7 +593,7 @@ uint32_t nv108_grhub_code[] = {
593 0xb0ff2a0e, 593 0xb0ff2a0e,
594 0x1bf401e4, 594 0x1bf401e4,
595 0x7ef2b20c, 595 0x7ef2b20c,
596 0xf40007d6, 596 0xf400081c,
597/* 0x057a: main_not_ctx_chan */ 597/* 0x057a: main_not_ctx_chan */
598 0xe4b0400e, 598 0xe4b0400e,
599 0x2c1bf402, 599 0x2c1bf402,
@@ -602,7 +602,7 @@ uint32_t nv108_grhub_code[] = {
602 0x0009f602, 602 0x0009f602,
603 0x32f404bd, 603 0x32f404bd,
604 0x0232f401, 604 0x0232f401,
605 0x0008367e, 605 0x00087c7e,
606 0x99f094bd, 606 0x99f094bd,
607 0x17008007, 607 0x17008007,
608 0x0009f602, 608 0x0009f602,
@@ -642,238 +642,238 @@ uint32_t nv108_grhub_code[] = {
642/* 0x061a: ih_no_ctxsw */ 642/* 0x061a: ih_no_ctxsw */
643 0xabe40000, 643 0xabe40000,
644 0x0bf40400, 644 0x0bf40400,
645 0x01004b10, 645 0x07088e56,
646 0x448ebfb2,
647 0x8f7e4001,
648/* 0x062e: ih_no_fwmthd */
649 0x044b0000,
650 0xffb0bd01,
651 0x0bf4b4ab,
652 0x0700800c,
653 0x000bf603,
654/* 0x0642: ih_no_other */
655 0x004004bd,
656 0x000af601,
657 0xf0fc04bd,
658 0xd0fce0fc,
659 0xa0fcb0fc,
660 0x80fc90fc,
661 0xfc0088fe,
662 0x0032f480,
663/* 0x0662: ctx_4170s */
664 0xf5f001f8,
665 0x8effb210,
666 0x7e404170,
667 0xf800008f,
668/* 0x0671: ctx_4170w */
669 0x41708e00,
670 0x00657e40, 646 0x00657e40,
671 0xf0ffb200, 647 0x80ffb200,
672 0x1bf410f4, 648 0xf6020400,
673/* 0x0683: ctx_redswitch */
674 0x4e00f8f3,
675 0xe5f00200,
676 0x20e5f040,
677 0x8010e5f0,
678 0xf6018500,
679 0x04bd000e,
680/* 0x069a: ctx_redswitch_delay */
681 0xf2b6080f,
682 0xfd1bf401,
683 0x0400e5f1,
684 0x0100e5f1,
685 0x01850080,
686 0xbd000ef6,
687/* 0x06b3: ctx_86c */
688 0x8000f804,
689 0xf6022300,
690 0x04bd000f, 649 0x04bd000f,
691 0x148effb2, 650 0x4007048e,
692 0x8f7e408a, 651 0x0000657e,
693 0xffb20000, 652 0x0080ffb2,
694 0x41a88c8e, 653 0x0ff60203,
654 0xc704bd00,
655 0xee9450fe,
656 0x07008f02,
657 0x00efbb40,
658 0x0000657e,
659 0x02020080,
660 0xbd000ff6,
661 0x7e030f04,
662 0x4b0002f8,
663 0xbfb20100,
664 0x4001448e,
695 0x00008f7e, 665 0x00008f7e,
696/* 0x06d2: ctx_mem */ 666/* 0x0674: ih_no_fwmthd */
697 0x008000f8, 667 0xbd05044b,
698 0x0ff60284, 668 0xb4abffb0,
699/* 0x06db: ctx_mem_wait */ 669 0x800c0bf4,
700 0x8f04bd00, 670 0xf6030700,
701 0xcf028400, 671 0x04bd000b,
702 0xfffd00ff, 672/* 0x0688: ih_no_other */
703 0xf61bf405, 673 0xf6010040,
704/* 0x06ea: ctx_load */ 674 0x04bd000a,
705 0x94bd00f8, 675 0xe0fcf0fc,
706 0x800599f0, 676 0xb0fcd0fc,
707 0xf6023700, 677 0x90fca0fc,
708 0x04bd0009, 678 0x88fe80fc,
709 0xb87e0c0a, 679 0xf480fc00,
710 0xf4bd0000, 680 0x01f80032,
711 0x02890080, 681/* 0x06a8: ctx_4170s */
682 0xb210f5f0,
683 0x41708eff,
684 0x008f7e40,
685/* 0x06b7: ctx_4170w */
686 0x8e00f800,
687 0x7e404170,
688 0xb2000065,
689 0x10f4f0ff,
690 0xf8f31bf4,
691/* 0x06c9: ctx_redswitch */
692 0x02004e00,
693 0xf040e5f0,
694 0xe5f020e5,
695 0x85008010,
696 0x000ef601,
697 0x080f04bd,
698/* 0x06e0: ctx_redswitch_delay */
699 0xf401f2b6,
700 0xe5f1fd1b,
701 0xe5f10400,
702 0x00800100,
703 0x0ef60185,
704 0xf804bd00,
705/* 0x06f9: ctx_86c */
706 0x23008000,
707 0x000ff602,
708 0xffb204bd,
709 0x408a148e,
710 0x00008f7e,
711 0x8c8effb2,
712 0x8f7e41a8,
713 0x00f80000,
714/* 0x0718: ctx_mem */
715 0x02840080,
712 0xbd000ff6, 716 0xbd000ff6,
713 0xc1008004, 717/* 0x0721: ctx_mem_wait */
714 0x0002f602, 718 0x84008f04,
715 0x008004bd, 719 0x00ffcf02,
716 0x02f60283, 720 0xf405fffd,
717 0x0f04bd00, 721 0x00f8f61b,
718 0x06d27e07, 722/* 0x0730: ctx_load */
719 0xc0008000, 723 0x99f094bd,
720 0x0002f602, 724 0x37008005,
721 0x0bfe04bd, 725 0x0009f602,
722 0x1f2af000, 726 0x0c0a04bd,
723 0xb60424b6, 727 0x0000b87e,
724 0x94bd0220, 728 0x0080f4bd,
725 0x800899f0, 729 0x0ff60289,
726 0xf6023700, 730 0x8004bd00,
727 0x04bd0009, 731 0xf602c100,
728 0x02810080, 732 0x04bd0002,
729 0xbd0002f6, 733 0x02830080,
730 0x0000d204,
731 0x25f08000,
732 0x88008002,
733 0x0002f602,
734 0x100104bd,
735 0xf0020042,
736 0x12fa0223,
737 0xbd03f805,
738 0x0899f094,
739 0x02170080,
740 0xbd0009f6,
741 0x81019804,
742 0x981814b6,
743 0x25b68002,
744 0x0512fd08,
745 0xbd1601b5,
746 0x0999f094,
747 0x02370080,
748 0xbd0009f6,
749 0x81008004,
750 0x0001f602,
751 0x010204bd,
752 0x02880080,
753 0xbd0002f6, 734 0xbd0002f6,
754 0x01004104, 735 0x7e070f04,
755 0xfa0613f0, 736 0x80000718,
756 0x03f80501, 737 0xf602c000,
738 0x04bd0002,
739 0xf0000bfe,
740 0x24b61f2a,
741 0x0220b604,
757 0x99f094bd, 742 0x99f094bd,
758 0x17008009, 743 0x37008008,
759 0x0009f602, 744 0x0009f602,
760 0x94bd04bd, 745 0x008004bd,
761 0x800599f0, 746 0x02f60281,
747 0xd204bd00,
748 0x80000000,
749 0x800225f0,
750 0xf6028800,
751 0x04bd0002,
752 0x00421001,
753 0x0223f002,
754 0xf80512fa,
755 0xf094bd03,
756 0x00800899,
757 0x09f60217,
758 0x9804bd00,
759 0x14b68101,
760 0x80029818,
761 0xfd0825b6,
762 0x01b50512,
763 0xf094bd16,
764 0x00800999,
765 0x09f60237,
766 0x8004bd00,
767 0xf6028100,
768 0x04bd0001,
769 0x00800102,
770 0x02f60288,
771 0x4104bd00,
772 0x13f00100,
773 0x0501fa06,
774 0x94bd03f8,
775 0x800999f0,
762 0xf6021700, 776 0xf6021700,
763 0x04bd0009, 777 0x04bd0009,
764/* 0x07d6: ctx_chan */ 778 0x99f094bd,
765 0xea7e00f8, 779 0x17008005,
766 0x0c0a0006, 780 0x0009f602,
767 0x0000b87e, 781 0x00f804bd,
768 0xd27e050f, 782/* 0x081c: ctx_chan */
769 0x00f80006, 783 0x0007307e,
770/* 0x07e8: ctx_mmio_exec */ 784 0xb87e0c0a,
771 0x80410398, 785 0x050f0000,
786 0x0007187e,
787/* 0x082e: ctx_mmio_exec */
788 0x039800f8,
789 0x81008041,
790 0x0003f602,
791 0x34bd04bd,
792/* 0x083c: ctx_mmio_loop */
793 0xf4ff34c4,
794 0x00450e1b,
795 0x0653f002,
796 0xf80535fa,
797/* 0x084d: ctx_mmio_pull */
798 0x804e9803,
799 0x7e814f98,
800 0xb600008f,
801 0x12b60830,
802 0xdf1bf401,
803/* 0x0860: ctx_mmio_done */
804 0x80160398,
772 0xf6028100, 805 0xf6028100,
773 0x04bd0003, 806 0x04bd0003,
774/* 0x07f6: ctx_mmio_loop */ 807 0x414000b5,
775 0x34c434bd, 808 0x13f00100,
776 0x0e1bf4ff, 809 0x0601fa06,
777 0xf0020045, 810 0x00f803f8,
778 0x35fa0653, 811/* 0x087c: ctx_xfer */
779/* 0x0807: ctx_mmio_pull */ 812 0x0080040e,
780 0x9803f805, 813 0x0ef60302,
781 0x4f98804e, 814/* 0x0887: ctx_xfer_idle */
782 0x008f7e81, 815 0x8e04bd00,
783 0x0830b600, 816 0xcf030000,
784 0xf40112b6, 817 0xe4f100ee,
785/* 0x081a: ctx_mmio_done */ 818 0x1bf42000,
786 0x0398df1b, 819 0x0611f4f5,
787 0x81008016, 820/* 0x089b: ctx_xfer_pre */
788 0x0003f602, 821 0x0f0c02f4,
789 0x00b504bd, 822 0x06f97e10,
790 0x01004140, 823 0x1b11f400,
791 0xfa0613f0, 824/* 0x08a4: ctx_xfer_pre_load */
792 0x03f80601, 825 0xa87e020f,
793/* 0x0836: ctx_xfer */ 826 0xb77e0006,
794 0x040e00f8, 827 0xc97e0006,
795 0x03020080, 828 0xf4bd0006,
796 0xbd000ef6, 829 0x0006a87e,
797/* 0x0841: ctx_xfer_idle */ 830 0x0007307e,
798 0x00008e04, 831/* 0x08bc: ctx_xfer_exec */
799 0x00eecf03, 832 0xbd160198,
800 0x2000e4f1, 833 0x05008024,
801 0xf4f51bf4, 834 0x0002f601,
802 0x02f40611, 835 0x1fb204bd,
803/* 0x0855: ctx_xfer_pre */ 836 0x41a5008e,
804 0x7e100f0c,
805 0xf40006b3,
806/* 0x085e: ctx_xfer_pre_load */
807 0x020f1b11,
808 0x0006627e,
809 0x0006717e,
810 0x0006837e,
811 0x627ef4bd,
812 0xea7e0006,
813/* 0x0876: ctx_xfer_exec */
814 0x01980006,
815 0x8024bd16,
816 0xf6010500,
817 0x04bd0002,
818 0x008e1fb2,
819 0x8f7e41a5,
820 0xfcf00000,
821 0x022cf001,
822 0xfd0124b6,
823 0xffb205f2,
824 0x41a5048e,
825 0x00008f7e, 837 0x00008f7e,
826 0x0002167e, 838 0xf001fcf0,
827 0xfc8024bd, 839 0x24b6022c,
828 0x02f60247, 840 0x05f2fd01,
829 0xf004bd00, 841 0x048effb2,
830 0x20b6012c, 842 0x8f7e41a5,
831 0x4afc8003, 843 0x167e0000,
832 0x0002f602, 844 0x24bd0002,
833 0xacf004bd, 845 0x0247fc80,
834 0x06a5f001, 846 0xbd0002f6,
835 0x0c98000b, 847 0x012cf004,
836 0x010d9800, 848 0x800320b6,
837 0x3d7e000e, 849 0xf6024afc,
838 0x080a0001, 850 0x04bd0002,
839 0x0000ec7e, 851 0xf001acf0,
840 0x00020a7e, 852 0x000b06a5,
841 0x0a1201f4, 853 0x98000c98,
842 0x00b87e0c, 854 0x000e010d,
843 0x7e050f00, 855 0x00013d7e,
844 0xf40006d2, 856 0xec7e080a,
845/* 0x08f2: ctx_xfer_post */ 857 0x0a7e0000,
846 0x020f2d02, 858 0x01f40002,
847 0x0006627e, 859 0x7e0c0a12,
848 0xb37ef4bd, 860 0x0f0000b8,
849 0x277e0006, 861 0x07187e05,
850 0x717e0002, 862 0x2d02f400,
863/* 0x0938: ctx_xfer_post */
864 0xa87e020f,
851 0xf4bd0006, 865 0xf4bd0006,
852 0x0006627e, 866 0x0006f97e,
853 0x981011f4, 867 0x0002277e,
854 0x11fd4001, 868 0x0006b77e,
855 0x070bf405, 869 0xa87ef4bd,
856 0x0007e87e, 870 0x11f40006,
857/* 0x091c: ctx_xfer_no_post_mmio */ 871 0x40019810,
858/* 0x091c: ctx_xfer_done */ 872 0xf40511fd,
859 0x000000f8, 873 0x2e7e070b,
860 0x00000000, 874/* 0x0962: ctx_xfer_no_post_mmio */
861 0x00000000, 875/* 0x0962: ctx_xfer_done */
862 0x00000000, 876 0x00f80008,
863 0x00000000,
864 0x00000000,
865 0x00000000,
866 0x00000000,
867 0x00000000,
868 0x00000000,
869 0x00000000,
870 0x00000000,
871 0x00000000,
872 0x00000000,
873 0x00000000,
874 0x00000000,
875 0x00000000,
876 0x00000000,
877 0x00000000, 877 0x00000000,
878 0x00000000, 878 0x00000000,
879 0x00000000, 879 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index f8f7b278a13f..92dfe6a4ac87 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -528,10 +528,10 @@ uint32_t nvc0_grhub_code[] = {
528 0x0001d001, 528 0x0001d001,
529 0x17f104bd, 529 0x17f104bd,
530 0xf7f00100, 530 0xf7f00100,
531 0xb521f502, 531 0x0d21f502,
532 0xc721f507, 532 0x1f21f508,
533 0x10f7f007, 533 0x10f7f008,
534 0x081421f5, 534 0x086c21f5,
535 0x98000e98, 535 0x98000e98,
536 0x21f5010f, 536 0x21f5010f,
537 0x14950150, 537 0x14950150,
@@ -574,9 +574,9 @@ uint32_t nvc0_grhub_code[] = {
574 0xb6800040, 574 0xb6800040,
575 0x1bf40132, 575 0x1bf40132,
576 0x00f7f0be, 576 0x00f7f0be,
577 0x081421f5, 577 0x086c21f5,
578 0xf500f7f0, 578 0xf500f7f0,
579 0xf107b521, 579 0xf1080d21,
580 0xf0010007, 580 0xf0010007,
581 0x01d00203, 581 0x01d00203,
582 0xbd04bd00, 582 0xbd04bd00,
@@ -610,8 +610,8 @@ uint32_t nvc0_grhub_code[] = {
610 0x09d00203, 610 0x09d00203,
611 0xf404bd00, 611 0xf404bd00,
612 0x31f40132, 612 0x31f40132,
613 0xe821f502, 613 0x4021f502,
614 0xf094bd09, 614 0xf094bd0a,
615 0x07f10799, 615 0x07f10799,
616 0x03f01700, 616 0x03f01700,
617 0x0009d002, 617 0x0009d002,
@@ -621,7 +621,7 @@ uint32_t nvc0_grhub_code[] = {
621 0x0203f00f, 621 0x0203f00f,
622 0xbd0009d0, 622 0xbd0009d0,
623 0x0131f404, 623 0x0131f404,
624 0x09e821f5, 624 0x0a4021f5,
625 0x99f094bd, 625 0x99f094bd,
626 0x0007f106, 626 0x0007f106,
627 0x0203f017, 627 0x0203f017,
@@ -631,7 +631,7 @@ uint32_t nvc0_grhub_code[] = {
631 0x12b920f9, 631 0x12b920f9,
632 0x0132f402, 632 0x0132f402,
633 0xf50232f4, 633 0xf50232f4,
634 0xfc09e821, 634 0xfc0a4021,
635 0x0007f120, 635 0x0007f120,
636 0x0203f0c0, 636 0x0203f0c0,
637 0xbd0002d0, 637 0xbd0002d0,
@@ -640,7 +640,7 @@ uint32_t nvc0_grhub_code[] = {
640 0xf41f23c8, 640 0xf41f23c8,
641 0x31f40d0b, 641 0x31f40d0b,
642 0x0232f401, 642 0x0232f401,
643 0x09e821f5, 643 0x0a4021f5,
644/* 0x063c: chsw_done */ 644/* 0x063c: chsw_done */
645 0xf10127f0, 645 0xf10127f0,
646 0xf0c30007, 646 0xf0c30007,
@@ -654,7 +654,7 @@ uint32_t nvc0_grhub_code[] = {
654/* 0x0660: main_not_ctx_switch */ 654/* 0x0660: main_not_ctx_switch */
655 0xf401e4b0, 655 0xf401e4b0,
656 0xf2b90d1b, 656 0xf2b90d1b,
657 0x7821f502, 657 0xd021f502,
658 0x460ef409, 658 0x460ef409,
659/* 0x0670: main_not_ctx_chan */ 659/* 0x0670: main_not_ctx_chan */
660 0xf402e4b0, 660 0xf402e4b0,
@@ -664,8 +664,8 @@ uint32_t nvc0_grhub_code[] = {
664 0x09d00203, 664 0x09d00203,
665 0xf404bd00, 665 0xf404bd00,
666 0x32f40132, 666 0x32f40132,
667 0xe821f502, 667 0x4021f502,
668 0xf094bd09, 668 0xf094bd0a,
669 0x07f10799, 669 0x07f10799,
670 0x03f01700, 670 0x03f01700,
671 0x0009d002, 671 0x0009d002,
@@ -710,18 +710,40 @@ uint32_t nvc0_grhub_code[] = {
710/* 0x072b: ih_no_ctxsw */ 710/* 0x072b: ih_no_ctxsw */
711 0xe40421f4, 711 0xe40421f4,
712 0xf40400ab, 712 0xf40400ab,
713 0xb7f1140b, 713 0xe7f16c0b,
714 0xe3f00708,
715 0x6821f440,
716 0xf102ffb9,
717 0xf0040007,
718 0x0fd00203,
719 0xf104bd00,
720 0xf00704e7,
721 0x21f440e3,
722 0x02ffb968,
723 0x030007f1,
724 0xd00203f0,
725 0x04bd000f,
726 0x9450fec7,
727 0xf7f102ee,
728 0xf3f00700,
729 0x00efbb40,
730 0xf16821f4,
731 0xf0020007,
732 0x0fd00203,
733 0xf004bd00,
734 0x21f503f7,
735 0xb7f1037e,
714 0xbfb90100, 736 0xbfb90100,
715 0x44e7f102, 737 0x44e7f102,
716 0x40e3f001, 738 0x40e3f001,
717/* 0x0743: ih_no_fwmthd */ 739/* 0x079b: ih_no_fwmthd */
718 0xf19d21f4, 740 0xf19d21f4,
719 0xbd0104b7, 741 0xbd0504b7,
720 0xb4abffb0, 742 0xb4abffb0,
721 0xf10f0bf4, 743 0xf10f0bf4,
722 0xf0070007, 744 0xf0070007,
723 0x0bd00303, 745 0x0bd00303,
724/* 0x075b: ih_no_other */ 746/* 0x07b3: ih_no_other */
725 0xf104bd00, 747 0xf104bd00,
726 0xf0010007, 748 0xf0010007,
727 0x0ad00003, 749 0x0ad00003,
@@ -731,36 +753,36 @@ uint32_t nvc0_grhub_code[] = {
731 0xfc90fca0, 753 0xfc90fca0,
732 0x0088fe80, 754 0x0088fe80,
733 0x32f480fc, 755 0x32f480fc,
734/* 0x077f: ctx_4160s */ 756/* 0x07d7: ctx_4160s */
735 0xf001f800, 757 0xf001f800,
736 0xffb901f7, 758 0xffb901f7,
737 0x60e7f102, 759 0x60e7f102,
738 0x40e3f041, 760 0x40e3f041,
739/* 0x078f: ctx_4160s_wait */ 761/* 0x07e7: ctx_4160s_wait */
740 0xf19d21f4, 762 0xf19d21f4,
741 0xf04160e7, 763 0xf04160e7,
742 0x21f440e3, 764 0x21f440e3,
743 0x02ffb968, 765 0x02ffb968,
744 0xf404ffc8, 766 0xf404ffc8,
745 0x00f8f00b, 767 0x00f8f00b,
746/* 0x07a4: ctx_4160c */ 768/* 0x07fc: ctx_4160c */
747 0xffb9f4bd, 769 0xffb9f4bd,
748 0x60e7f102, 770 0x60e7f102,
749 0x40e3f041, 771 0x40e3f041,
750 0xf89d21f4, 772 0xf89d21f4,
751/* 0x07b5: ctx_4170s */ 773/* 0x080d: ctx_4170s */
752 0x10f5f000, 774 0x10f5f000,
753 0xf102ffb9, 775 0xf102ffb9,
754 0xf04170e7, 776 0xf04170e7,
755 0x21f440e3, 777 0x21f440e3,
756/* 0x07c7: ctx_4170w */ 778/* 0x081f: ctx_4170w */
757 0xf100f89d, 779 0xf100f89d,
758 0xf04170e7, 780 0xf04170e7,
759 0x21f440e3, 781 0x21f440e3,
760 0x02ffb968, 782 0x02ffb968,
761 0xf410f4f0, 783 0xf410f4f0,
762 0x00f8f01b, 784 0x00f8f01b,
763/* 0x07dc: ctx_redswitch */ 785/* 0x0834: ctx_redswitch */
764 0x0200e7f1, 786 0x0200e7f1,
765 0xf040e5f0, 787 0xf040e5f0,
766 0xe5f020e5, 788 0xe5f020e5,
@@ -768,7 +790,7 @@ uint32_t nvc0_grhub_code[] = {
768 0x0103f085, 790 0x0103f085,
769 0xbd000ed0, 791 0xbd000ed0,
770 0x08f7f004, 792 0x08f7f004,
771/* 0x07f8: ctx_redswitch_delay */ 793/* 0x0850: ctx_redswitch_delay */
772 0xf401f2b6, 794 0xf401f2b6,
773 0xe5f1fd1b, 795 0xe5f1fd1b,
774 0xe5f10400, 796 0xe5f10400,
@@ -776,7 +798,7 @@ uint32_t nvc0_grhub_code[] = {
776 0x03f08500, 798 0x03f08500,
777 0x000ed001, 799 0x000ed001,
778 0x00f804bd, 800 0x00f804bd,
779/* 0x0814: ctx_86c */ 801/* 0x086c: ctx_86c */
780 0x1b0007f1, 802 0x1b0007f1,
781 0xd00203f0, 803 0xd00203f0,
782 0x04bd000f, 804 0x04bd000f,
@@ -787,16 +809,16 @@ uint32_t nvc0_grhub_code[] = {
787 0xa86ce7f1, 809 0xa86ce7f1,
788 0xf441e3f0, 810 0xf441e3f0,
789 0x00f89d21, 811 0x00f89d21,
790/* 0x083c: ctx_mem */ 812/* 0x0894: ctx_mem */
791 0x840007f1, 813 0x840007f1,
792 0xd00203f0, 814 0xd00203f0,
793 0x04bd000f, 815 0x04bd000f,
794/* 0x0848: ctx_mem_wait */ 816/* 0x08a0: ctx_mem_wait */
795 0x8400f7f1, 817 0x8400f7f1,
796 0xcf02f3f0, 818 0xcf02f3f0,
797 0xfffd00ff, 819 0xfffd00ff,
798 0xf31bf405, 820 0xf31bf405,
799/* 0x085a: ctx_load */ 821/* 0x08b2: ctx_load */
800 0x94bd00f8, 822 0x94bd00f8,
801 0xf10599f0, 823 0xf10599f0,
802 0xf00f0007, 824 0xf00f0007,
@@ -814,7 +836,7 @@ uint32_t nvc0_grhub_code[] = {
814 0x02d00203, 836 0x02d00203,
815 0xf004bd00, 837 0xf004bd00,
816 0x21f507f7, 838 0x21f507f7,
817 0x07f1083c, 839 0x07f10894,
818 0x03f0c000, 840 0x03f0c000,
819 0x0002d002, 841 0x0002d002,
820 0x0bfe04bd, 842 0x0bfe04bd,
@@ -869,31 +891,31 @@ uint32_t nvc0_grhub_code[] = {
869 0x03f01700, 891 0x03f01700,
870 0x0009d002, 892 0x0009d002,
871 0x00f804bd, 893 0x00f804bd,
872/* 0x0978: ctx_chan */ 894/* 0x09d0: ctx_chan */
873 0x077f21f5, 895 0x07d721f5,
874 0x085a21f5, 896 0x08b221f5,
875 0xf40ca7f0, 897 0xf40ca7f0,
876 0xf7f0d021, 898 0xf7f0d021,
877 0x3c21f505, 899 0x9421f505,
878 0xa421f508, 900 0xfc21f508,
879/* 0x0993: ctx_mmio_exec */ 901/* 0x09eb: ctx_mmio_exec */
880 0x9800f807, 902 0x9800f807,
881 0x07f14103, 903 0x07f14103,
882 0x03f08100, 904 0x03f08100,
883 0x0003d002, 905 0x0003d002,
884 0x34bd04bd, 906 0x34bd04bd,
885/* 0x09a4: ctx_mmio_loop */ 907/* 0x09fc: ctx_mmio_loop */
886 0xf4ff34c4, 908 0xf4ff34c4,
887 0x57f10f1b, 909 0x57f10f1b,
888 0x53f00200, 910 0x53f00200,
889 0x0535fa06, 911 0x0535fa06,
890/* 0x09b6: ctx_mmio_pull */ 912/* 0x0a0e: ctx_mmio_pull */
891 0x4e9803f8, 913 0x4e9803f8,
892 0x814f9880, 914 0x814f9880,
893 0xb69d21f4, 915 0xb69d21f4,
894 0x12b60830, 916 0x12b60830,
895 0xdf1bf401, 917 0xdf1bf401,
896/* 0x09c8: ctx_mmio_done */ 918/* 0x0a20: ctx_mmio_done */
897 0xf1160398, 919 0xf1160398,
898 0xf0810007, 920 0xf0810007,
899 0x03d00203, 921 0x03d00203,
@@ -902,30 +924,30 @@ uint32_t nvc0_grhub_code[] = {
902 0x13f00100, 924 0x13f00100,
903 0x0601fa06, 925 0x0601fa06,
904 0x00f803f8, 926 0x00f803f8,
905/* 0x09e8: ctx_xfer */ 927/* 0x0a40: ctx_xfer */
906 0xf104e7f0, 928 0xf104e7f0,
907 0xf0020007, 929 0xf0020007,
908 0x0ed00303, 930 0x0ed00303,
909/* 0x09f7: ctx_xfer_idle */ 931/* 0x0a4f: ctx_xfer_idle */
910 0xf104bd00, 932 0xf104bd00,
911 0xf00000e7, 933 0xf00000e7,
912 0xeecf03e3, 934 0xeecf03e3,
913 0x00e4f100, 935 0x00e4f100,
914 0xf21bf420, 936 0xf21bf420,
915 0xf40611f4, 937 0xf40611f4,
916/* 0x0a0e: ctx_xfer_pre */ 938/* 0x0a66: ctx_xfer_pre */
917 0xf7f01102, 939 0xf7f01102,
918 0x1421f510, 940 0x6c21f510,
919 0x7f21f508, 941 0xd721f508,
920 0x1c11f407, 942 0x1c11f407,
921/* 0x0a1c: ctx_xfer_pre_load */ 943/* 0x0a74: ctx_xfer_pre_load */
922 0xf502f7f0, 944 0xf502f7f0,
923 0xf507b521, 945 0xf5080d21,
924 0xf507c721, 946 0xf5081f21,
925 0xbd07dc21, 947 0xbd083421,
926 0xb521f5f4, 948 0x0d21f5f4,
927 0x5a21f507, 949 0xb221f508,
928/* 0x0a35: ctx_xfer_exec */ 950/* 0x0a8d: ctx_xfer_exec */
929 0x16019808, 951 0x16019808,
930 0x07f124bd, 952 0x07f124bd,
931 0x03f00500, 953 0x03f00500,
@@ -960,23 +982,65 @@ uint32_t nvc0_grhub_code[] = {
960 0x1301f402, 982 0x1301f402,
961 0xf40ca7f0, 983 0xf40ca7f0,
962 0xf7f0d021, 984 0xf7f0d021,
963 0x3c21f505, 985 0x9421f505,
964 0x3202f408, 986 0x3202f408,
965/* 0x0ac4: ctx_xfer_post */ 987/* 0x0b1c: ctx_xfer_post */
966 0xf502f7f0, 988 0xf502f7f0,
967 0xbd07b521, 989 0xbd080d21,
968 0x1421f5f4, 990 0x6c21f5f4,
969 0x7f21f508, 991 0x7f21f508,
970 0xc721f502, 992 0x1f21f502,
971 0xf5f4bd07, 993 0xf5f4bd08,
972 0xf407b521, 994 0xf4080d21,
973 0x01981011, 995 0x01981011,
974 0x0511fd40, 996 0x0511fd40,
975 0xf5070bf4, 997 0xf5070bf4,
976/* 0x0aef: ctx_xfer_no_post_mmio */ 998/* 0x0b47: ctx_xfer_no_post_mmio */
977 0xf5099321, 999 0xf509eb21,
978/* 0x0af3: ctx_xfer_done */ 1000/* 0x0b4b: ctx_xfer_done */
979 0xf807a421, 1001 0xf807fc21,
1002 0x00000000,
1003 0x00000000,
1004 0x00000000,
1005 0x00000000,
1006 0x00000000,
1007 0x00000000,
1008 0x00000000,
1009 0x00000000,
1010 0x00000000,
1011 0x00000000,
1012 0x00000000,
1013 0x00000000,
1014 0x00000000,
1015 0x00000000,
1016 0x00000000,
1017 0x00000000,
1018 0x00000000,
1019 0x00000000,
1020 0x00000000,
1021 0x00000000,
1022 0x00000000,
1023 0x00000000,
1024 0x00000000,
1025 0x00000000,
1026 0x00000000,
1027 0x00000000,
1028 0x00000000,
1029 0x00000000,
1030 0x00000000,
1031 0x00000000,
1032 0x00000000,
1033 0x00000000,
1034 0x00000000,
1035 0x00000000,
1036 0x00000000,
1037 0x00000000,
1038 0x00000000,
1039 0x00000000,
1040 0x00000000,
1041 0x00000000,
1042 0x00000000,
1043 0x00000000,
980 0x00000000, 1044 0x00000000,
981 0x00000000, 1045 0x00000000,
982 0x00000000, 1046 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
index 624215a005b0..62b0c7601d8b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
@@ -528,10 +528,10 @@ uint32_t nvd7_grhub_code[] = {
528 0x0001d001, 528 0x0001d001,
529 0x17f104bd, 529 0x17f104bd,
530 0xf7f00100, 530 0xf7f00100,
531 0xb521f502, 531 0x0d21f502,
532 0xc721f507, 532 0x1f21f508,
533 0x10f7f007, 533 0x10f7f008,
534 0x081421f5, 534 0x086c21f5,
535 0x98000e98, 535 0x98000e98,
536 0x21f5010f, 536 0x21f5010f,
537 0x14950150, 537 0x14950150,
@@ -574,9 +574,9 @@ uint32_t nvd7_grhub_code[] = {
574 0xb6800040, 574 0xb6800040,
575 0x1bf40132, 575 0x1bf40132,
576 0x00f7f0be, 576 0x00f7f0be,
577 0x081421f5, 577 0x086c21f5,
578 0xf500f7f0, 578 0xf500f7f0,
579 0xf107b521, 579 0xf1080d21,
580 0xf0010007, 580 0xf0010007,
581 0x01d00203, 581 0x01d00203,
582 0xbd04bd00, 582 0xbd04bd00,
@@ -610,8 +610,8 @@ uint32_t nvd7_grhub_code[] = {
610 0x09d00203, 610 0x09d00203,
611 0xf404bd00, 611 0xf404bd00,
612 0x31f40132, 612 0x31f40132,
613 0xe821f502, 613 0x4021f502,
614 0xf094bd09, 614 0xf094bd0a,
615 0x07f10799, 615 0x07f10799,
616 0x03f01700, 616 0x03f01700,
617 0x0009d002, 617 0x0009d002,
@@ -621,7 +621,7 @@ uint32_t nvd7_grhub_code[] = {
621 0x0203f00f, 621 0x0203f00f,
622 0xbd0009d0, 622 0xbd0009d0,
623 0x0131f404, 623 0x0131f404,
624 0x09e821f5, 624 0x0a4021f5,
625 0x99f094bd, 625 0x99f094bd,
626 0x0007f106, 626 0x0007f106,
627 0x0203f017, 627 0x0203f017,
@@ -631,7 +631,7 @@ uint32_t nvd7_grhub_code[] = {
631 0x12b920f9, 631 0x12b920f9,
632 0x0132f402, 632 0x0132f402,
633 0xf50232f4, 633 0xf50232f4,
634 0xfc09e821, 634 0xfc0a4021,
635 0x0007f120, 635 0x0007f120,
636 0x0203f0c0, 636 0x0203f0c0,
637 0xbd0002d0, 637 0xbd0002d0,
@@ -640,7 +640,7 @@ uint32_t nvd7_grhub_code[] = {
640 0xf41f23c8, 640 0xf41f23c8,
641 0x31f40d0b, 641 0x31f40d0b,
642 0x0232f401, 642 0x0232f401,
643 0x09e821f5, 643 0x0a4021f5,
644/* 0x063c: chsw_done */ 644/* 0x063c: chsw_done */
645 0xf10127f0, 645 0xf10127f0,
646 0xf0c30007, 646 0xf0c30007,
@@ -654,7 +654,7 @@ uint32_t nvd7_grhub_code[] = {
654/* 0x0660: main_not_ctx_switch */ 654/* 0x0660: main_not_ctx_switch */
655 0xf401e4b0, 655 0xf401e4b0,
656 0xf2b90d1b, 656 0xf2b90d1b,
657 0x7821f502, 657 0xd021f502,
658 0x460ef409, 658 0x460ef409,
659/* 0x0670: main_not_ctx_chan */ 659/* 0x0670: main_not_ctx_chan */
660 0xf402e4b0, 660 0xf402e4b0,
@@ -664,8 +664,8 @@ uint32_t nvd7_grhub_code[] = {
664 0x09d00203, 664 0x09d00203,
665 0xf404bd00, 665 0xf404bd00,
666 0x32f40132, 666 0x32f40132,
667 0xe821f502, 667 0x4021f502,
668 0xf094bd09, 668 0xf094bd0a,
669 0x07f10799, 669 0x07f10799,
670 0x03f01700, 670 0x03f01700,
671 0x0009d002, 671 0x0009d002,
@@ -710,18 +710,40 @@ uint32_t nvd7_grhub_code[] = {
710/* 0x072b: ih_no_ctxsw */ 710/* 0x072b: ih_no_ctxsw */
711 0xe40421f4, 711 0xe40421f4,
712 0xf40400ab, 712 0xf40400ab,
713 0xb7f1140b, 713 0xe7f16c0b,
714 0xe3f00708,
715 0x6821f440,
716 0xf102ffb9,
717 0xf0040007,
718 0x0fd00203,
719 0xf104bd00,
720 0xf00704e7,
721 0x21f440e3,
722 0x02ffb968,
723 0x030007f1,
724 0xd00203f0,
725 0x04bd000f,
726 0x9450fec7,
727 0xf7f102ee,
728 0xf3f00700,
729 0x00efbb40,
730 0xf16821f4,
731 0xf0020007,
732 0x0fd00203,
733 0xf004bd00,
734 0x21f503f7,
735 0xb7f1037e,
714 0xbfb90100, 736 0xbfb90100,
715 0x44e7f102, 737 0x44e7f102,
716 0x40e3f001, 738 0x40e3f001,
717/* 0x0743: ih_no_fwmthd */ 739/* 0x079b: ih_no_fwmthd */
718 0xf19d21f4, 740 0xf19d21f4,
719 0xbd0104b7, 741 0xbd0504b7,
720 0xb4abffb0, 742 0xb4abffb0,
721 0xf10f0bf4, 743 0xf10f0bf4,
722 0xf0070007, 744 0xf0070007,
723 0x0bd00303, 745 0x0bd00303,
724/* 0x075b: ih_no_other */ 746/* 0x07b3: ih_no_other */
725 0xf104bd00, 747 0xf104bd00,
726 0xf0010007, 748 0xf0010007,
727 0x0ad00003, 749 0x0ad00003,
@@ -731,36 +753,36 @@ uint32_t nvd7_grhub_code[] = {
731 0xfc90fca0, 753 0xfc90fca0,
732 0x0088fe80, 754 0x0088fe80,
733 0x32f480fc, 755 0x32f480fc,
734/* 0x077f: ctx_4160s */ 756/* 0x07d7: ctx_4160s */
735 0xf001f800, 757 0xf001f800,
736 0xffb901f7, 758 0xffb901f7,
737 0x60e7f102, 759 0x60e7f102,
738 0x40e3f041, 760 0x40e3f041,
739/* 0x078f: ctx_4160s_wait */ 761/* 0x07e7: ctx_4160s_wait */
740 0xf19d21f4, 762 0xf19d21f4,
741 0xf04160e7, 763 0xf04160e7,
742 0x21f440e3, 764 0x21f440e3,
743 0x02ffb968, 765 0x02ffb968,
744 0xf404ffc8, 766 0xf404ffc8,
745 0x00f8f00b, 767 0x00f8f00b,
746/* 0x07a4: ctx_4160c */ 768/* 0x07fc: ctx_4160c */
747 0xffb9f4bd, 769 0xffb9f4bd,
748 0x60e7f102, 770 0x60e7f102,
749 0x40e3f041, 771 0x40e3f041,
750 0xf89d21f4, 772 0xf89d21f4,
751/* 0x07b5: ctx_4170s */ 773/* 0x080d: ctx_4170s */
752 0x10f5f000, 774 0x10f5f000,
753 0xf102ffb9, 775 0xf102ffb9,
754 0xf04170e7, 776 0xf04170e7,
755 0x21f440e3, 777 0x21f440e3,
756/* 0x07c7: ctx_4170w */ 778/* 0x081f: ctx_4170w */
757 0xf100f89d, 779 0xf100f89d,
758 0xf04170e7, 780 0xf04170e7,
759 0x21f440e3, 781 0x21f440e3,
760 0x02ffb968, 782 0x02ffb968,
761 0xf410f4f0, 783 0xf410f4f0,
762 0x00f8f01b, 784 0x00f8f01b,
763/* 0x07dc: ctx_redswitch */ 785/* 0x0834: ctx_redswitch */
764 0x0200e7f1, 786 0x0200e7f1,
765 0xf040e5f0, 787 0xf040e5f0,
766 0xe5f020e5, 788 0xe5f020e5,
@@ -768,7 +790,7 @@ uint32_t nvd7_grhub_code[] = {
768 0x0103f085, 790 0x0103f085,
769 0xbd000ed0, 791 0xbd000ed0,
770 0x08f7f004, 792 0x08f7f004,
771/* 0x07f8: ctx_redswitch_delay */ 793/* 0x0850: ctx_redswitch_delay */
772 0xf401f2b6, 794 0xf401f2b6,
773 0xe5f1fd1b, 795 0xe5f1fd1b,
774 0xe5f10400, 796 0xe5f10400,
@@ -776,7 +798,7 @@ uint32_t nvd7_grhub_code[] = {
776 0x03f08500, 798 0x03f08500,
777 0x000ed001, 799 0x000ed001,
778 0x00f804bd, 800 0x00f804bd,
779/* 0x0814: ctx_86c */ 801/* 0x086c: ctx_86c */
780 0x1b0007f1, 802 0x1b0007f1,
781 0xd00203f0, 803 0xd00203f0,
782 0x04bd000f, 804 0x04bd000f,
@@ -787,16 +809,16 @@ uint32_t nvd7_grhub_code[] = {
787 0xa86ce7f1, 809 0xa86ce7f1,
788 0xf441e3f0, 810 0xf441e3f0,
789 0x00f89d21, 811 0x00f89d21,
790/* 0x083c: ctx_mem */ 812/* 0x0894: ctx_mem */
791 0x840007f1, 813 0x840007f1,
792 0xd00203f0, 814 0xd00203f0,
793 0x04bd000f, 815 0x04bd000f,
794/* 0x0848: ctx_mem_wait */ 816/* 0x08a0: ctx_mem_wait */
795 0x8400f7f1, 817 0x8400f7f1,
796 0xcf02f3f0, 818 0xcf02f3f0,
797 0xfffd00ff, 819 0xfffd00ff,
798 0xf31bf405, 820 0xf31bf405,
799/* 0x085a: ctx_load */ 821/* 0x08b2: ctx_load */
800 0x94bd00f8, 822 0x94bd00f8,
801 0xf10599f0, 823 0xf10599f0,
802 0xf00f0007, 824 0xf00f0007,
@@ -814,7 +836,7 @@ uint32_t nvd7_grhub_code[] = {
814 0x02d00203, 836 0x02d00203,
815 0xf004bd00, 837 0xf004bd00,
816 0x21f507f7, 838 0x21f507f7,
817 0x07f1083c, 839 0x07f10894,
818 0x03f0c000, 840 0x03f0c000,
819 0x0002d002, 841 0x0002d002,
820 0x0bfe04bd, 842 0x0bfe04bd,
@@ -869,31 +891,31 @@ uint32_t nvd7_grhub_code[] = {
869 0x03f01700, 891 0x03f01700,
870 0x0009d002, 892 0x0009d002,
871 0x00f804bd, 893 0x00f804bd,
872/* 0x0978: ctx_chan */ 894/* 0x09d0: ctx_chan */
873 0x077f21f5, 895 0x07d721f5,
874 0x085a21f5, 896 0x08b221f5,
875 0xf40ca7f0, 897 0xf40ca7f0,
876 0xf7f0d021, 898 0xf7f0d021,
877 0x3c21f505, 899 0x9421f505,
878 0xa421f508, 900 0xfc21f508,
879/* 0x0993: ctx_mmio_exec */ 901/* 0x09eb: ctx_mmio_exec */
880 0x9800f807, 902 0x9800f807,
881 0x07f14103, 903 0x07f14103,
882 0x03f08100, 904 0x03f08100,
883 0x0003d002, 905 0x0003d002,
884 0x34bd04bd, 906 0x34bd04bd,
885/* 0x09a4: ctx_mmio_loop */ 907/* 0x09fc: ctx_mmio_loop */
886 0xf4ff34c4, 908 0xf4ff34c4,
887 0x57f10f1b, 909 0x57f10f1b,
888 0x53f00200, 910 0x53f00200,
889 0x0535fa06, 911 0x0535fa06,
890/* 0x09b6: ctx_mmio_pull */ 912/* 0x0a0e: ctx_mmio_pull */
891 0x4e9803f8, 913 0x4e9803f8,
892 0x814f9880, 914 0x814f9880,
893 0xb69d21f4, 915 0xb69d21f4,
894 0x12b60830, 916 0x12b60830,
895 0xdf1bf401, 917 0xdf1bf401,
896/* 0x09c8: ctx_mmio_done */ 918/* 0x0a20: ctx_mmio_done */
897 0xf1160398, 919 0xf1160398,
898 0xf0810007, 920 0xf0810007,
899 0x03d00203, 921 0x03d00203,
@@ -902,30 +924,30 @@ uint32_t nvd7_grhub_code[] = {
902 0x13f00100, 924 0x13f00100,
903 0x0601fa06, 925 0x0601fa06,
904 0x00f803f8, 926 0x00f803f8,
905/* 0x09e8: ctx_xfer */ 927/* 0x0a40: ctx_xfer */
906 0xf104e7f0, 928 0xf104e7f0,
907 0xf0020007, 929 0xf0020007,
908 0x0ed00303, 930 0x0ed00303,
909/* 0x09f7: ctx_xfer_idle */ 931/* 0x0a4f: ctx_xfer_idle */
910 0xf104bd00, 932 0xf104bd00,
911 0xf00000e7, 933 0xf00000e7,
912 0xeecf03e3, 934 0xeecf03e3,
913 0x00e4f100, 935 0x00e4f100,
914 0xf21bf420, 936 0xf21bf420,
915 0xf40611f4, 937 0xf40611f4,
916/* 0x0a0e: ctx_xfer_pre */ 938/* 0x0a66: ctx_xfer_pre */
917 0xf7f01102, 939 0xf7f01102,
918 0x1421f510, 940 0x6c21f510,
919 0x7f21f508, 941 0xd721f508,
920 0x1c11f407, 942 0x1c11f407,
921/* 0x0a1c: ctx_xfer_pre_load */ 943/* 0x0a74: ctx_xfer_pre_load */
922 0xf502f7f0, 944 0xf502f7f0,
923 0xf507b521, 945 0xf5080d21,
924 0xf507c721, 946 0xf5081f21,
925 0xbd07dc21, 947 0xbd083421,
926 0xb521f5f4, 948 0x0d21f5f4,
927 0x5a21f507, 949 0xb221f508,
928/* 0x0a35: ctx_xfer_exec */ 950/* 0x0a8d: ctx_xfer_exec */
929 0x16019808, 951 0x16019808,
930 0x07f124bd, 952 0x07f124bd,
931 0x03f00500, 953 0x03f00500,
@@ -960,23 +982,65 @@ uint32_t nvd7_grhub_code[] = {
960 0x1301f402, 982 0x1301f402,
961 0xf40ca7f0, 983 0xf40ca7f0,
962 0xf7f0d021, 984 0xf7f0d021,
963 0x3c21f505, 985 0x9421f505,
964 0x3202f408, 986 0x3202f408,
965/* 0x0ac4: ctx_xfer_post */ 987/* 0x0b1c: ctx_xfer_post */
966 0xf502f7f0, 988 0xf502f7f0,
967 0xbd07b521, 989 0xbd080d21,
968 0x1421f5f4, 990 0x6c21f5f4,
969 0x7f21f508, 991 0x7f21f508,
970 0xc721f502, 992 0x1f21f502,
971 0xf5f4bd07, 993 0xf5f4bd08,
972 0xf407b521, 994 0xf4080d21,
973 0x01981011, 995 0x01981011,
974 0x0511fd40, 996 0x0511fd40,
975 0xf5070bf4, 997 0xf5070bf4,
976/* 0x0aef: ctx_xfer_no_post_mmio */ 998/* 0x0b47: ctx_xfer_no_post_mmio */
977 0xf5099321, 999 0xf509eb21,
978/* 0x0af3: ctx_xfer_done */ 1000/* 0x0b4b: ctx_xfer_done */
979 0xf807a421, 1001 0xf807fc21,
1002 0x00000000,
1003 0x00000000,
1004 0x00000000,
1005 0x00000000,
1006 0x00000000,
1007 0x00000000,
1008 0x00000000,
1009 0x00000000,
1010 0x00000000,
1011 0x00000000,
1012 0x00000000,
1013 0x00000000,
1014 0x00000000,
1015 0x00000000,
1016 0x00000000,
1017 0x00000000,
1018 0x00000000,
1019 0x00000000,
1020 0x00000000,
1021 0x00000000,
1022 0x00000000,
1023 0x00000000,
1024 0x00000000,
1025 0x00000000,
1026 0x00000000,
1027 0x00000000,
1028 0x00000000,
1029 0x00000000,
1030 0x00000000,
1031 0x00000000,
1032 0x00000000,
1033 0x00000000,
1034 0x00000000,
1035 0x00000000,
1036 0x00000000,
1037 0x00000000,
1038 0x00000000,
1039 0x00000000,
1040 0x00000000,
1041 0x00000000,
1042 0x00000000,
1043 0x00000000,
980 0x00000000, 1044 0x00000000,
981 0x00000000, 1045 0x00000000,
982 0x00000000, 1046 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
index 6547b3dfc7ed..51c3797d8537 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
@@ -528,10 +528,10 @@ uint32_t nve0_grhub_code[] = {
528 0x0001d001, 528 0x0001d001,
529 0x17f104bd, 529 0x17f104bd,
530 0xf7f00100, 530 0xf7f00100,
531 0x7f21f502, 531 0xd721f502,
532 0x9121f507, 532 0xe921f507,
533 0x10f7f007, 533 0x10f7f007,
534 0x07de21f5, 534 0x083621f5,
535 0x98000e98, 535 0x98000e98,
536 0x21f5010f, 536 0x21f5010f,
537 0x14950150, 537 0x14950150,
@@ -574,9 +574,9 @@ uint32_t nve0_grhub_code[] = {
574 0xb6800040, 574 0xb6800040,
575 0x1bf40132, 575 0x1bf40132,
576 0x00f7f0be, 576 0x00f7f0be,
577 0x07de21f5, 577 0x083621f5,
578 0xf500f7f0, 578 0xf500f7f0,
579 0xf1077f21, 579 0xf107d721,
580 0xf0010007, 580 0xf0010007,
581 0x01d00203, 581 0x01d00203,
582 0xbd04bd00, 582 0xbd04bd00,
@@ -610,8 +610,8 @@ uint32_t nve0_grhub_code[] = {
610 0x09d00203, 610 0x09d00203,
611 0xf404bd00, 611 0xf404bd00,
612 0x31f40132, 612 0x31f40132,
613 0xaa21f502, 613 0x0221f502,
614 0xf094bd09, 614 0xf094bd0a,
615 0x07f10799, 615 0x07f10799,
616 0x03f01700, 616 0x03f01700,
617 0x0009d002, 617 0x0009d002,
@@ -621,7 +621,7 @@ uint32_t nve0_grhub_code[] = {
621 0x0203f00f, 621 0x0203f00f,
622 0xbd0009d0, 622 0xbd0009d0,
623 0x0131f404, 623 0x0131f404,
624 0x09aa21f5, 624 0x0a0221f5,
625 0x99f094bd, 625 0x99f094bd,
626 0x0007f106, 626 0x0007f106,
627 0x0203f017, 627 0x0203f017,
@@ -631,7 +631,7 @@ uint32_t nve0_grhub_code[] = {
631 0x12b920f9, 631 0x12b920f9,
632 0x0132f402, 632 0x0132f402,
633 0xf50232f4, 633 0xf50232f4,
634 0xfc09aa21, 634 0xfc0a0221,
635 0x0007f120, 635 0x0007f120,
636 0x0203f0c0, 636 0x0203f0c0,
637 0xbd0002d0, 637 0xbd0002d0,
@@ -640,7 +640,7 @@ uint32_t nve0_grhub_code[] = {
640 0xf41f23c8, 640 0xf41f23c8,
641 0x31f40d0b, 641 0x31f40d0b,
642 0x0232f401, 642 0x0232f401,
643 0x09aa21f5, 643 0x0a0221f5,
644/* 0x063c: chsw_done */ 644/* 0x063c: chsw_done */
645 0xf10127f0, 645 0xf10127f0,
646 0xf0c30007, 646 0xf0c30007,
@@ -654,7 +654,7 @@ uint32_t nve0_grhub_code[] = {
654/* 0x0660: main_not_ctx_switch */ 654/* 0x0660: main_not_ctx_switch */
655 0xf401e4b0, 655 0xf401e4b0,
656 0xf2b90d1b, 656 0xf2b90d1b,
657 0x4221f502, 657 0x9a21f502,
658 0x460ef409, 658 0x460ef409,
659/* 0x0670: main_not_ctx_chan */ 659/* 0x0670: main_not_ctx_chan */
660 0xf402e4b0, 660 0xf402e4b0,
@@ -664,8 +664,8 @@ uint32_t nve0_grhub_code[] = {
664 0x09d00203, 664 0x09d00203,
665 0xf404bd00, 665 0xf404bd00,
666 0x32f40132, 666 0x32f40132,
667 0xaa21f502, 667 0x0221f502,
668 0xf094bd09, 668 0xf094bd0a,
669 0x07f10799, 669 0x07f10799,
670 0x03f01700, 670 0x03f01700,
671 0x0009d002, 671 0x0009d002,
@@ -710,18 +710,40 @@ uint32_t nve0_grhub_code[] = {
710/* 0x072b: ih_no_ctxsw */ 710/* 0x072b: ih_no_ctxsw */
711 0xe40421f4, 711 0xe40421f4,
712 0xf40400ab, 712 0xf40400ab,
713 0xb7f1140b, 713 0xe7f16c0b,
714 0xe3f00708,
715 0x6821f440,
716 0xf102ffb9,
717 0xf0040007,
718 0x0fd00203,
719 0xf104bd00,
720 0xf00704e7,
721 0x21f440e3,
722 0x02ffb968,
723 0x030007f1,
724 0xd00203f0,
725 0x04bd000f,
726 0x9450fec7,
727 0xf7f102ee,
728 0xf3f00700,
729 0x00efbb40,
730 0xf16821f4,
731 0xf0020007,
732 0x0fd00203,
733 0xf004bd00,
734 0x21f503f7,
735 0xb7f1037e,
714 0xbfb90100, 736 0xbfb90100,
715 0x44e7f102, 737 0x44e7f102,
716 0x40e3f001, 738 0x40e3f001,
717/* 0x0743: ih_no_fwmthd */ 739/* 0x079b: ih_no_fwmthd */
718 0xf19d21f4, 740 0xf19d21f4,
719 0xbd0104b7, 741 0xbd0504b7,
720 0xb4abffb0, 742 0xb4abffb0,
721 0xf10f0bf4, 743 0xf10f0bf4,
722 0xf0070007, 744 0xf0070007,
723 0x0bd00303, 745 0x0bd00303,
724/* 0x075b: ih_no_other */ 746/* 0x07b3: ih_no_other */
725 0xf104bd00, 747 0xf104bd00,
726 0xf0010007, 748 0xf0010007,
727 0x0ad00003, 749 0x0ad00003,
@@ -731,19 +753,19 @@ uint32_t nve0_grhub_code[] = {
731 0xfc90fca0, 753 0xfc90fca0,
732 0x0088fe80, 754 0x0088fe80,
733 0x32f480fc, 755 0x32f480fc,
734/* 0x077f: ctx_4170s */ 756/* 0x07d7: ctx_4170s */
735 0xf001f800, 757 0xf001f800,
736 0xffb910f5, 758 0xffb910f5,
737 0x70e7f102, 759 0x70e7f102,
738 0x40e3f041, 760 0x40e3f041,
739 0xf89d21f4, 761 0xf89d21f4,
740/* 0x0791: ctx_4170w */ 762/* 0x07e9: ctx_4170w */
741 0x70e7f100, 763 0x70e7f100,
742 0x40e3f041, 764 0x40e3f041,
743 0xb96821f4, 765 0xb96821f4,
744 0xf4f002ff, 766 0xf4f002ff,
745 0xf01bf410, 767 0xf01bf410,
746/* 0x07a6: ctx_redswitch */ 768/* 0x07fe: ctx_redswitch */
747 0xe7f100f8, 769 0xe7f100f8,
748 0xe5f00200, 770 0xe5f00200,
749 0x20e5f040, 771 0x20e5f040,
@@ -751,7 +773,7 @@ uint32_t nve0_grhub_code[] = {
751 0xf0850007, 773 0xf0850007,
752 0x0ed00103, 774 0x0ed00103,
753 0xf004bd00, 775 0xf004bd00,
754/* 0x07c2: ctx_redswitch_delay */ 776/* 0x081a: ctx_redswitch_delay */
755 0xf2b608f7, 777 0xf2b608f7,
756 0xfd1bf401, 778 0xfd1bf401,
757 0x0400e5f1, 779 0x0400e5f1,
@@ -759,7 +781,7 @@ uint32_t nve0_grhub_code[] = {
759 0x850007f1, 781 0x850007f1,
760 0xd00103f0, 782 0xd00103f0,
761 0x04bd000e, 783 0x04bd000e,
762/* 0x07de: ctx_86c */ 784/* 0x0836: ctx_86c */
763 0x07f100f8, 785 0x07f100f8,
764 0x03f01b00, 786 0x03f01b00,
765 0x000fd002, 787 0x000fd002,
@@ -770,17 +792,17 @@ uint32_t nve0_grhub_code[] = {
770 0xe7f102ff, 792 0xe7f102ff,
771 0xe3f0a86c, 793 0xe3f0a86c,
772 0x9d21f441, 794 0x9d21f441,
773/* 0x0806: ctx_mem */ 795/* 0x085e: ctx_mem */
774 0x07f100f8, 796 0x07f100f8,
775 0x03f08400, 797 0x03f08400,
776 0x000fd002, 798 0x000fd002,
777/* 0x0812: ctx_mem_wait */ 799/* 0x086a: ctx_mem_wait */
778 0xf7f104bd, 800 0xf7f104bd,
779 0xf3f08400, 801 0xf3f08400,
780 0x00ffcf02, 802 0x00ffcf02,
781 0xf405fffd, 803 0xf405fffd,
782 0x00f8f31b, 804 0x00f8f31b,
783/* 0x0824: ctx_load */ 805/* 0x087c: ctx_load */
784 0x99f094bd, 806 0x99f094bd,
785 0x0007f105, 807 0x0007f105,
786 0x0203f00f, 808 0x0203f00f,
@@ -797,7 +819,7 @@ uint32_t nve0_grhub_code[] = {
797 0x0203f083, 819 0x0203f083,
798 0xbd0002d0, 820 0xbd0002d0,
799 0x07f7f004, 821 0x07f7f004,
800 0x080621f5, 822 0x085e21f5,
801 0xc00007f1, 823 0xc00007f1,
802 0xd00203f0, 824 0xd00203f0,
803 0x04bd0002, 825 0x04bd0002,
@@ -852,29 +874,29 @@ uint32_t nve0_grhub_code[] = {
852 0x170007f1, 874 0x170007f1,
853 0xd00203f0, 875 0xd00203f0,
854 0x04bd0009, 876 0x04bd0009,
855/* 0x0942: ctx_chan */ 877/* 0x099a: ctx_chan */
856 0x21f500f8, 878 0x21f500f8,
857 0xa7f00824, 879 0xa7f0087c,
858 0xd021f40c, 880 0xd021f40c,
859 0xf505f7f0, 881 0xf505f7f0,
860 0xf8080621, 882 0xf8085e21,
861/* 0x0955: ctx_mmio_exec */ 883/* 0x09ad: ctx_mmio_exec */
862 0x41039800, 884 0x41039800,
863 0x810007f1, 885 0x810007f1,
864 0xd00203f0, 886 0xd00203f0,
865 0x04bd0003, 887 0x04bd0003,
866/* 0x0966: ctx_mmio_loop */ 888/* 0x09be: ctx_mmio_loop */
867 0x34c434bd, 889 0x34c434bd,
868 0x0f1bf4ff, 890 0x0f1bf4ff,
869 0x020057f1, 891 0x020057f1,
870 0xfa0653f0, 892 0xfa0653f0,
871 0x03f80535, 893 0x03f80535,
872/* 0x0978: ctx_mmio_pull */ 894/* 0x09d0: ctx_mmio_pull */
873 0x98804e98, 895 0x98804e98,
874 0x21f4814f, 896 0x21f4814f,
875 0x0830b69d, 897 0x0830b69d,
876 0xf40112b6, 898 0xf40112b6,
877/* 0x098a: ctx_mmio_done */ 899/* 0x09e2: ctx_mmio_done */
878 0x0398df1b, 900 0x0398df1b,
879 0x0007f116, 901 0x0007f116,
880 0x0203f081, 902 0x0203f081,
@@ -883,30 +905,30 @@ uint32_t nve0_grhub_code[] = {
883 0x010017f1, 905 0x010017f1,
884 0xfa0613f0, 906 0xfa0613f0,
885 0x03f80601, 907 0x03f80601,
886/* 0x09aa: ctx_xfer */ 908/* 0x0a02: ctx_xfer */
887 0xe7f000f8, 909 0xe7f000f8,
888 0x0007f104, 910 0x0007f104,
889 0x0303f002, 911 0x0303f002,
890 0xbd000ed0, 912 0xbd000ed0,
891/* 0x09b9: ctx_xfer_idle */ 913/* 0x0a11: ctx_xfer_idle */
892 0x00e7f104, 914 0x00e7f104,
893 0x03e3f000, 915 0x03e3f000,
894 0xf100eecf, 916 0xf100eecf,
895 0xf42000e4, 917 0xf42000e4,
896 0x11f4f21b, 918 0x11f4f21b,
897 0x0d02f406, 919 0x0d02f406,
898/* 0x09d0: ctx_xfer_pre */ 920/* 0x0a28: ctx_xfer_pre */
899 0xf510f7f0, 921 0xf510f7f0,
900 0xf407de21, 922 0xf4083621,
901/* 0x09da: ctx_xfer_pre_load */ 923/* 0x0a32: ctx_xfer_pre_load */
902 0xf7f01c11, 924 0xf7f01c11,
903 0x7f21f502, 925 0xd721f502,
904 0x9121f507, 926 0xe921f507,
905 0xa621f507, 927 0xfe21f507,
906 0xf5f4bd07, 928 0xf5f4bd07,
907 0xf5077f21, 929 0xf507d721,
908/* 0x09f3: ctx_xfer_exec */ 930/* 0x0a4b: ctx_xfer_exec */
909 0x98082421, 931 0x98087c21,
910 0x24bd1601, 932 0x24bd1601,
911 0x050007f1, 933 0x050007f1,
912 0xd00103f0, 934 0xd00103f0,
@@ -941,21 +963,21 @@ uint32_t nve0_grhub_code[] = {
941 0xa7f01301, 963 0xa7f01301,
942 0xd021f40c, 964 0xd021f40c,
943 0xf505f7f0, 965 0xf505f7f0,
944 0xf4080621, 966 0xf4085e21,
945/* 0x0a82: ctx_xfer_post */ 967/* 0x0ada: ctx_xfer_post */
946 0xf7f02e02, 968 0xf7f02e02,
947 0x7f21f502, 969 0xd721f502,
948 0xf5f4bd07, 970 0xf5f4bd07,
949 0xf507de21, 971 0xf5083621,
950 0xf5027f21, 972 0xf5027f21,
951 0xbd079121, 973 0xbd07e921,
952 0x7f21f5f4, 974 0xd721f5f4,
953 0x1011f407, 975 0x1011f407,
954 0xfd400198, 976 0xfd400198,
955 0x0bf40511, 977 0x0bf40511,
956 0x5521f507, 978 0xad21f507,
957/* 0x0aad: ctx_xfer_no_post_mmio */ 979/* 0x0b05: ctx_xfer_no_post_mmio */
958/* 0x0aad: ctx_xfer_done */ 980/* 0x0b05: ctx_xfer_done */
959 0x0000f809, 981 0x0000f809,
960 0x00000000, 982 0x00000000,
961 0x00000000, 983 0x00000000,
@@ -977,4 +999,46 @@ uint32_t nve0_grhub_code[] = {
977 0x00000000, 999 0x00000000,
978 0x00000000, 1000 0x00000000,
979 0x00000000, 1001 0x00000000,
1002 0x00000000,
1003 0x00000000,
1004 0x00000000,
1005 0x00000000,
1006 0x00000000,
1007 0x00000000,
1008 0x00000000,
1009 0x00000000,
1010 0x00000000,
1011 0x00000000,
1012 0x00000000,
1013 0x00000000,
1014 0x00000000,
1015 0x00000000,
1016 0x00000000,
1017 0x00000000,
1018 0x00000000,
1019 0x00000000,
1020 0x00000000,
1021 0x00000000,
1022 0x00000000,
1023 0x00000000,
1024 0x00000000,
1025 0x00000000,
1026 0x00000000,
1027 0x00000000,
1028 0x00000000,
1029 0x00000000,
1030 0x00000000,
1031 0x00000000,
1032 0x00000000,
1033 0x00000000,
1034 0x00000000,
1035 0x00000000,
1036 0x00000000,
1037 0x00000000,
1038 0x00000000,
1039 0x00000000,
1040 0x00000000,
1041 0x00000000,
1042 0x00000000,
1043 0x00000000,
980}; 1044};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
index a5aee5a4302f..a0af4b703a8e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
@@ -528,10 +528,10 @@ uint32_t nvf0_grhub_code[] = {
528 0x0001d001, 528 0x0001d001,
529 0x17f104bd, 529 0x17f104bd,
530 0xf7f00100, 530 0xf7f00100,
531 0x7f21f502, 531 0xd721f502,
532 0x9121f507, 532 0xe921f507,
533 0x10f7f007, 533 0x10f7f007,
534 0x07de21f5, 534 0x083621f5,
535 0x98000e98, 535 0x98000e98,
536 0x21f5010f, 536 0x21f5010f,
537 0x14950150, 537 0x14950150,
@@ -574,9 +574,9 @@ uint32_t nvf0_grhub_code[] = {
574 0xb6800040, 574 0xb6800040,
575 0x1bf40132, 575 0x1bf40132,
576 0x00f7f0be, 576 0x00f7f0be,
577 0x07de21f5, 577 0x083621f5,
578 0xf500f7f0, 578 0xf500f7f0,
579 0xf1077f21, 579 0xf107d721,
580 0xf0010007, 580 0xf0010007,
581 0x01d00203, 581 0x01d00203,
582 0xbd04bd00, 582 0xbd04bd00,
@@ -610,8 +610,8 @@ uint32_t nvf0_grhub_code[] = {
610 0x09d00203, 610 0x09d00203,
611 0xf404bd00, 611 0xf404bd00,
612 0x31f40132, 612 0x31f40132,
613 0xaa21f502, 613 0x0221f502,
614 0xf094bd09, 614 0xf094bd0a,
615 0x07f10799, 615 0x07f10799,
616 0x03f01700, 616 0x03f01700,
617 0x0009d002, 617 0x0009d002,
@@ -621,7 +621,7 @@ uint32_t nvf0_grhub_code[] = {
621 0x0203f037, 621 0x0203f037,
622 0xbd0009d0, 622 0xbd0009d0,
623 0x0131f404, 623 0x0131f404,
624 0x09aa21f5, 624 0x0a0221f5,
625 0x99f094bd, 625 0x99f094bd,
626 0x0007f106, 626 0x0007f106,
627 0x0203f017, 627 0x0203f017,
@@ -631,7 +631,7 @@ uint32_t nvf0_grhub_code[] = {
631 0x12b920f9, 631 0x12b920f9,
632 0x0132f402, 632 0x0132f402,
633 0xf50232f4, 633 0xf50232f4,
634 0xfc09aa21, 634 0xfc0a0221,
635 0x0007f120, 635 0x0007f120,
636 0x0203f0c0, 636 0x0203f0c0,
637 0xbd0002d0, 637 0xbd0002d0,
@@ -640,7 +640,7 @@ uint32_t nvf0_grhub_code[] = {
640 0xf41f23c8, 640 0xf41f23c8,
641 0x31f40d0b, 641 0x31f40d0b,
642 0x0232f401, 642 0x0232f401,
643 0x09aa21f5, 643 0x0a0221f5,
644/* 0x063c: chsw_done */ 644/* 0x063c: chsw_done */
645 0xf10127f0, 645 0xf10127f0,
646 0xf0c30007, 646 0xf0c30007,
@@ -654,7 +654,7 @@ uint32_t nvf0_grhub_code[] = {
654/* 0x0660: main_not_ctx_switch */ 654/* 0x0660: main_not_ctx_switch */
655 0xf401e4b0, 655 0xf401e4b0,
656 0xf2b90d1b, 656 0xf2b90d1b,
657 0x4221f502, 657 0x9a21f502,
658 0x460ef409, 658 0x460ef409,
659/* 0x0670: main_not_ctx_chan */ 659/* 0x0670: main_not_ctx_chan */
660 0xf402e4b0, 660 0xf402e4b0,
@@ -664,8 +664,8 @@ uint32_t nvf0_grhub_code[] = {
664 0x09d00203, 664 0x09d00203,
665 0xf404bd00, 665 0xf404bd00,
666 0x32f40132, 666 0x32f40132,
667 0xaa21f502, 667 0x0221f502,
668 0xf094bd09, 668 0xf094bd0a,
669 0x07f10799, 669 0x07f10799,
670 0x03f01700, 670 0x03f01700,
671 0x0009d002, 671 0x0009d002,
@@ -710,18 +710,40 @@ uint32_t nvf0_grhub_code[] = {
710/* 0x072b: ih_no_ctxsw */ 710/* 0x072b: ih_no_ctxsw */
711 0xe40421f4, 711 0xe40421f4,
712 0xf40400ab, 712 0xf40400ab,
713 0xb7f1140b, 713 0xe7f16c0b,
714 0xe3f00708,
715 0x6821f440,
716 0xf102ffb9,
717 0xf0040007,
718 0x0fd00203,
719 0xf104bd00,
720 0xf00704e7,
721 0x21f440e3,
722 0x02ffb968,
723 0x030007f1,
724 0xd00203f0,
725 0x04bd000f,
726 0x9450fec7,
727 0xf7f102ee,
728 0xf3f00700,
729 0x00efbb40,
730 0xf16821f4,
731 0xf0020007,
732 0x0fd00203,
733 0xf004bd00,
734 0x21f503f7,
735 0xb7f1037e,
714 0xbfb90100, 736 0xbfb90100,
715 0x44e7f102, 737 0x44e7f102,
716 0x40e3f001, 738 0x40e3f001,
717/* 0x0743: ih_no_fwmthd */ 739/* 0x079b: ih_no_fwmthd */
718 0xf19d21f4, 740 0xf19d21f4,
719 0xbd0104b7, 741 0xbd0504b7,
720 0xb4abffb0, 742 0xb4abffb0,
721 0xf10f0bf4, 743 0xf10f0bf4,
722 0xf0070007, 744 0xf0070007,
723 0x0bd00303, 745 0x0bd00303,
724/* 0x075b: ih_no_other */ 746/* 0x07b3: ih_no_other */
725 0xf104bd00, 747 0xf104bd00,
726 0xf0010007, 748 0xf0010007,
727 0x0ad00003, 749 0x0ad00003,
@@ -731,19 +753,19 @@ uint32_t nvf0_grhub_code[] = {
731 0xfc90fca0, 753 0xfc90fca0,
732 0x0088fe80, 754 0x0088fe80,
733 0x32f480fc, 755 0x32f480fc,
734/* 0x077f: ctx_4170s */ 756/* 0x07d7: ctx_4170s */
735 0xf001f800, 757 0xf001f800,
736 0xffb910f5, 758 0xffb910f5,
737 0x70e7f102, 759 0x70e7f102,
738 0x40e3f041, 760 0x40e3f041,
739 0xf89d21f4, 761 0xf89d21f4,
740/* 0x0791: ctx_4170w */ 762/* 0x07e9: ctx_4170w */
741 0x70e7f100, 763 0x70e7f100,
742 0x40e3f041, 764 0x40e3f041,
743 0xb96821f4, 765 0xb96821f4,
744 0xf4f002ff, 766 0xf4f002ff,
745 0xf01bf410, 767 0xf01bf410,
746/* 0x07a6: ctx_redswitch */ 768/* 0x07fe: ctx_redswitch */
747 0xe7f100f8, 769 0xe7f100f8,
748 0xe5f00200, 770 0xe5f00200,
749 0x20e5f040, 771 0x20e5f040,
@@ -751,7 +773,7 @@ uint32_t nvf0_grhub_code[] = {
751 0xf0850007, 773 0xf0850007,
752 0x0ed00103, 774 0x0ed00103,
753 0xf004bd00, 775 0xf004bd00,
754/* 0x07c2: ctx_redswitch_delay */ 776/* 0x081a: ctx_redswitch_delay */
755 0xf2b608f7, 777 0xf2b608f7,
756 0xfd1bf401, 778 0xfd1bf401,
757 0x0400e5f1, 779 0x0400e5f1,
@@ -759,7 +781,7 @@ uint32_t nvf0_grhub_code[] = {
759 0x850007f1, 781 0x850007f1,
760 0xd00103f0, 782 0xd00103f0,
761 0x04bd000e, 783 0x04bd000e,
762/* 0x07de: ctx_86c */ 784/* 0x0836: ctx_86c */
763 0x07f100f8, 785 0x07f100f8,
764 0x03f02300, 786 0x03f02300,
765 0x000fd002, 787 0x000fd002,
@@ -770,17 +792,17 @@ uint32_t nvf0_grhub_code[] = {
770 0xe7f102ff, 792 0xe7f102ff,
771 0xe3f0a88c, 793 0xe3f0a88c,
772 0x9d21f441, 794 0x9d21f441,
773/* 0x0806: ctx_mem */ 795/* 0x085e: ctx_mem */
774 0x07f100f8, 796 0x07f100f8,
775 0x03f08400, 797 0x03f08400,
776 0x000fd002, 798 0x000fd002,
777/* 0x0812: ctx_mem_wait */ 799/* 0x086a: ctx_mem_wait */
778 0xf7f104bd, 800 0xf7f104bd,
779 0xf3f08400, 801 0xf3f08400,
780 0x00ffcf02, 802 0x00ffcf02,
781 0xf405fffd, 803 0xf405fffd,
782 0x00f8f31b, 804 0x00f8f31b,
783/* 0x0824: ctx_load */ 805/* 0x087c: ctx_load */
784 0x99f094bd, 806 0x99f094bd,
785 0x0007f105, 807 0x0007f105,
786 0x0203f037, 808 0x0203f037,
@@ -797,7 +819,7 @@ uint32_t nvf0_grhub_code[] = {
797 0x0203f083, 819 0x0203f083,
798 0xbd0002d0, 820 0xbd0002d0,
799 0x07f7f004, 821 0x07f7f004,
800 0x080621f5, 822 0x085e21f5,
801 0xc00007f1, 823 0xc00007f1,
802 0xd00203f0, 824 0xd00203f0,
803 0x04bd0002, 825 0x04bd0002,
@@ -852,29 +874,29 @@ uint32_t nvf0_grhub_code[] = {
852 0x170007f1, 874 0x170007f1,
853 0xd00203f0, 875 0xd00203f0,
854 0x04bd0009, 876 0x04bd0009,
855/* 0x0942: ctx_chan */ 877/* 0x099a: ctx_chan */
856 0x21f500f8, 878 0x21f500f8,
857 0xa7f00824, 879 0xa7f0087c,
858 0xd021f40c, 880 0xd021f40c,
859 0xf505f7f0, 881 0xf505f7f0,
860 0xf8080621, 882 0xf8085e21,
861/* 0x0955: ctx_mmio_exec */ 883/* 0x09ad: ctx_mmio_exec */
862 0x41039800, 884 0x41039800,
863 0x810007f1, 885 0x810007f1,
864 0xd00203f0, 886 0xd00203f0,
865 0x04bd0003, 887 0x04bd0003,
866/* 0x0966: ctx_mmio_loop */ 888/* 0x09be: ctx_mmio_loop */
867 0x34c434bd, 889 0x34c434bd,
868 0x0f1bf4ff, 890 0x0f1bf4ff,
869 0x020057f1, 891 0x020057f1,
870 0xfa0653f0, 892 0xfa0653f0,
871 0x03f80535, 893 0x03f80535,
872/* 0x0978: ctx_mmio_pull */ 894/* 0x09d0: ctx_mmio_pull */
873 0x98804e98, 895 0x98804e98,
874 0x21f4814f, 896 0x21f4814f,
875 0x0830b69d, 897 0x0830b69d,
876 0xf40112b6, 898 0xf40112b6,
877/* 0x098a: ctx_mmio_done */ 899/* 0x09e2: ctx_mmio_done */
878 0x0398df1b, 900 0x0398df1b,
879 0x0007f116, 901 0x0007f116,
880 0x0203f081, 902 0x0203f081,
@@ -883,30 +905,30 @@ uint32_t nvf0_grhub_code[] = {
883 0x010017f1, 905 0x010017f1,
884 0xfa0613f0, 906 0xfa0613f0,
885 0x03f80601, 907 0x03f80601,
886/* 0x09aa: ctx_xfer */ 908/* 0x0a02: ctx_xfer */
887 0xe7f000f8, 909 0xe7f000f8,
888 0x0007f104, 910 0x0007f104,
889 0x0303f002, 911 0x0303f002,
890 0xbd000ed0, 912 0xbd000ed0,
891/* 0x09b9: ctx_xfer_idle */ 913/* 0x0a11: ctx_xfer_idle */
892 0x00e7f104, 914 0x00e7f104,
893 0x03e3f000, 915 0x03e3f000,
894 0xf100eecf, 916 0xf100eecf,
895 0xf42000e4, 917 0xf42000e4,
896 0x11f4f21b, 918 0x11f4f21b,
897 0x0d02f406, 919 0x0d02f406,
898/* 0x09d0: ctx_xfer_pre */ 920/* 0x0a28: ctx_xfer_pre */
899 0xf510f7f0, 921 0xf510f7f0,
900 0xf407de21, 922 0xf4083621,
901/* 0x09da: ctx_xfer_pre_load */ 923/* 0x0a32: ctx_xfer_pre_load */
902 0xf7f01c11, 924 0xf7f01c11,
903 0x7f21f502, 925 0xd721f502,
904 0x9121f507, 926 0xe921f507,
905 0xa621f507, 927 0xfe21f507,
906 0xf5f4bd07, 928 0xf5f4bd07,
907 0xf5077f21, 929 0xf507d721,
908/* 0x09f3: ctx_xfer_exec */ 930/* 0x0a4b: ctx_xfer_exec */
909 0x98082421, 931 0x98087c21,
910 0x24bd1601, 932 0x24bd1601,
911 0x050007f1, 933 0x050007f1,
912 0xd00103f0, 934 0xd00103f0,
@@ -941,21 +963,21 @@ uint32_t nvf0_grhub_code[] = {
941 0xa7f01301, 963 0xa7f01301,
942 0xd021f40c, 964 0xd021f40c,
943 0xf505f7f0, 965 0xf505f7f0,
944 0xf4080621, 966 0xf4085e21,
945/* 0x0a82: ctx_xfer_post */ 967/* 0x0ada: ctx_xfer_post */
946 0xf7f02e02, 968 0xf7f02e02,
947 0x7f21f502, 969 0xd721f502,
948 0xf5f4bd07, 970 0xf5f4bd07,
949 0xf507de21, 971 0xf5083621,
950 0xf5027f21, 972 0xf5027f21,
951 0xbd079121, 973 0xbd07e921,
952 0x7f21f5f4, 974 0xd721f5f4,
953 0x1011f407, 975 0x1011f407,
954 0xfd400198, 976 0xfd400198,
955 0x0bf40511, 977 0x0bf40511,
956 0x5521f507, 978 0xad21f507,
957/* 0x0aad: ctx_xfer_no_post_mmio */ 979/* 0x0b05: ctx_xfer_no_post_mmio */
958/* 0x0aad: ctx_xfer_done */ 980/* 0x0b05: ctx_xfer_done */
959 0x0000f809, 981 0x0000f809,
960 0x00000000, 982 0x00000000,
961 0x00000000, 983 0x00000000,
@@ -977,4 +999,46 @@ uint32_t nvf0_grhub_code[] = {
977 0x00000000, 999 0x00000000,
978 0x00000000, 1000 0x00000000,
979 0x00000000, 1001 0x00000000,
1002 0x00000000,
1003 0x00000000,
1004 0x00000000,
1005 0x00000000,
1006 0x00000000,
1007 0x00000000,
1008 0x00000000,
1009 0x00000000,
1010 0x00000000,
1011 0x00000000,
1012 0x00000000,
1013 0x00000000,
1014 0x00000000,
1015 0x00000000,
1016 0x00000000,
1017 0x00000000,
1018 0x00000000,
1019 0x00000000,
1020 0x00000000,
1021 0x00000000,
1022 0x00000000,
1023 0x00000000,
1024 0x00000000,
1025 0x00000000,
1026 0x00000000,
1027 0x00000000,
1028 0x00000000,
1029 0x00000000,
1030 0x00000000,
1031 0x00000000,
1032 0x00000000,
1033 0x00000000,
1034 0x00000000,
1035 0x00000000,
1036 0x00000000,
1037 0x00000000,
1038 0x00000000,
1039 0x00000000,
1040 0x00000000,
1041 0x00000000,
1042 0x00000000,
1043 0x00000000,
980}; 1044};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
index a47d49db5232..2a0b0f844299 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
@@ -30,6 +30,12 @@
30#define GK110 0xf0 30#define GK110 0xf0
31#define GK208 0x108 31#define GK208 0x108
32 32
33#define NV_PGRAPH_TRAPPED_ADDR 0x400704
34#define NV_PGRAPH_TRAPPED_DATA_LO 0x400708
35#define NV_PGRAPH_TRAPPED_DATA_HI 0x40070c
36
37#define NV_PGRAPH_FE_OBJECT_TABLE(n) ((n) * 4 + 0x400700)
38
33#define NV_PGRAPH_FECS_INTR_ACK 0x409004 39#define NV_PGRAPH_FECS_INTR_ACK 0x409004
34#define NV_PGRAPH_FECS_INTR 0x409008 40#define NV_PGRAPH_FECS_INTR 0x409008
35#define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400 41#define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
index fd1d380de094..1718ae4e8224 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
@@ -3,5 +3,6 @@
3 3
4#define E_BAD_COMMAND 0x00000001 4#define E_BAD_COMMAND 0x00000001
5#define E_CMD_OVERFLOW 0x00000002 5#define E_CMD_OVERFLOW 0x00000002
6#define E_BAD_FWMTHD 0x00000003
6 7
7#endif 8#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 1a2d56493cf6..20665c21d80e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -976,7 +976,6 @@ nv50_graph_init(struct nouveau_object *object)
976 break; 976 break;
977 case 0xa0: 977 case 0xa0:
978 default: 978 default:
979 nv_wr32(priv, 0x402cc0, 0x00000000);
980 if (nv_device(priv)->chipset == 0xa0 || 979 if (nv_device(priv)->chipset == 0xa0 ||
981 nv_device(priv)->chipset == 0xaa || 980 nv_device(priv)->chipset == 0xaa ||
982 nv_device(priv)->chipset == 0xac) { 981 nv_device(priv)->chipset == 0xac) {
@@ -991,10 +990,10 @@ nv50_graph_init(struct nouveau_object *object)
991 990
992 /* zero out zcull regions */ 991 /* zero out zcull regions */
993 for (i = 0; i < 8; i++) { 992 for (i = 0; i < 8; i++) {
994 nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000); 993 nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000);
995 nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000); 994 nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000);
996 nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000); 995 nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000);
997 nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000); 996 nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000);
998 } 997 }
999 return 0; 998 return 0;
1000} 999}
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index bf7bdb1f291e..aa0838916354 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -789,17 +789,40 @@ nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
789static void 789static void
790nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) 790nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
791{ 791{
792 u32 ustat = nv_rd32(priv, 0x409c18); 792 u32 stat = nv_rd32(priv, 0x409c18);
793 793
794 if (ustat & 0x00000001) 794 if (stat & 0x00000001) {
795 nv_error(priv, "CTXCTL ucode error\n"); 795 u32 code = nv_rd32(priv, 0x409814);
796 if (ustat & 0x00080000) 796 if (code == E_BAD_FWMTHD) {
797 nv_error(priv, "CTXCTL watchdog timeout\n"); 797 u32 class = nv_rd32(priv, 0x409808);
798 if (ustat & ~0x00080001) 798 u32 addr = nv_rd32(priv, 0x40980c);
799 nv_error(priv, "CTXCTL 0x%08x\n", ustat); 799 u32 subc = (addr & 0x00070000) >> 16;
800 u32 mthd = (addr & 0x00003ffc);
801 u32 data = nv_rd32(priv, 0x409810);
802
803 nv_error(priv, "FECS MTHD subc %d class 0x%04x "
804 "mthd 0x%04x data 0x%08x\n",
805 subc, class, mthd, data);
800 806
801 nvc0_graph_ctxctl_debug(priv); 807 nv_wr32(priv, 0x409c20, 0x00000001);
802 nv_wr32(priv, 0x409c20, ustat); 808 stat &= ~0x00000001;
809 } else {
810 nv_error(priv, "FECS ucode error %d\n", code);
811 }
812 }
813
814 if (stat & 0x00080000) {
815 nv_error(priv, "FECS watchdog timeout\n");
816 nvc0_graph_ctxctl_debug(priv);
817 nv_wr32(priv, 0x409c20, 0x00080000);
818 stat &= ~0x00080000;
819 }
820
821 if (stat) {
822 nv_error(priv, "FECS 0x%08x\n", stat);
823 nvc0_graph_ctxctl_debug(priv);
824 nv_wr32(priv, 0x409c20, stat);
825 }
803} 826}
804 827
805static void 828static void
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index 75203a99d902..ffc289198dd8 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -38,6 +38,8 @@
38#include <engine/fifo.h> 38#include <engine/fifo.h>
39#include <engine/graph.h> 39#include <engine/graph.h>
40 40
41#include "fuc/os.h"
42
41#define GPC_MAX 32 43#define GPC_MAX 32
42#define TPC_MAX (GPC_MAX * 8) 44#define TPC_MAX (GPC_MAX * 8)
43 45
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
index db1b39d08013..825f7bb46b67 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
@@ -84,6 +84,7 @@ extern struct nouveau_oclass *nv4e_i2c_oclass;
84extern struct nouveau_oclass *nv50_i2c_oclass; 84extern struct nouveau_oclass *nv50_i2c_oclass;
85extern struct nouveau_oclass *nv94_i2c_oclass; 85extern struct nouveau_oclass *nv94_i2c_oclass;
86extern struct nouveau_oclass *nvd0_i2c_oclass; 86extern struct nouveau_oclass *nvd0_i2c_oclass;
87extern struct nouveau_oclass *gf117_i2c_oclass;
87extern struct nouveau_oclass *nve0_i2c_oclass; 88extern struct nouveau_oclass *nve0_i2c_oclass;
88 89
89static inline int 90static inline int
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
index 4ac1aa30ea11..0e62a3240144 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
@@ -307,7 +307,6 @@ calc_clk(struct nve0_clock_priv *priv,
307 info->dsrc = src0; 307 info->dsrc = src0;
308 if (div0) { 308 if (div0) {
309 info->ddiv |= 0x80000000; 309 info->ddiv |= 0x80000000;
310 info->ddiv |= div0 << 8;
311 info->ddiv |= div0; 310 info->ddiv |= div0;
312 } 311 }
313 if (div1D) { 312 if (div1D) {
@@ -352,7 +351,7 @@ nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
352{ 351{
353 struct nve0_clock_info *info = &priv->eng[clk]; 352 struct nve0_clock_info *info = &priv->eng[clk];
354 if (!info->ssel) { 353 if (!info->ssel) {
355 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); 354 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv);
356 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); 355 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
357 } 356 }
358} 357}
@@ -389,7 +388,10 @@ static void
389nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) 388nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
390{ 389{
391 struct nve0_clock_info *info = &priv->eng[clk]; 390 struct nve0_clock_info *info = &priv->eng[clk];
392 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); 391 if (info->ssel)
392 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv);
393 else
394 nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv);
393} 395}
394 396
395static void 397static void
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
index 84c7efbc4f38..1ad3ea503133 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
@@ -262,8 +262,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
262 struct nve0_ram *ram = (void *)pfb->ram; 262 struct nve0_ram *ram = (void *)pfb->ram;
263 struct nve0_ramfuc *fuc = &ram->fuc; 263 struct nve0_ramfuc *fuc = &ram->fuc;
264 struct nouveau_ram_data *next = ram->base.next; 264 struct nouveau_ram_data *next = ram->base.next;
265 int vc = !(next->bios.ramcfg_11_02_08); 265 int vc = !next->bios.ramcfg_11_02_08;
266 int mv = !(next->bios.ramcfg_11_02_04); 266 int mv = !next->bios.ramcfg_11_02_04;
267 u32 mask, data; 267 u32 mask, data;
268 268
269 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 269 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
@@ -370,8 +370,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
370 } 370 }
371 } 371 }
372 372
373 if ( (next->bios.ramcfg_11_02_40) || 373 if (next->bios.ramcfg_11_02_40 ||
374 (next->bios.ramcfg_11_07_10)) { 374 next->bios.ramcfg_11_07_10) {
375 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 375 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
376 ram_nsec(fuc, 20000); 376 ram_nsec(fuc, 20000);
377 } 377 }
@@ -417,7 +417,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
417 ram_mask(fuc, 0x10f694, 0xff00ff00, data); 417 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
418 } 418 }
419 419
420 if (ram->mode == 2 && (next->bios.ramcfg_11_08_10)) 420 if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
421 data = 0x00000080; 421 data = 0x00000080;
422 else 422 else
423 data = 0x00000000; 423 data = 0x00000000;
@@ -425,13 +425,13 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
425 425
426 mask = 0x00070000; 426 mask = 0x00070000;
427 data = 0x00000000; 427 data = 0x00000000;
428 if (!(next->bios.ramcfg_11_02_80)) 428 if (!next->bios.ramcfg_11_02_80)
429 data |= 0x03000000; 429 data |= 0x03000000;
430 if (!(next->bios.ramcfg_11_02_40)) 430 if (!next->bios.ramcfg_11_02_40)
431 data |= 0x00002000; 431 data |= 0x00002000;
432 if (!(next->bios.ramcfg_11_07_10)) 432 if (!next->bios.ramcfg_11_07_10)
433 data |= 0x00004000; 433 data |= 0x00004000;
434 if (!(next->bios.ramcfg_11_07_08)) 434 if (!next->bios.ramcfg_11_07_08)
435 data |= 0x00000003; 435 data |= 0x00000003;
436 else 436 else
437 data |= 0x74000000; 437 data |= 0x74000000;
@@ -486,7 +486,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
486 486
487 data = mask = 0x00000000; 487 data = mask = 0x00000000;
488 if (NOTE00(ramcfg_02_03 != 0)) { 488 if (NOTE00(ramcfg_02_03 != 0)) {
489 data |= (next->bios.ramcfg_11_02_03) << 8; 489 data |= next->bios.ramcfg_11_02_03 << 8;
490 mask |= 0x00000300; 490 mask |= 0x00000300;
491 } 491 }
492 if (NOTE00(ramcfg_01_10)) { 492 if (NOTE00(ramcfg_01_10)) {
@@ -498,7 +498,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
498 498
499 data = mask = 0x00000000; 499 data = mask = 0x00000000;
500 if (NOTE00(timing_30_07 != 0)) { 500 if (NOTE00(timing_30_07 != 0)) {
501 data |= (next->bios.timing_20_30_07) << 28; 501 data |= next->bios.timing_20_30_07 << 28;
502 mask |= 0x70000000; 502 mask |= 0x70000000;
503 } 503 }
504 if (NOTE00(ramcfg_01_01)) { 504 if (NOTE00(ramcfg_01_01)) {
@@ -510,7 +510,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
510 510
511 data = mask = 0x00000000; 511 data = mask = 0x00000000;
512 if (NOTE00(timing_30_07 != 0)) { 512 if (NOTE00(timing_30_07 != 0)) {
513 data |= (next->bios.timing_20_30_07) << 28; 513 data |= next->bios.timing_20_30_07 << 28;
514 mask |= 0x70000000; 514 mask |= 0x70000000;
515 } 515 }
516 if (NOTE00(ramcfg_01_02)) { 516 if (NOTE00(ramcfg_01_02)) {
@@ -522,16 +522,16 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
522 522
523 mask = 0x33f00000; 523 mask = 0x33f00000;
524 data = 0x00000000; 524 data = 0x00000000;
525 if (!(next->bios.ramcfg_11_01_04)) 525 if (!next->bios.ramcfg_11_01_04)
526 data |= 0x20200000; 526 data |= 0x20200000;
527 if (!(next->bios.ramcfg_11_07_80)) 527 if (!next->bios.ramcfg_11_07_80)
528 data |= 0x12800000; 528 data |= 0x12800000;
529 /*XXX: see note above about there probably being some condition 529 /*XXX: see note above about there probably being some condition
530 * for the 10f824 stuff that uses ramcfg 3... 530 * for the 10f824 stuff that uses ramcfg 3...
531 */ 531 */
532 if ( (next->bios.ramcfg_11_03_f0)) { 532 if (next->bios.ramcfg_11_03_f0) {
533 if (next->bios.rammap_11_08_0c) { 533 if (next->bios.rammap_11_08_0c) {
534 if (!(next->bios.ramcfg_11_07_80)) 534 if (!next->bios.ramcfg_11_07_80)
535 mask |= 0x00000020; 535 mask |= 0x00000020;
536 else 536 else
537 data |= 0x00000020; 537 data |= 0x00000020;
@@ -563,7 +563,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
563 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); 563 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
564 } 564 }
565 565
566 data = (next->bios.timing_20_30_07) << 8; 566 data = next->bios.timing_20_30_07 << 8;
567 if (next->bios.ramcfg_11_01_01) 567 if (next->bios.ramcfg_11_01_01)
568 data |= 0x80000000; 568 data |= 0x80000000;
569 ram_mask(fuc, 0x100778, 0x00000700, data); 569 ram_mask(fuc, 0x100778, 0x00000700, data);
@@ -588,7 +588,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
588 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 588 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
589 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 589 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
590 590
591 if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) { 591 if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
592 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); 592 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
593 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ 593 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
594 ram_nsec(fuc, 1000); 594 ram_nsec(fuc, 1000);
@@ -621,8 +621,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
621 data = ram_rd32(fuc, 0x10f978); 621 data = ram_rd32(fuc, 0x10f978);
622 data &= ~0x00046144; 622 data &= ~0x00046144;
623 data |= 0x0000000b; 623 data |= 0x0000000b;
624 if (!(next->bios.ramcfg_11_07_08)) { 624 if (!next->bios.ramcfg_11_07_08) {
625 if (!(next->bios.ramcfg_11_07_04)) 625 if (!next->bios.ramcfg_11_07_04)
626 data |= 0x0000200c; 626 data |= 0x0000200c;
627 else 627 else
628 data |= 0x00000000; 628 data |= 0x00000000;
@@ -636,11 +636,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
636 ram_wr32(fuc, 0x10f830, data); 636 ram_wr32(fuc, 0x10f830, data);
637 } 637 }
638 638
639 if (!(next->bios.ramcfg_11_07_08)) { 639 if (!next->bios.ramcfg_11_07_08) {
640 data = 0x88020000; 640 data = 0x88020000;
641 if ( (next->bios.ramcfg_11_07_04)) 641 if ( next->bios.ramcfg_11_07_04)
642 data |= 0x10000000; 642 data |= 0x10000000;
643 if (!(next->bios.rammap_11_08_10)) 643 if (!next->bios.rammap_11_08_10)
644 data |= 0x00080000; 644 data |= 0x00080000;
645 } else { 645 } else {
646 data = 0xa40e0000; 646 data = 0xa40e0000;
@@ -689,8 +689,8 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
689 const u32 runk0 = ram->fN1 << 16; 689 const u32 runk0 = ram->fN1 << 16;
690 const u32 runk1 = ram->fN1; 690 const u32 runk1 = ram->fN1;
691 struct nouveau_ram_data *next = ram->base.next; 691 struct nouveau_ram_data *next = ram->base.next;
692 int vc = !(next->bios.ramcfg_11_02_08); 692 int vc = !next->bios.ramcfg_11_02_08;
693 int mv = !(next->bios.ramcfg_11_02_04); 693 int mv = !next->bios.ramcfg_11_02_04;
694 u32 mask, data; 694 u32 mask, data;
695 695
696 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 696 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
@@ -705,7 +705,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
705 } 705 }
706 706
707 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 707 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
708 if ((next->bios.ramcfg_11_03_f0)) 708 if (next->bios.ramcfg_11_03_f0)
709 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); 709 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
710 710
711 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 711 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
@@ -761,7 +761,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
761 761
762 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 762 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
763 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 763 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
764 data |= (next->bios.ramcfg_11_03_30) << 12; 764 data |= next->bios.ramcfg_11_03_30 << 16;
765 ram_wr32(fuc, 0x1373ec, data); 765 ram_wr32(fuc, 0x1373ec, data);
766 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 766 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
767 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); 767 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
@@ -793,8 +793,8 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
793 } 793 }
794 } 794 }
795 795
796 if ( (next->bios.ramcfg_11_02_40) || 796 if (next->bios.ramcfg_11_02_40 ||
797 (next->bios.ramcfg_11_07_10)) { 797 next->bios.ramcfg_11_07_10) {
798 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 798 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
799 ram_nsec(fuc, 20000); 799 ram_nsec(fuc, 20000);
800 } 800 }
@@ -810,13 +810,13 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
810 810
811 mask = 0x00010000; 811 mask = 0x00010000;
812 data = 0x00000000; 812 data = 0x00000000;
813 if (!(next->bios.ramcfg_11_02_80)) 813 if (!next->bios.ramcfg_11_02_80)
814 data |= 0x03000000; 814 data |= 0x03000000;
815 if (!(next->bios.ramcfg_11_02_40)) 815 if (!next->bios.ramcfg_11_02_40)
816 data |= 0x00002000; 816 data |= 0x00002000;
817 if (!(next->bios.ramcfg_11_07_10)) 817 if (!next->bios.ramcfg_11_07_10)
818 data |= 0x00004000; 818 data |= 0x00004000;
819 if (!(next->bios.ramcfg_11_07_08)) 819 if (!next->bios.ramcfg_11_07_08)
820 data |= 0x00000003; 820 data |= 0x00000003;
821 else 821 else
822 data |= 0x14000000; 822 data |= 0x14000000;
@@ -844,16 +844,16 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
844 844
845 mask = 0x33f00000; 845 mask = 0x33f00000;
846 data = 0x00000000; 846 data = 0x00000000;
847 if (!(next->bios.ramcfg_11_01_04)) 847 if (!next->bios.ramcfg_11_01_04)
848 data |= 0x20200000; 848 data |= 0x20200000;
849 if (!(next->bios.ramcfg_11_07_80)) 849 if (!next->bios.ramcfg_11_07_80)
850 data |= 0x12800000; 850 data |= 0x12800000;
851 /*XXX: see note above about there probably being some condition 851 /*XXX: see note above about there probably being some condition
852 * for the 10f824 stuff that uses ramcfg 3... 852 * for the 10f824 stuff that uses ramcfg 3...
853 */ 853 */
854 if ( (next->bios.ramcfg_11_03_f0)) { 854 if (next->bios.ramcfg_11_03_f0) {
855 if (next->bios.rammap_11_08_0c) { 855 if (next->bios.rammap_11_08_0c) {
856 if (!(next->bios.ramcfg_11_07_80)) 856 if (!next->bios.ramcfg_11_07_80)
857 mask |= 0x00000020; 857 mask |= 0x00000020;
858 else 858 else
859 data |= 0x00000020; 859 data |= 0x00000020;
@@ -876,7 +876,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
876 data = next->bios.timing_20_2c_1fc0; 876 data = next->bios.timing_20_2c_1fc0;
877 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 877 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
878 878
879 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8); 879 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
880 880
881 ram_wr32(fuc, 0x10f090, 0x4000007f); 881 ram_wr32(fuc, 0x10f090, 0x4000007f);
882 ram_nsec(fuc, 1000); 882 ram_nsec(fuc, 1000);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c
new file mode 100644
index 000000000000..fa891c39866b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c
@@ -0,0 +1,39 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "nv50.h"
26
27struct nouveau_oclass *
28gf117_i2c_oclass = &(struct nouveau_i2c_impl) {
29 .base.handle = NV_SUBDEV(I2C, 0xd7),
30 .base.ofuncs = &(struct nouveau_ofuncs) {
31 .ctor = _nouveau_i2c_ctor,
32 .dtor = _nouveau_i2c_dtor,
33 .init = _nouveau_i2c_init,
34 .fini = _nouveau_i2c_fini,
35 },
36 .sclass = nvd0_i2c_sclass,
37 .pad_x = &nv04_i2c_pad_oclass,
38 .pad_s = &nv04_i2c_pad_oclass,
39}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
index 7120124dceac..ebef970a0645 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
@@ -95,6 +95,23 @@ nve0_ibus_intr(struct nouveau_subdev *subdev)
95} 95}
96 96
97static int 97static int
98nve0_ibus_init(struct nouveau_object *object)
99{
100 struct nve0_ibus_priv *priv = (void *)object;
101 int ret = nouveau_ibus_init(&priv->base);
102 if (ret == 0) {
103 nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000);
104 nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200);
105 nv_mask(priv, 0x122310, 0x0003ffff, 0x00000800);
106 nv_mask(priv, 0x122348, 0x0003ffff, 0x00000100);
107 nv_mask(priv, 0x1223b0, 0x0003ffff, 0x00000fff);
108 nv_mask(priv, 0x122348, 0x0003ffff, 0x00000200);
109 nv_mask(priv, 0x122358, 0x0003ffff, 0x00002880);
110 }
111 return ret;
112}
113
114static int
98nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 115nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
99 struct nouveau_oclass *oclass, void *data, u32 size, 116 struct nouveau_oclass *oclass, void *data, u32 size,
100 struct nouveau_object **pobject) 117 struct nouveau_object **pobject)
@@ -117,7 +134,7 @@ nve0_ibus_oclass = {
117 .ofuncs = &(struct nouveau_ofuncs) { 134 .ofuncs = &(struct nouveau_ofuncs) {
118 .ctor = nve0_ibus_ctor, 135 .ctor = nve0_ibus_ctor,
119 .dtor = _nouveau_ibus_dtor, 136 .dtor = _nouveau_ibus_dtor,
120 .init = _nouveau_ibus_init, 137 .init = nve0_ibus_init,
121 .fini = _nouveau_ibus_fini, 138 .fini = _nouveau_ibus_fini,
122 }, 139 },
123}; 140};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
index 2284ecb1c9b8..c2bb616a8da5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
@@ -83,7 +83,7 @@ host_send:
83 // increment GET 83 // increment GET
84 add b32 $r1 0x1 84 add b32 $r1 0x1
85 and $r14 $r1 #fifo_qmaskf 85 and $r14 $r1 #fifo_qmaskf
86 nv_iowr(NV_PPWR_FIFO_GET(0), $r1) 86 nv_iowr(NV_PPWR_FIFO_GET(0), $r14)
87 bra #host_send 87 bra #host_send
88 host_send_done: 88 host_send_done:
89 ret 89 ret
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
index 4bd43a99fdcc..39a5dc150a05 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
@@ -1018,7 +1018,7 @@ uint32_t nv108_pwr_code[] = {
1018 0xb600023f, 1018 0xb600023f,
1019 0x1ec40110, 1019 0x1ec40110,
1020 0x04b0400f, 1020 0x04b0400f,
1021 0xbd0001f6, 1021 0xbd000ef6,
1022 0xc70ef404, 1022 0xc70ef404,
1023/* 0x0328: host_send_done */ 1023/* 0x0328: host_send_done */
1024/* 0x032a: host_recv */ 1024/* 0x032a: host_recv */
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
index 5a73fa620978..254205cd5166 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
@@ -1124,7 +1124,7 @@ uint32_t nva3_pwr_code[] = {
1124 0x0f1ec401, 1124 0x0f1ec401,
1125 0x04b007f1, 1125 0x04b007f1,
1126 0xd00604b6, 1126 0xd00604b6,
1127 0x04bd0001, 1127 0x04bd000e,
1128/* 0x03cb: host_send_done */ 1128/* 0x03cb: host_send_done */
1129 0xf8ba0ef4, 1129 0xf8ba0ef4,
1130/* 0x03cd: host_recv */ 1130/* 0x03cd: host_recv */
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
index 4dba00d2dd1a..7ac87405d01b 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
@@ -1124,7 +1124,7 @@ uint32_t nvc0_pwr_code[] = {
1124 0x0f1ec401, 1124 0x0f1ec401,
1125 0x04b007f1, 1125 0x04b007f1,
1126 0xd00604b6, 1126 0xd00604b6,
1127 0x04bd0001, 1127 0x04bd000e,
1128/* 0x03cb: host_send_done */ 1128/* 0x03cb: host_send_done */
1129 0xf8ba0ef4, 1129 0xf8ba0ef4,
1130/* 0x03cd: host_recv */ 1130/* 0x03cd: host_recv */
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
index 5e24c6bc041d..cd9ff1a73284 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
@@ -1033,7 +1033,7 @@ uint32_t nvd0_pwr_code[] = {
1033 0xb6026b21, 1033 0xb6026b21,
1034 0x1ec40110, 1034 0x1ec40110,
1035 0xb007f10f, 1035 0xb007f10f,
1036 0x0001d004, 1036 0x000ed004,
1037 0x0ef404bd, 1037 0x0ef404bd,
1038/* 0x0365: host_send_done */ 1038/* 0x0365: host_send_done */
1039/* 0x0367: host_recv */ 1039/* 0x0367: host_recv */
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 26b5647188ef..47ad74255bf1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -736,6 +736,9 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
736 fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y, 736 fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y,
737 new_bo->bo.offset }; 737 new_bo->bo.offset };
738 738
739 /* Keep vblanks on during flip, for the target crtc of this flip */
740 drm_vblank_get(dev, nouveau_crtc(crtc)->index);
741
739 /* Emit a page flip */ 742 /* Emit a page flip */
740 if (nv_device(drm->device)->card_type >= NV_50) { 743 if (nv_device(drm->device)->card_type >= NV_50) {
741 ret = nv50_display_flip_next(crtc, fb, chan, swap_interval); 744 ret = nv50_display_flip_next(crtc, fb, chan, swap_interval);
@@ -779,6 +782,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
779 return 0; 782 return 0;
780 783
781fail_unreserve: 784fail_unreserve:
785 drm_vblank_put(dev, nouveau_crtc(crtc)->index);
782 ttm_bo_unreserve(&old_bo->bo); 786 ttm_bo_unreserve(&old_bo->bo);
783fail_unpin: 787fail_unpin:
784 mutex_unlock(&chan->cli->mutex); 788 mutex_unlock(&chan->cli->mutex);
@@ -817,6 +821,9 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
817 drm_send_vblank_event(dev, crtcid, s->event); 821 drm_send_vblank_event(dev, crtcid, s->event);
818 } 822 }
819 823
824 /* Give up ownership of vblank for page-flipped crtc */
825 drm_vblank_put(dev, s->crtc);
826
820 list_del(&s->head); 827 list_del(&s->head);
821 if (ps) 828 if (ps)
822 *ps = *s; 829 *ps = *s;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 26c12a3fe430..a03c73411a56 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1052,7 +1052,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
1052 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1052 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1053 1053
1054 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ 1054 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1055 if (ASIC_IS_DCE5(rdev) && !ASIC_IS_DCE8(rdev) && 1055 if (ASIC_IS_DCE5(rdev) &&
1056 (encoder_mode == ATOM_ENCODER_MODE_HDMI) && 1056 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1057 (radeon_crtc->bpc > 8)) 1057 (radeon_crtc->bpc > 8))
1058 clock = radeon_crtc->adjusted_clock; 1058 clock = radeon_crtc->adjusted_clock;
@@ -1136,6 +1136,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1136 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1136 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1137 u32 tmp, viewport_w, viewport_h; 1137 u32 tmp, viewport_w, viewport_h;
1138 int r; 1138 int r;
1139 bool bypass_lut = false;
1139 1140
1140 /* no fb bound */ 1141 /* no fb bound */
1141 if (!atomic && !crtc->primary->fb) { 1142 if (!atomic && !crtc->primary->fb) {
@@ -1174,33 +1175,73 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1174 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1175 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1175 radeon_bo_unreserve(rbo); 1176 radeon_bo_unreserve(rbo);
1176 1177
1177 switch (target_fb->bits_per_pixel) { 1178 switch (target_fb->pixel_format) {
1178 case 8: 1179 case DRM_FORMAT_C8:
1179 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1180 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1180 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1181 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1181 break; 1182 break;
1182 case 15: 1183 case DRM_FORMAT_XRGB4444:
1184 case DRM_FORMAT_ARGB4444:
1185 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1186 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1187#ifdef __BIG_ENDIAN
1188 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1189#endif
1190 break;
1191 case DRM_FORMAT_XRGB1555:
1192 case DRM_FORMAT_ARGB1555:
1183 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1193 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1184 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1194 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1195#ifdef __BIG_ENDIAN
1196 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1197#endif
1198 break;
1199 case DRM_FORMAT_BGRX5551:
1200 case DRM_FORMAT_BGRA5551:
1201 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1202 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1203#ifdef __BIG_ENDIAN
1204 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1205#endif
1185 break; 1206 break;
1186 case 16: 1207 case DRM_FORMAT_RGB565:
1187 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1208 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1188 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1209 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1189#ifdef __BIG_ENDIAN 1210#ifdef __BIG_ENDIAN
1190 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1211 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1191#endif 1212#endif
1192 break; 1213 break;
1193 case 24: 1214 case DRM_FORMAT_XRGB8888:
1194 case 32: 1215 case DRM_FORMAT_ARGB8888:
1195 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1216 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1196 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1217 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1197#ifdef __BIG_ENDIAN 1218#ifdef __BIG_ENDIAN
1198 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1219 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1199#endif 1220#endif
1200 break; 1221 break;
1222 case DRM_FORMAT_XRGB2101010:
1223 case DRM_FORMAT_ARGB2101010:
1224 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1225 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1226#ifdef __BIG_ENDIAN
1227 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1228#endif
1229 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1230 bypass_lut = true;
1231 break;
1232 case DRM_FORMAT_BGRX1010102:
1233 case DRM_FORMAT_BGRA1010102:
1234 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1235 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1236#ifdef __BIG_ENDIAN
1237 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1238#endif
1239 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1240 bypass_lut = true;
1241 break;
1201 default: 1242 default:
1202 DRM_ERROR("Unsupported screen depth %d\n", 1243 DRM_ERROR("Unsupported screen format %s\n",
1203 target_fb->bits_per_pixel); 1244 drm_get_format_name(target_fb->pixel_format));
1204 return -EINVAL; 1245 return -EINVAL;
1205 } 1246 }
1206 1247
@@ -1329,6 +1370,18 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1329 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1370 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1330 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1371 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1331 1372
1373 /*
1374 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1375 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1376 * retain the full precision throughout the pipeline.
1377 */
1378 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1379 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1380 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1381
1382 if (bypass_lut)
1383 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1384
1332 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1385 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1333 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1386 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1334 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1387 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
@@ -1396,6 +1449,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1396 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1449 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1397 u32 tmp, viewport_w, viewport_h; 1450 u32 tmp, viewport_w, viewport_h;
1398 int r; 1451 int r;
1452 bool bypass_lut = false;
1399 1453
1400 /* no fb bound */ 1454 /* no fb bound */
1401 if (!atomic && !crtc->primary->fb) { 1455 if (!atomic && !crtc->primary->fb) {
@@ -1433,18 +1487,30 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1433 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1487 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1434 radeon_bo_unreserve(rbo); 1488 radeon_bo_unreserve(rbo);
1435 1489
1436 switch (target_fb->bits_per_pixel) { 1490 switch (target_fb->pixel_format) {
1437 case 8: 1491 case DRM_FORMAT_C8:
1438 fb_format = 1492 fb_format =
1439 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1493 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1440 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1494 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1441 break; 1495 break;
1442 case 15: 1496 case DRM_FORMAT_XRGB4444:
1497 case DRM_FORMAT_ARGB4444:
1498 fb_format =
1499 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1500 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1501#ifdef __BIG_ENDIAN
1502 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1503#endif
1504 break;
1505 case DRM_FORMAT_XRGB1555:
1443 fb_format = 1506 fb_format =
1444 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1507 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1445 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1508 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1509#ifdef __BIG_ENDIAN
1510 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1511#endif
1446 break; 1512 break;
1447 case 16: 1513 case DRM_FORMAT_RGB565:
1448 fb_format = 1514 fb_format =
1449 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1515 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1450 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1516 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
@@ -1452,8 +1518,8 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1452 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1518 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1453#endif 1519#endif
1454 break; 1520 break;
1455 case 24: 1521 case DRM_FORMAT_XRGB8888:
1456 case 32: 1522 case DRM_FORMAT_ARGB8888:
1457 fb_format = 1523 fb_format =
1458 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1524 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1459 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1525 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
@@ -1461,9 +1527,20 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1461 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1527 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1462#endif 1528#endif
1463 break; 1529 break;
1530 case DRM_FORMAT_XRGB2101010:
1531 case DRM_FORMAT_ARGB2101010:
1532 fb_format =
1533 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1534 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1535#ifdef __BIG_ENDIAN
1536 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1537#endif
1538 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1539 bypass_lut = true;
1540 break;
1464 default: 1541 default:
1465 DRM_ERROR("Unsupported screen depth %d\n", 1542 DRM_ERROR("Unsupported screen format %s\n",
1466 target_fb->bits_per_pixel); 1543 drm_get_format_name(target_fb->pixel_format));
1467 return -EINVAL; 1544 return -EINVAL;
1468 } 1545 }
1469 1546
@@ -1502,6 +1579,13 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1502 if (rdev->family >= CHIP_R600) 1579 if (rdev->family >= CHIP_R600)
1503 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1580 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1504 1581
1582 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1583 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1584 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1585
1586 if (bypass_lut)
1587 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1588
1505 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1589 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1506 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1590 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1507 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1591 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index a0f63ff5a5e9..333d143fca2c 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -116,6 +116,8 @@
116# define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 116# define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1
117# define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2 117# define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2
118# define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4 118# define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4
119#define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x6808
120# define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8)
119#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c 121#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c
120# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 122# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
121# define EVERGREEN_GRPH_ENDIAN_NONE 0 123# define EVERGREEN_GRPH_ENDIAN_NONE 0
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 1dd0d32993d5..136b7bc7cd20 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -402,6 +402,7 @@
402 * block and vice versa. This applies to GRPH, CUR, etc. 402 * block and vice versa. This applies to GRPH, CUR, etc.
403 */ 403 */
404#define AVIVO_D1GRPH_LUT_SEL 0x6108 404#define AVIVO_D1GRPH_LUT_SEL 0x6108
405# define AVIVO_LUT_10BIT_BYPASS_EN (1 << 8)
405#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 406#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
406#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 407#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
407#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 408#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 933c5c39654d..1b9177ed181f 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1288,17 +1288,15 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector,
1288 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1288 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1289 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) 1289 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
1290 return MODE_OK; 1290 return MODE_OK;
1291 else if (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_A) { 1291 else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) {
1292 if (ASIC_IS_DCE6(rdev)) { 1292 /* HDMI 1.3+ supports max clock of 340 Mhz */
1293 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1293 if (mode->clock > 340000)
1294 if (mode->clock > 340000)
1295 return MODE_CLOCK_HIGH;
1296 else
1297 return MODE_OK;
1298 } else
1299 return MODE_CLOCK_HIGH; 1294 return MODE_CLOCK_HIGH;
1300 } else 1295 else
1296 return MODE_OK;
1297 } else {
1301 return MODE_CLOCK_HIGH; 1298 return MODE_CLOCK_HIGH;
1299 }
1302 } 1300 }
1303 1301
1304 /* check against the max pixel clock */ 1302 /* check against the max pixel clock */
@@ -1549,6 +1547,8 @@ out:
1549static int radeon_dp_mode_valid(struct drm_connector *connector, 1547static int radeon_dp_mode_valid(struct drm_connector *connector,
1550 struct drm_display_mode *mode) 1548 struct drm_display_mode *mode)
1551{ 1549{
1550 struct drm_device *dev = connector->dev;
1551 struct radeon_device *rdev = dev->dev_private;
1552 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1552 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1553 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 1553 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1554 1554
@@ -1579,14 +1579,23 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
1579 return MODE_PANEL; 1579 return MODE_PANEL;
1580 } 1580 }
1581 } 1581 }
1582 return MODE_OK;
1583 } else { 1582 } else {
1584 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1583 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1585 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 1584 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1586 return radeon_dp_mode_valid_helper(connector, mode); 1585 return radeon_dp_mode_valid_helper(connector, mode);
1587 else 1586 } else {
1588 return MODE_OK; 1587 if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) {
1588 /* HDMI 1.3+ supports max clock of 340 Mhz */
1589 if (mode->clock > 340000)
1590 return MODE_CLOCK_HIGH;
1591 } else {
1592 if (mode->clock > 165000)
1593 return MODE_CLOCK_HIGH;
1594 }
1595 }
1589 } 1596 }
1597
1598 return MODE_OK;
1590} 1599}
1591 1600
1592static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = { 1601static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 5ed617056b9c..8fc362aa6a1a 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -66,7 +66,8 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
66 (radeon_crtc->lut_b[i] << 0)); 66 (radeon_crtc->lut_b[i] << 0));
67 } 67 }
68 68
69 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
70} 71}
71 72
72static void dce4_crtc_load_lut(struct drm_crtc *crtc) 73static void dce4_crtc_load_lut(struct drm_crtc *crtc)
@@ -357,8 +358,9 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
357 358
358 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 359 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
359 360
361 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
360 radeon_fence_unref(&work->fence); 362 radeon_fence_unref(&work->fence);
361 radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id); 363 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
362 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 364 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
363} 365}
364 366
@@ -459,6 +461,12 @@ static void radeon_flip_work_func(struct work_struct *__work)
459 base &= ~7; 461 base &= ~7;
460 } 462 }
461 463
464 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
465 if (r) {
466 DRM_ERROR("failed to get vblank before flip\n");
467 goto pflip_cleanup;
468 }
469
462 /* We borrow the event spin lock for protecting flip_work */ 470 /* We borrow the event spin lock for protecting flip_work */
463 spin_lock_irqsave(&crtc->dev->event_lock, flags); 471 spin_lock_irqsave(&crtc->dev->event_lock, flags);
464 472
@@ -473,6 +481,16 @@ static void radeon_flip_work_func(struct work_struct *__work)
473 481
474 return; 482 return;
475 483
484pflip_cleanup:
485 if (unlikely(radeon_bo_reserve(work->new_rbo, false) != 0)) {
486 DRM_ERROR("failed to reserve new rbo in error path\n");
487 goto cleanup;
488 }
489 if (unlikely(radeon_bo_unpin(work->new_rbo) != 0)) {
490 DRM_ERROR("failed to unpin new rbo in error path\n");
491 }
492 radeon_bo_unreserve(work->new_rbo);
493
476cleanup: 494cleanup:
477 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 495 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
478 radeon_fence_unref(&work->fence); 496 radeon_fence_unref(&work->fence);
diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c
index 5e0f6ff2e2f5..b33b00b386de 100644
--- a/drivers/tty/vt/vt.c
+++ b/drivers/tty/vt/vt.c
@@ -3226,8 +3226,7 @@ int do_unbind_con_driver(const struct consw *csw, int first, int last, int deflt
3226 for (i = 0; i < MAX_NR_CON_DRIVER; i++) { 3226 for (i = 0; i < MAX_NR_CON_DRIVER; i++) {
3227 con_back = &registered_con_driver[i]; 3227 con_back = &registered_con_driver[i];
3228 3228
3229 if (con_back->con && 3229 if (con_back->con && con_back->con != csw) {
3230 !(con_back->flag & CON_DRIVER_FLAG_MODULE)) {
3231 defcsw = con_back->con; 3230 defcsw = con_back->con;
3232 retval = 0; 3231 retval = 0;
3233 break; 3232 break;
@@ -3332,6 +3331,7 @@ static int vt_unbind(struct con_driver *con)
3332{ 3331{
3333 const struct consw *csw = NULL; 3332 const struct consw *csw = NULL;
3334 int i, more = 1, first = -1, last = -1, deflt = 0; 3333 int i, more = 1, first = -1, last = -1, deflt = 0;
3334 int ret;
3335 3335
3336 if (!con->con || !(con->flag & CON_DRIVER_FLAG_MODULE) || 3336 if (!con->con || !(con->flag & CON_DRIVER_FLAG_MODULE) ||
3337 con_is_graphics(con->con, con->first, con->last)) 3337 con_is_graphics(con->con, con->first, con->last))
@@ -3357,8 +3357,10 @@ static int vt_unbind(struct con_driver *con)
3357 3357
3358 if (first != -1) { 3358 if (first != -1) {
3359 console_lock(); 3359 console_lock();
3360 do_unbind_con_driver(csw, first, last, deflt); 3360 ret = do_unbind_con_driver(csw, first, last, deflt);
3361 console_unlock(); 3361 console_unlock();
3362 if (ret != 0)
3363 return ret;
3362 } 3364 }
3363 3365
3364 first = -1; 3366 first = -1;
@@ -3645,17 +3647,20 @@ err:
3645 */ 3647 */
3646int do_unregister_con_driver(const struct consw *csw) 3648int do_unregister_con_driver(const struct consw *csw)
3647{ 3649{
3648 int i, retval = -ENODEV; 3650 int i;
3649 3651
3650 /* cannot unregister a bound driver */ 3652 /* cannot unregister a bound driver */
3651 if (con_is_bound(csw)) 3653 if (con_is_bound(csw))
3652 goto err; 3654 return -EBUSY;
3655
3656 if (csw == conswitchp)
3657 return -EINVAL;
3653 3658
3654 for (i = 0; i < MAX_NR_CON_DRIVER; i++) { 3659 for (i = 0; i < MAX_NR_CON_DRIVER; i++) {
3655 struct con_driver *con_driver = &registered_con_driver[i]; 3660 struct con_driver *con_driver = &registered_con_driver[i];
3656 3661
3657 if (con_driver->con == csw && 3662 if (con_driver->con == csw &&
3658 con_driver->flag & CON_DRIVER_FLAG_MODULE) { 3663 con_driver->flag & CON_DRIVER_FLAG_INIT) {
3659 vtconsole_deinit_device(con_driver); 3664 vtconsole_deinit_device(con_driver);
3660 device_destroy(vtconsole_class, 3665 device_destroy(vtconsole_class,
3661 MKDEV(0, con_driver->node)); 3666 MKDEV(0, con_driver->node));
@@ -3666,12 +3671,11 @@ int do_unregister_con_driver(const struct consw *csw)
3666 con_driver->flag = 0; 3671 con_driver->flag = 0;
3667 con_driver->first = 0; 3672 con_driver->first = 0;
3668 con_driver->last = 0; 3673 con_driver->last = 0;
3669 retval = 0; 3674 return 0;
3670 break;
3671 } 3675 }
3672 } 3676 }
3673err: 3677
3674 return retval; 3678 return -ENODEV;
3675} 3679}
3676EXPORT_SYMBOL_GPL(do_unregister_con_driver); 3680EXPORT_SYMBOL_GPL(do_unregister_con_driver);
3677 3681
diff --git a/drivers/video/console/dummycon.c b/drivers/video/console/dummycon.c
index b63860f7beab..40bec8d64b0a 100644
--- a/drivers/video/console/dummycon.c
+++ b/drivers/video/console/dummycon.c
@@ -77,3 +77,4 @@ const struct consw dummy_con = {
77 .con_set_palette = DUMMY, 77 .con_set_palette = DUMMY,
78 .con_scrolldelta = DUMMY, 78 .con_scrolldelta = DUMMY,
79}; 79};
80EXPORT_SYMBOL_GPL(dummy_con);
diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c
index f267284b423b..6e6aa704fe84 100644
--- a/drivers/video/console/vgacon.c
+++ b/drivers/video/console/vgacon.c
@@ -1441,5 +1441,6 @@ const struct consw vga_con = {
1441 .con_build_attr = vgacon_build_attr, 1441 .con_build_attr = vgacon_build_attr,
1442 .con_invert_region = vgacon_invert_region, 1442 .con_invert_region = vgacon_invert_region,
1443}; 1443};
1444EXPORT_SYMBOL(vga_con);
1444 1445
1445MODULE_LICENSE("GPL"); 1446MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-03 04:28:33 -0500