7 files changed, 646 insertions, 5 deletions

diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt
new file mode 100644
index 000000000000..cfda0d57d302
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt
@@ -0,0 +1,29 @@
+Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver
+
+The Atmel HLCDC PWM is subdevice of the HLCDC MFD device.
+See ../mfd/atmel-hlcdc.txt for more details.
+
+Required properties:
+ - compatible: value should be one of the following:
+   "atmel,hlcdc-pwm"
+ - pinctr-names: the pin control state names. Should contain "default".
+ - pinctrl-0: should contain the pinctrl states described by pinctrl
+   default.
+ - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells
+   bindings defined in pwm.txt in this directory.
+
+Example:
+
+        hlcdc: hlcdc@f0030000 {
+                compatible = "atmel,sama5d3-hlcdc";
+                reg = <0xf0030000 0x2000>;
+                clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+                clock-names = "periph_clk","sys_clk", "slow_clk";
+
+                hlcdc_pwm: hlcdc-pwm {
+                        compatible = "atmel,hlcdc-pwm";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_lcd_pwm>;
+                        #pwm-cells = <3>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt
new file mode 100644
index 000000000000..fb6fb31bc4c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt
@@ -0,0 +1,30 @@
+BCM2835 PWM controller (Raspberry Pi controller)
+
+Required properties:
+- compatible: should be "brcm,bcm2835-pwm"
+- reg: physical base address and length of the controller's registers
+- clock: This clock defines the base clock frequency of the PWM hardware
+  system, the period and the duty_cycle of the PWM signal is a multiple of
+  the base period.
+- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of
+  the cells format.
+
+Examples:
+
+pwm@2020c000 {
+        compatible = "brcm,bcm2835-pwm";
+        reg = <0x2020c000 0x28>;
+        clocks = <&clk_pwm>;
+        #pwm-cells = <2>;
+};
+
+clocks {
+        ....
+                clk_pwm: pwm {
+                        compatible = "fixed-clock";
+                        reg = <3>;
+                        #clock-cells = <0>;
+                        clock-frequency = <9200000>;
+                };
+        ....
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index ef2dd2e4754b..a3ecf5809634 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -50,6 +50,17 @@ config PWM_ATMEL
           To compile this driver as a module, choose M here: the module
           will be called pwm-atmel.
 
+config PWM_ATMEL_HLCDC_PWM
+        tristate "Atmel HLCDC PWM support"
+        depends on MFD_ATMEL_HLCDC
+        help
+          Generic PWM framework driver for the PWM output of the HLCDC
+          (Atmel High-end LCD Controller). This PWM output is mainly used
+          to control the LCD backlight.
+
+          To compile this driver as a module, choose M here: the module
+          will be called pwm-atmel-hlcdc.
+
 config PWM_ATMEL_TCB
         tristate "Atmel TC Block PWM support"
         depends on ATMEL_TCLIB && OF
@@ -71,6 +82,15 @@ config PWM_BCM_KONA
           To compile this driver as a module, choose M here: the module
           will be called pwm-bcm-kona.
 
+config PWM_BCM2835
+        tristate "BCM2835 PWM support"
+        depends on ARCH_BCM2835
+        help
+          PWM framework driver for BCM2835 controller (Raspberry Pi)
+
+          To compile this driver as a module, choose M here: the module
+          will be called pwm-bcm2835.
+
 config PWM_BFIN
         tristate "Blackfin PWM support"
         depends on BFIN_GPTIMERS
@@ -235,7 +255,7 @@ config PWM_ROCKCHIP
 
 config PWM_SAMSUNG
         tristate "Samsung PWM support"
-        depends on PLAT_SAMSUNG
+        depends on PLAT_SAMSUNG || ARCH_EXYNOS
         help
           Generic PWM framework driver for Samsung.
 
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c458606c3755..65259ac1e8de 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -2,8 +2,10 @@ obj-$(CONFIG_PWM)		+= core.o
 obj-$(CONFIG_PWM_SYSFS)         += sysfs.o
 obj-$(CONFIG_PWM_AB8500)        += pwm-ab8500.o
 obj-$(CONFIG_PWM_ATMEL)         += pwm-atmel.o
+obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM)       += pwm-atmel-hlcdc.o
 obj-$(CONFIG_PWM_ATMEL_TCB)     += pwm-atmel-tcb.o
 obj-$(CONFIG_PWM_BCM_KONA)      += pwm-bcm-kona.o
+obj-$(CONFIG_PWM_BCM2835)       += pwm-bcm2835.o
 obj-$(CONFIG_PWM_BFIN)          += pwm-bfin.o
 obj-$(CONFIG_PWM_CLPS711X)      += pwm-clps711x.o
 obj-$(CONFIG_PWM_EP93XX)        += pwm-ep93xx.o
diff --git a/drivers/pwm/pwm-atmel-hlcdc.c b/drivers/pwm/pwm-atmel-hlcdc.c
new file mode 100644
index 000000000000..e7a785fadcdf
--- /dev/null
+++ b/drivers/pwm/pwm-atmel-hlcdc.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright (C) 2014 Free Electrons
+ * Copyright (C) 2014 Atmel
+ *
+ * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/atmel-hlcdc.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+
+#define ATMEL_HLCDC_PWMCVAL_MASK        GENMASK(15, 8)
+#define ATMEL_HLCDC_PWMCVAL(x)          (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
+#define ATMEL_HLCDC_PWMPOL              BIT(4)
+#define ATMEL_HLCDC_PWMPS_MASK          GENMASK(2, 0)
+#define ATMEL_HLCDC_PWMPS_MAX           0x6
+#define ATMEL_HLCDC_PWMPS(x)            ((x) & ATMEL_HLCDC_PWMPS_MASK)
+
+struct atmel_hlcdc_pwm_errata {
+        bool slow_clk_erratum;
+        bool div1_clk_erratum;
+};
+
+struct atmel_hlcdc_pwm {
+        struct pwm_chip chip;
+        struct atmel_hlcdc *hlcdc;
+        struct clk *cur_clk;
+        const struct atmel_hlcdc_pwm_errata *errata;
+};
+
+static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
+{
+        return container_of(chip, struct atmel_hlcdc_pwm, chip);
+}
+
+static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
+                                  struct pwm_device *pwm,
+                                  int duty_ns, int period_ns)
+{
+        struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
+        struct atmel_hlcdc *hlcdc = chip->hlcdc;
+        struct clk *new_clk = hlcdc->slow_clk;
+        u64 pwmcval = duty_ns * 256;
+        unsigned long clk_freq;
+        u64 clk_period_ns;
+        u32 pwmcfg;
+        int pres;
+
+        if (!chip->errata || !chip->errata->slow_clk_erratum) {
+                clk_freq = clk_get_rate(new_clk);
+                clk_period_ns = (u64)NSEC_PER_SEC * 256;
+                do_div(clk_period_ns, clk_freq);
+        }
+
+        /* Errata: cannot use slow clk on some IP revisions */
+        if ((chip->errata && chip->errata->slow_clk_erratum) ||
+            clk_period_ns > period_ns) {
+                new_clk = hlcdc->sys_clk;
+                clk_freq = clk_get_rate(new_clk);
+                clk_period_ns = (u64)NSEC_PER_SEC * 256;
+                do_div(clk_period_ns, clk_freq);
+        }
+
+        for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
+                /* Errata: cannot divide by 1 on some IP revisions */
+                if (!pres && chip->errata && chip->errata->div1_clk_erratum)
+                        continue;
+
+                if ((clk_period_ns << pres) >= period_ns)
+                        break;
+        }
+
+        if (pres > ATMEL_HLCDC_PWMPS_MAX)
+                return -EINVAL;
+
+        pwmcfg = ATMEL_HLCDC_PWMPS(pres);
+
+        if (new_clk != chip->cur_clk) {
+                u32 gencfg = 0;
+                int ret;
+
+                ret = clk_prepare_enable(new_clk);
+                if (ret)
+                        return ret;
+
+                clk_disable_unprepare(chip->cur_clk);
+                chip->cur_clk = new_clk;
+
+                if (new_clk == hlcdc->sys_clk)
+                        gencfg = ATMEL_HLCDC_CLKPWMSEL;
+
+                ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(0),
+                                         ATMEL_HLCDC_CLKPWMSEL, gencfg);
+                if (ret)
+                        return ret;
+        }
+
+        do_div(pwmcval, period_ns);
+
+        /*
+         * The PWM duty cycle is configurable from 0/256 to 255/256 of the
+         * period cycle. Hence we can't set a duty cycle occupying the
+         * whole period cycle if we're asked to.
+         * Set it to 255 if pwmcval is greater than 256.
+         */
+        if (pwmcval > 255)
+                pwmcval = 255;
+
+        pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
+
+        return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
+                                  ATMEL_HLCDC_PWMCVAL_MASK |
+                                  ATMEL_HLCDC_PWMPS_MASK,
+                                  pwmcfg);
+}
+
+static int atmel_hlcdc_pwm_set_polarity(struct pwm_chip *c,
+                                        struct pwm_device *pwm,
+                                        enum pwm_polarity polarity)
+{
+        struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
+        struct atmel_hlcdc *hlcdc = chip->hlcdc;
+        u32 cfg = 0;
+
+        if (polarity == PWM_POLARITY_NORMAL)
+                cfg = ATMEL_HLCDC_PWMPOL;
+
+        return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
+                                  ATMEL_HLCDC_PWMPOL, cfg);
+}
+
+static int atmel_hlcdc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
+{
+        struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
+        struct atmel_hlcdc *hlcdc = chip->hlcdc;
+        u32 status;
+        int ret;
+
+        ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PWM);
+        if (ret)
+                return ret;
+
+        while (true) {
+                ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
+                if (ret)
+                        return ret;
+
+                if ((status & ATMEL_HLCDC_PWM) != 0)
+                        break;
+
+                usleep_range(1, 10);
+        }
+
+        return 0;
+}
+
+static void atmel_hlcdc_pwm_disable(struct pwm_chip *c,
+                                    struct pwm_device *pwm)
+{
+        struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
+        struct atmel_hlcdc *hlcdc = chip->hlcdc;
+        u32 status;
+        int ret;
+
+        ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PWM);
+        if (ret)
+                return;
+
+        while (true) {
+                ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
+                if (ret)
+                        return;
+
+                if ((status & ATMEL_HLCDC_PWM) == 0)
+                        break;
+
+                usleep_range(1, 10);
+        }
+}
+
+static const struct pwm_ops atmel_hlcdc_pwm_ops = {
+        .config = atmel_hlcdc_pwm_config,
+        .set_polarity = atmel_hlcdc_pwm_set_polarity,
+        .enable = atmel_hlcdc_pwm_enable,
+        .disable = atmel_hlcdc_pwm_disable,
+        .owner = THIS_MODULE,
+};
+
+static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
+        .slow_clk_erratum = true,
+};
+
+static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
+        .div1_clk_erratum = true,
+};
+
+static const struct of_device_id atmel_hlcdc_dt_ids[] = {
+        {
+                .compatible = "atmel,at91sam9x5-hlcdc",
+                .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
+        },
+        {
+                .compatible = "atmel,sama5d3-hlcdc",
+                .data = &atmel_hlcdc_pwm_sama5d3_errata,
+        },
+        { /* sentinel */ },
+};
+
+static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *match;
+        struct device *dev = &pdev->dev;
+        struct atmel_hlcdc_pwm *chip;
+        struct atmel_hlcdc *hlcdc;
+        int ret;
+
+        hlcdc = dev_get_drvdata(dev->parent);
+
+        chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+        if (!chip)
+                return -ENOMEM;
+
+        ret = clk_prepare_enable(hlcdc->periph_clk);
+        if (ret)
+                return ret;
+
+        match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
+        if (match)
+                chip->errata = match->data;
+
+        chip->hlcdc = hlcdc;
+        chip->chip.ops = &atmel_hlcdc_pwm_ops;
+        chip->chip.dev = dev;
+        chip->chip.base = -1;
+        chip->chip.npwm = 1;
+        chip->chip.of_xlate = of_pwm_xlate_with_flags;
+        chip->chip.of_pwm_n_cells = 3;
+        chip->chip.can_sleep = 1;
+
+        ret = pwmchip_add(&chip->chip);
+        if (ret) {
+                clk_disable_unprepare(hlcdc->periph_clk);
+                return ret;
+        }
+
+        platform_set_drvdata(pdev, chip);
+
+        return 0;
+}
+
+static int atmel_hlcdc_pwm_remove(struct platform_device *pdev)
+{
+        struct atmel_hlcdc_pwm *chip = platform_get_drvdata(pdev);
+        int ret;
+
+        ret = pwmchip_remove(&chip->chip);
+        if (ret)
+                return ret;
+
+        clk_disable_unprepare(chip->hlcdc->periph_clk);
+
+        return 0;
+}
+
+static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
+        { .compatible = "atmel,hlcdc-pwm" },
+        { /* sentinel */ },
+};
+
+static struct platform_driver atmel_hlcdc_pwm_driver = {
+        .driver = {
+                .name = "atmel-hlcdc-pwm",
+                .of_match_table = atmel_hlcdc_pwm_dt_ids,
+        },
+        .probe = atmel_hlcdc_pwm_probe,
+        .remove = atmel_hlcdc_pwm_remove,
+};
+module_platform_driver(atmel_hlcdc_pwm_driver);
+
+MODULE_ALIAS("platform:atmel-hlcdc-pwm");
+MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
+MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pwm/pwm-bcm2835.c b/drivers/pwm/pwm-bcm2835.c
new file mode 100644
index 000000000000..b4c7f956b6fa
--- /dev/null
+++ b/drivers/pwm/pwm-bcm2835.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+
+#define PWM_CONTROL             0x000
+#define PWM_CONTROL_SHIFT(x)    ((x) * 8)
+#define PWM_CONTROL_MASK        0xff
+#define PWM_MODE                0x80            /* set timer in PWM mode */
+#define PWM_ENABLE              (1 << 0)
+#define PWM_POLARITY            (1 << 4)
+
+#define PERIOD(x)               (((x) * 0x10) + 0x10)
+#define DUTY(x)                 (((x) * 0x10) + 0x14)
+
+#define MIN_PERIOD              108             /* 9.2 MHz max. PWM clock */
+
+struct bcm2835_pwm {
+        struct pwm_chip chip;
+        struct device *dev;
+        unsigned long scaler;
+        void __iomem *base;
+        struct clk *clk;
+};
+
+static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
+{
+        return container_of(chip, struct bcm2835_pwm, chip);
+}
+
+static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+        struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
+        u32 value;
+
+        value = readl(pc->base + PWM_CONTROL);
+        value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
+        value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
+        writel(value, pc->base + PWM_CONTROL);
+
+        return 0;
+}
+
+static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+        struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
+        u32 value;
+
+        value = readl(pc->base + PWM_CONTROL);
+        value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
+        writel(value, pc->base + PWM_CONTROL);
+}
+
+static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+                              int duty_ns, int period_ns)
+{
+        struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
+
+        if (period_ns <= MIN_PERIOD) {
+                dev_err(pc->dev, "period %d not supported, minimum %d\n",
+                        period_ns, MIN_PERIOD);
+                return -EINVAL;
+        }
+
+        writel(duty_ns / pc->scaler, pc->base + DUTY(pwm->hwpwm));
+        writel(period_ns / pc->scaler, pc->base + PERIOD(pwm->hwpwm));
+
+        return 0;
+}
+
+static int bcm2835_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+        struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
+        u32 value;
+
+        value = readl(pc->base + PWM_CONTROL);
+        value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
+        writel(value, pc->base + PWM_CONTROL);
+
+        return 0;
+}
+
+static void bcm2835_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+        struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
+        u32 value;
+
+        value = readl(pc->base + PWM_CONTROL);
+        value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
+        writel(value, pc->base + PWM_CONTROL);
+}
+
+static int bcm2835_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
+                                enum pwm_polarity polarity)
+{
+        struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
+        u32 value;
+
+        value = readl(pc->base + PWM_CONTROL);
+
+        if (polarity == PWM_POLARITY_NORMAL)
+                value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
+        else
+                value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
+
+        writel(value, pc->base + PWM_CONTROL);
+
+        return 0;
+}
+
+static const struct pwm_ops bcm2835_pwm_ops = {
+        .request = bcm2835_pwm_request,
+        .free = bcm2835_pwm_free,
+        .config = bcm2835_pwm_config,
+        .enable = bcm2835_pwm_enable,
+        .disable = bcm2835_pwm_disable,
+        .set_polarity = bcm2835_set_polarity,
+        .owner = THIS_MODULE,
+};
+
+static int bcm2835_pwm_probe(struct platform_device *pdev)
+{
+        struct bcm2835_pwm *pc;
+        struct resource *res;
+        int ret;
+
+        pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
+        if (!pc)
+                return -ENOMEM;
+
+        pc->dev = &pdev->dev;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        pc->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(pc->base))
+                return PTR_ERR(pc->base);
+
+        pc->clk = devm_clk_get(&pdev->dev, NULL);
+        if (IS_ERR(pc->clk)) {
+                dev_err(&pdev->dev, "clock not found: %ld\n", PTR_ERR(pc->clk));
+                return PTR_ERR(pc->clk);
+        }
+
+        ret = clk_prepare_enable(pc->clk);
+        if (ret)
+                return ret;
+
+        pc->scaler = NSEC_PER_SEC / clk_get_rate(pc->clk);
+
+        pc->chip.dev = &pdev->dev;
+        pc->chip.ops = &bcm2835_pwm_ops;
+        pc->chip.npwm = 2;
+
+        platform_set_drvdata(pdev, pc);
+
+        ret = pwmchip_add(&pc->chip);
+        if (ret < 0)
+                goto add_fail;
+
+        return 0;
+
+add_fail:
+        clk_disable_unprepare(pc->clk);
+        return ret;
+}
+
+static int bcm2835_pwm_remove(struct platform_device *pdev)
+{
+        struct bcm2835_pwm *pc = platform_get_drvdata(pdev);
+
+        clk_disable_unprepare(pc->clk);
+
+        return pwmchip_remove(&pc->chip);
+}
+
+static const struct of_device_id bcm2835_pwm_of_match[] = {
+        { .compatible = "brcm,bcm2835-pwm", },
+        { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
+
+static struct platform_driver bcm2835_pwm_driver = {
+        .driver = {
+                .name = "bcm2835-pwm",
+                .of_match_table = bcm2835_pwm_of_match,
+        },
+        .probe = bcm2835_pwm_probe,
+        .remove = bcm2835_pwm_remove,
+};
+module_platform_driver(bcm2835_pwm_driver);
+
+MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be");
+MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index 0f2cc7ef7784..f9dfc8b6407a 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -17,6 +17,7 @@
 #include <linux/mutex.h>
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
+#include <linux/pm.h>
 #include <linux/pwm.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
@@ -299,7 +300,7 @@ static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
 {
         int ret;
 
-        if (fpc->use_count != 0)
+        if (fpc->use_count++ != 0)
                 return 0;
 
         /* select counter clock source */
@@ -316,8 +317,6 @@ static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
                 return ret;
         }
 
-        fpc->use_count++;
-
         return 0;
 }
 
@@ -399,12 +398,23 @@ static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
         return 0;
 }
 
+static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
+{
+        switch (reg) {
+        case FTM_CNT:
+                return true;
+        }
+        return false;
+}
+
 static const struct regmap_config fsl_pwm_regmap_config = {
         .reg_bits = 32,
         .reg_stride = 4,
         .val_bits = 32,
 
         .max_register = FTM_PWMLOAD,
+        .volatile_reg = fsl_pwm_volatile_reg,
+        .cache_type = REGCACHE_RBTREE,
 };
 
 static int fsl_pwm_probe(struct platform_device *pdev)
@@ -427,7 +437,7 @@ static int fsl_pwm_probe(struct platform_device *pdev)
         if (IS_ERR(base))
                 return PTR_ERR(base);
 
-        fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
+        fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
                                                 &fsl_pwm_regmap_config);
         if (IS_ERR(fpc->regmap)) {
                 dev_err(&pdev->dev, "regmap init failed\n");
@@ -478,6 +488,51 @@ static int fsl_pwm_remove(struct platform_device *pdev)
         return pwmchip_remove(&fpc->chip);
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int fsl_pwm_suspend(struct device *dev)
+{
+        struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
+        u32 val;
+
+        regcache_cache_only(fpc->regmap, true);
+        regcache_mark_dirty(fpc->regmap);
+
+        /* read from cache */
+        regmap_read(fpc->regmap, FTM_OUTMASK, &val);
+        if ((val & 0xFF) != 0xFF) {
+                clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
+                clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
+                clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);
+        }
+
+        return 0;
+}
+
+static int fsl_pwm_resume(struct device *dev)
+{
+        struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
+        u32 val;
+
+        /* read from cache */
+        regmap_read(fpc->regmap, FTM_OUTMASK, &val);
+        if ((val & 0xFF) != 0xFF) {
+                clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);
+                clk_prepare_enable(fpc->clk[fpc->cnt_select]);
+                clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
+        }
+
+        /* restore all registers from cache */
+        regcache_cache_only(fpc->regmap, false);
+        regcache_sync(fpc->regmap);
+
+        return 0;
+}
+#endif
+
+static const struct dev_pm_ops fsl_pwm_pm_ops = {
+        SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
+};
+
 static const struct of_device_id fsl_pwm_dt_ids[] = {
         { .compatible = "fsl,vf610-ftm-pwm", },
         { /* sentinel */ }
@@ -488,6 +543,7 @@ static struct platform_driver fsl_pwm_driver = {
         .driver = {
                 .name = "fsl-ftm-pwm",
                 .of_match_table = fsl_pwm_dt_ids,
+                .pm = &fsl_pwm_pm_ops,
         },
         .probe = fsl_pwm_probe,
         .remove = fsl_pwm_remove,