2 files changed, 57 insertions, 31 deletions

diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 045e6db6f58a..4924f4be2b99 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -368,36 +368,58 @@
 #define THERM_LOG_THRESHOLD1           (1 << 9)
 
 /* MISC_ENABLE bits: architectural */
-#define MSR_BIT_FAST_STRING                             0
-#define MSR_IA32_MISC_ENABLE_FAST_STRING        (1ULL << MSR_BIT_FAST_STRING)
-#define MSR_IA32_MISC_ENABLE_TCC                (1ULL << 1)
-#define MSR_IA32_MISC_ENABLE_EMON               (1ULL << 7)
-#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL        (1ULL << 11)
-#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL       (1ULL << 12)
-#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
-#define MSR_IA32_MISC_ENABLE_MWAIT              (1ULL << 18)
-#define MSR_BIT_LIMIT_CPUID                             22
-#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID        (1ULL << MSR_BIT_LIMIT_CPUID);
-#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE       (1ULL << 23)
-#define MSR_IA32_MISC_ENABLE_XD_DISABLE         (1ULL << 34)
+#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT            0
+#define MSR_IA32_MISC_ENABLE_FAST_STRING                (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
+#define MSR_IA32_MISC_ENABLE_TCC_BIT                    1
+#define MSR_IA32_MISC_ENABLE_TCC                        (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
+#define MSR_IA32_MISC_ENABLE_EMON_BIT                   7
+#define MSR_IA32_MISC_ENABLE_EMON                       (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
+#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT            11
+#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL                (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
+#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT           12
+#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL               (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
+#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT     16
+#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP         (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
+#define MSR_IA32_MISC_ENABLE_MWAIT_BIT                  18
+#define MSR_IA32_MISC_ENABLE_MWAIT                      (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
+#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT            22
+#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID                (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT);
+#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT           23
+#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE               (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
+#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT             34
+#define MSR_IA32_MISC_ENABLE_XD_DISABLE                 (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
 
 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
-#define MSR_IA32_MISC_ENABLE_X87_COMPAT         (1ULL << 2)
-#define MSR_IA32_MISC_ENABLE_TM1                (1ULL << 3)
-#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
-#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE    (1ULL << 6)
-#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK      (1ULL << 8)
-#define MSR_BIT_PRF_DIS                         9
-#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE   (1ULL << MSR_BIT_PRF_DIS)
-#define MSR_IA32_MISC_ENABLE_FERR               (1ULL << 10)
-#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX     (1ULL << 10)
-#define MSR_IA32_MISC_ENABLE_TM2                (1ULL << 13)
-#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE   (1ULL << 19)
-#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK     (1ULL << 20)
-#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT        (1ULL << 24)
-#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE   (1ULL << 37)
-#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE      (1ULL << 38)
-#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE    (1ULL << 39)
+#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT             2
+#define MSR_IA32_MISC_ENABLE_X87_COMPAT                 (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
+#define MSR_IA32_MISC_ENABLE_TM1_BIT                    3
+#define MSR_IA32_MISC_ENABLE_TM1                        (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
+#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT     4
+#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE         (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
+#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT        6
+#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE            (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
+#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT          8
+#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK              (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
+#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT       9
+#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE           (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
+#define MSR_IA32_MISC_ENABLE_FERR_BIT                   10
+#define MSR_IA32_MISC_ENABLE_FERR                       (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
+#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT         10
+#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX             (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
+#define MSR_IA32_MISC_ENABLE_TM2_BIT                    13
+#define MSR_IA32_MISC_ENABLE_TM2                        (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
+#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT       19
+#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE           (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
+#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT         20
+#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK             (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
+#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT            24
+#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT                (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
+#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT       37
+#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE           (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
+#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT          38
+#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE              (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
+#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT        39
+#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE            (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
 
 #define MSR_IA32_TSC_DEADLINE           0x000006E0
 
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 44ca6317af43..34bbb555e269 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -31,7 +31,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 
         /* Unmask CPUID levels if masked: */
         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
-                if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_LIMIT_CPUID) > 0) {
+                if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
+                                  MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
                         c->cpuid_level = cpuid_eax(0);
                         get_cpu_cap(c);
                 }
@@ -126,7 +127,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
          * (model 2) with the same problem.
          */
         if (c->x86 == 15)
-                if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_FAST_STRING) > 0)
+                if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
+                                  MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
                         pr_info("kmemcheck: Disabling fast string operations\n");
 #endif
 
@@ -216,7 +218,9 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
          * Hardware prefetcher may cause stale data to be loaded into the cache.
          */
         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
-                if (msr_set_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_PRF_DIS) > 0) {
+                if (msr_set_bit(MSR_IA32_MISC_ENABLE,
+                                MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
+                    > 0) {
                         pr_info("CPU: C0 stepping P4 Xeon detected.\n");
                         pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
                 }