diff options
| -rw-r--r-- | drivers/infiniband/hw/nes/nes.c | 1 | ||||
| -rw-r--r-- | drivers/infiniband/hw/nes/nes.h | 5 | ||||
| -rw-r--r-- | drivers/infiniband/hw/nes/nes_hw.c | 396 | ||||
| -rw-r--r-- | drivers/infiniband/hw/nes/nes_hw.h | 2 | ||||
| -rw-r--r-- | drivers/infiniband/hw/nes/nes_nic.c | 57 |
5 files changed, 243 insertions, 218 deletions
diff --git a/drivers/infiniband/hw/nes/nes.c b/drivers/infiniband/hw/nes/nes.c index b9d09bafd6c1..4272c52e38a4 100644 --- a/drivers/infiniband/hw/nes/nes.c +++ b/drivers/infiniband/hw/nes/nes.c | |||
| @@ -110,6 +110,7 @@ static unsigned int sysfs_idx_addr; | |||
| 110 | 110 | ||
| 111 | static struct pci_device_id nes_pci_table[] = { | 111 | static struct pci_device_id nes_pci_table[] = { |
| 112 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020, PCI_ANY_ID, PCI_ANY_ID}, | 112 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020, PCI_ANY_ID, PCI_ANY_ID}, |
| 113 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020_KR, PCI_ANY_ID, PCI_ANY_ID}, | ||
| 113 | {0} | 114 | {0} |
| 114 | }; | 115 | }; |
| 115 | 116 | ||
diff --git a/drivers/infiniband/hw/nes/nes.h b/drivers/infiniband/hw/nes/nes.h index cffdac4a899f..cc78fee1dd51 100644 --- a/drivers/infiniband/hw/nes/nes.h +++ b/drivers/infiniband/hw/nes/nes.h | |||
| @@ -64,8 +64,9 @@ | |||
| 64 | * NetEffect PCI vendor id and NE010 PCI device id. | 64 | * NetEffect PCI vendor id and NE010 PCI device id. |
| 65 | */ | 65 | */ |
| 66 | #ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */ | 66 | #ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */ |
| 67 | #define PCI_VENDOR_ID_NETEFFECT 0x1678 | 67 | #define PCI_VENDOR_ID_NETEFFECT 0x1678 |
| 68 | #define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100 | 68 | #define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100 |
| 69 | #define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110 | ||
| 69 | #endif | 70 | #endif |
| 70 | 71 | ||
| 71 | #define NE020_REV 4 | 72 | #define NE020_REV 4 |
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c index 310cc7cab396..ce7f53833577 100644 --- a/drivers/infiniband/hw/nes/nes_hw.c +++ b/drivers/infiniband/hw/nes/nes_hw.c | |||
| @@ -748,16 +748,28 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, | |||
| 748 | 748 | ||
| 749 | if (hw_rev != NE020_REV) { | 749 | if (hw_rev != NE020_REV) { |
| 750 | /* init serdes 0 */ | 750 | /* init serdes 0 */ |
| 751 | if (wide_ppm_offset && (nesadapter->phy_type[0] == NES_PHY_TYPE_CX4)) | 751 | switch (nesadapter->phy_type[0]) { |
| 752 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA); | 752 | case NES_PHY_TYPE_CX4: |
| 753 | else | 753 | if (wide_ppm_offset) |
| 754 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA); | ||
| 755 | else | ||
| 756 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
| 757 | break; | ||
| 758 | case NES_PHY_TYPE_KR: | ||
| 759 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
| 760 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000); | ||
| 761 | break; | ||
| 762 | case NES_PHY_TYPE_PUMA_1G: | ||
| 754 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | 763 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); |
| 755 | |||
| 756 | if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) { | ||
| 757 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); | 764 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); |
| 758 | sds |= 0x00000100; | 765 | sds |= 0x00000100; |
| 759 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds); | 766 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds); |
| 767 | break; | ||
| 768 | default: | ||
| 769 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
| 770 | break; | ||
| 760 | } | 771 | } |
| 772 | |||
| 761 | if (!OneG_Mode) | 773 | if (!OneG_Mode) |
| 762 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000); | 774 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000); |
| 763 | 775 | ||
| @@ -778,6 +790,9 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, | |||
| 778 | if (wide_ppm_offset) | 790 | if (wide_ppm_offset) |
| 779 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA); | 791 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA); |
| 780 | break; | 792 | break; |
| 793 | case NES_PHY_TYPE_KR: | ||
| 794 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000); | ||
| 795 | break; | ||
| 781 | case NES_PHY_TYPE_PUMA_1G: | 796 | case NES_PHY_TYPE_PUMA_1G: |
| 782 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1); | 797 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1); |
| 783 | sds |= 0x000000100; | 798 | sds |= 0x000000100; |
| @@ -1279,115 +1294,115 @@ int nes_destroy_cqp(struct nes_device *nesdev) | |||
| 1279 | 1294 | ||
| 1280 | 1295 | ||
| 1281 | /** | 1296 | /** |
| 1282 | * nes_init_phy | 1297 | * nes_init_1g_phy |
| 1283 | */ | 1298 | */ |
| 1284 | int nes_init_phy(struct nes_device *nesdev) | 1299 | int nes_init_1g_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index) |
| 1285 | { | 1300 | { |
| 1286 | struct nes_adapter *nesadapter = nesdev->nesadapter; | ||
| 1287 | u32 counter = 0; | 1301 | u32 counter = 0; |
| 1288 | u32 sds; | ||
| 1289 | u32 mac_index = nesdev->mac_index; | ||
| 1290 | u32 tx_config = 0; | ||
| 1291 | u16 phy_data; | 1302 | u16 phy_data; |
| 1292 | u32 temp_phy_data = 0; | 1303 | int ret = 0; |
| 1293 | u32 temp_phy_data2 = 0; | ||
| 1294 | u8 phy_type = nesadapter->phy_type[mac_index]; | ||
| 1295 | u8 phy_index = nesadapter->phy_index[mac_index]; | ||
| 1296 | |||
| 1297 | if ((nesadapter->OneG_Mode) && | ||
| 1298 | (phy_type != NES_PHY_TYPE_PUMA_1G)) { | ||
| 1299 | nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index); | ||
| 1300 | if (phy_type == NES_PHY_TYPE_1G) { | ||
| 1301 | tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); | ||
| 1302 | tx_config &= 0xFFFFFFE3; | ||
| 1303 | tx_config |= 0x04; | ||
| 1304 | nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); | ||
| 1305 | } | ||
| 1306 | |||
| 1307 | nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data); | ||
| 1308 | nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000); | ||
| 1309 | 1304 | ||
| 1310 | /* Reset the PHY */ | 1305 | nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data); |
| 1311 | nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000); | 1306 | nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000); |
| 1312 | udelay(100); | ||
| 1313 | counter = 0; | ||
| 1314 | do { | ||
| 1315 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
| 1316 | if (counter++ > 100) | ||
| 1317 | break; | ||
| 1318 | } while (phy_data & 0x8000); | ||
| 1319 | 1307 | ||
| 1320 | /* Setting no phy loopback */ | 1308 | /* Reset the PHY */ |
| 1321 | phy_data &= 0xbfff; | 1309 | nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000); |
| 1322 | phy_data |= 0x1140; | 1310 | udelay(100); |
| 1323 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data); | 1311 | counter = 0; |
| 1312 | do { | ||
| 1324 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | 1313 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); |
| 1325 | nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data); | 1314 | if (counter++ > 100) { |
| 1326 | nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data); | 1315 | ret = -1; |
| 1327 | 1316 | break; | |
| 1328 | /* Setting the interrupt mask */ | 1317 | } |
| 1329 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | 1318 | } while (phy_data & 0x8000); |
| 1330 | nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee); | 1319 | |
| 1331 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | 1320 | /* Setting no phy loopback */ |
| 1321 | phy_data &= 0xbfff; | ||
| 1322 | phy_data |= 0x1140; | ||
| 1323 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data); | ||
| 1324 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
| 1325 | nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data); | ||
| 1326 | nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data); | ||
| 1327 | |||
| 1328 | /* Setting the interrupt mask */ | ||
| 1329 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | ||
| 1330 | nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee); | ||
| 1331 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | ||
| 1332 | |||
| 1333 | /* turning on flow control */ | ||
| 1334 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
| 1335 | nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00); | ||
| 1336 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
| 1337 | |||
| 1338 | /* Clear Half duplex */ | ||
| 1339 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | ||
| 1340 | nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100)); | ||
| 1341 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | ||
| 1342 | |||
| 1343 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
| 1344 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300); | ||
| 1345 | |||
| 1346 | return ret; | ||
| 1347 | } | ||
| 1332 | 1348 | ||
| 1333 | /* turning on flow control */ | ||
| 1334 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
