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-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h72
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h284
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h147
-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h166
-rw-r--r--include/asm-blackfin/mach-bf548/dma.h63
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h306
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h189
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h97
8 files changed, 1324 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
new file mode 100644
index 000000000000..ddc150e6fb0f
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -0,0 +1,72 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf548/anomaly.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING.
29 * If not, write to the Free Software Foundation,
30 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 */
32
33#ifndef _MACH_ANOMALY_H_
34#define _MACH_ANOMALY_H_
35#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
36 slot1 and store of a P register in slot 2 is not
37 supported */
38#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
39 Channel DMA stops */
40#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
41 registers. */
42#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
43 Shadow of a Conditional Branch */
44#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
45 interrupt not functional */
46#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
47 SPORT external receive and transmit clocks. */
48#define ANOMALY_05000272 /* Certain data cache write through modes fail for
49 VDDint <=0.9V */
50#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
51 Boundary of Reserved Memory */
52#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
53 LC Registers Are Interrupted */
54#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
55#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
56#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
57 the USB FIFO Simultaneously */
58#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
59 function */
60#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
61 */
62#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
63#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
64 Skew */
65#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
66#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
67 of Host DMA Port */
68#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
69 Allowed Configuration on Host DMA Port */
70#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
71
72#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
new file mode 100644
index 000000000000..0b211020443d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -0,0 +1,284 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/bf548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: System MMR register and memory map for ADSP-BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF548_H__
31#define __MACH_BF548_H__
32
33/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
34
35#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
36#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
37#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
38#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
39#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
40#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | \
41 RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
42
43#define OFFSET_(x) ((x) & 0x0000FFFF)
44
45/*some misc defines*/
46#define IMASK_IVG15 0x8000
47#define IMASK_IVG14 0x4000
48#define IMASK_IVG13 0x2000
49#define IMASK_IVG12 0x1000
50
51#define IMASK_IVG11 0x0800
52#define IMASK_IVG10 0x0400
53#define IMASK_IVG9 0x0200
54#define IMASK_IVG8 0x0100
55
56#define IMASK_IVG7 0x0080
57#define IMASK_IVGTMR 0x0040
58#define IMASK_IVGHW 0x0020
59
60/***************************/
61
62
63#define BLKFIN_DSUBBANKS 4
64#define BLKFIN_DWAYS 2
65#define BLKFIN_DLINES 64
66#define BLKFIN_ISUBBANKS 4
67#define BLKFIN_IWAYS 4
68#define BLKFIN_ILINES 32
69
70#define WAY0_L 0x1
71#define WAY1_L 0x2
72#define WAY01_L 0x3
73#define WAY2_L 0x4
74#define WAY02_L 0x5
75#define WAY12_L 0x6
76#define WAY012_L 0x7
77
78#define WAY3_L 0x8
79#define WAY03_L 0x9
80#define WAY13_L 0xA
81#define WAY013_L 0xB
82
83#define WAY32_L 0xC
84#define WAY320_L 0xD
85#define WAY321_L 0xE
86#define WAYALL_L 0xF
87
88#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
89
90/********************************* EBIU Settings ************************************/
91#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
92#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
93
94#ifdef CONFIG_C_AMBEN_ALL
95#define V_AMBEN AMBEN_ALL
96#endif
97#ifdef CONFIG_C_AMBEN
98#define V_AMBEN 0x0
99#endif
100#ifdef CONFIG_C_AMBEN_B0
101#define V_AMBEN AMBEN_B0
102#endif
103#ifdef CONFIG_C_AMBEN_B0_B1
104#define V_AMBEN AMBEN_B0_B1
105#endif
106#ifdef CONFIG_C_AMBEN_B0_B1_B2
107#define V_AMBEN AMBEN_B0_B1_B2
108#endif
109#ifdef CONFIG_C_AMCKEN
110#define V_AMCKEN AMCKEN
111#else
112#define V_AMCKEN 0x0
113#endif
114#ifdef CONFIG_C_CDPRIO
115#define V_CDPRIO 0x100
116#else
117#define V_CDPRIO 0x0
118#endif
119
120#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
121
122#define MAX_VC 650000000
123#define MIN_VC 50000000
124
125/********************************PLL Settings **************************************/
126#ifdef CONFIG_BFIN_KERNEL_CLOCK
127#if (CONFIG_VCO_MULT < 0)
128#error "VCO Multiplier is less than 0. Please select a different value"
129#endif
130
131#if (CONFIG_VCO_MULT == 0)
132#error "VCO Multiplier should be greater than 0. Please select a different value"
133#endif
134
135#if (CONFIG_VCO_MULT > 64)
136#error "VCO Multiplier is more than 64. Please select a different value"
137#endif
138
139#ifndef CONFIG_CLKIN_HALF
140#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
141#else
142#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
143#endif
144
145#ifndef CONFIG_PLL_BYPASS
146#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
147#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
148#else
149#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
150#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
151#endif
152
153#if (CONFIG_SCLK_DIV < 1)
154#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
155#endif
156
157#if (CONFIG_SCLK_DIV > 15)
158#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
159#endif
160
161#if (CONFIG_CCLK_DIV != 1)
162#if (CONFIG_CCLK_DIV != 2)
163#if (CONFIG_CCLK_DIV != 4)
164#if (CONFIG_CCLK_DIV != 8)
165#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
166#endif
167#endif
168#endif
169#endif
170
171#if (CONFIG_VCO_HZ > MAX_VC)
172#error "VCO selected is more than maximum value. Please change the VCO multipler"
173#endif
174
175#if (CONFIG_SCLK_HZ > 133000000)
176#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
177#endif
178
179#if (CONFIG_SCLK_HZ < 27000000)
180#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
181#endif
182
183#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
184#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
185#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
186#error "Please select sclk less than cclk"
187#endif
188#endif
189#endif
190
191#if (CONFIG_CCLK_DIV == 1)
192#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
193#endif
194#if (CONFIG_CCLK_DIV == 2)
195#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
196#endif
197#if (CONFIG_CCLK_DIV == 4)
198#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
199#endif
200#if (CONFIG_CCLK_DIV == 8)
201#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
202#endif
203#ifndef CONFIG_CCLK_ACT_DIV
204#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
205#endif
206
207#endif /* CONFIG_BFIN_KERNEL_CLOCK */
208
209#ifdef CONFIG_BF542
210#define CPU "BF542"
211#define CPUID 0x027c8000
212#endif
213#ifdef CONFIG_BF544
214#define CPU "BF544"
215#define CPUID 0x027c8000
216#endif
217#ifdef CONFIG_BF548
218#define CPU "BF548"
219#define CPUID 0x027c6000
220#endif
221#ifdef CONFIG_BF549
222#define CPU "BF549"
223#endif
224#ifndef CPU
225#define CPU "UNKNOWN"
226#define CPUID 0x0
227#endif
228
229#if (CONFIG_MEM_SIZE % 4)
230#error "SDRAM mem size must be multible of 4MB"
231#endif
232
233#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
234#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
235#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
236#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
237
238/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
239
240#define ANOMALY_05000158_WORKAROUND 0x200
241#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
242#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
243 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
244#else /*Write Through */
245#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
246 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
247#endif
248
249
250#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
251#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
252#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
253#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
254
255#define SIZE_1K 0x00000400 /* 1K */
256#define SIZE_4K 0x00001000 /* 4K */
257#define SIZE_1M 0x00100000 /* 1M */
258#define SIZE_4M 0x00400000 /* 4M */
259
260#define MAX_CPLBS (16 * 2)
261
262/*
263* Number of required data CPLB switchtable entries
264* MEMSIZE / 4 (we mostly install 4M page size CPLBs
265* approx 16 for smaller 1MB page size CPLBs for allignment purposes
266* 1 for L1 Data Memory
267* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
268* 1 for ASYNC Memory
269*/
270
271
272#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
273
274/*
275* Number of required instruction CPLB switchtable entries
276* MEMSIZE / 4 (we mostly install 4M page size CPLBs
277* approx 12 for smaller 1MB page size CPLBs for allignment purposes
278* 1 for L1 Instruction Memory
279* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
280*/
281
282#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
283
284#endif /* __MACH_BF48_H__ */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
new file mode 100644
index 000000000000..8f5d9c4d8d5b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -0,0 +1,147 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3
4#define NR_PORTS 2
5
6#define OFFSET_THR 0x00 /* Transmit Holding register */
7#define OFFSET_RBR 0x00 /* Receive Buffer register */
8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
9#define OFFSET_IER 0x04 /* Interrupt Enable Register */
10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
12#define OFFSET_LCR 0x0C /* Line Control Register */
13#define OFFSET_MCR 0x10 /* Modem Control Register */
14#define OFFSET_LSR 0x14 /* Line Status Register */
15#define OFFSET_MSR 0x18 /* Modem Status Register */
16#define OFFSET_SCR 0x1C /* SCR Scratch Register */
17#define OFFSET_GCTL 0x24 /* Global Control Register */
18
19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
27
28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
34
35#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
36# define CONFIG_SERIAL_BFIN_CTSRTS
37
38# ifndef CONFIG_UART0_CTS_PIN
39# define CONFIG_UART0_CTS_PIN -1
40# endif
41
42# ifndef CONFIG_UART0_RTS_PIN
43# define CONFIG_UART0_RTS_PIN -1
44# endif
45
46# ifndef CONFIG_UART1_CTS_PIN
47# define CONFIG_UART1_CTS_PIN -1
48# endif
49
50# ifndef CONFIG_UART1_RTS_PIN
51# define CONFIG_UART1_RTS_PIN -1
52# endif
53#endif
54/*
55 * The pin configuration is different from schematic
56 */
57struct bfin_serial_port {
58 struct uart_port port;
59 unsigned int old_status;
60#ifdef CONFIG_SERIAL_BFIN_DMA
61 int tx_done;
62 int tx_count;
63 struct circ_buf rx_dma_buf;
64 struct timer_list rx_dma_timer;
65 int rx_dma_nrows;
66 unsigned int tx_dma_channel;
67 unsigned int rx_dma_channel;
68 struct work_struct tx_dma_workqueue;
69#else
70 struct work_struct cts_workqueue;
71#endif
72#ifdef CONFIG_SERIAL_BFIN_CTSRTS
73 int cts_pin;
74 int rts_pin;
75#endif
76};
77
78struct bfin_serial_port bfin_serial_ports[NR_PORTS];
79struct bfin_serial_res {
80 unsigned long uart_base_addr;
81 int uart_irq;
82#ifdef CONFIG_SERIAL_BFIN_DMA
83 unsigned int uart_tx_dma_channel;
84 unsigned int uart_rx_dma_channel;
85#endif
86#ifdef CONFIG_SERIAL_BFIN_CTSRTS
87 int uart_cts_pin;
88 int uart_rts_pin;
89#endif
90};
91
92struct bfin_serial_res bfin_serial_resource[] = {
93#ifdef CONFIG_SERIAL_BFIN_UART0
94 {
95 0xFFC00400,
96 IRQ_UART0_RX,
97#ifdef CONFIG_SERIAL_BFIN_DMA
98 CH_UART0_TX,
99 CH_UART0_RX,
100#endif
101#ifdef CONFIG_BFIN_UART0_CTSRTS
102 CONFIG_UART0_CTS_PIN,
103 CONFIG_UART0_RTS_PIN,
104#endif
105 },
106#endif
107#ifdef CONFIG_SERIAL_BFIN_UART1
108 {
109 0xFFC02000,
110 IRQ_UART1_RX,
111#ifdef CONFIG_SERIAL_BFIN_DMA
112 CH_UART1_TX,
113 CH_UART1_RX,
114#endif
115#ifdef CONFIG_BFIN_UART1_CTSRTS
116 CONFIG_UART1_CTS_PIN,
117 CONFIG_UART1_RTS_PIN,
118#endif
119 },
120#endif
121};
122
123int nr_ports = ARRAY_SIZE(bfin_serial_resource);
124
125static void bfin_serial_hw_init(struct bfin_serial_port *uart)
126{
127 unsigned short val;
128 val = bfin_read16(BFIN_PORT_MUX);
129 val &= ~(PFDE | PFTE);
130 bfin_write16(BFIN_PORT_MUX, val);
131
132 val = bfin_read16(PORTF_FER);
133 val |= 0xF;
134 bfin_write16(PORTF_FER, val);
135
136#ifdef CONFIG_SERIAL_BFIN_CTSRTS
137 if (uart->cts_pin >= 0) {
138 gpio_request(uart->cts_pin, NULL);
139 gpio_direction_input(uart->cts_pin);
140 }
141
142 if (uart->rts_pin >= 0) {
143 gpio_request(uart->rts_pin, NULL);
144 gpio_direction_output(uart->rts_pin);
145 }
146#endif
147}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
new file mode 100644
index 000000000000..094c41a63194
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -0,0 +1,166 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF548_FAMILY
36
37#ifdef CONFIG_BF542
38#include "bf542.h"
39
40#ifdef CONFIG_BF544
41#include "bf544.h"
42#endif
43
44#ifdef CONFIG_BF548
45#include "bf548.h"
46#endif
47
48#ifdef CONFIG_BF549
49#include "bf549.h"
50#endif
51
52#include "mem_map.h"
53#include "anomaly.h"
54
55#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
56#ifdef CONFIG_BF542
57#include "cdefBF542.h"
58#endif
59
60#ifdef CONFIG_BF544
61#include "cdefBF544.h"
62#endif
63#ifdef CONFIG_BF548
64#include "cdefBF548.h"
65#endif
66#ifdef CONFIG_BF549
67#include "cdefBF549.h"
68#endif
69
70/* UART 1*/
71#define bfin_read_UART_THR() bfin_read_UART1_THR()
72#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
73#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
74#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
75#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
76#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
77#define bfin_read_UART_IER() bfin_read_UART1_IER()
78#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
79#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
80#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
81#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
82#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
83#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
84#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
85#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
86#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
87#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
88#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
89#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
90#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
91#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
92#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
93
94#endif
95
96/* MAP used DEFINES from BF533 to BF54x - so we don't need to change
97 * them in the driver, kernel, etc. */
98
99/* UART_IIR Register */
100#define STATUS(x) ((x << 1) & 0x06)
101#define STATUS_P1 0x02
102#define STATUS_P0 0x01
103
104/* UART 0*/
105
106/* DMA Channnel */
107#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
108#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
109#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
110#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val)
111#define CH_UART_RX CH_UART1_RX
112#define CH_UART_TX CH_UART1_TX
113
114/* System Interrupt Controller */
115#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX()
116#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val)
117#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX()
118#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val)
119#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR()
120#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val)
121#define IRQ_UART_RX IRQ_UART1_RX
122#define IRQ_UART_TX IRQ_UART1_TX
123#define IRQ_UART_ERROR IRQ_UART1_ERROR
124
125/* MMR Registers*/
126#define bfin_read_UART_THR() bfin_read_UART1_THR()
127#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
128#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
129#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
130#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
131#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
132#define bfin_read_UART_IER() bfin_read_UART1_IER()
133#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
134#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
135#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
136#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
137#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
138#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
139#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
140#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
141#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
142#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
143#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
144#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
145#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
146#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
147#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
148#define UART_THR UART1_THR
149#define UART_RBR UART1_RBR
150#define UART_DLL UART1_DLL
151#define UART_IER UART1_IER
152#define UART_DLH UART1_DLH
153#define UART_IIR UART1_IIR
154#define UART_LCR UART1_LCR
155#define UART_MCR UART1_MCR
156#define UART_LSR UART1_LSR
157#define UART_SCR UART1_SCR
158#define UART_GCTL UART1_GCTL
159
160/* PLL_DIV Masks */
161#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
162#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
163#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
164#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
165
166#endif
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
new file mode 100644
index 000000000000..5a334c813c79
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/dma.h
@@ -0,0 +1,63 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define CH_SPORT0_RX 0
36#define CH_SPORT0_TX 1
37#define CH_SPORT1_RX 2
38#define CH_SPORT1_TX 3
39#define CH_SPI0 4
40#define CH_SPI1 5
41#define CH_UART0_RX 6
42#define CH_UART0_TX 7
43#define CH_UART1_RX 8
44#define CH_UART1_TX 9
45#define CH_ATAPI_RX 10
46#define CH_ATAPI_TX 11
47
48#define CH_EPPI0 12
49#define CH_EPPI1 13
50#define CH_EPPI2 14
51#define CH_PIXC_IMAGE 15
52#define CH_PIXC_OVERLAY 16
53#define CH_PIXC_OUTPUT 17
54#define CH_SPORT2_RX 18
55#define CH_SPORT2_TX 19
56#define CH_SPORT3_RX 20
57#define CH_SPORT3_TX 21
58#define CH_SDH 22
59#define CH_SPI2 23
60
61#define MAX_BLACKFIN_DMA_CHANNEL CH_SPI2
62
63#endif
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
new file mode 100644
index 000000000000..a7f6703ea1dd
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -0,0 +1,306 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/irq.h
3 * based on: include/asm-blackfin/mach-bf537/irq.h
4 * author: Roy Huang (roy.huang@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF548_IRQ_H_
33#define _BF548_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38Core Emulation **
39Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47.....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52 */
53
54#define NR_PERI_INTS 32
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt*/
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMAC0_ERR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
70#define IRQ_EPPI0_ERR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
71#define IRQ_SPORT0_ERR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
72#define IRQ_SPORT1_ERR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
73#define IRQ_SPI0_ERR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
74#define IRQ_UART0_ERR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
75#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
76#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
77#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
78#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
79#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
80#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
81#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
82#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
83#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
84#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
85#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
86#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
87#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
95#define IRQ_MXVR BFIN_IRQ(27) /* SPORT3 Error Interrupt */
96#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
97#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
98#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
99#define IRQ_UART2_ERR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
100#define IRQ_CAN0_ERR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
101#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
102#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
103#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
104#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
105#define IRQ_EPP1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
106#define IRQ_EPP2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
107#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
108#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
109#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
110#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
111#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
112#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
113#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
114#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
115#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
116#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
117#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
118#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
119#define IRQ_MXVR_ERR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
120#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
121#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
122#define IRQ_EPP1_ERR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
123#define IRQ_EPP2_ERR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
124#define IRQ_UART3_ERR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
125#define IRQ_HOST_ERR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
126#define IRQ_PIXC_ERR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
127#define IRQ_NFC_ERR BFIN_IRQ(60) /* NFC Error Interrupt */
128#define IRQ_ATAPI_ERR BFIN_IRQ(61) /* ATAPI Error Interrupt */
129#define IRQ_CAN1_ERR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
130#define IRQ_HS_DMA_ERR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
131#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
132#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
133#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
134#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
135#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
136#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
137#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
138#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
139#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
140#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
141#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
142#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
143#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
144#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
145#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
146#define IRQ_TMR0 BFIN_IRQ(86) /* Timer 0 Interrupt */
147#define IRQ_TMR1 BFIN_IRQ(87) /* Timer 1 Interrupt */
148#define IRQ_TMR2 BFIN_IRQ(88) /* Timer 2 Interrupt */
149#define IRQ_TMR3 BFIN_IRQ(89) /* Timer 3 Interrupt */
150#define IRQ_TMR4 BFIN_IRQ(90) /* Timer 4 Interrupt */
151#define IRQ_TMR5 BFIN_IRQ(91) /* Timer 5 Interrupt */
152#define IRQ_TMR6 BFIN_IRQ(92) /* Timer 6 Interrupt */
153#define IRQ_TMR7 BFIN_IRQ(93) /* Timer 7 Interrupt */
154#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
155#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
156
157#define SYS_IRQS IRQ_PINT3
158
159#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
160#define IRQ_PA0 BFIN_PA_IRQ(0)
161#define IRQ_PA1 BFIN_PA_IRQ(1)
162#define IRQ_PA2 BFIN_PA_IRQ(2)
163#define IRQ_PA3 BFIN_PA_IRQ(3)
164#define IRQ_PA4 BFIN_PA_IRQ(4)
165#define IRQ_PA5 BFIN_PA_IRQ(5)
166#define IRQ_PA6 BFIN_PA_IRQ(6)
167#define IRQ_PA7 BFIN_PA_IRQ(7)
168#define IRQ_PA8 BFIN_PA_IRQ(8)
169#define IRQ_PA9 BFIN_PA_IRQ(9)
170#define IRQ_PA10 BFIN_PA_IRQ(10)
171#define IRQ_PA11 BFIN_PA_IRQ(11)
172#define IRQ_PA12 BFIN_PA_IRQ(12)
173#define IRQ_PA13 BFIN_PA_IRQ(13)
174#define IRQ_PA14 BFIN_PA_IRQ(14)
175#define IRQ_PA15 BFIN_PA_IRQ(15)
176
177#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
178#define IRQ_PB0 BFIN_PB_IRQ(0)
179#define IRQ_PB1 BFIN_PB_IRQ(1)
180#define IRQ_PB2 BFIN_PB_IRQ(2)
181#define IRQ_PB3 BFIN_PB_IRQ(3)
182#define IRQ_PB4 BFIN_PB_IRQ(4)
183#define IRQ_PB5 BFIN_PB_IRQ(5)
184#define IRQ_PB6 BFIN_PB_IRQ(6)
185#define IRQ_PB7 BFIN_PB_IRQ(7)
186#define IRQ_PB8 BFIN_PB_IRQ(8)
187#define IRQ_PB9 BFIN_PB_IRQ(9)
188#define IRQ_PB10 BFIN_PB_IRQ(10)
189#define IRQ_PB11 BFIN_PB_IRQ(11)
190#define IRQ_PB12 BFIN_PB_IRQ(12)
191#define IRQ_PB13 BFIN_PB_IRQ(13)
192#define IRQ_PB14 BFIN_PB_IRQ(14)
193#define IRQ_PB15 BFIN_PB_IRQ(15)
194
195#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
196#define IRQ_PC0 BFIN_PC_IRQ(0)
197#define IRQ_PC1 BFIN_PC_IRQ(1)
198#define IRQ_PC2 BFIN_PC_IRQ(2)
199#define IRQ_PC3 BFIN_PC_IRQ(3)
200#define IRQ_PC4 BFIN_PC_IRQ(4)
201#define IRQ_PC5 BFIN_PC_IRQ(5)
202#define IRQ_PC6 BFIN_PC_IRQ(6)
203#define IRQ_PC7 BFIN_PC_IRQ(7)
204#define IRQ_PC8 BFIN_PC_IRQ(8)
205#define IRQ_PC9 BFIN_PC_IRQ(9)
206#define IRQ_PC10 BFIN_PC_IRQ(10)
207#define IRQ_PC11 BFIN_PC_IRQ(11)
208#define IRQ_PC12 BFIN_PC_IRQ(12)
209#define IRQ_PC13 BFIN_PC_IRQ(13)
210#define IRQ_PC14 BFIN_PC_IRQ(14)
211#define IRQ_PC15 BFIN_PC_IRQ(15)
212
213#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
214#define IRQ_PD0 BFIN_PD_IRQ(0)
215#define IRQ_PD1 BFIN_PD_IRQ(1)
216#define IRQ_PD2 BFIN_PD_IRQ(2)
217#define IRQ_PD3 BFIN_PD_IRQ(3)
218#define IRQ_PD4 BFIN_PD_IRQ(4)
219#define IRQ_PD5 BFIN_PD_IRQ(5)
220#define IRQ_PD6 BFIN_PD_IRQ(6)
221#define IRQ_PD7 BFIN_PD_IRQ(7)
222#define IRQ_PD8 BFIN_PD_IRQ(8)
223#define IRQ_PD9 BFIN_PD_IRQ(9)
224#define IRQ_PD10 BFIN_PD_IRQ(10)
225#define IRQ_PD11 BFIN_PD_IRQ(11)
226#define IRQ_PD12 BFIN_PD_IRQ(12)
227#define IRQ_PD13 BFIN_PD_IRQ(13)
228#define IRQ_PD14 BFIN_PD_IRQ(14)
229#define IRQ_PD15 BFIN_PD_IRQ(15)
230
231#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
232#define IRQ_PE0 BFIN_PE_IRQ(0)
233#define IRQ_PE1 BFIN_PE_IRQ(1)
234#define IRQ_PE2 BFIN_PE_IRQ(2)
235#define IRQ_PE3 BFIN_PE_IRQ(3)
236#define IRQ_PE4 BFIN_PE_IRQ(4)
237#define IRQ_PE5 BFIN_PE_IRQ(5)
238#define IRQ_PE6 BFIN_PE_IRQ(6)
239#define IRQ_PE7 BFIN_PE_IRQ(7)
240#define IRQ_PE8 BFIN_PE_IRQ(8)
241#define IRQ_PE9 BFIN_PE_IRQ(9)
242#define IRQ_PE10 BFIN_PE_IRQ(10)
243#define IRQ_PE11 BFIN_PE_IRQ(11)
244#define IRQ_PE12 BFIN_PE_IRQ(12)
245#define IRQ_PE13 BFIN_PE_IRQ(13)
246#define IRQ_PE14 BFIN_PE_IRQ(14)
247#define IRQ_PE15 BFIN_PE_IRQ(15)
248
249
250#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
251#define NR_IRQS (IRQ_PH15+1)
252#else
253#define NR_IRQS (IRQ_UART1_ERROR+1)
254#endif
255
256#define IVG7 7
257#define IVG8 8
258#define IVG9 9
259#define IVG10 10
260#define IVG11 11
261#define IVG12 12
262#define IVG13 13
263#define IVG14 14
264#define IVG15 15
265
266/* IAR0 BIT FIELDS*/
267#define IRQ_PLL_WAKEUP_POS 0
268#define IRQ_DMA_ERROR_POS 4
269#define IRQ_ERROR_POS 8
270#define IRQ_RTC_POS 12
271#define IRQ_PPI_POS 16
272#define IRQ_SPORT0_RX_POS 20
273#define IRQ_SPORT0_TX_POS 24
274#define IRQ_SPORT1_RX_POS 28
275
276/* IAR1 BIT FIELDS*/
277#define IRQ_SPORT1_TX_POS 0
278#define IRQ_TWI_POS 4
279#define IRQ_SPI_POS 8
280#define IRQ_UART0_RX_POS 12
281#define IRQ_UART0_TX_POS 16
282#define IRQ_UART1_RX_POS 20
283#define IRQ_UART1_TX_POS 24
284#define IRQ_CAN_RX_POS 28
285
286/* IAR2 BIT FIELDS*/
287#define IRQ_CAN_TX_POS 0
288#define IRQ_MAC_RX_POS 4
289#define IRQ_MAC_TX_POS 8
290#define IRQ_TMR0_POS 12
291#define IRQ_TMR1_POS 16
292#define IRQ_TMR2_POS 20
293#define IRQ_TMR3_POS 24
294#define IRQ_TMR4_POS 28
295
296/* IAR3 BIT FIELDS*/
297#define IRQ_TMR5_POS 0
298#define IRQ_TMR6_POS 4
299#define IRQ_TMR7_POS 8
300#define IRQ_PROG_INTA_POS 12
301#define IRQ_PORTG_INTB_POS 16
302#define IRQ_MEM_DMA0_POS 20
303#define IRQ_MEM_DMA1_POS 24
304#define IRQ_WATCH_POS 28
305
306#endif /* _BF537_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
new file mode 100644
index 000000000000..0cb279e973d7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -0,0 +1,189 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT46V32M16)
33
34#if defined CONFIG_CLKIN_HALF
35#define CLKIN_HALF 1
36#else
37#define CLKIN_HALF 0
38#endif
39
40#if defined CONFIG_PLL_BYPASS
41#define PLL_BYPASS 1
42#else
43#define PLL_BYPASS 0
44#endif
45
46/***************************************Currently Not Being Used *********************************/
47#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
48#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
49#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
50#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
51#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
52
53#if (flash_EBIU_AMBCTL_TT > 3)
54#define flash_EBIU_AMBCTL0_TT B0TT_4
55#endif
56#if (flash_EBIU_AMBCTL_TT == 3)
57#define flash_EBIU_AMBCTL0_TT B0TT_3
58#endif
59#if (flash_EBIU_AMBCTL_TT == 2)
60#define flash_EBIU_AMBCTL0_TT B0TT_2
61#endif
62#if (flash_EBIU_AMBCTL_TT < 2)
63#define flash_EBIU_AMBCTL0_TT B0TT_1
64#endif
65
66#if (flash_EBIU_AMBCTL_ST > 3)
67#define flash_EBIU_AMBCTL0_ST B0ST_4
68#endif
69#if (flash_EBIU_AMBCTL_ST == 3)
70#define flash_EBIU_AMBCTL0_ST B0ST_3
71#endif
72#if (flash_EBIU_AMBCTL_ST == 2)
73#define flash_EBIU_AMBCTL0_ST B0ST_2
74#endif
75#if (flash_EBIU_AMBCTL_ST < 2)
76#define flash_EBIU_AMBCTL0_ST B0ST_1
77#endif
78
79#if (flash_EBIU_AMBCTL_HT > 2)
80#define flash_EBIU_AMBCTL0_HT B0HT_3
81#endif
82#if (flash_EBIU_AMBCTL_HT == 2)
83#define flash_EBIU_AMBCTL0_HT B0HT_2
84#endif
85#if (flash_EBIU_AMBCTL_HT == 1)
86#define flash_EBIU_AMBCTL0_HT B0HT_1
87#endif
88#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
89#define flash_EBIU_AMBCTL0_HT B0HT_0
90#endif
91#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
92#define flash_EBIU_AMBCTL0_HT B0HT_1
93#endif
94
95#if (flash_EBIU_AMBCTL_WAT > 14)
96#define flash_EBIU_AMBCTL0_WAT B0WAT_15
97#endif
98#if (flash_EBIU_AMBCTL_WAT == 14)
99#define flash_EBIU_AMBCTL0_WAT B0WAT_14
100#endif
101#if (flash_EBIU_AMBCTL_WAT == 13)
102#define flash_EBIU_AMBCTL0_WAT B0WAT_13
103#endif
104#if (flash_EBIU_AMBCTL_WAT == 12)
105#define flash_EBIU_AMBCTL0_WAT B0WAT_12
106#endif
107#if (flash_EBIU_AMBCTL_WAT == 11)
108#define flash_EBIU_AMBCTL0_WAT B0WAT_11
109#endif
110#if (flash_EBIU_AMBCTL_WAT == 10)
111#define flash_EBIU_AMBCTL0_WAT B0WAT_10
112#endif
113#if (flash_EBIU_AMBCTL_WAT == 9)
114#define flash_EBIU_AMBCTL0_WAT B0WAT_9
115#endif
116#if (flash_EBIU_AMBCTL_WAT == 8)
117#define flash_EBIU_AMBCTL0_WAT B0WAT_8
118#endif
119#if (flash_EBIU_AMBCTL_WAT == 7)
120#define flash_EBIU_AMBCTL0_WAT B0WAT_7
121#endif
122#if (flash_EBIU_AMBCTL_WAT == 6)
123#define flash_EBIU_AMBCTL0_WAT B0WAT_6
124#endif
125#if (flash_EBIU_AMBCTL_WAT == 5)
126#define flash_EBIU_AMBCTL0_WAT B0WAT_5
127#endif
128#if (flash_EBIU_AMBCTL_WAT == 4)
129#define flash_EBIU_AMBCTL0_WAT B0WAT_4
130#endif
131#if (flash_EBIU_AMBCTL_WAT == 3)
132#define flash_EBIU_AMBCTL0_WAT B0WAT_3
133#endif
134#if (flash_EBIU_AMBCTL_WAT == 2)
135#define flash_EBIU_AMBCTL0_WAT B0WAT_2
136#endif
137#if (flash_EBIU_AMBCTL_WAT == 1)
138#define flash_EBIU_AMBCTL0_WAT B0WAT_1
139#endif
140
141#if (flash_EBIU_AMBCTL_RAT > 14)
142#define flash_EBIU_AMBCTL0_RAT B0RAT_15
143#endif
144#if (flash_EBIU_AMBCTL_RAT == 14)
145#define flash_EBIU_AMBCTL0_RAT B0RAT_14
146#endif
147#if (flash_EBIU_AMBCTL_RAT == 13)
148#define flash_EBIU_AMBCTL0_RAT B0RAT_13
149#endif
150#if (flash_EBIU_AMBCTL_RAT == 12)
151#define flash_EBIU_AMBCTL0_RAT B0RAT_12
152#endif
153#if (flash_EBIU_AMBCTL_RAT == 11)
154#define flash_EBIU_AMBCTL0_RAT B0RAT_11
155#endif
156#if (flash_EBIU_AMBCTL_RAT == 10)
157#define flash_EBIU_AMBCTL0_RAT B0RAT_10
158#endif
159#if (flash_EBIU_AMBCTL_RAT == 9)
160#define flash_EBIU_AMBCTL0_RAT B0RAT_9
161#endif
162#if (flash_EBIU_AMBCTL_RAT == 8)
163#define flash_EBIU_AMBCTL0_RAT B0RAT_8
164#endif
165#if (flash_EBIU_AMBCTL_RAT == 7)
166#define flash_EBIU_AMBCTL0_RAT B0RAT_7
167#endif
168#if (flash_EBIU_AMBCTL_RAT == 6)
169#define flash_EBIU_AMBCTL0_RAT B0RAT_6
170#endif
171#if (flash_EBIU_AMBCTL_RAT == 5)
172#define flash_EBIU_AMBCTL0_RAT B0RAT_5
173#endif
174#if (flash_EBIU_AMBCTL_RAT == 4)
175#define flash_EBIU_AMBCTL0_RAT B0RAT_4
176#endif
177#if (flash_EBIU_AMBCTL_RAT == 3)
178#define flash_EBIU_AMBCTL0_RAT B0RAT_3
179#endif
180#if (flash_EBIU_AMBCTL_RAT == 2)
181#define flash_EBIU_AMBCTL0_RAT B0RAT_2
182#endif
183#if (flash_EBIU_AMBCTL_RAT == 1)
184#define flash_EBIU_AMBCTL0_RAT B0RAT_1
185#endif
186
187#define flash_EBIU_AMBCTL0 \
188 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
189 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
new file mode 100644
index 000000000000..72d80e8a6e81
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -0,0 +1,97 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_548_H_
32#define _MEM_MAP_548_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
40#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
42#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50
51/* Level 1 Memory */
52
53/* Memory Map for ADSP-BF548 processors */
54#ifdef CONFIG_BLKFIN_ICACHE
55#define BLKFIN_ICACHESIZE (16*1024)
56#else
57#define BLKFIN_ICACHESIZE (0*1024)
58#endif
59
60#define L1_CODE_START 0xFFA00000
61#define L1_DATA_A_START 0xFF800000
62#define L1_DATA_B_START 0xFF900000
63
64#define L1_CODE_LENGTH 0xC000
65
66#ifdef CONFIG_BLKFIN_DCACHE
67
68#ifdef CONFIG_BLKFIN_DCACHE_BANKA
69#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
70#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
71#define L1_DATA_B_LENGTH 0x8000
72#define BLKFIN_DCACHESIZE (16*1024)
73#define BLKFIN_DSUPBANKS 1
74#else
75#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
77#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
78#define BLKFIN_DCACHESIZE (32*1024)
79#define BLKFIN_DSUPBANKS 2
80#endif
81
82#else
83#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
84#define L1_DATA_A_LENGTH 0x8000
85#define L1_DATA_B_LENGTH 0x8000
86#define BLKFIN_DCACHESIZE (0*1024)
87#define BLKFIN_DSUPBANKS 0
88#endif /*CONFIG_BLKFIN_DCACHE*/
89
90/* Scratch Pad Memory */
91
92#if defined(CONFIG_BF54x)
93#define L1_SCRATCH_START 0xFFB00000
94#define L1_SCRATCH_LENGTH 0x1000
95#endif
96
97#endif/* _MEM_MAP_548_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 05:59:00 -0500