diff options
| -rw-r--r-- | drivers/clk/samsung/clk-pll.c | 30 |
1 files changed, 12 insertions, 18 deletions
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 362f12dcd944..f62f85418488 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c | |||
| @@ -13,6 +13,14 @@ | |||
| 13 | #include "clk.h" | 13 | #include "clk.h" |
| 14 | #include "clk-pll.h" | 14 | #include "clk-pll.h" |
| 15 | 15 | ||
| 16 | struct samsung_clk_pll { | ||
| 17 | struct clk_hw hw; | ||
| 18 | void __iomem *lock_reg; | ||
| 19 | void __iomem *con_reg; | ||
| 20 | }; | ||
| 21 | |||
| 22 | #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) | ||
| 23 | |||
| 16 | /* | 24 | /* |
| 17 | * PLL35xx Clock Type | 25 | * PLL35xx Clock Type |
| 18 | */ | 26 | */ |
| @@ -24,17 +32,10 @@ | |||
| 24 | #define PLL35XX_PDIV_SHIFT (8) | 32 | #define PLL35XX_PDIV_SHIFT (8) |
| 25 | #define PLL35XX_SDIV_SHIFT (0) | 33 | #define PLL35XX_SDIV_SHIFT (0) |
| 26 | 34 | ||
| 27 | struct samsung_clk_pll35xx { | ||
| 28 | struct clk_hw hw; | ||
| 29 | const void __iomem *con_reg; | ||
| 30 | }; | ||
| 31 | |||
| 32 | #define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw) | ||
| 33 | |||
| 34 | static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, | 35 | static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, |
| 35 | unsigned long parent_rate) | 36 | unsigned long parent_rate) |
| 36 | { | 37 | { |
| 37 | struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw); | 38 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
| 38 | u32 mdiv, pdiv, sdiv, pll_con; | 39 | u32 mdiv, pdiv, sdiv, pll_con; |
| 39 | u64 fvco = parent_rate; | 40 | u64 fvco = parent_rate; |
| 40 | 41 | ||
| @@ -56,7 +57,7 @@ static const struct clk_ops samsung_pll35xx_clk_ops = { | |||
| 56 | struct clk * __init samsung_clk_register_pll35xx(const char *name, | 57 | struct clk * __init samsung_clk_register_pll35xx(const char *name, |
| 57 | const char *pname, const void __iomem *con_reg) | 58 | const char *pname, const void __iomem *con_reg) |
| 58 | { | 59 | { |
| 59 | struct samsung_clk_pll35xx *pll; | 60 | struct samsung_clk_pll *pll; |
| 60 | struct clk *clk; | 61 | struct clk *clk; |
| 61 | struct clk_init_data init; | 62 | struct clk_init_data init; |
| 62 | 63 | ||
| @@ -100,17 +101,10 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, | |||
| 100 | #define PLL36XX_PDIV_SHIFT (8) | 101 | #define PLL36XX_PDIV_SHIFT (8) |
| 101 | #define PLL36XX_SDIV_SHIFT (0) | 102 | #define PLL36XX_SDIV_SHIFT (0) |
| 102 | 103 | ||
| 103 | struct samsung_clk_pll36xx { | ||
| 104 | struct clk_hw hw; | ||
| 105 | const void __iomem *con_reg; | ||
| 106 | }; | ||
| 107 | |||
| 108 | #define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw) | ||
| 109 | |||
| 110 | static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, | 104 | static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, |
| 111 | unsigned long parent_rate) | 105 | unsigned long parent_rate) |
| 112 | { | 106 | { |
| 113 | struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw); | 107 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
| 114 | u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; | 108 | u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; |
| 115 | s16 kdiv; | 109 | s16 kdiv; |
| 116 | u64 fvco = parent_rate; | 110 | u64 fvco = parent_rate; |
| @@ -136,7 +130,7 @@ static const struct clk_ops samsung_pll36xx_clk_ops = { | |||
| 136 | struct clk * __init samsung_clk_register_pll36xx(const char *name, | 130 | struct clk * __init samsung_clk_register_pll36xx(const char *name, |
| 137 | const char *pname, const void __iomem *con_reg) | 131 | const char *pname, const void __iomem *con_reg) |
| 138 | { | 132 | { |
| 139 | struct samsung_clk_pll36xx *pll; | 133 | struct samsung_clk_pll *pll; |
| 140 | struct clk *clk; | 134 | struct clk *clk; |
| 141 | struct clk_init_data init; | 135 | struct clk_init_data init; |
| 142 | 136 | ||
