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-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 58e1d79185ce..6c1511263a55 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -23,6 +23,7 @@
23 next-level-cache = <&L2>; 23 next-level-cache = <&L2>;
24 qcom,acc = <&acc0>; 24 qcom,acc = <&acc0>;
25 qcom,saw = <&saw0>; 25 qcom,saw = <&saw0>;
26 cpu-idle-states = <&CPU_SPC>;
26 }; 27 };
27 28
28 cpu@1 { 29 cpu@1 {
@@ -33,6 +34,7 @@
33 next-level-cache = <&L2>; 34 next-level-cache = <&L2>;
34 qcom,acc = <&acc1>; 35 qcom,acc = <&acc1>;
35 qcom,saw = <&saw1>; 36 qcom,saw = <&saw1>;
37 cpu-idle-states = <&CPU_SPC>;
36 }; 38 };
37 39
38 cpu@2 { 40 cpu@2 {
@@ -43,6 +45,7 @@
43 next-level-cache = <&L2>; 45 next-level-cache = <&L2>;
44 qcom,acc = <&acc2>; 46 qcom,acc = <&acc2>;
45 qcom,saw = <&saw2>; 47 qcom,saw = <&saw2>;
48 cpu-idle-states = <&CPU_SPC>;
46 }; 49 };
47 50
48 cpu@3 { 51 cpu@3 {
@@ -53,12 +56,23 @@
53 next-level-cache = <&L2>; 56 next-level-cache = <&L2>;
54 qcom,acc = <&acc3>; 57 qcom,acc = <&acc3>;
55 qcom,saw = <&saw3>; 58 qcom,saw = <&saw3>;
59 cpu-idle-states = <&CPU_SPC>;
56 }; 60 };
57 61
58 L2: l2-cache { 62 L2: l2-cache {
59 compatible = "cache"; 63 compatible = "cache";
60 cache-level = <2>; 64 cache-level = <2>;
61 }; 65 };
66
67 idle-states {
68 CPU_SPC: spc {
69 compatible = "qcom,idle-state-spc",
70 "arm,idle-state";
71 entry-latency-us = <400>;
72 exit-latency-us = <900>;
73 min-residency-us = <3000>;
74 };
75 };
62 }; 76 };
63 77
64 cpu-pmu { 78 cpu-pmu {