diff options
-rw-r--r-- | drivers/video/omap2/dss/dispc.c | 7 | ||||
-rw-r--r-- | drivers/video/omap2/dss/dsi.c | 42 | ||||
-rw-r--r-- | drivers/video/omap2/dss/dss.c | 19 | ||||
-rw-r--r-- | drivers/video/omap2/dss/dss.h | 7 | ||||
-rw-r--r-- | drivers/video/omap2/dss/dss_features.c | 23 | ||||
-rw-r--r-- | drivers/video/omap2/dss/dss_features.h | 1 |
6 files changed, 81 insertions, 18 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index a06b2ea41e98..2c82d9a3df4b 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c | |||
@@ -2379,14 +2379,15 @@ unsigned long dispc_pclk_rate(enum omap_channel channel) | |||
2379 | void dispc_dump_clocks(struct seq_file *s) | 2379 | void dispc_dump_clocks(struct seq_file *s) |
2380 | { | 2380 | { |
2381 | int lcd, pcd; | 2381 | int lcd, pcd; |
2382 | enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); | ||
2382 | 2383 | ||
2383 | enable_clocks(1); | 2384 | enable_clocks(1); |
2384 | 2385 | ||
2385 | seq_printf(s, "- DISPC -\n"); | 2386 | seq_printf(s, "- DISPC -\n"); |
2386 | 2387 | ||
2387 | seq_printf(s, "dispc fclk source = %s\n", | 2388 | seq_printf(s, "dispc fclk source = %s (%s)\n", |
2388 | dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ? | 2389 | dss_get_generic_clk_source_name(dispc_clk_src), |
2389 | "dss1_alwon_fclk" : "dsi1_pll_fclk"); | 2390 | dss_feat_get_clk_source_name(dispc_clk_src)); |
2390 | 2391 | ||
2391 | seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); | 2392 | seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); |
2392 | 2393 | ||
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index df35aed828da..3ef94227bbe7 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c | |||
@@ -1022,10 +1022,14 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) | |||
1022 | 1022 | ||
1023 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); | 1023 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); |
1024 | 1024 | ||
1025 | DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", | 1025 | DSSDBG("regm3 = %d, %s (%s) = %lu\n", cinfo->regm3, |
1026 | cinfo->regm3, cinfo->dsi1_pll_fclk); | 1026 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1027 | DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", | 1027 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1028 | cinfo->regm4, cinfo->dsi2_pll_fclk); | 1028 | cinfo->dsi1_pll_fclk); |
1029 | DSSDBG("regm4 = %d, %s (%s) = %lu\n", cinfo->regm4, | ||
1030 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | ||
1031 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | ||
1032 | cinfo->dsi2_pll_fclk); | ||
1029 | 1033 | ||
1030 | REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ | 1034 | REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ |
1031 | 1035 | ||
@@ -1169,6 +1173,10 @@ void dsi_dump_clocks(struct seq_file *s) | |||
1169 | { | 1173 | { |
1170 | int clksel; | 1174 | int clksel; |
1171 | struct dsi_clock_info *cinfo = &dsi.current_cinfo; | 1175 | struct dsi_clock_info *cinfo = &dsi.current_cinfo; |
1176 | enum dss_clk_source dispc_clk_src, dsi_clk_src; | ||
1177 | |||
1178 | dispc_clk_src = dss_get_dispc_clk_source(); | ||
1179 | dsi_clk_src = dss_get_dsi_clk_source(); | ||
1172 | 1180 | ||
1173 | enable_clocks(1); | 1181 | enable_clocks(1); |
1174 | 1182 | ||
@@ -1185,23 +1193,27 @@ void dsi_dump_clocks(struct seq_file *s) | |||
1185 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", | 1193 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", |
1186 | cinfo->clkin4ddr, cinfo->regm); | 1194 | cinfo->clkin4ddr, cinfo->regm); |
1187 | 1195 | ||
1188 | seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n", | 1196 | seq_printf(s, "%s (%s)\t%-16luregm3 %u\t(%s)\n", |
1197 | dss_get_generic_clk_source_name(dispc_clk_src), | ||
1198 | dss_feat_get_clk_source_name(dispc_clk_src), | ||
1189 | cinfo->dsi1_pll_fclk, | 1199 | cinfo->dsi1_pll_fclk, |
1190 | cinfo->regm3, | 1200 | cinfo->regm3, |
1191 | dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ? | 1201 | dispc_clk_src == DSS_CLK_SRC_FCK ? |
1192 | "off" : "on"); | 1202 | "off" : "on"); |
1193 | 1203 | ||
1194 | seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n", | 1204 | seq_printf(s, "%s (%s)\t%-16luregm4 %u\t(%s)\n", |
1205 | dss_get_generic_clk_source_name(dsi_clk_src), | ||
1206 | dss_feat_get_clk_source_name(dsi_clk_src), | ||
1195 | cinfo->dsi2_pll_fclk, | 1207 | cinfo->dsi2_pll_fclk, |
1196 | cinfo->regm4, | 1208 | cinfo->regm4, |
1197 | dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ? | 1209 | dsi_clk_src == DSS_CLK_SRC_FCK ? |
1198 | "off" : "on"); | 1210 | "off" : "on"); |
1199 | 1211 | ||
1200 | seq_printf(s, "- DSI -\n"); | 1212 | seq_printf(s, "- DSI -\n"); |
1201 | 1213 | ||
1202 | seq_printf(s, "dsi fclk source = %s\n", | 1214 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
1203 | dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ? | 1215 | dss_get_generic_clk_source_name(dsi_clk_src), |
1204 | "dss1_alwon_fclk" : "dsi2_pll_fclk"); | 1216 | dss_feat_get_clk_source_name(dsi_clk_src)); |
1205 | 1217 | ||
1206 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); | 1218 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); |
1207 | 1219 | ||
@@ -3235,13 +3247,17 @@ int dsi_init_display(struct omap_dss_device *dssdev) | |||
3235 | void dsi_wait_dsi1_pll_active(void) | 3247 | void dsi_wait_dsi1_pll_active(void) |
3236 | { | 3248 | { |
3237 | if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) | 3249 | if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) |
3238 | DSSERR("DSI1 PLL clock not active\n"); | 3250 | DSSERR("%s (%s) not active\n", |
3251 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), | ||
3252 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); | ||
3239 | } | 3253 | } |
3240 | 3254 | ||
3241 | void dsi_wait_dsi2_pll_active(void) | 3255 | void dsi_wait_dsi2_pll_active(void) |
3242 | { | 3256 | { |
3243 | if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) | 3257 | if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) |
3244 | DSSERR("DSI2 PLL clock not active\n"); | 3258 | DSSERR("%s (%s) not active\n", |
3259 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | ||
3260 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); | ||
3245 | } | 3261 | } |
3246 | 3262 | ||
3247 | static int dsi_init(struct platform_device *pdev) | 3263 | static int dsi_init(struct platform_device *pdev) |
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 998c188c8823..d049598bb412 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c | |||
@@ -81,6 +81,12 @@ static struct { | |||
81 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; | 81 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
82 | } dss; | 82 | } dss; |
83 | 83 | ||
84 | static const struct dss_clk_source_name dss_generic_clk_source_names[] = { | ||
85 | { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" }, | ||
86 | { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" }, | ||
87 | { DSS_CLK_SRC_FCK, "DSS_FCK" }, | ||
88 | }; | ||
89 | |||
84 | static void dss_clk_enable_all_no_ctx(void); | 90 | static void dss_clk_enable_all_no_ctx(void); |
85 | static void dss_clk_disable_all_no_ctx(void); | 91 | static void dss_clk_disable_all_no_ctx(void); |
86 | static void dss_clk_enable_no_ctx(enum dss_clock clks); | 92 | static void dss_clk_enable_no_ctx(enum dss_clock clks); |
@@ -223,6 +229,11 @@ void dss_sdi_disable(void) | |||
223 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | 229 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
224 | } | 230 | } |
225 | 231 | ||
232 | const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src) | ||
233 | { | ||
234 | return dss_generic_clk_source_names[clk_src].clksrc_name; | ||
235 | } | ||
236 | |||
226 | void dss_dump_clocks(struct seq_file *s) | 237 | void dss_dump_clocks(struct seq_file *s) |
227 | { | 238 | { |
228 | unsigned long dpll4_ck_rate; | 239 | unsigned long dpll4_ck_rate; |
@@ -238,12 +249,16 @@ void dss_dump_clocks(struct seq_file *s) | |||
238 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); | 249 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); |
239 | 250 | ||
240 | if (cpu_is_omap3630()) | 251 | if (cpu_is_omap3630()) |
241 | seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", | 252 | seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", |
253 | dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), | ||
254 | dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), | ||
242 | dpll4_ck_rate, | 255 | dpll4_ck_rate, |
243 | dpll4_ck_rate / dpll4_m4_ck_rate, | 256 | dpll4_ck_rate / dpll4_m4_ck_rate, |
244 | dss_clk_get_rate(DSS_CLK_FCK)); | 257 | dss_clk_get_rate(DSS_CLK_FCK)); |
245 | else | 258 | else |
246 | seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", | 259 | seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", |
260 | dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), | ||
261 | dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), | ||
247 | dpll4_ck_rate, | 262 | dpll4_ck_rate, |
248 | dpll4_ck_rate / dpll4_m4_ck_rate, | 263 | dpll4_ck_rate / dpll4_m4_ck_rate, |
249 | dss_clk_get_rate(DSS_CLK_FCK)); | 264 | dss_clk_get_rate(DSS_CLK_FCK)); |
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index a166ff36ec90..42ca70f2bfd5 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h | |||
@@ -123,6 +123,12 @@ enum dss_clk_source { | |||
123 | DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */ | 123 | DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */ |
124 | }; | 124 | }; |
125 | 125 | ||
126 | /* Correlates clock source name and dss_clk_source member */ | ||
127 | struct dss_clk_source_name { | ||
128 | enum dss_clk_source clksrc; | ||
129 | const char *clksrc_name; | ||
130 | }; | ||
131 | |||
126 | struct dss_clock_info { | 132 | struct dss_clock_info { |
127 | /* rates that we get with dividers below */ | 133 | /* rates that we get with dividers below */ |
128 | unsigned long fck; | 134 | unsigned long fck; |
@@ -215,6 +221,7 @@ void dss_clk_enable(enum dss_clock clks); | |||
215 | void dss_clk_disable(enum dss_clock clks); | 221 | void dss_clk_disable(enum dss_clock clks); |
216 | unsigned long dss_clk_get_rate(enum dss_clock clk); | 222 | unsigned long dss_clk_get_rate(enum dss_clock clk); |
217 | int dss_need_ctx_restore(void); | 223 | int dss_need_ctx_restore(void); |
224 | const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src); | ||
218 | void dss_dump_clocks(struct seq_file *s); | 225 | void dss_dump_clocks(struct seq_file *s); |
219 | 226 | ||
220 | void dss_dump_regs(struct seq_file *s); | 227 | void dss_dump_regs(struct seq_file *s); |
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 3ebe0d91afd2..ccae57b34f5c 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <plat/display.h> | 25 | #include <plat/display.h> |
26 | #include <plat/cpu.h> | 26 | #include <plat/cpu.h> |
27 | 27 | ||
28 | #include "dss.h" | ||
28 | #include "dss_features.h" | 29 | #include "dss_features.h" |
29 | 30 | ||
30 | /* Defines a generic omap register field */ | 31 | /* Defines a generic omap register field */ |
@@ -44,6 +45,7 @@ struct omap_dss_features { | |||
44 | const unsigned long max_dss_fck; | 45 | const unsigned long max_dss_fck; |
45 | const enum omap_display_type *supported_displays; | 46 | const enum omap_display_type *supported_displays; |
46 | const enum omap_color_mode *supported_color_modes; | 47 | const enum omap_color_mode *supported_color_modes; |
48 | const struct dss_clk_source_name *clksrc_names; | ||
47 | }; | 49 | }; |
48 | 50 | ||
49 | /* This struct is assigned to one of the below during initialization */ | 51 | /* This struct is assigned to one of the below during initialization */ |
@@ -157,6 +159,18 @@ static const enum omap_color_mode omap3_dss_supported_color_modes[] = { | |||
157 | OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, | 159 | OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, |
158 | }; | 160 | }; |
159 | 161 | ||
162 | static const struct dss_clk_source_name omap2_dss_clk_source_names[] = { | ||
163 | { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "N/A" }, | ||
164 | { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "N/A" }, | ||
165 | { DSS_CLK_SRC_FCK, "DSS_FCLK1" }, | ||
166 | }; | ||
167 | |||
168 | static const struct dss_clk_source_name omap3_dss_clk_source_names[] = { | ||
169 | { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI1_PLL_FCLK" }, | ||
170 | { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI2_PLL_FCLK" }, | ||
171 | { DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" }, | ||
172 | }; | ||
173 | |||
160 | /* OMAP2 DSS Features */ | 174 | /* OMAP2 DSS Features */ |
161 | static struct omap_dss_features omap2_dss_features = { | 175 | static struct omap_dss_features omap2_dss_features = { |
162 | .reg_fields = omap2_dss_reg_fields, | 176 | .reg_fields = omap2_dss_reg_fields, |
@@ -172,6 +186,7 @@ static struct omap_dss_features omap2_dss_features = { | |||
172 | .max_dss_fck = 173000000, | 186 | .max_dss_fck = 173000000, |
173 | .supported_displays = omap2_dss_supported_displays, | 187 | .supported_displays = omap2_dss_supported_displays, |
174 | .supported_color_modes = omap2_dss_supported_color_modes, | 188 | .supported_color_modes = omap2_dss_supported_color_modes, |
189 | .clksrc_names = omap2_dss_clk_source_names, | ||
175 | }; | 190 | }; |
176 | 191 | ||
177 | /* OMAP3 DSS Features */ | 192 | /* OMAP3 DSS Features */ |
@@ -190,6 +205,7 @@ static struct omap_dss_features omap3430_dss_features = { | |||
190 | .max_dss_fck = 173000000, | 205 | .max_dss_fck = 173000000, |
191 | .supported_displays = omap3430_dss_supported_displays, | 206 | .supported_displays = omap3430_dss_supported_displays, |
192 | .supported_color_modes = omap3_dss_supported_color_modes, | 207 | .supported_color_modes = omap3_dss_supported_color_modes, |
208 | .clksrc_names = omap3_dss_clk_source_names, | ||
193 | }; | 209 | }; |
194 | 210 | ||
195 | static struct omap_dss_features omap3630_dss_features = { | 211 | static struct omap_dss_features omap3630_dss_features = { |
@@ -208,6 +224,7 @@ static struct omap_dss_features omap3630_dss_features = { | |||
208 | .max_dss_fck = 173000000, | 224 | .max_dss_fck = 173000000, |
209 | .supported_displays = omap3630_dss_supported_displays, | 225 | .supported_displays = omap3630_dss_supported_displays, |
210 | .supported_color_modes = omap3_dss_supported_color_modes, | 226 | .supported_color_modes = omap3_dss_supported_color_modes, |
227 | .clksrc_names = omap3_dss_clk_source_names, | ||
211 | }; | 228 | }; |
212 | 229 | ||
213 | /* OMAP4 DSS Features */ | 230 | /* OMAP4 DSS Features */ |
@@ -224,6 +241,7 @@ static struct omap_dss_features omap4_dss_features = { | |||
224 | .max_dss_fck = 186000000, | 241 | .max_dss_fck = 186000000, |
225 | .supported_displays = omap4_dss_supported_displays, | 242 | .supported_displays = omap4_dss_supported_displays, |
226 | .supported_color_modes = omap3_dss_supported_color_modes, | 243 | .supported_color_modes = omap3_dss_supported_color_modes, |
244 | .clksrc_names = omap3_dss_clk_source_names, | ||
227 | }; | 245 | }; |
228 | 246 | ||
229 | /* Functions returning values related to a DSS feature */ | 247 | /* Functions returning values related to a DSS feature */ |
@@ -260,6 +278,11 @@ bool dss_feat_color_mode_supported(enum omap_plane plane, | |||
260 | color_mode; | 278 | color_mode; |
261 | } | 279 | } |
262 | 280 | ||
281 | const char *dss_feat_get_clk_source_name(enum dss_clk_source id) | ||
282 | { | ||
283 | return omap_current_dss_features->clksrc_names[id].clksrc_name; | ||
284 | } | ||
285 | |||
263 | /* DSS has_feature check */ | 286 | /* DSS has_feature check */ |
264 | bool dss_has_feature(enum dss_feat_id id) | 287 | bool dss_has_feature(enum dss_feat_id id) |
265 | { | 288 | { |
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 18ab19515817..65d6de7e0feb 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h | |||
@@ -57,6 +57,7 @@ enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel | |||
57 | enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); | 57 | enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); |
58 | bool dss_feat_color_mode_supported(enum omap_plane plane, | 58 | bool dss_feat_color_mode_supported(enum omap_plane plane, |
59 | enum omap_color_mode color_mode); | 59 | enum omap_color_mode color_mode); |
60 | const char *dss_feat_get_clk_source_name(enum dss_clk_source id); | ||
60 | 61 | ||
61 | bool dss_has_feature(enum dss_feat_id id); | 62 | bool dss_has_feature(enum dss_feat_id id); |
62 | void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); | 63 | void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); |