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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-davinci/Kconfig2
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c52
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c28
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c18
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c18
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c12
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c60
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c22
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c54
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c20
-rw-r--r--arch/arm/mach-davinci/cdce949.c1
-rw-r--r--arch/arm/mach-davinci/clock.c32
-rw-r--r--arch/arm/mach-davinci/clock.h9
-rw-r--r--arch/arm/mach-davinci/common.c57
-rw-r--r--arch/arm/mach-davinci/cp_intc.c22
-rw-r--r--arch/arm/mach-davinci/da830.c29
-rw-r--r--arch/arm/mach-davinci/da850.c30
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c15
-rw-r--r--arch/arm/mach-davinci/devices.c50
-rw-r--r--arch/arm/mach-davinci/dm355.c21
-rw-r--r--arch/arm/mach-davinci/dm365.c34
-rw-r--r--arch/arm/mach-davinci/dm644x.c21
-rw-r--r--arch/arm/mach-davinci/dm646x.c53
-rw-r--r--arch/arm/mach-davinci/dma.c234
-rw-r--r--arch/arm/mach-davinci/gpio.c160
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h32
-rw-r--r--arch/arm/mach-davinci/include/mach/cp_intc.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h29
-rw-r--r--arch/arm/mach-davinci/include/mach/dm355.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h6
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h72
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h97
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h290
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h55
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/system.h5
-rw-r--r--arch/arm/mach-davinci/io.c20
-rw-r--r--arch/arm/mach-davinci/irq.c7
-rw-r--r--arch/arm/mach-davinci/mux.c19
-rw-r--r--arch/arm/mach-davinci/mux.h2
-rw-r--r--arch/arm/mach-davinci/psc.c10
-rw-r--r--arch/arm/mach-davinci/serial.c34
-rw-r--r--arch/arm/mach-davinci/time.c37
-rw-r--r--drivers/rtc/Kconfig10
-rw-r--r--drivers/rtc/Makefile1
-rw-r--r--drivers/rtc/rtc-davinci.c673
50 files changed, 1813 insertions, 664 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a07b6c47a6b8..2d70cece2ea2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -760,7 +760,6 @@ config ARCH_NOMADIK
760 760
761config ARCH_DAVINCI 761config ARCH_DAVINCI
762 bool "TI DaVinci" 762 bool "TI DaVinci"
763 select CPU_ARM926T
764 select GENERIC_CLOCKEVENTS 763 select GENERIC_CLOCKEVENTS
765 select ARCH_REQUIRE_GPIOLIB 764 select ARCH_REQUIRE_GPIOLIB
766 select ZONE_DMA 765 select ZONE_DMA
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0ebe185610bf..0316e201ada0 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -7,6 +7,7 @@ config CP_INTC
7 bool 7 bool
8 8
9config ARCH_DAVINCI_DMx 9config ARCH_DAVINCI_DMx
10 select CPU_ARM926T
10 bool 11 bool
11 12
12menu "TI DaVinci Implementations" 13menu "TI DaVinci Implementations"
@@ -41,6 +42,7 @@ config ARCH_DAVINCI_DA850
41 select ARCH_HAS_CPUFREQ 42 select ARCH_HAS_CPUFREQ
42 43
43config ARCH_DAVINCI_DA8XX 44config ARCH_DAVINCI_DA8XX
45 select CPU_ARM926T
44 bool 46 bool
45 47
46config ARCH_DAVINCI_DM365 48config ARCH_DAVINCI_DM365
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index dc19870b23cd..212d97084bd7 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -33,9 +33,6 @@
33#define DA830_EVM_PHY_MASK 0x0 33#define DA830_EVM_PHY_MASK 0x0
34#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ 34#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
35 35
36#define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000
37#define DA830_EMIF25_CONTROL_BASE 0x68000000
38
39/* 36/*
40 * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. 37 * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
41 */ 38 */
@@ -157,7 +154,7 @@ static __init void da830_evm_usb_init(void)
157 __func__, ret); 154 __func__, ret);
158 } 155 }
159 156
160 ret = da8xx_pinmux_setup(da830_evm_usb11_pins); 157 ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
161 if (ret) { 158 if (ret) {
162 pr_warning("%s: USB 1.1 PinMux setup failed: %d\n", 159 pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
163 __func__, ret); 160 __func__, ret);
@@ -229,15 +226,22 @@ static const short da830_evm_mmc_sd_pins[] = {
229}; 226};
230 227
231#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1) 228#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
229#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
232 230
233static int da830_evm_mmc_get_ro(int index) 231static int da830_evm_mmc_get_ro(int index)
234{ 232{
235 return gpio_get_value(DA830_MMCSD_WP_PIN); 233 return gpio_get_value(DA830_MMCSD_WP_PIN);
236} 234}
237 235
236static int da830_evm_mmc_get_cd(int index)
237{
238 return !gpio_get_value(DA830_MMCSD_CD_PIN);
239}
240
238static struct davinci_mmc_config da830_evm_mmc_config = { 241static struct davinci_mmc_config da830_evm_mmc_config = {
239 .get_ro = da830_evm_mmc_get_ro, 242 .get_ro = da830_evm_mmc_get_ro,
240 .wires = 4, 243 .get_cd = da830_evm_mmc_get_cd,
244 .wires = 8,
241 .max_freq = 50000000, 245 .max_freq = 50000000,
242 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, 246 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
243 .version = MMC_CTLR_VERSION_2, 247 .version = MMC_CTLR_VERSION_2,
@@ -247,7 +251,7 @@ static inline void da830_evm_init_mmc(void)
247{ 251{
248 int ret; 252 int ret;
249 253
250 ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins); 254 ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
251 if (ret) { 255 if (ret) {
252 pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n", 256 pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
253 ret); 257 ret);
@@ -262,6 +266,14 @@ static inline void da830_evm_init_mmc(void)
262 } 266 }
263 gpio_direction_input(DA830_MMCSD_WP_PIN); 267 gpio_direction_input(DA830_MMCSD_WP_PIN);
264 268
269 ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
270 if (ret) {
271 pr_warning("da830_evm_init: can not open GPIO %d\n",
272 DA830_MMCSD_CD_PIN);
273 return;
274 }
275 gpio_direction_input(DA830_MMCSD_CD_PIN);
276
265 ret = da8xx_register_mmcsd0(&da830_evm_mmc_config); 277 ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
266 if (ret) { 278 if (ret) {
267 pr_warning("da830_evm_init: mmc/sd registration failed: %d\n", 279 pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
@@ -360,13 +372,13 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
360 372
361static struct resource da830_evm_nand_resources[] = { 373static struct resource da830_evm_nand_resources[] = {
362 [0] = { /* First memory resource is NAND I/O window */ 374 [0] = { /* First memory resource is NAND I/O window */
363 .start = DA830_EMIF25_ASYNC_DATA_CE3_BASE, 375 .start = DA8XX_AEMIF_CS3_BASE,
364 .end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1, 376 .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
365 .flags = IORESOURCE_MEM, 377 .flags = IORESOURCE_MEM,
366 }, 378 },
367 [1] = { /* Second memory resource is AEMIF control registers */ 379 [1] = { /* Second memory resource is AEMIF control registers */
368 .start = DA830_EMIF25_CONTROL_BASE, 380 .start = DA8XX_AEMIF_CTL_BASE,
369 .end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1, 381 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
370 .flags = IORESOURCE_MEM, 382 .flags = IORESOURCE_MEM,
371 }, 383 },
372}; 384};
@@ -392,7 +404,7 @@ static inline void da830_evm_init_nand(int mux_mode)
392 return; 404 return;
393 } 405 }
394 406
395 ret = da8xx_pinmux_setup(da830_evm_emif25_pins); 407 ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
396 if (ret) 408 if (ret)
397 pr_warning("da830_evm_init: emif25 mux setup failed: %d\n", 409 pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
398 ret); 410 ret);
@@ -412,7 +424,7 @@ static inline void da830_evm_init_lcdc(int mux_mode)
412{ 424{
413 int ret; 425 int ret;
414 426
415 ret = da8xx_pinmux_setup(da830_lcdcntl_pins); 427 ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
416 if (ret) 428 if (ret)
417 pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n", 429 pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
418 ret); 430 ret);
@@ -492,7 +504,7 @@ static __init void da830_evm_init(void)
492 pr_warning("da830_evm_init: edma registration failed: %d\n", 504 pr_warning("da830_evm_init: edma registration failed: %d\n",
493 ret); 505 ret);
494 506
495 ret = da8xx_pinmux_setup(da830_i2c0_pins); 507 ret = davinci_cfg_reg_list(da830_i2c0_pins);
496 if (ret) 508 if (ret)
497 pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n", 509 pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
498 ret); 510 ret);
@@ -508,7 +520,7 @@ static __init void da830_evm_init(void)
508 soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; 520 soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
509 soc_info->emac_pdata->rmii_en = 1; 521 soc_info->emac_pdata->rmii_en = 1;
510 522
511 ret = da8xx_pinmux_setup(da830_cpgmac_pins); 523 ret = davinci_cfg_reg_list(da830_cpgmac_pins);
512 if (ret) 524 if (ret)
513 pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n", 525 pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
514 ret); 526 ret);
@@ -527,7 +539,7 @@ static __init void da830_evm_init(void)
527 i2c_register_board_info(1, da830_evm_i2c_devices, 539 i2c_register_board_info(1, da830_evm_i2c_devices,
528 ARRAY_SIZE(da830_evm_i2c_devices)); 540 ARRAY_SIZE(da830_evm_i2c_devices));
529 541
530 ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins); 542 ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
531 if (ret) 543 if (ret)
532 pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n", 544 pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
533 ret); 545 ret);
@@ -549,14 +561,6 @@ static int __init da830_evm_console_init(void)
549console_initcall(da830_evm_console_init); 561console_initcall(da830_evm_console_init);
550#endif 562#endif
551 563
552static __init void da830_evm_irq_init(void)
553{
554 struct davinci_soc_info *soc_info = &davinci_soc_info;
555
556 cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
557 soc_info->intc_irq_prios);
558}
559
560static void __init da830_evm_map_io(void) 564static void __init da830_evm_map_io(void)
561{ 565{
562 da830_init(); 566 da830_init();
@@ -567,7 +571,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
567 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 571 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
568 .boot_params = (DA8XX_DDR_BASE + 0x100), 572 .boot_params = (DA8XX_DDR_BASE + 0x100),
569 .map_io = da830_evm_map_io, 573 .map_io = da830_evm_map_io,
570 .init_irq = da830_evm_irq_init, 574 .init_irq = cp_intc_init,
571 .timer = &davinci_timer, 575 .timer = &davinci_timer,
572 .init_machine = da830_evm_init, 576 .init_machine = da830_evm_init,
573MACHINE_END 577MACHINE_END
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 411284d0b0fa..abd04932917b 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -206,12 +206,12 @@ static __init void da850_evm_setup_nor_nand(void)
206 int ret = 0; 206 int ret = 0;
207 207
208 if (ui_card_detected & !HAS_MMC) { 208 if (ui_card_detected & !HAS_MMC) {
209 ret = da8xx_pinmux_setup(da850_nand_pins); 209 ret = davinci_cfg_reg_list(da850_nand_pins);
210 if (ret) 210 if (ret)
211 pr_warning("da850_evm_init: nand mux setup failed: " 211 pr_warning("da850_evm_init: nand mux setup failed: "
212 "%d\n", ret); 212 "%d\n", ret);
213 213
214 ret = da8xx_pinmux_setup(da850_nor_pins); 214 ret = davinci_cfg_reg_list(da850_nor_pins);
215 if (ret) 215 if (ret)
216 pr_warning("da850_evm_init: nor mux setup failed: %d\n", 216 pr_warning("da850_evm_init: nor mux setup failed: %d\n",
217 ret); 217 ret);
@@ -568,12 +568,12 @@ static int __init da850_evm_config_emac(void)
568 568
569 if (rmii_en) { 569 if (rmii_en) {
570 val |= BIT(8); 570 val |= BIT(8);
571 ret = da8xx_pinmux_setup(da850_rmii_pins); 571 ret = davinci_cfg_reg_list(da850_rmii_pins);
572 pr_info("EMAC: RMII PHY configured, MII PHY will not be" 572 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
573 " functional\n"); 573 " functional\n");
574 } else { 574 } else {
575 val &= ~BIT(8); 575 val &= ~BIT(8);
576 ret = da8xx_pinmux_setup(da850_cpgmac_pins); 576 ret = davinci_cfg_reg_list(da850_cpgmac_pins);
577 pr_info("EMAC: MII PHY configured, RMII PHY will not be" 577 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
578 " functional\n"); 578 " functional\n");
579 } 579 }
@@ -626,7 +626,7 @@ static __init void da850_evm_init(void)
626 pr_warning("da850_evm_init: edma registration failed: %d\n", 626 pr_warning("da850_evm_init: edma registration failed: %d\n",
627 ret); 627 ret);
628 628
629 ret = da8xx_pinmux_setup(da850_i2c0_pins); 629 ret = davinci_cfg_reg_list(da850_i2c0_pins);
630 if (ret) 630 if (ret)
631 pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n", 631 pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
632 ret); 632 ret);
@@ -643,7 +643,7 @@ static __init void da850_evm_init(void)
643 ret); 643 ret);
644 644
645 if (HAS_MMC) { 645 if (HAS_MMC) {
646 ret = da8xx_pinmux_setup(da850_mmcsd0_pins); 646 ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
647 if (ret) 647 if (ret)
648 pr_warning("da850_evm_init: mmcsd0 mux setup failed:" 648 pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
649 " %d\n", ret); 649 " %d\n", ret);
@@ -679,20 +679,20 @@ static __init void da850_evm_init(void)
679 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); 679 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
680 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); 680 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
681 681
682 ret = da8xx_pinmux_setup(da850_mcasp_pins); 682 ret = davinci_cfg_reg_list(da850_mcasp_pins);
683 if (ret) 683 if (ret)
684 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", 684 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
685 ret); 685 ret);
686 686
687 da8xx_register_mcasp(0, &da850_evm_snd_data); 687 da8xx_register_mcasp(0, &da850_evm_snd_data);
688 688
689 ret = da8xx_pinmux_setup(da850_lcdcntl_pins); 689 ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
690 if (ret) 690 if (ret)
691 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n", 691 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
692 ret); 692 ret);
693 693
694 /* Handle board specific muxing for LCD here */ 694 /* Handle board specific muxing for LCD here */
695 ret = da8xx_pinmux_setup(da850_evm_lcdc_pins); 695 ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
696 if (ret) 696 if (ret)
697 pr_warning("da850_evm_init: evm specific lcd mux setup " 697 pr_warning("da850_evm_init: evm specific lcd mux setup "
698 "failed: %d\n", ret); 698 "failed: %d\n", ret);
@@ -736,14 +736,6 @@ static int __init da850_evm_console_init(void)
736console_initcall(da850_evm_console_init); 736console_initcall(da850_evm_console_init);
737#endif 737#endif
738 738
739static __init void da850_evm_irq_init(void)
740{
741 struct davinci_soc_info *soc_info = &davinci_soc_info;
742
743 cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
744 soc_info->intc_irq_prios);
745}
746
747static void __init da850_evm_map_io(void) 739static void __init da850_evm_map_io(void)
748{ 740{
749 da850_init(); 741 da850_init();
@@ -754,7 +746,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
754 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 746 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
755 .boot_params = (DA8XX_DDR_BASE + 0x100), 747 .boot_params = (DA8XX_DDR_BASE + 0x100),
756 .map_io = da850_evm_map_io, 748 .map_io = da850_evm_map_io,
757 .init_irq = da850_evm_irq_init, 749 .init_irq = cp_intc_init,
758 .timer = &davinci_timer, 750 .timer = &davinci_timer,
759 .init_machine = da850_evm_init, 751 .init_machine = da850_evm_init,
760MACHINE_END 752MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index aa48e3f69715..a3191015efee 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -33,9 +33,6 @@
33#include <mach/mmc.h> 33#include <mach/mmc.h>
34#include <mach/usb.h> 34#include <mach/usb.h>
35 35
36#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
37#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
38
39/* NOTE: this is geared for the standard config, with a socketed 36/* NOTE: this is geared for the standard config, with a socketed
40 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you 37 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
41 * swap chips, maybe with a different block size, partitioning may 38 * swap chips, maybe with a different block size, partitioning may
@@ -86,12 +83,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
86 83
87static struct resource davinci_nand_resources[] = { 84static struct resource davinci_nand_resources[] = {
88 { 85 {
89 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, 86 .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
90 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, 87 .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
91 .flags = IORESOURCE_MEM, 88 .flags = IORESOURCE_MEM,
92 }, { 89 }, {
93 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, 90 .start = DM355_ASYNC_EMIF_CONTROL_BASE,
94 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, 91 .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
95 .flags = IORESOURCE_MEM, 92 .flags = IORESOURCE_MEM,
96 }, 93 },
97}; 94};
@@ -353,17 +350,12 @@ static __init void dm355_evm_init(void)
353 dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data); 350 dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data);
354} 351}
355 352
356static __init void dm355_evm_irq_init(void)
357{
358 davinci_irq_init();
359}
360
361MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") 353MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
362 .phys_io = IO_PHYS, 354 .phys_io = IO_PHYS,
363 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 355 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
364 .boot_params = (0x80000100), 356 .boot_params = (0x80000100),
365 .map_io = dm355_evm_map_io, 357 .map_io = dm355_evm_map_io,
366 .init_irq = dm355_evm_irq_init, 358 .init_irq = davinci_irq_init,
367 .timer = &davinci_timer, 359 .timer = &davinci_timer,
368 .init_machine = dm355_evm_init, 360 .init_machine = dm355_evm_init,
369MACHINE_END 361MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 21f32eb41e8c..f1d8132cf0c3 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -30,9 +30,6 @@
30#include <mach/mmc.h> 30#include <mach/mmc.h>
31#include <mach/usb.h> 31#include <mach/usb.h>
32 32
33#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
34#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
35
36/* NOTE: this is geared for the standard config, with a socketed 33/* NOTE: this is geared for the standard config, with a socketed
37 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you 34 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
38 * swap chips, maybe with a different block size, partitioning may 35 * swap chips, maybe with a different block size, partitioning may
@@ -82,12 +79,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
82 79
83static struct resource davinci_nand_resources[] = { 80static struct resource davinci_nand_resources[] = {
84 { 81 {
85 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, 82 .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
86 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, 83 .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
87 .flags = IORESOURCE_MEM, 84 .flags = IORESOURCE_MEM,
88 }, { 85 }, {
89 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, 86 .start = DM355_ASYNC_EMIF_CONTROL_BASE,
90 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, 87 .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
91 .flags = IORESOURCE_MEM, 88 .flags = IORESOURCE_MEM,
92 }, 89 },
93}; 90};
@@ -272,17 +269,12 @@ static __init void dm355_leopard_init(void)
272 ARRAY_SIZE(dm355_leopard_spi_info)); 269 ARRAY_SIZE(dm355_leopard_spi_info));
273} 270}
274 271
275static __init void dm355_leopard_irq_init(void)
276{
277 davinci_irq_init();
278}
279
280MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") 272MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
281 .phys_io = IO_PHYS, 273 .phys_io = IO_PHYS,
282 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 274 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
283 .boot_params = (0x80000100), 275 .boot_params = (0x80000100),
284 .map_io = dm355_leopard_map_io, 276 .map_io = dm355_leopard_map_io,
285 .init_irq = dm355_leopard_irq_init, 277 .init_irq = davinci_irq_init,
286 .timer = &davinci_timer, 278 .timer = &davinci_timer,
287 .init_machine = dm355_leopard_init, 279 .init_machine = dm355_leopard_init,
288MACHINE_END 280MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index df4ab2105869..98814e6a5987 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -54,11 +54,6 @@ static inline int have_tvp7002(void)
54 return 0; 54 return 0;
55} 55}
56 56
57
58#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
59#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
60#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
61
62#define DM365_EVM_PHY_MASK (0x2) 57#define DM365_EVM_PHY_MASK (0x2)
63#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 58#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
64 59
@@ -613,17 +608,12 @@ static __init void dm365_evm_init(void)
613 ARRAY_SIZE(dm365_evm_spi_info)); 608 ARRAY_SIZE(dm365_evm_spi_info));
614} 609}
615 610
616static __init void dm365_evm_irq_init(void)
617{
618 davinci_irq_init();
619}
620
621MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") 611MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
622 .phys_io = IO_PHYS, 612 .phys_io = IO_PHYS,
623 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 613 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
624 .boot_params = (0x80000100), 614 .boot_params = (0x80000100),
625 .map_io = dm365_evm_map_io, 615 .map_io = dm365_evm_map_io,
626 .init_irq = dm365_evm_irq_init, 616 .init_irq = davinci_irq_init,
627 .timer = &davinci_timer, 617 .timer = &davinci_timer,
628 .init_machine = dm365_evm_init, 618 .init_machine = dm365_evm_init,
629MACHINE_END 619MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 976e11b7fa4a..34c8b418cd72 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -41,14 +41,6 @@
41#define DM644X_EVM_PHY_MASK (0x2) 41#define DM644X_EVM_PHY_MASK (0x2)
42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
43 43
44#define DAVINCI_CFC_ATA_BASE 0x01C66000
45
46#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
47#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
48#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
49#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
50#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
51
52#define LXT971_PHY_ID (0x001378e2) 44#define LXT971_PHY_ID (0x001378e2)
53#define LXT971_PHY_MASK (0xfffffff0) 45#define LXT971_PHY_MASK (0xfffffff0)
54 46
@@ -92,8 +84,8 @@ static struct physmap_flash_data davinci_evm_norflash_data = {
92/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF 84/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
93 * limits addresses to 16M, so using addresses past 16M will wrap */ 85 * limits addresses to 16M, so using addresses past 16M will wrap */
94static struct resource davinci_evm_norflash_resource = { 86static struct resource davinci_evm_norflash_resource = {
95 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, 87 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
96 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, 88 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
97 .flags = IORESOURCE_MEM, 89 .flags = IORESOURCE_MEM,
98}; 90};
99 91
@@ -111,7 +103,7 @@ static struct platform_device davinci_evm_norflash_device = {
111 * It may used instead of the (default) NOR chip to boot, using TI's 103 * It may used instead of the (default) NOR chip to boot, using TI's
112 * tools to install the secondary boot loader (UBL) and U-Boot. 104 * tools to install the secondary boot loader (UBL) and U-Boot.
113 */ 105 */
114struct mtd_partition davinci_evm_nandflash_partition[] = { 106static struct mtd_partition davinci_evm_nandflash_partition[] = {
115 /* Bootloader layout depends on whose u-boot is installed, but we 107 /* Bootloader layout depends on whose u-boot is installed, but we
116 * can hide all the details. 108 * can hide all the details.
117 * - block 0 for u-boot environment ... in mainline u-boot 109 * - block 0 for u-boot environment ... in mainline u-boot
@@ -154,12 +146,12 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
154 146
155static struct resource davinci_evm_nandflash_resource[] = { 147static struct resource davinci_evm_nandflash_resource[] = {
156 { 148 {
157 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, 149 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
158 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, 150 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
159 .flags = IORESOURCE_MEM, 151 .flags = IORESOURCE_MEM,
160 }, { 152 }, {
161 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, 153 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
162 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, 154 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
163 .flags = IORESOURCE_MEM, 155 .flags = IORESOURCE_MEM,
164 }, 156 },
165}; 157};
@@ -258,32 +250,6 @@ static struct platform_device rtc_dev = {
258 .id = -1, 250 .id = -1,
259}; 251};
260 252
261static struct resource ide_resources[] = {
262 {
263 .start = DAVINCI_CFC_ATA_BASE,
264 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
265 .flags = IORESOURCE_MEM,
266 },
267 {
268 .start = IRQ_IDE,
269 .end = IRQ_IDE,
270 .flags = IORESOURCE_IRQ,
271 },
272};
273
274static u64 ide_dma_mask = DMA_BIT_MASK(32);
275
276static struct platform_device ide_dev = {
277 .name = "palm_bk3710",
278 .id = -1,
279 .resource = ide_resources,
280 .num_resources = ARRAY_SIZE(ide_resources),
281 .dev = {
282 .dma_mask = &ide_dma_mask,
283 .coherent_dma_mask = DMA_BIT_MASK(32),
284 },
285};
286
287static struct snd_platform_data dm644x_evm_snd_data; 253static struct snd_platform_data dm644x_evm_snd_data;
288 254
289/*----------------------------------------------------------------------*/ 255/*----------------------------------------------------------------------*/
@@ -704,10 +670,7 @@ static __init void davinci_evm_init(void)
704 pr_warning("WARNING: both IDE and Flash are " 670 pr_warning("WARNING: both IDE and Flash are "
705 "enabled, but they share AEMIF pins.\n" 671 "enabled, but they share AEMIF pins.\n"
706 "\tDisable IDE for NAND/NOR support.\n"); 672 "\tDisable IDE for NAND/NOR support.\n");
707 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 673 davinci_init_ide();
708 davinci_cfg_reg(DM644X_ATAEN);
709 davinci_cfg_reg(DM644X_HDIREN);
710 platform_device_register(&ide_dev);
711 } else if (HAS_NAND || HAS_NOR) { 674 } else if (HAS_NAND || HAS_NOR) {
712 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 675 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
713 davinci_cfg_reg(DM644X_ATAEN_DISABLE); 676 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
@@ -741,18 +704,13 @@ static __init void davinci_evm_init(void)
741 704
742} 705}
743 706
744static __init void davinci_evm_irq_init(void)
745{
746 davinci_irq_init();
747}
748
749MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") 707MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
750 /* Maintainer: MontaVista Software <source@mvista.com> */ 708 /* Maintainer: MontaVista Software <source@mvista.com> */
751 .phys_io = IO_PHYS, 709 .phys_io = IO_PHYS,
752 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 710 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
753 .boot_params = (DAVINCI_DDR_BASE + 0x100), 711 .boot_params = (DAVINCI_DDR_BASE + 0x100),
754 .map_io = davinci_evm_map_io, 712 .map_io = davinci_evm_map_io,
755 .init_irq = davinci_evm_irq_init, 713 .init_irq = davinci_irq_init,
756 .timer = &davinci_timer, 714 .timer = &davinci_timer,
757 .init_machine = davinci_evm_init, 715 .init_machine = davinci_evm_init,
758MACHINE_END 716MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 5ba3cb2daaa0..6d8889342c9f 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -80,17 +80,14 @@ static struct davinci_nand_pdata davinci_nand_data = {
80 .options = 0, 80 .options = 0,
81}; 81};
82 82
83#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
84#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
85
86static struct resource davinci_nand_resources[] = { 83static struct resource davinci_nand_resources[] = {
87 { 84 {
88 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, 85 .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
89 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, 86 .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
90 .flags = IORESOURCE_MEM, 87 .flags = IORESOURCE_MEM,
91 }, { 88 }, {
92 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, 89 .start = DM646X_ASYNC_EMIF_CONTROL_BASE,
93 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, 90 .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
94 .flags = IORESOURCE_MEM, 91 .flags = IORESOURCE_MEM,
95 }, 92 },
96}; 93};
@@ -736,17 +733,12 @@ static __init void evm_init(void)
736 platform_device_register(&davinci_nand_device); 733 platform_device_register(&davinci_nand_device);
737 734
738 if (HAS_ATA) 735 if (HAS_ATA)
739 dm646x_init_ide(); 736 davinci_init_ide();
740 737
741 soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; 738 soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
742 soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; 739 soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
743} 740}
744 741
745static __init void davinci_dm646x_evm_irq_init(void)
746{
747 davinci_irq_init();
748}
749
750#define DM646X_EVM_REF_FREQ 27000000 742#define DM646X_EVM_REF_FREQ 27000000
751#define DM6467T_EVM_REF_FREQ 33000000 743#define DM6467T_EVM_REF_FREQ 33000000
752 744
@@ -763,7 +755,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
763 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 755 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
764 .boot_params = (0x80000100), 756 .boot_params = (0x80000100),
765 .map_io = davinci_map_io, 757 .map_io = davinci_map_io,
766 .init_irq = davinci_dm646x_evm_irq_init, 758 .init_irq = davinci_irq_init,
767 .timer = &davinci_timer, 759 .timer = &davinci_timer,
768 .init_machine = evm_init, 760 .init_machine = evm_init,
769MACHINE_END 761MACHINE_END
@@ -773,7 +765,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
773 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 765 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
774 .boot_params = (0x80000100), 766 .boot_params = (0x80000100),
775 .map_io = davinci_map_io, 767 .map_io = davinci_map_io,
776 .init_irq = davinci_dm646x_evm_irq_init, 768 .init_irq = davinci_irq_init,
777 .timer = &davinci_timer, 769 .timer = &davinci_timer,
778 .init_machine = evm_init, 770 .init_machine = evm_init,
779MACHINE_END 771MACHINE_END
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index bd9ca079b69d..4c30e929bbf9 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -31,6 +31,7 @@
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32 32
33#include <mach/dm644x.h> 33#include <mach/dm644x.h>
34#include <mach/common.h>
34#include <mach/i2c.h> 35#include <mach/i2c.h>
35#include <mach/serial.h> 36#include <mach/serial.h>
36#include <mach/mux.h> 37#include <mach/mux.h>
@@ -41,11 +42,6 @@
41#define NEUROS_OSD2_PHY_MASK 0x2 42#define NEUROS_OSD2_PHY_MASK 0x2
42#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ 43#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
43 44
44#define DAVINCI_CFC_ATA_BASE 0x01C66000
45
46#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
47#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
48
49#define LXT971_PHY_ID 0x001378e2 45#define LXT971_PHY_ID 0x001378e2
50#define LXT971_PHY_MASK 0xfffffff0 46#define LXT971_PHY_MASK 0xfffffff0
51 47
@@ -60,7 +56,7 @@
60 56
61#define NAND_BLOCK_SIZE SZ_128K 57#define NAND_BLOCK_SIZE SZ_128K
62 58
63struct mtd_partition davinci_ntosd2_nandflash_partition[] = { 59static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
64 { 60 {
65 /* UBL (a few copies) plus U-Boot */ 61 /* UBL (a few copies) plus U-Boot */
66 .name = "bootloader", 62 .name = "bootloader",
@@ -98,12 +94,12 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
98 94
99static struct resource davinci_ntosd2_nandflash_resource[] = { 95static struct resource davinci_ntosd2_nandflash_resource[] = {
100 { 96 {
101 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, 97 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
102 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, 98 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
103 .flags = IORESOURCE_MEM, 99 .flags = IORESOURCE_MEM,
104 }, { 100 }, {
105 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, 101 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
106 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, 102 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
107 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
108 }, 104 },
109}; 105};
@@ -130,32 +126,6 @@ static struct platform_device davinci_fb_device = {
130 .num_resources = 0, 126 .num_resources = 0,
131}; 127};
132 128
133static struct resource ide_resources[] = {
134 {
135 .start = DAVINCI_CFC_ATA_BASE,
136 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
137 .flags = IORESOURCE_MEM,
138 },
139 {
140 .start = IRQ_IDE,
141 .end = IRQ_IDE,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static u64 ide_dma_mask = DMA_BIT_MASK(32);
147
148static struct platform_device ide_dev = {
149 .name = "palm_bk3710",
150 .id = -1,
151 .resource = ide_resources,
152 .num_resources = ARRAY_SIZE(ide_resources),
153 .dev = {
154 .dma_mask = &ide_dma_mask,
155 .coherent_dma_mask = DMA_BIT_MASK(32),
156 },
157};
158
159static struct snd_platform_data dm644x_ntosd2_snd_data; 129static struct snd_platform_data dm644x_ntosd2_snd_data;
160 130
161static struct gpio_led ntosd2_leds[] = { 131static struct gpio_led ntosd2_leds[] = {
@@ -259,10 +229,7 @@ static __init void davinci_ntosd2_init(void)
259 pr_warning("WARNING: both IDE and Flash are " 229 pr_warning("WARNING: both IDE and Flash are "
260 "enabled, but they share AEMIF pins.\n" 230 "enabled, but they share AEMIF pins.\n"
261 "\tDisable IDE for NAND/NOR support.\n"); 231 "\tDisable IDE for NAND/NOR support.\n");
262 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 232 davinci_init_ide();
263 davinci_cfg_reg(DM644X_ATAEN);
264 davinci_cfg_reg(DM644X_HDIREN);
265 platform_device_register(&ide_dev);
266 } else if (HAS_NAND) { 233 } else if (HAS_NAND) {
267 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 234 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
268 davinci_cfg_reg(DM644X_ATAEN_DISABLE); 235 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
@@ -306,18 +273,13 @@ static __init void davinci_ntosd2_init(void)
306 davinci_setup_mmc(0, &davinci_ntosd2_mmc_config); 273 davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
307} 274}
308 275
309static __init void davinci_ntosd2_irq_init(void)
310{
311 davinci_irq_init();
312}
313
314MACHINE_START(NEUROS_OSD2, "Neuros OSD2") 276MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
315 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */ 277 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
316 .phys_io = IO_PHYS, 278 .phys_io = IO_PHYS,
317 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 279 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
318 .boot_params = (DAVINCI_DDR_BASE + 0x100), 280 .boot_params = (DAVINCI_DDR_BASE + 0x100),
319 .map_io = davinci_ntosd2_map_io, 281 .map_io = davinci_ntosd2_map_io,
320 .init_irq = davinci_ntosd2_irq_init, 282 .init_irq = davinci_irq_init,
321 .timer = &davinci_timer, 283 .timer = &davinci_timer,
322 .init_machine = davinci_ntosd2_init, 284 .init_machine = davinci_ntosd2_init,
323MACHINE_END 285MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 08d373bfcc8a..23e664a1a802 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -45,10 +45,7 @@
45#define SFFSDR_PHY_MASK (0x2) 45#define SFFSDR_PHY_MASK (0x2)
46#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 46#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
47 47
48#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 48static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
49#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
50
51struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
52 /* U-Boot Environment: Block 0 49 /* U-Boot Environment: Block 0
53 * UBL: Block 1 50 * UBL: Block 1
54 * U-Boot: Blocks 6-7 (256 kb) 51 * U-Boot: Blocks 6-7 (256 kb)
@@ -76,12 +73,12 @@ static struct flash_platform_data davinci_sffsdr_nandflash_data = {
76 73
77static struct resource davinci_sffsdr_nandflash_resource[] = { 74static struct resource davinci_sffsdr_nandflash_resource[] = {
78 { 75 {
79 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, 76 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
80 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, 77 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
81 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
82 }, { 79 }, {
83 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, 80 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
84 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, 81 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
85 .flags = IORESOURCE_MEM, 82 .flags = IORESOURCE_MEM,
86 }, 83 },
87}; 84};
@@ -155,18 +152,13 @@ static __init void davinci_sffsdr_init(void)
155 davinci_cfg_reg(DM644X_VLYNQWD); 152 davinci_cfg_reg(DM644X_VLYNQWD);
156} 153}
157 154
158static __init void davinci_sffsdr_irq_init(void)
159{
160 davinci_irq_init();
161}
162
163MACHINE_START(SFFSDR, "Lyrtech SFFSDR") 155MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
164 /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */ 156 /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
165 .phys_io = IO_PHYS, 157 .phys_io = IO_PHYS,
166 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 158 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
167 .boot_params = (DAVINCI_DDR_BASE + 0x100), 159 .boot_params = (DAVINCI_DDR_BASE + 0x100),
168 .map_io = davinci_sffsdr_map_io, 160 .map_io = davinci_sffsdr_map_io,
169 .init_irq = davinci_sffsdr_irq_init, 161 .init_irq = davinci_irq_init,
170 .timer = &davinci_timer, 162 .timer = &davinci_timer,
171 .init_machine = davinci_sffsdr_init, 163 .init_machine = davinci_sffsdr_init,
172MACHINE_END 164MACHINE_END
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
index aec375690543..ba8b12b2913b 100644
--- a/arch/arm/mach-davinci/cdce949.c
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -19,6 +19,7 @@
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20 20
21#include <mach/clock.h> 21#include <mach/clock.h>
22#include <mach/cdce949.h>
22 23
23#include "clock.h" 24#include "clock.h"
24 25
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index bf6218ee94e1..054c303caead 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -22,6 +22,7 @@
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24 24
25#include <mach/clock.h>
25#include <mach/psc.h> 26#include <mach/psc.h>
26#include <mach/cputype.h> 27#include <mach/cputype.h>
27#include "clock.h" 28#include "clock.h"
@@ -42,7 +43,8 @@ static void __clk_enable(struct clk *clk)
42 if (clk->parent) 43 if (clk->parent)
43 __clk_enable(clk->parent); 44 __clk_enable(clk->parent);
44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) 45 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
45 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1); 46 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
47 PSC_STATE_ENABLE);
46} 48}
47 49
48static void __clk_disable(struct clk *clk) 50static void __clk_disable(struct clk *clk)
@@ -51,7 +53,9 @@ static void __clk_disable(struct clk *clk)
51 return; 53 return;
52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && 54 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
53 (clk->flags & CLK_PSC)) 55 (clk->flags & CLK_PSC))
54 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0); 56 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
57 (clk->flags & PSC_SWRSTDISABLE) ?
58 PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
55 if (clk->parent) 59 if (clk->parent)
56 __clk_disable(clk->parent); 60 __clk_disable(clk->parent);
57} 61}
@@ -233,7 +237,10 @@ static int __init clk_disable_unused(void)
233 continue; 237 continue;
234 238
235 pr_info("Clocks: disable unused %s\n", ck->name); 239 pr_info("Clocks: disable unused %s\n", ck->name);
236 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0); 240
241 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
242 (ck->flags & PSC_SWRSTDISABLE) ?
243 PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
237 } 244 }
238 spin_unlock_irq(&clockfw_lock); 245 spin_unlock_irq(&clockfw_lock);
239 246
@@ -272,7 +279,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
272 279
273 v = __raw_readl(pll->base + clk->div_reg); 280 v = __raw_readl(pll->base + clk->div_reg);
274 if (v & PLLDIV_EN) { 281 if (v & PLLDIV_EN) {
275 plldiv = (v & PLLDIV_RATIO_MASK) + 1; 282 plldiv = (v & pll->div_ratio_mask) + 1;
276 if (plldiv) 283 if (plldiv)
277 rate /= plldiv; 284 rate /= plldiv;
278 } 285 }
@@ -295,7 +302,6 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
295 struct pll_data *pll = clk->pll_data; 302 struct pll_data *pll = clk->pll_data;
296 unsigned long rate = clk->rate; 303 unsigned long rate = clk->rate;
297 304
298 pll->base = IO_ADDRESS(pll->phys_base);
299 ctrl = __raw_readl(pll->base + PLLCTL); 305 ctrl = __raw_readl(pll->base + PLLCTL);
300 rate = pll->input_rate = clk->parent->rate; 306 rate = pll->input_rate = clk->parent->rate;
301 307
@@ -312,7 +318,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
312 if (pll->flags & PLL_HAS_PREDIV) { 318 if (pll->flags & PLL_HAS_PREDIV) {
313 prediv = __raw_readl(pll->base + PREDIV); 319 prediv = __raw_readl(pll->base + PREDIV);
314 if (prediv & PLLDIV_EN) 320 if (prediv & PLLDIV_EN)
315 prediv = (prediv & PLLDIV_RATIO_MASK) + 1; 321 prediv = (prediv & pll->div_ratio_mask) + 1;
316 else 322 else
317 prediv = 1; 323 prediv = 1;
318 } 324 }
@@ -324,7 +330,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
324 if (pll->flags & PLL_HAS_POSTDIV) { 330 if (pll->flags & PLL_HAS_POSTDIV) {
325 postdiv = __raw_readl(pll->base + POSTDIV); 331 postdiv = __raw_readl(pll->base + POSTDIV);
326 if (postdiv & PLLDIV_EN) 332 if (postdiv & PLLDIV_EN)
327 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; 333 postdiv = (postdiv & pll->div_ratio_mask) + 1;
328 else 334 else
329 postdiv = 1; 335 postdiv = 1;
330 } 336 }
@@ -451,6 +457,18 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
451 clk->recalc = clk_leafclk_recalc; 457 clk->recalc = clk_leafclk_recalc;
452 } 458 }
453 459
460 if (clk->pll_data) {
461 struct pll_data *pll = clk->pll_data;
462
463 if (!pll->div_ratio_mask)
464 pll->div_ratio_mask = PLLDIV_RATIO_MASK;
465
466 if (pll->phys_base && !pll->base) {
467 pll->base = ioremap(pll->phys_base, SZ_4K);
468 WARN_ON(!pll->base);
469 }
470 }
471
454 if (clk->recalc) 472 if (clk->recalc)
455 clk->rate = clk->recalc(clk); 473 clk->rate = clk->recalc(clk);
456 474
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index aa0a61150325..01e36483ac3d 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -76,6 +76,7 @@ struct pll_data {
76 u32 num; 76 u32 num;
77 u32 flags; 77 u32 flags;
78 u32 input_rate; 78 u32 input_rate;
79 u32 div_ratio_mask;
79}; 80};
80#define PLL_HAS_PREDIV 0x01 81#define PLL_HAS_PREDIV 0x01
81#define PLL_HAS_POSTDIV 0x02 82#define PLL_HAS_POSTDIV 0x02
@@ -101,10 +102,11 @@ struct clk {
101 102
102/* Clock flags: SoC-specific flags start at BIT(16) */ 103/* Clock flags: SoC-specific flags start at BIT(16) */
103#define ALWAYS_ENABLED BIT(1) 104#define ALWAYS_ENABLED BIT(1)
104#define CLK_PSC BIT(2) 105#define CLK_PSC BIT(2)
105#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ 106#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
106#define CLK_PLL BIT(4) /* PLL-derived clock */ 107#define CLK_PLL BIT(4) /* PLL-derived clock */
107#define PRE_PLL BIT(5) /* source is before PLL mult/div */ 108#define PRE_PLL BIT(5) /* source is before PLL mult/div */
109#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
108 110
109#define CLK(dev, con, ck) \ 111#define CLK(dev, con, ck) \
110 { \ 112 { \
@@ -118,6 +120,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
118 unsigned int mult, unsigned int postdiv); 120 unsigned int mult, unsigned int postdiv);
119 121
120extern struct platform_device davinci_wdt_device; 122extern struct platform_device davinci_wdt_device;
123extern void davinci_watchdog_reset(struct platform_device *);
121 124
122#endif 125#endif
123 126
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 94f27cbcd55a..1d2557394235 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -37,26 +37,43 @@ void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context)
37 pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr); 37 pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
38} 38}
39 39
40static struct davinci_id * __init davinci_get_id(u32 jtag_id) 40static int __init davinci_init_id(struct davinci_soc_info *soc_info)
41{ 41{
42 int i; 42 int i;
43 struct davinci_id *dip; 43 struct davinci_id *dip;
44 u8 variant = (jtag_id & 0xf0000000) >> 28; 44 u8 variant;
45 u16 part_no = (jtag_id & 0x0ffff000) >> 12; 45 u16 part_no;
46 void __iomem *base;
47
48 base = ioremap(soc_info->jtag_id_reg, SZ_4K);
49 if (!base) {
50 pr_err("Unable to map JTAG ID register\n");
51 return -ENOMEM;
52 }
53
54 soc_info->jtag_id = __raw_readl(base);
55 iounmap(base);
56
57 variant = (soc_info->jtag_id & 0xf0000000) >> 28;
58 part_no = (soc_info->jtag_id & 0x0ffff000) >> 12;
46 59
47 for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num; 60 for (i = 0, dip = soc_info->ids; i < soc_info->ids_num;
48 i++, dip++) 61 i++, dip++)
49 /* Don't care about the manufacturer right now */ 62 /* Don't care about the manufacturer right now */
50 if ((dip->part_no == part_no) && (dip->variant == variant)) 63 if ((dip->part_no == part_no) && (dip->variant == variant)) {
51 return dip; 64 soc_info->cpu_id = dip->cpu_id;
52 65 pr_info("DaVinci %s variant 0x%x\n", dip->name,
53 return NULL; 66 dip->variant);
67 return 0;
68 }
69
70 pr_err("Unknown DaVinci JTAG ID 0x%x\n", soc_info->jtag_id);
71 return -EINVAL;
54} 72}
55 73
56void __init davinci_common_init(struct davinci_soc_info *soc_info) 74void __init davinci_common_init(struct davinci_soc_info *soc_info)
57{ 75{
58 int ret; 76 int ret;
59 struct davinci_id *dip;
60 77
61 if (!soc_info) { 78 if (!soc_info) {
62 ret = -EINVAL; 79 ret = -EINVAL;
@@ -77,22 +94,16 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
77 local_flush_tlb_all(); 94 local_flush_tlb_all();
78 flush_cache_all(); 95 flush_cache_all();
79 96
97 if (!davinci_soc_info.reset)
98 davinci_soc_info.reset = davinci_watchdog_reset;
99
80 /* 100 /*
81 * We want to check CPU revision early for cpu_is_xxxx() macros. 101 * We want to check CPU revision early for cpu_is_xxxx() macros.
82 * IO space mapping must be initialized before we can do that. 102 * IO space mapping must be initialized before we can do that.
83 */ 103 */
84 davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base); 104 ret = davinci_init_id(&davinci_soc_info);
85 105 if (ret < 0)
86 dip = davinci_get_id(davinci_soc_info.jtag_id);
87 if (!dip) {
88 ret = -EINVAL;
89 pr_err("Unknown DaVinci JTAG ID 0x%x\n",
90 davinci_soc_info.jtag_id);
91 goto err; 106 goto err;
92 }
93
94 davinci_soc_info.cpu_id = dip->cpu_id;
95 pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant);
96 107
97 if (davinci_soc_info.cpu_clks) { 108 if (davinci_soc_info.cpu_clks) {
98 ret = davinci_clk_init(davinci_soc_info.cpu_clks); 109 ret = davinci_clk_init(davinci_soc_info.cpu_clks);
@@ -101,8 +112,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
101 goto err; 112 goto err;
102 } 113 }
103 114
104 davinci_intc_base = davinci_soc_info.intc_base;
105 davinci_intc_type = davinci_soc_info.intc_type;
106 return; 115 return;
107 116
108err: 117err:
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 37311d1830eb..bb4c40ecb803 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -13,18 +13,17 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/io.h> 14#include <linux/io.h>
15 15
16#include <mach/common.h>
16#include <mach/cp_intc.h> 17#include <mach/cp_intc.h>
17 18
18static void __iomem *cp_intc_base;
19
20static inline unsigned int cp_intc_read(unsigned offset) 19static inline unsigned int cp_intc_read(unsigned offset)
21{ 20{
22 return __raw_readl(cp_intc_base + offset); 21 return __raw_readl(davinci_intc_base + offset);
23} 22}
24 23
25static inline void cp_intc_write(unsigned long value, unsigned offset) 24static inline void cp_intc_write(unsigned long value, unsigned offset)
26{ 25{
27 __raw_writel(value, cp_intc_base + offset); 26 __raw_writel(value, davinci_intc_base + offset);
28} 27}
29 28
30static void cp_intc_ack_irq(unsigned int irq) 29static void cp_intc_ack_irq(unsigned int irq)
@@ -100,13 +99,18 @@ static struct irq_chip cp_intc_irq_chip = {
100 .set_wake = cp_intc_set_wake, 99 .set_wake = cp_intc_set_wake,
101}; 100};
102 101
103void __init cp_intc_init(void __iomem *base, unsigned short num_irq, 102void __init cp_intc_init(void)
104 u8 *irq_prio)
105{ 103{
104 unsigned long num_irq = davinci_soc_info.intc_irq_num;
105 u8 *irq_prio = davinci_soc_info.intc_irq_prios;
106 u32 *host_map = davinci_soc_info.intc_host_map;
106 unsigned num_reg = BITS_TO_LONGS(num_irq); 107 unsigned num_reg = BITS_TO_LONGS(num_irq);
107 int i; 108 int i;
108 109
109 cp_intc_base = base; 110 davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
111 davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
112 if (WARN_ON(!davinci_intc_base))
113 return;
110 114
111 cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); 115 cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
112 116
@@ -157,6 +161,10 @@ void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
157 cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i)); 161 cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
158 } 162 }
159 163
164 if (host_map)
165 for (i = 0; host_map[i] != -1; i++)
166 cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
167
160 /* Set up genirq dispatching for cp_intc */ 168 /* Set up genirq dispatching for cp_intc */
161 for (i = 0; i < num_irq; i++) { 169 for (i = 0; i < num_irq; i++) {
162 set_irq_chip(i, &cp_intc_irq_chip); 170 set_irq_chip(i, &cp_intc_irq_chip);
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index e8cb982f5e8e..23e9eda5a377 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -19,6 +19,7 @@
19#include <mach/common.h> 19#include <mach/common.h>
20#include <mach/time.h> 20#include <mach/time.h>
21#include <mach/da8xx.h> 21#include <mach/da8xx.h>
22#include <mach/gpio.h>
22 23
23#include "clock.h" 24#include "clock.h"
24#include "mux.h" 25#include "mux.h"
@@ -1126,10 +1127,7 @@ static struct map_desc da830_io_desc[] = {
1126 }, 1127 },
1127}; 1128};
1128 1129
1129static void __iomem *da830_psc_bases[] = { 1130static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
1130 IO_ADDRESS(DA8XX_PSC0_BASE),
1131 IO_ADDRESS(DA8XX_PSC1_BASE),
1132};
1133 1131
1134/* Contents of JTAG ID register used to identify exact cpu type */ 1132/* Contents of JTAG ID register used to identify exact cpu type */
1135static struct davinci_id da830_ids[] = { 1133static struct davinci_id da830_ids[] = {
@@ -1158,14 +1156,14 @@ static struct davinci_id da830_ids[] = {
1158 1156
1159static struct davinci_timer_instance da830_timer_instance[2] = { 1157static struct davinci_timer_instance da830_timer_instance[2] = {
1160 { 1158 {
1161 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), 1159 .base = DA8XX_TIMER64P0_BASE,
1162 .bottom_irq = IRQ_DA8XX_TINT12_0, 1160 .bottom_irq = IRQ_DA8XX_TINT12_0,
1163 .top_irq = IRQ_DA8XX_TINT34_0, 1161 .top_irq = IRQ_DA8XX_TINT34_0,
1164 .cmp_off = DA830_CMP12_0, 1162 .cmp_off = DA830_CMP12_0,
1165 .cmp_irq = IRQ_DA830_T12CMPINT0_0, 1163 .cmp_irq = IRQ_DA830_T12CMPINT0_0,
1166 }, 1164 },
1167 { 1165 {
1168 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), 1166 .base = DA8XX_TIMER64P1_BASE,
1169 .bottom_irq = IRQ_DA8XX_TINT12_1, 1167 .bottom_irq = IRQ_DA8XX_TINT12_1,
1170 .top_irq = IRQ_DA8XX_TINT34_1, 1168 .top_irq = IRQ_DA8XX_TINT34_1,
1171 .cmp_off = DA830_CMP12_0, 1169 .cmp_off = DA830_CMP12_0,
@@ -1187,34 +1185,33 @@ static struct davinci_timer_info da830_timer_info = {
1187static struct davinci_soc_info davinci_soc_info_da830 = { 1185static struct davinci_soc_info davinci_soc_info_da830 = {
1188 .io_desc = da830_io_desc, 1186 .io_desc = da830_io_desc,
1189 .io_desc_num = ARRAY_SIZE(da830_io_desc), 1187 .io_desc_num = ARRAY_SIZE(da830_io_desc),
1188 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1190 .ids = da830_ids, 1189 .ids = da830_ids,
1191 .ids_num = ARRAY_SIZE(da830_ids), 1190 .ids_num = ARRAY_SIZE(da830_ids),
1192 .cpu_clks = da830_clks, 1191 .cpu_clks = da830_clks,
1193 .psc_bases = da830_psc_bases, 1192 .psc_bases = da830_psc_bases,
1194 .psc_bases_num = ARRAY_SIZE(da830_psc_bases), 1193 .psc_bases_num = ARRAY_SIZE(da830_psc_bases),
1194 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
1195 .pinmux_pins = da830_pins, 1195 .pinmux_pins = da830_pins,
1196 .pinmux_pins_num = ARRAY_SIZE(da830_pins), 1196 .pinmux_pins_num = ARRAY_SIZE(da830_pins),
1197 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, 1197 .intc_base = DA8XX_CP_INTC_BASE,
1198 .intc_type = DAVINCI_INTC_TYPE_CP_INTC, 1198 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1199 .intc_irq_prios = da830_default_priorities, 1199 .intc_irq_prios = da830_default_priorities,
1200 .intc_irq_num = DA830_N_CP_INTC_IRQ, 1200 .intc_irq_num = DA830_N_CP_INTC_IRQ,
1201 .timer_info = &da830_timer_info, 1201 .timer_info = &da830_timer_info,
1202 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), 1202 .gpio_type = GPIO_TYPE_DAVINCI,
1203 .gpio_base = DA8XX_GPIO_BASE,
1203 .gpio_num = 128, 1204 .gpio_num = 128,
1204 .gpio_irq = IRQ_DA8XX_GPIO0, 1205 .gpio_irq = IRQ_DA8XX_GPIO0,
1205 .serial_dev = &da8xx_serial_device, 1206 .serial_dev = &da8xx_serial_device,
1206 .emac_pdata = &da8xx_emac_pdata, 1207 .emac_pdata = &da8xx_emac_pdata,
1208 .reset_device = &da8xx_wdt_device,
1207}; 1209};
1208 1210
1209void __init da830_init(void) 1211void __init da830_init(void)
1210{ 1212{
1211 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1212 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1213 return;
1214
1215 davinci_soc_info_da830.jtag_id_base =
1216 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1217 davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
1218
1219 davinci_common_init(&davinci_soc_info_da830); 1213 davinci_common_init(&davinci_soc_info_da830);
1214
1215 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1216 WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
1220} 1217}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index d0fd7566712a..6b8331bf8cf3 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -27,6 +27,7 @@
27#include <mach/da8xx.h> 27#include <mach/da8xx.h>
28#include <mach/cpufreq.h> 28#include <mach/cpufreq.h>
29#include <mach/pm.h> 29#include <mach/pm.h>
30#include <mach/gpio.h>
30 31
31#include "clock.h" 32#include "clock.h"
32#include "mux.h" 33#include "mux.h"
@@ -781,10 +782,7 @@ static struct map_desc da850_io_desc[] = {
781 }, 782 },
782}; 783};
783 784
784static void __iomem *da850_psc_bases[] = { 785static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
785 IO_ADDRESS(DA8XX_PSC0_BASE),
786 IO_ADDRESS(DA8XX_PSC1_BASE),
787};
788 786
789/* Contents of JTAG ID register used to identify exact cpu type */ 787/* Contents of JTAG ID register used to identify exact cpu type */
790static struct davinci_id da850_ids[] = { 788static struct davinci_id da850_ids[] = {
@@ -799,22 +797,22 @@ static struct davinci_id da850_ids[] = {
799 797
800static struct davinci_timer_instance da850_timer_instance[4] = { 798static struct davinci_timer_instance da850_timer_instance[4] = {
801 { 799 {
802 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), 800 .base = DA8XX_TIMER64P0_BASE,
803 .bottom_irq = IRQ_DA8XX_TINT12_0, 801 .bottom_irq = IRQ_DA8XX_TINT12_0,
804 .top_irq = IRQ_DA8XX_TINT34_0, 802 .top_irq = IRQ_DA8XX_TINT34_0,
805 }, 803 },
806 { 804 {
807 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), 805 .base = DA8XX_TIMER64P1_BASE,
808 .bottom_irq = IRQ_DA8XX_TINT12_1, 806 .bottom_irq = IRQ_DA8XX_TINT12_1,
809 .top_irq = IRQ_DA8XX_TINT34_1, 807 .top_irq = IRQ_DA8XX_TINT34_1,
810 }, 808 },
811 { 809 {
812 .base = IO_ADDRESS(DA850_TIMER64P2_BASE), 810 .base = DA850_TIMER64P2_BASE,
813 .bottom_irq = IRQ_DA850_TINT12_2, 811 .bottom_irq = IRQ_DA850_TINT12_2,
814 .top_irq = IRQ_DA850_TINT34_2, 812 .top_irq = IRQ_DA850_TINT34_2,
815 }, 813 },
816 { 814 {
817 .base = IO_ADDRESS(DA850_TIMER64P3_BASE), 815 .base = DA850_TIMER64P3_BASE,
818 .bottom_irq = IRQ_DA850_TINT12_3, 816 .bottom_irq = IRQ_DA850_TINT12_3,
819 .top_irq = IRQ_DA850_TINT34_3, 817 .top_irq = IRQ_DA850_TINT34_3,
820 }, 818 },
@@ -1072,31 +1070,37 @@ no_ddrpll_mem:
1072static struct davinci_soc_info davinci_soc_info_da850 = { 1070static struct davinci_soc_info davinci_soc_info_da850 = {
1073 .io_desc = da850_io_desc, 1071 .io_desc = da850_io_desc,
1074 .io_desc_num = ARRAY_SIZE(da850_io_desc), 1072 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1073 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1075 .ids = da850_ids, 1074 .ids = da850_ids,
1076 .ids_num = ARRAY_SIZE(da850_ids), 1075 .ids_num = ARRAY_SIZE(da850_ids),
1077 .cpu_clks = da850_clks, 1076 .cpu_clks = da850_clks,
1078 .psc_bases = da850_psc_bases, 1077 .psc_bases = da850_psc_bases,
1079 .psc_bases_num = ARRAY_SIZE(da850_psc_bases), 1078 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1079 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
1080 .pinmux_pins = da850_pins, 1080 .pinmux_pins = da850_pins,
1081 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 1081 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1082 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, 1082 .intc_base = DA8XX_CP_INTC_BASE,
1083 .intc_type = DAVINCI_INTC_TYPE_CP_INTC, 1083 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1084 .intc_irq_prios = da850_default_priorities, 1084 .intc_irq_prios = da850_default_priorities,
1085 .intc_irq_num = DA850_N_CP_INTC_IRQ, 1085 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1086 .timer_info = &da850_timer_info, 1086 .timer_info = &da850_timer_info,
1087 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), 1087 .gpio_type = GPIO_TYPE_DAVINCI,
1088 .gpio_base = DA8XX_GPIO_BASE,
1088 .gpio_num = 144, 1089 .gpio_num = 144,
1089 .gpio_irq = IRQ_DA8XX_GPIO0, 1090 .gpio_irq = IRQ_DA8XX_GPIO0,
1090 .serial_dev = &da8xx_serial_device, 1091 .serial_dev = &da8xx_serial_device,
1091 .emac_pdata = &da8xx_emac_pdata, 1092 .emac_pdata = &da8xx_emac_pdata,
1092 .sram_dma = DA8XX_ARM_RAM_BASE, 1093 .sram_dma = DA8XX_ARM_RAM_BASE,
1093 .sram_len = SZ_8K, 1094 .sram_len = SZ_8K,
1095 .reset_device = &da8xx_wdt_device,
1094}; 1096};
1095 1097
1096void __init da850_init(void) 1098void __init da850_init(void)
1097{ 1099{
1098 unsigned int v; 1100 unsigned int v;
1099 1101
1102 davinci_common_init(&davinci_soc_info_da850);
1103
1100 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); 1104 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1101 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) 1105 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1102 return; 1106 return;
@@ -1105,12 +1109,6 @@ void __init da850_init(void)
1105 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) 1109 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1106 return; 1110 return;
1107 1111
1108 davinci_soc_info_da850.jtag_id_base =
1109 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1110 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
1111
1112 davinci_common_init(&davinci_soc_info_da850);
1113
1114 /* 1112 /*
1115 * Move the clock source of Async3 domain to PLL1 SYSCLK2. 1113 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1116 * This helps keeping the peripherals on this domain insulated 1114 * This helps keeping the peripherals on this domain insulated
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 0a96791d3b0f..8cda729be273 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -326,7 +326,7 @@ static struct resource da8xx_watchdog_resources[] = {
326 }, 326 },
327}; 327};
328 328
329struct platform_device davinci_wdt_device = { 329struct platform_device da8xx_wdt_device = {
330 .name = "watchdog", 330 .name = "watchdog",
331 .id = -1, 331 .id = -1,
332 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 332 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
@@ -335,7 +335,7 @@ struct platform_device davinci_wdt_device = {
335 335
336int __init da8xx_register_watchdog(void) 336int __init da8xx_register_watchdog(void)
337{ 337{
338 return platform_device_register(&davinci_wdt_device); 338 return platform_device_register(&da8xx_wdt_device);
339} 339}
340 340
341static struct resource da8xx_emac_resources[] = { 341static struct resource da8xx_emac_resources[] = {
@@ -584,10 +584,17 @@ static struct platform_device da8xx_rtc_device = {
584int da8xx_register_rtc(void) 584int da8xx_register_rtc(void)
585{ 585{
586 int ret; 586 int ret;
587 void __iomem *base;
588
589 base = ioremap(DA8XX_RTC_BASE, SZ_4K);
590 if (WARN_ON(!base))
591 return -ENOMEM;
587 592
588 /* Unlock the rtc's registers */ 593 /* Unlock the rtc's registers */
589 __raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c)); 594 __raw_writel(0x83e70b13, base + 0x6c);
590 __raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70)); 595 __raw_writel(0x95a4f1e0, base + 0x70);
596
597 iounmap(base);
591 598
592 ret = platform_device_register(&da8xx_rtc_device); 599 ret = platform_device_register(&da8xx_rtc_device);
593 if (!ret) 600 if (!ret)
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 147949650c25..8b7201e4c79c 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,7 +23,10 @@
23#include <mach/mmc.h> 23#include <mach/mmc.h>
24#include <mach/time.h> 24#include <mach/time.h>
25 25
26#include "clock.h"
27
26#define DAVINCI_I2C_BASE 0x01C21000 28#define DAVINCI_I2C_BASE 0x01C21000
29#define DAVINCI_ATA_BASE 0x01C66000
27#define DAVINCI_MMCSD0_BASE 0x01E10000 30#define DAVINCI_MMCSD0_BASE 0x01E10000
28#define DM355_MMCSD0_BASE 0x01E11000 31#define DM355_MMCSD0_BASE 0x01E11000
29#define DM355_MMCSD1_BASE 0x01E00000 32#define DM355_MMCSD1_BASE 0x01E00000
@@ -58,6 +61,49 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
58 (void) platform_device_register(&davinci_i2c_device); 61 (void) platform_device_register(&davinci_i2c_device);
59} 62}
60 63
64static struct resource ide_resources[] = {
65 {
66 .start = DAVINCI_ATA_BASE,
67 .end = DAVINCI_ATA_BASE + 0x7ff,
68 .flags = IORESOURCE_MEM,
69 },
70 {
71 .start = IRQ_IDE,
72 .end = IRQ_IDE,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77static u64 ide_dma_mask = DMA_BIT_MASK(32);
78
79static struct platform_device ide_device = {
80 .name = "palm_bk3710",
81 .id = -1,
82 .resource = ide_resources,
83 .num_resources = ARRAY_SIZE(ide_resources),
84 .dev = {
85 .dma_mask = &ide_dma_mask,
86 .coherent_dma_mask = DMA_BIT_MASK(32),
87 },
88};
89
90void __init davinci_init_ide(void)
91{
92 if (cpu_is_davinci_dm644x()) {
93 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
94 davinci_cfg_reg(DM644X_ATAEN);
95 davinci_cfg_reg(DM644X_HDIREN);
96 } else if (cpu_is_davinci_dm646x()) {
97 /* IRQ_DM646X_IDE is the same as IRQ_IDE */
98 davinci_cfg_reg(DM646X_ATAEN);
99 } else {
100 WARN_ON(1);
101 return;
102 }
103
104 platform_device_register(&ide_device);
105}
106
61#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE) 107#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
62 108
63static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); 109static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
@@ -251,12 +297,12 @@ static void davinci_init_wdt(void)
251 297
252struct davinci_timer_instance davinci_timer_instance[2] = { 298struct davinci_timer_instance davinci_timer_instance[2] = {
253 { 299 {
254 .base = IO_ADDRESS(DAVINCI_TIMER0_BASE), 300 .base = DAVINCI_TIMER0_BASE,
255 .bottom_irq = IRQ_TINT0_TINT12, 301 .bottom_irq = IRQ_TINT0_TINT12,
256 .top_irq = IRQ_TINT0_TINT34, 302 .top_irq = IRQ_TINT0_TINT34,
257 }, 303 },
258 { 304 {
259 .base = IO_ADDRESS(DAVINCI_TIMER1_BASE), 305 .base = DAVINCI_TIMER1_BASE,
260 .bottom_irq = IRQ_TINT1_TINT12, 306 .bottom_irq = IRQ_TINT1_TINT12,
261 .top_irq = IRQ_TINT1_TINT34, 307 .top_irq = IRQ_TINT1_TINT34,
262 }, 308 },
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 3dc0a88712eb..383478116ef5 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -450,11 +450,6 @@ void __init dm355_init_spi0(unsigned chipselect_mask,
450 450
451/*----------------------------------------------------------------------*/ 451/*----------------------------------------------------------------------*/
452 452
453#define PINMUX0 0x00
454#define PINMUX1 0x04
455#define PINMUX2 0x08
456#define PINMUX3 0x0c
457#define PINMUX4 0x10
458#define INTMUX 0x18 453#define INTMUX 0x18
459#define EVTMUX 0x1c 454#define EVTMUX 0x1c
460 455
@@ -788,9 +783,7 @@ static struct davinci_id dm355_ids[] = {
788 }, 783 },
789}; 784};
790 785
791static void __iomem *dm355_psc_bases[] = { 786static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
792 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
793};
794 787
795/* 788/*
796 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers 789 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
@@ -798,7 +791,7 @@ static void __iomem *dm355_psc_bases[] = {
798 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) 791 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
799 * T1_TOP: Timer 1, top : <unused> 792 * T1_TOP: Timer 1, top : <unused>
800 */ 793 */
801struct davinci_timer_info dm355_timer_info = { 794static struct davinci_timer_info dm355_timer_info = {
802 .timers = davinci_timer_instance, 795 .timers = davinci_timer_instance,
803 .clockevent_id = T0_BOT, 796 .clockevent_id = T0_BOT,
804 .clocksource_id = T0_TOP, 797 .clocksource_id = T0_TOP,
@@ -845,26 +838,28 @@ static struct platform_device dm355_serial_device = {
845static struct davinci_soc_info davinci_soc_info_dm355 = { 838static struct davinci_soc_info davinci_soc_info_dm355 = {
846 .io_desc = dm355_io_desc, 839 .io_desc = dm355_io_desc,
847 .io_desc_num = ARRAY_SIZE(dm355_io_desc), 840 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
848 .jtag_id_base = IO_ADDRESS(0x01c40028), 841 .jtag_id_reg = 0x01c40028,
849 .ids = dm355_ids, 842 .ids = dm355_ids,
850 .ids_num = ARRAY_SIZE(dm355_ids), 843 .ids_num = ARRAY_SIZE(dm355_ids),
851 .cpu_clks = dm355_clks, 844 .cpu_clks = dm355_clks,
852 .psc_bases = dm355_psc_bases, 845 .psc_bases = dm355_psc_bases,
853 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases), 846 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
854 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 847 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
855 .pinmux_pins = dm355_pins, 848 .pinmux_pins = dm355_pins,
856 .pinmux_pins_num = ARRAY_SIZE(dm355_pins), 849 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
857 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), 850 .intc_base = DAVINCI_ARM_INTC_BASE,
858 .intc_type = DAVINCI_INTC_TYPE_AINTC, 851 .intc_type = DAVINCI_INTC_TYPE_AINTC,
859 .intc_irq_prios = dm355_default_priorities, 852 .intc_irq_prios = dm355_default_priorities,
860 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 853 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
861 .timer_info = &dm355_timer_info, 854 .timer_info = &dm355_timer_info,
862 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), 855 .gpio_type = GPIO_TYPE_DAVINCI,
856 .gpio_base = DAVINCI_GPIO_BASE,
863 .gpio_num = 104, 857 .gpio_num = 104,
864 .gpio_irq = IRQ_DM355_GPIOBNK0, 858 .gpio_irq = IRQ_DM355_GPIOBNK0,
865 .serial_dev = &dm355_serial_device, 859 .serial_dev = &dm355_serial_device,
866 .sram_dma = 0x00010000, 860 .sram_dma = 0x00010000,
867 .sram_len = SZ_32K, 861 .sram_len = SZ_32K,
862 .reset_device = &davinci_wdt_device,
868}; 863};
869 864
870void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) 865void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0d6ee583f65c..a146849d78f0 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -467,11 +467,6 @@ static struct clk_lookup dm365_clks[] = {
467 467
468/*----------------------------------------------------------------------*/ 468/*----------------------------------------------------------------------*/
469 469
470#define PINMUX0 0x00
471#define PINMUX1 0x04
472#define PINMUX2 0x08
473#define PINMUX3 0x0c
474#define PINMUX4 0x10
475#define INTMUX 0x18 470#define INTMUX 0x18
476#define EVTMUX 0x1c 471#define EVTMUX 0x1c
477 472
@@ -490,11 +485,14 @@ MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
490MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) 485MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
491MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) 486MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
492 487
493MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false) 488MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
489MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
494MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) 490MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
495MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) 491MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
496MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) 492MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
497MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) 493MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
494MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
495MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
498 496
499MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) 497MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
500MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) 498MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
@@ -573,9 +571,17 @@ MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
573MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) 571MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
574MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) 572MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
575 573
574MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
575MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
576MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
577
576MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) 578MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
579MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
580MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
581MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
577MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) 582MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
578MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) 583MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
584MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
579 585
580MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) 586MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
581MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) 587MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
@@ -1006,11 +1012,9 @@ static struct davinci_id dm365_ids[] = {
1006 }, 1012 },
1007}; 1013};
1008 1014
1009static void __iomem *dm365_psc_bases[] = { 1015static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1010 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
1011};
1012 1016
1013struct davinci_timer_info dm365_timer_info = { 1017static struct davinci_timer_info dm365_timer_info = {
1014 .timers = davinci_timer_instance, 1018 .timers = davinci_timer_instance,
1015 .clockevent_id = T0_BOT, 1019 .clockevent_id = T0_BOT,
1016 .clocksource_id = T0_TOP, 1020 .clocksource_id = T0_TOP,
@@ -1049,21 +1053,22 @@ static struct platform_device dm365_serial_device = {
1049static struct davinci_soc_info davinci_soc_info_dm365 = { 1053static struct davinci_soc_info davinci_soc_info_dm365 = {
1050 .io_desc = dm365_io_desc, 1054 .io_desc = dm365_io_desc,
1051 .io_desc_num = ARRAY_SIZE(dm365_io_desc), 1055 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
1052 .jtag_id_base = IO_ADDRESS(0x01c40028), 1056 .jtag_id_reg = 0x01c40028,
1053 .ids = dm365_ids, 1057 .ids = dm365_ids,
1054 .ids_num = ARRAY_SIZE(dm365_ids), 1058 .ids_num = ARRAY_SIZE(dm365_ids),
1055 .cpu_clks = dm365_clks, 1059 .cpu_clks = dm365_clks,
1056 .psc_bases = dm365_psc_bases, 1060 .psc_bases = dm365_psc_bases,
1057 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), 1061 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
1058 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 1062 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
1059 .pinmux_pins = dm365_pins, 1063 .pinmux_pins = dm365_pins,
1060 .pinmux_pins_num = ARRAY_SIZE(dm365_pins), 1064 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
1061 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), 1065 .intc_base = DAVINCI_ARM_INTC_BASE,
1062 .intc_type = DAVINCI_INTC_TYPE_AINTC, 1066 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1063 .intc_irq_prios = dm365_default_priorities, 1067 .intc_irq_prios = dm365_default_priorities,
1064 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 1068 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1065 .timer_info = &dm365_timer_info, 1069 .timer_info = &dm365_timer_info,
1066 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), 1070 .gpio_type = GPIO_TYPE_DAVINCI,
1071 .gpio_base = DAVINCI_GPIO_BASE,
1067 .gpio_num = 104, 1072 .gpio_num = 104,
1068 .gpio_irq = IRQ_DM365_GPIO0, 1073 .gpio_irq = IRQ_DM365_GPIO0,
1069 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ 1074 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */
@@ -1071,6 +1076,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
1071 .emac_pdata = &dm365_emac_pdata, 1076 .emac_pdata = &dm365_emac_pdata,
1072 .sram_dma = 0x00010000, 1077 .sram_dma = 0x00010000,
1073 .sram_len = SZ_32K, 1078 .sram_len = SZ_32K,
1079 .reset_device = &davinci_wdt_device,
1074}; 1080};
1075 1081
1076void __init dm365_init_asp(struct snd_platform_data *pdata) 1082void __init dm365_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 2f2ae8bc77bb..7ad15208b841 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -277,7 +277,7 @@ static struct clk timer2_clk = {
277 .usecount = 1, /* REVISIT: why cant' this be disabled? */ 277 .usecount = 1, /* REVISIT: why cant' this be disabled? */
278}; 278};
279 279
280struct clk_lookup dm644x_clks[] = { 280static struct clk_lookup dm644x_clks[] = {
281 CLK(NULL, "ref", &ref_clk), 281 CLK(NULL, "ref", &ref_clk),
282 CLK(NULL, "pll1", &pll1_clk), 282 CLK(NULL, "pll1", &pll1_clk),
283 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), 283 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -350,9 +350,6 @@ static struct platform_device dm644x_emac_device = {
350 .resource = dm644x_emac_resources, 350 .resource = dm644x_emac_resources,
351}; 351};
352 352
353#define PINMUX0 0x00
354#define PINMUX1 0x04
355
356/* 353/*
357 * Device specific mux setup 354 * Device specific mux setup
358 * 355 *
@@ -677,9 +674,7 @@ static struct davinci_id dm644x_ids[] = {
677 }, 674 },
678}; 675};
679 676
680static void __iomem *dm644x_psc_bases[] = { 677static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
681 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
682};
683 678
684/* 679/*
685 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers 680 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
@@ -687,7 +682,7 @@ static void __iomem *dm644x_psc_bases[] = {
687 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) 682 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
688 * T1_TOP: Timer 1, top : <unused> 683 * T1_TOP: Timer 1, top : <unused>
689 */ 684 */
690struct davinci_timer_info dm644x_timer_info = { 685static struct davinci_timer_info dm644x_timer_info = {
691 .timers = davinci_timer_instance, 686 .timers = davinci_timer_instance,
692 .clockevent_id = T0_BOT, 687 .clockevent_id = T0_BOT,
693 .clocksource_id = T0_TOP, 688 .clocksource_id = T0_TOP,
@@ -734,27 +729,29 @@ static struct platform_device dm644x_serial_device = {
734static struct davinci_soc_info davinci_soc_info_dm644x = { 729static struct davinci_soc_info davinci_soc_info_dm644x = {
735 .io_desc = dm644x_io_desc, 730 .io_desc = dm644x_io_desc,
736 .io_desc_num = ARRAY_SIZE(dm644x_io_desc), 731 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
737 .jtag_id_base = IO_ADDRESS(0x01c40028), 732 .jtag_id_reg = 0x01c40028,
738 .ids = dm644x_ids, 733 .ids = dm644x_ids,
739 .ids_num = ARRAY_SIZE(dm644x_ids), 734 .ids_num = ARRAY_SIZE(dm644x_ids),
740 .cpu_clks = dm644x_clks, 735 .cpu_clks = dm644x_clks,
741 .psc_bases = dm644x_psc_bases, 736 .psc_bases = dm644x_psc_bases,
742 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), 737 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
743 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 738 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
744 .pinmux_pins = dm644x_pins, 739 .pinmux_pins = dm644x_pins,
745 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), 740 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
746 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), 741 .intc_base = DAVINCI_ARM_INTC_BASE,
747 .intc_type = DAVINCI_INTC_TYPE_AINTC, 742 .intc_type = DAVINCI_INTC_TYPE_AINTC,
748 .intc_irq_prios = dm644x_default_priorities, 743 .intc_irq_prios = dm644x_default_priorities,
749 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 744 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
750 .timer_info = &dm644x_timer_info, 745 .timer_info = &dm644x_timer_info,
751 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), 746 .gpio_type = GPIO_TYPE_DAVINCI,
747 .gpio_base = DAVINCI_GPIO_BASE,
752 .gpio_num = 71, 748 .gpio_num = 71,
753 .gpio_irq = IRQ_GPIOBNK0, 749 .gpio_irq = IRQ_GPIOBNK0,
754 .serial_dev = &dm644x_serial_device, 750 .serial_dev = &dm644x_serial_device,
755 .emac_pdata = &dm644x_emac_pdata, 751 .emac_pdata = &dm644x_emac_pdata,
756 .sram_dma = 0x00008000, 752 .sram_dma = 0x00008000,
757 .sram_len = SZ_16K, 753 .sram_len = SZ_16K,
754 .reset_device = &davinci_wdt_device,
758}; 755};
759 756
760void __init dm644x_init_asp(struct snd_platform_data *pdata) 757void __init dm644x_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 893baf4ad37d..94045656cff6 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -311,7 +311,7 @@ static struct clk vpif1_clk = {
311 .flags = ALWAYS_ENABLED, 311 .flags = ALWAYS_ENABLED,
312}; 312};
313 313
314struct clk_lookup dm646x_clks[] = { 314static struct clk_lookup dm646x_clks[] = {
315 CLK(NULL, "ref", &ref_clk), 315 CLK(NULL, "ref", &ref_clk),
316 CLK(NULL, "aux", &aux_clkin), 316 CLK(NULL, "aux", &aux_clkin),
317 CLK(NULL, "pll1", &pll1_clk), 317 CLK(NULL, "pll1", &pll1_clk),
@@ -401,9 +401,6 @@ static struct platform_device dm646x_emac_device = {
401 .resource = dm646x_emac_resources, 401 .resource = dm646x_emac_resources,
402}; 402};
403 403
404#define PINMUX0 0x00
405#define PINMUX1 0x04
406
407/* 404/*
408 * Device specific mux setup 405 * Device specific mux setup
409 * 406 *
@@ -596,32 +593,6 @@ static struct platform_device dm646x_edma_device = {
596 .resource = edma_resources, 593 .resource = edma_resources,
597}; 594};
598 595
599static struct resource ide_resources[] = {
600 {
601 .start = DM646X_ATA_REG_BASE,
602 .end = DM646X_ATA_REG_BASE + 0x7ff,
603 .flags = IORESOURCE_MEM,
604 },
605 {
606 .start = IRQ_DM646X_IDE,
607 .end = IRQ_DM646X_IDE,
608 .flags = IORESOURCE_IRQ,
609 },
610};
611
612static u64 ide_dma_mask = DMA_BIT_MASK(32);
613
614static struct platform_device ide_dev = {
615 .name = "palm_bk3710",
616 .id = -1,
617 .resource = ide_resources,
618 .num_resources = ARRAY_SIZE(ide_resources),
619 .dev = {
620 .dma_mask = &ide_dma_mask,
621 .coherent_dma_mask = DMA_BIT_MASK(32),
622 },
623};
624
625static struct resource dm646x_mcasp0_resources[] = { 596static struct resource dm646x_mcasp0_resources[] = {
626 { 597 {
627 .name = "mcasp0", 598 .name = "mcasp0",
@@ -787,9 +758,7 @@ static struct davinci_id dm646x_ids[] = {
787 }, 758 },
788}; 759};
789 760
790static void __iomem *dm646x_psc_bases[] = { 761static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
791 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
792};
793 762
794/* 763/*
795 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers 764 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
@@ -797,7 +766,7 @@ static void __iomem *dm646x_psc_bases[] = {
797 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) 766 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
798 * T1_TOP: Timer 1, top : <unused> 767 * T1_TOP: Timer 1, top : <unused>
799 */ 768 */
800struct davinci_timer_info dm646x_timer_info = { 769static struct davinci_timer_info dm646x_timer_info = {
801 .timers = davinci_timer_instance, 770 .timers = davinci_timer_instance,
802 .clockevent_id = T0_BOT, 771 .clockevent_id = T0_BOT,
803 .clocksource_id = T0_TOP, 772 .clocksource_id = T0_TOP,
@@ -844,35 +813,31 @@ static struct platform_device dm646x_serial_device = {
844static struct davinci_soc_info davinci_soc_info_dm646x = { 813static struct davinci_soc_info davinci_soc_info_dm646x = {
845 .io_desc = dm646x_io_desc, 814 .io_desc = dm646x_io_desc,
846 .io_desc_num = ARRAY_SIZE(dm646x_io_desc), 815 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
847 .jtag_id_base = IO_ADDRESS(0x01c40028), 816 .jtag_id_reg = 0x01c40028,
848 .ids = dm646x_ids, 817 .ids = dm646x_ids,
849 .ids_num = ARRAY_SIZE(dm646x_ids), 818 .ids_num = ARRAY_SIZE(dm646x_ids),
850 .cpu_clks = dm646x_clks, 819 .cpu_clks = dm646x_clks,
851 .psc_bases = dm646x_psc_bases, 820 .psc_bases = dm646x_psc_bases,
852 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), 821 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
853 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 822 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
854 .pinmux_pins = dm646x_pins, 823 .pinmux_pins = dm646x_pins,
855 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), 824 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
856 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), 825 .intc_base = DAVINCI_ARM_INTC_BASE,
857 .intc_type = DAVINCI_INTC_TYPE_AINTC, 826 .intc_type = DAVINCI_INTC_TYPE_AINTC,
858 .intc_irq_prios = dm646x_default_priorities, 827 .intc_irq_prios = dm646x_default_priorities,
859 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 828 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
860 .timer_info = &dm646x_timer_info, 829 .timer_info = &dm646x_timer_info,
861 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), 830 .gpio_type = GPIO_TYPE_DAVINCI,
831 .gpio_base = DAVINCI_GPIO_BASE,
862 .gpio_num = 43, /* Only 33 usable */ 832 .gpio_num = 43, /* Only 33 usable */
863 .gpio_irq = IRQ_DM646X_GPIOBNK0, 833 .gpio_irq = IRQ_DM646X_GPIOBNK0,
864 .serial_dev = &dm646x_serial_device, 834 .serial_dev = &dm646x_serial_device,
865 .emac_pdata = &dm646x_emac_pdata, 835 .emac_pdata = &dm646x_emac_pdata,
866 .sram_dma = 0x10010000, 836 .sram_dma = 0x10010000,
867 .sram_len = SZ_32K, 837 .sram_len = SZ_32K,
838 .reset_device = &davinci_wdt_device,
868}; 839};
869 840
870void __init dm646x_init_ide()
871{
872 davinci_cfg_reg(DM646X_ATAEN);
873 platform_device_register(&ide_dev);
874}
875
876void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) 841void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
877{ 842{
878 dm646x_mcasp0_device.dev.platform_data = pdata; 843 dm646x_mcasp0_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 53137387aee1..d33827aadda7 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -243,7 +243,7 @@ struct edma {
243 } intr_data[EDMA_MAX_DMACH]; 243 } intr_data[EDMA_MAX_DMACH];
244}; 244};
245 245
246static struct edma *edma_info[EDMA_MAX_CC]; 246static struct edma *edma_cc[EDMA_MAX_CC];
247static int arch_num_cc; 247static int arch_num_cc;
248 248
249/* dummy param set used to (re)initialize parameter RAM slots */ 249/* dummy param set used to (re)initialize parameter RAM slots */
@@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
261 261
262 /* default to low priority queue */ 262 /* default to low priority queue */
263 if (queue_no == EVENTQ_DEFAULT) 263 if (queue_no == EVENTQ_DEFAULT)
264 queue_no = edma_info[ctlr]->default_queue; 264 queue_no = edma_cc[ctlr]->default_queue;
265 265
266 queue_no &= 7; 266 queue_no &= 7;
267 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), 267 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
@@ -310,29 +310,27 @@ setup_dma_interrupt(unsigned lch,
310 ctlr = EDMA_CTLR(lch); 310 ctlr = EDMA_CTLR(lch);
311 lch = EDMA_CHAN_SLOT(lch); 311 lch = EDMA_CHAN_SLOT(lch);
312 312
313 if (!callback) { 313 if (!callback)
314 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, 314 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
315 (1 << (lch & 0x1f))); 315 BIT(lch & 0x1f));
316 }
317 316
318 edma_info[ctlr]->intr_data[lch].callback = callback; 317 edma_cc[ctlr]->intr_data[lch].callback = callback;
319 edma_info[ctlr]->intr_data[lch].data = data; 318 edma_cc[ctlr]->intr_data[lch].data = data;
320 319
321 if (callback) { 320 if (callback) {
322 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, 321 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
323 (1 << (lch & 0x1f))); 322 BIT(lch & 0x1f));
324 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, 323 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
325 (1 << (lch & 0x1f))); 324 BIT(lch & 0x1f));
326 } 325 }
327} 326}
328 327
329static int irq2ctlr(int irq) 328static int irq2ctlr(int irq)
330{ 329{
331 if (irq >= edma_info[0]->irq_res_start && 330 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
332 irq <= edma_info[0]->irq_res_end)
333 return 0; 331 return 0;
334 else if (irq >= edma_info[1]->irq_res_start && 332 else if (irq >= edma_cc[1]->irq_res_start &&
335 irq <= edma_info[1]->irq_res_end) 333 irq <= edma_cc[1]->irq_res_end)
336 return 1; 334 return 1;
337 335
338 return -1; 336 return -1;
@@ -353,15 +351,17 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
353 351
354 dev_dbg(data, "dma_irq_handler\n"); 352 dev_dbg(data, "dma_irq_handler\n");
355 353
356 if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) 354 if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
357 && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) 355 (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
358 return IRQ_NONE; 356 return IRQ_NONE;
359 357
360 while (1) { 358 while (1) {
361 int j; 359 int j;
362 if (edma_shadow0_read_array(ctlr, SH_IPR, 0)) 360 if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
361 edma_shadow0_read_array(ctlr, SH_IER, 0))
363 j = 0; 362 j = 0;
364 else if (edma_shadow0_read_array(ctlr, SH_IPR, 1)) 363 else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
364 edma_shadow0_read_array(ctlr, SH_IER, 1))
365 j = 1; 365 j = 1;
366 else 366 else
367 break; 367 break;
@@ -369,17 +369,17 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
369 edma_shadow0_read_array(ctlr, SH_IPR, j)); 369 edma_shadow0_read_array(ctlr, SH_IPR, j));
370 for (i = 0; i < 32; i++) { 370 for (i = 0; i < 32; i++) {
371 int k = (j << 5) + i; 371 int k = (j << 5) + i;
372 if (edma_shadow0_read_array(ctlr, SH_IPR, j) & 372 if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
373 (1 << i)) { 373 && (edma_shadow0_read_array(ctlr,
374 SH_IER, j) & BIT(i))) {
374 /* Clear the corresponding IPR bits */ 375 /* Clear the corresponding IPR bits */
375 edma_shadow0_write_array(ctlr, SH_ICR, j, 376 edma_shadow0_write_array(ctlr, SH_ICR, j,
376 (1 << i)); 377 BIT(i));
377 if (edma_info[ctlr]->intr_data[k].callback) { 378 if (edma_cc[ctlr]->intr_data[k].callback)
378 edma_info[ctlr]->intr_data[k].callback( 379 edma_cc[ctlr]->intr_data[k].callback(
379 k, DMA_COMPLETE, 380 k, DMA_COMPLETE,
380 edma_info[ctlr]->intr_data[k]. 381 edma_cc[ctlr]->intr_data[k].
381 data); 382 data);
382 }
383 } 383 }
384 } 384 }
385 cnt++; 385 cnt++;
@@ -423,19 +423,19 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
423 for (i = 0; i < 32; i++) { 423 for (i = 0; i < 32; i++) {
424 int k = (j << 5) + i; 424 int k = (j << 5) + i;
425 if (edma_read_array(ctlr, EDMA_EMR, j) & 425 if (edma_read_array(ctlr, EDMA_EMR, j) &
426 (1 << i)) { 426 BIT(i)) {
427 /* Clear the corresponding EMR bits */ 427 /* Clear the corresponding EMR bits */
428 edma_write_array(ctlr, EDMA_EMCR, j, 428 edma_write_array(ctlr, EDMA_EMCR, j,
429 1 << i); 429 BIT(i));
430 /* Clear any SER */ 430 /* Clear any SER */
431 edma_shadow0_write_array(ctlr, SH_SECR, 431 edma_shadow0_write_array(ctlr, SH_SECR,
432 j, (1 << i)); 432 j, BIT(i));
433 if (edma_info[ctlr]->intr_data[k]. 433 if (edma_cc[ctlr]->intr_data[k].
434 callback) { 434 callback) {
435 edma_info[ctlr]->intr_data[k]. 435 edma_cc[ctlr]->intr_data[k].
436 callback(k, 436 callback(k,
437 DMA_CC_ERROR, 437 DMA_CC_ERROR,
438 edma_info[ctlr]->intr_data 438 edma_cc[ctlr]->intr_data
439 [k].data); 439 [k].data);
440 } 440 }
441 } 441 }
@@ -444,11 +444,11 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
444 dev_dbg(data, "QEMR %02x\n", 444 dev_dbg(data, "QEMR %02x\n",
445 edma_read(ctlr, EDMA_QEMR)); 445 edma_read(ctlr, EDMA_QEMR));
446 for (i = 0; i < 8; i++) { 446 for (i = 0; i < 8; i++) {
447 if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) { 447 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
448 /* Clear the corresponding IPR bits */ 448 /* Clear the corresponding IPR bits */
449 edma_write(ctlr, EDMA_QEMCR, 1 << i); 449 edma_write(ctlr, EDMA_QEMCR, BIT(i));
450 edma_shadow0_write(ctlr, SH_QSECR, 450 edma_shadow0_write(ctlr, SH_QSECR,
451 (1 << i)); 451 BIT(i));
452 452
453 /* NOTE: not reported!! */ 453 /* NOTE: not reported!! */
454 } 454 }
@@ -460,20 +460,19 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
460 * to just write CCERRCLR with CCERR value... 460 * to just write CCERRCLR with CCERR value...
461 */ 461 */
462 for (i = 0; i < 8; i++) { 462 for (i = 0; i < 8; i++) {
463 if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) { 463 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
464 /* Clear the corresponding IPR bits */ 464 /* Clear the corresponding IPR bits */
465 edma_write(ctlr, EDMA_CCERRCLR, 1 << i); 465 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
466 466
467 /* NOTE: not reported!! */ 467 /* NOTE: not reported!! */
468 } 468 }
469 } 469 }
470 } 470 }
471 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) 471 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
472 && (edma_read_array(ctlr, EDMA_EMR, 1) == 0) 472 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
473 && (edma_read(ctlr, EDMA_QEMR) == 0) 473 (edma_read(ctlr, EDMA_QEMR) == 0) &&
474 && (edma_read(ctlr, EDMA_CCERR) == 0)) { 474 (edma_read(ctlr, EDMA_CCERR) == 0))
475 break; 475 break;
476 }
477 cnt++; 476 cnt++;
478 if (cnt > 10) 477 if (cnt > 10)
479 break; 478 break;
@@ -511,9 +510,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
511 int stop_slot = start_slot; 510 int stop_slot = start_slot;
512 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); 511 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
513 512
514 for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) { 513 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
515 j = EDMA_CHAN_SLOT(i); 514 j = EDMA_CHAN_SLOT(i);
516 if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) { 515 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
517 /* Record our current beginning slot */ 516 /* Record our current beginning slot */
518 if (count == num_slots) 517 if (count == num_slots)
519 stop_slot = i; 518 stop_slot = i;
@@ -529,8 +528,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
529 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { 528 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
530 stop_slot = i; 529 stop_slot = i;
531 break; 530 break;
532 } else 531 } else {
533 count = num_slots; 532 count = num_slots;
533 }
534 } 534 }
535 } 535 }
536 536
@@ -540,12 +540,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
540 * of contiguous parameter RAM slots but do not find the exact number 540 * of contiguous parameter RAM slots but do not find the exact number
541 * requested as we may reach the total number of parameter RAM slots 541 * requested as we may reach the total number of parameter RAM slots
542 */ 542 */
543 if (i == edma_info[ctlr]->num_slots) 543 if (i == edma_cc[ctlr]->num_slots)
544 stop_slot = i; 544 stop_slot = i;
545 545
546 for (j = start_slot; j < stop_slot; j++) 546 for (j = start_slot; j < stop_slot; j++)
547 if (test_bit(j, tmp_inuse)) 547 if (test_bit(j, tmp_inuse))
548 clear_bit(j, edma_info[ctlr]->edma_inuse); 548 clear_bit(j, edma_cc[ctlr]->edma_inuse);
549 549
550 if (count) 550 if (count)
551 return -EBUSY; 551 return -EBUSY;
@@ -567,7 +567,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
567 (int)pdev->resource[i].start >= 0) { 567 (int)pdev->resource[i].start >= 0) {
568 ctlr = EDMA_CTLR(pdev->resource[i].start); 568 ctlr = EDMA_CTLR(pdev->resource[i].start);
569 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), 569 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
570 edma_info[ctlr]->edma_unused); 570 edma_cc[ctlr]->edma_unused);
571 } 571 }
572 } 572 }
573 573
@@ -641,14 +641,13 @@ int edma_alloc_channel(int channel,
641 for (i = 0; i < arch_num_cc; i++) { 641 for (i = 0; i < arch_num_cc; i++) {
642 channel = 0; 642 channel = 0;
643 for (;;) { 643 for (;;) {
644 channel = find_next_bit(edma_info[i]-> 644 channel = find_next_bit(edma_cc[i]->edma_unused,
645 edma_unused, 645 edma_cc[i]->num_channels,
646 edma_info[i]->num_channels,
647 channel); 646 channel);
648 if (channel == edma_info[i]->num_channels) 647 if (channel == edma_cc[i]->num_channels)
649 break; 648 break;
650 if (!test_and_set_bit(channel, 649 if (!test_and_set_bit(channel,
651 edma_info[i]->edma_inuse)) { 650 edma_cc[i]->edma_inuse)) {
652 done = 1; 651 done = 1;
653 ctlr = i; 652 ctlr = i;
654 break; 653 break;
@@ -660,14 +659,14 @@ int edma_alloc_channel(int channel,
660 } 659 }
661 if (!done) 660 if (!done)
662 return -ENOMEM; 661 return -ENOMEM;
663 } else if (channel >= edma_info[ctlr]->num_channels) { 662 } else if (channel >= edma_cc[ctlr]->num_channels) {
664 return -EINVAL; 663 return -EINVAL;
665 } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { 664 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
666 return -EBUSY; 665 return -EBUSY;
667 } 666 }
668 667
669 /* ensure access through shadow region 0 */ 668 /* ensure access through shadow region 0 */
670 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); 669 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
671 670
672 /* ensure no events are pending */ 671 /* ensure no events are pending */
673 edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); 672 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
@@ -703,7 +702,7 @@ void edma_free_channel(unsigned channel)
703 ctlr = EDMA_CTLR(channel); 702 ctlr = EDMA_CTLR(channel);
704 channel = EDMA_CHAN_SLOT(channel); 703 channel = EDMA_CHAN_SLOT(channel);
705 704
706 if (channel >= edma_info[ctlr]->num_channels) 705 if (channel >= edma_cc[ctlr]->num_channels)
707 return; 706 return;
708 707
709 setup_dma_interrupt(channel, NULL, NULL); 708 setup_dma_interrupt(channel, NULL, NULL);
@@ -711,7 +710,7 @@ void edma_free_channel(unsigned channel)
711 710
712 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), 711 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
713 &dummy_paramset, PARM_SIZE); 712 &dummy_paramset, PARM_SIZE);
714 clear_bit(channel, edma_info[ctlr]->edma_inuse); 713 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
715} 714}
716EXPORT_SYMBOL(edma_free_channel); 715EXPORT_SYMBOL(edma_free_channel);
717 716
@@ -735,20 +734,19 @@ int edma_alloc_slot(unsigned ctlr, int slot)
735 slot = EDMA_CHAN_SLOT(slot); 734 slot = EDMA_CHAN_SLOT(slot);
736 735
737 if (slot < 0) { 736 if (slot < 0) {
738 slot = edma_info[ctlr]->num_channels; 737 slot = edma_cc[ctlr]->num_channels;
739 for (;;) { 738 for (;;) {
740 slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse, 739 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
741 edma_info[ctlr]->num_slots, slot); 740 edma_cc[ctlr]->num_slots, slot);
742 if (slot == edma_info[ctlr]->num_slots) 741 if (slot == edma_cc[ctlr]->num_slots)
743 return -ENOMEM; 742 return -ENOMEM;
744 if (!test_and_set_bit(slot, 743 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
745 edma_info[ctlr]->edma_inuse))
746 break; 744 break;
747 } 745 }
748 } else if (slot < edma_info[ctlr]->num_channels || 746 } else if (slot < edma_cc[ctlr]->num_channels ||
749 slot >= edma_info[ctlr]->num_slots) { 747 slot >= edma_cc[ctlr]->num_slots) {
750 return -EINVAL; 748 return -EINVAL;
751 } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) { 749 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
752 return -EBUSY; 750 return -EBUSY;
753 } 751 }
754 752
@@ -774,13 +772,13 @@ void edma_free_slot(unsigned slot)
774 ctlr = EDMA_CTLR(slot); 772 ctlr = EDMA_CTLR(slot);
775 slot = EDMA_CHAN_SLOT(slot); 773 slot = EDMA_CHAN_SLOT(slot);
776 774
777 if (slot < edma_info[ctlr]->num_channels || 775 if (slot < edma_cc[ctlr]->num_channels ||
778 slot >= edma_info[ctlr]->num_slots) 776 slot >= edma_cc[ctlr]->num_slots)
779 return; 777 return;
780 778
781 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), 779 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
782 &dummy_paramset, PARM_SIZE); 780 &dummy_paramset, PARM_SIZE);
783 clear_bit(slot, edma_info[ctlr]->edma_inuse); 781 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
784} 782}
785EXPORT_SYMBOL(edma_free_slot); 783EXPORT_SYMBOL(edma_free_slot);
786 784
@@ -818,8 +816,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
818 * of slots 816 * of slots
819 */ 817 */
820 if ((id != EDMA_CONT_PARAMS_ANY) && 818 if ((id != EDMA_CONT_PARAMS_ANY) &&
821 (slot < edma_info[ctlr]->num_channels || 819 (slot < edma_cc[ctlr]->num_channels ||
822 slot >= edma_info[ctlr]->num_slots)) 820 slot >= edma_cc[ctlr]->num_slots))
823 return -EINVAL; 821 return -EINVAL;
824 822
825 /* 823 /*
@@ -828,13 +826,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
828 * channels 826 * channels
829 */ 827 */
830 if (count < 1 || count > 828 if (count < 1 || count >
831 (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels)) 829 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
832 return -EINVAL; 830 return -EINVAL;
833 831
834 switch (id) { 832 switch (id) {
835 case EDMA_CONT_PARAMS_ANY: 833 case EDMA_CONT_PARAMS_ANY:
836 return reserve_contiguous_slots(ctlr, id, count, 834 return reserve_contiguous_slots(ctlr, id, count,
837 edma_info[ctlr]->num_channels); 835 edma_cc[ctlr]->num_channels);
838 case EDMA_CONT_PARAMS_FIXED_EXACT: 836 case EDMA_CONT_PARAMS_FIXED_EXACT:
839 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: 837 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
840 return reserve_contiguous_slots(ctlr, id, count, slot); 838 return reserve_contiguous_slots(ctlr, id, count, slot);
@@ -866,8 +864,8 @@ int edma_free_cont_slots(unsigned slot, int count)
866 ctlr = EDMA_CTLR(slot); 864 ctlr = EDMA_CTLR(slot);
867 slot = EDMA_CHAN_SLOT(slot); 865 slot = EDMA_CHAN_SLOT(slot);
868 866
869 if (slot < edma_info[ctlr]->num_channels || 867 if (slot < edma_cc[ctlr]->num_channels ||
870 slot >= edma_info[ctlr]->num_slots || 868 slot >= edma_cc[ctlr]->num_slots ||
871 count < 1) 869 count < 1)
872 return -EINVAL; 870 return -EINVAL;
873 871
@@ -877,7 +875,7 @@ int edma_free_cont_slots(unsigned slot, int count)
877 875
878 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), 876 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
879 &dummy_paramset, PARM_SIZE); 877 &dummy_paramset, PARM_SIZE);
880 clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse); 878 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
881 } 879 }
882 880
883 return 0; 881 return 0;
@@ -907,7 +905,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port,
907 ctlr = EDMA_CTLR(slot); 905 ctlr = EDMA_CTLR(slot);
908 slot = EDMA_CHAN_SLOT(slot); 906 slot = EDMA_CHAN_SLOT(slot);
909 907
910 if (slot < edma_info[ctlr]->num_slots) { 908 if (slot < edma_cc[ctlr]->num_slots) {
911 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); 909 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
912 910
913 if (mode) { 911 if (mode) {
@@ -945,7 +943,7 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
945 ctlr = EDMA_CTLR(slot); 943 ctlr = EDMA_CTLR(slot);
946 slot = EDMA_CHAN_SLOT(slot); 944 slot = EDMA_CHAN_SLOT(slot);
947 945
948 if (slot < edma_info[ctlr]->num_slots) { 946 if (slot < edma_cc[ctlr]->num_slots) {
949 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); 947 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
950 948
951 if (mode) { 949 if (mode) {
@@ -1005,7 +1003,7 @@ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1005 ctlr = EDMA_CTLR(slot); 1003 ctlr = EDMA_CTLR(slot);
1006 slot = EDMA_CHAN_SLOT(slot); 1004 slot = EDMA_CHAN_SLOT(slot);
1007 1005
1008 if (slot < edma_info[ctlr]->num_slots) { 1006 if (slot < edma_cc[ctlr]->num_slots) {
1009 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 1007 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1010 0xffff0000, src_bidx); 1008 0xffff0000, src_bidx);
1011 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, 1009 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1031,7 +1029,7 @@ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1031 ctlr = EDMA_CTLR(slot); 1029 ctlr = EDMA_CTLR(slot);
1032 slot = EDMA_CHAN_SLOT(slot); 1030 slot = EDMA_CHAN_SLOT(slot);
1033 1031
1034 if (slot < edma_info[ctlr]->num_slots) { 1032 if (slot < edma_cc[ctlr]->num_slots) {
1035 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 1033 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1036 0x0000ffff, dest_bidx << 16); 1034 0x0000ffff, dest_bidx << 16);
1037 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, 1035 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1078,7 +1076,7 @@ void edma_set_transfer_params(unsigned slot,
1078 ctlr = EDMA_CTLR(slot); 1076 ctlr = EDMA_CTLR(slot);
1079 slot = EDMA_CHAN_SLOT(slot); 1077 slot = EDMA_CHAN_SLOT(slot);
1080 1078
1081 if (slot < edma_info[ctlr]->num_slots) { 1079 if (slot < edma_cc[ctlr]->num_slots) {
1082 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, 1080 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1083 0x0000ffff, bcnt_rld << 16); 1081 0x0000ffff, bcnt_rld << 16);
1084 if (sync_mode == ASYNC) 1082 if (sync_mode == ASYNC)
@@ -1108,9 +1106,9 @@ void edma_link(unsigned from, unsigned to)
1108 ctlr_to = EDMA_CTLR(to); 1106 ctlr_to = EDMA_CTLR(to);
1109 to = EDMA_CHAN_SLOT(to); 1107 to = EDMA_CHAN_SLOT(to);
1110 1108
1111 if (from >= edma_info[ctlr_from]->num_slots) 1109 if (from >= edma_cc[ctlr_from]->num_slots)
1112 return; 1110 return;
1113 if (to >= edma_info[ctlr_to]->num_slots) 1111 if (to >= edma_cc[ctlr_to]->num_slots)
1114 return; 1112 return;
1115 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, 1113 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1116 PARM_OFFSET(to)); 1114 PARM_OFFSET(to));
@@ -1131,7 +1129,7 @@ void edma_unlink(unsigned from)
1131 ctlr = EDMA_CTLR(from); 1129 ctlr = EDMA_CTLR(from);
1132 from = EDMA_CHAN_SLOT(from); 1130 from = EDMA_CHAN_SLOT(from);
1133 1131
1134 if (from >= edma_info[ctlr]->num_slots) 1132 if (from >= edma_cc[ctlr]->num_slots)
1135 return; 1133 return;
1136 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); 1134 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1137} 1135}
@@ -1158,7 +1156,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1158 ctlr = EDMA_CTLR(slot); 1156 ctlr = EDMA_CTLR(slot);
1159 slot = EDMA_CHAN_SLOT(slot); 1157 slot = EDMA_CHAN_SLOT(slot);
1160 1158
1161 if (slot >= edma_info[ctlr]->num_slots) 1159 if (slot >= edma_cc[ctlr]->num_slots)
1162 return; 1160 return;
1163 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, 1161 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1164 PARM_SIZE); 1162 PARM_SIZE);
@@ -1180,7 +1178,7 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
1180 ctlr = EDMA_CTLR(slot); 1178 ctlr = EDMA_CTLR(slot);
1181 slot = EDMA_CHAN_SLOT(slot); 1179 slot = EDMA_CHAN_SLOT(slot);
1182 1180
1183 if (slot >= edma_info[ctlr]->num_slots) 1181 if (slot >= edma_cc[ctlr]->num_slots)
1184 return; 1182 return;
1185 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), 1183 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1186 PARM_SIZE); 1184 PARM_SIZE);
@@ -1205,8 +1203,8 @@ void edma_pause(unsigned channel)
1205 ctlr = EDMA_CTLR(channel); 1203 ctlr = EDMA_CTLR(channel);
1206 channel = EDMA_CHAN_SLOT(channel); 1204 channel = EDMA_CHAN_SLOT(channel);
1207 1205
1208 if (channel < edma_info[ctlr]->num_channels) { 1206 if (channel < edma_cc[ctlr]->num_channels) {
1209 unsigned int mask = (1 << (channel & 0x1f)); 1207 unsigned int mask = BIT(channel & 0x1f);
1210 1208
1211 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); 1209 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1212 } 1210 }
@@ -1226,8 +1224,8 @@ void edma_resume(unsigned channel)
1226 ctlr = EDMA_CTLR(channel); 1224 ctlr = EDMA_CTLR(channel);
1227 channel = EDMA_CHAN_SLOT(channel); 1225 channel = EDMA_CHAN_SLOT(channel);
1228 1226
1229 if (channel < edma_info[ctlr]->num_channels) { 1227 if (channel < edma_cc[ctlr]->num_channels) {
1230 unsigned int mask = (1 << (channel & 0x1f)); 1228 unsigned int mask = BIT(channel & 0x1f);
1231 1229
1232 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); 1230 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1233 } 1231 }
@@ -1252,12 +1250,12 @@ int edma_start(unsigned channel)
1252 ctlr = EDMA_CTLR(channel); 1250 ctlr = EDMA_CTLR(channel);
1253 channel = EDMA_CHAN_SLOT(channel); 1251 channel = EDMA_CHAN_SLOT(channel);
1254 1252
1255 if (channel < edma_info[ctlr]->num_channels) { 1253 if (channel < edma_cc[ctlr]->num_channels) {
1256 int j = channel >> 5; 1254 int j = channel >> 5;
1257 unsigned int mask = (1 << (channel & 0x1f)); 1255 unsigned int mask = BIT(channel & 0x1f);
1258 1256
1259 /* EDMA channels without event association */ 1257 /* EDMA channels without event association */
1260 if (test_bit(channel, edma_info[ctlr]->edma_unused)) { 1258 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1261 pr_debug("EDMA: ESR%d %08x\n", j, 1259 pr_debug("EDMA: ESR%d %08x\n", j,
1262 edma_shadow0_read_array(ctlr, SH_ESR, j)); 1260 edma_shadow0_read_array(ctlr, SH_ESR, j));
1263 edma_shadow0_write_array(ctlr, SH_ESR, j, mask); 1261 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@@ -1298,9 +1296,9 @@ void edma_stop(unsigned channel)
1298 ctlr = EDMA_CTLR(channel); 1296 ctlr = EDMA_CTLR(channel);
1299 channel = EDMA_CHAN_SLOT(channel); 1297 channel = EDMA_CHAN_SLOT(channel);
1300 1298
1301 if (channel < edma_info[ctlr]->num_channels) { 1299 if (channel < edma_cc[ctlr]->num_channels) {
1302 int j = channel >> 5; 1300 int j = channel >> 5;
1303 unsigned int mask = (1 << (channel & 0x1f)); 1301 unsigned int mask = BIT(channel & 0x1f);
1304 1302
1305 edma_shadow0_write_array(ctlr, SH_EECR, j, mask); 1303 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1306 edma_shadow0_write_array(ctlr, SH_ECR, j, mask); 1304 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
@@ -1337,9 +1335,9 @@ void edma_clean_channel(unsigned channel)
1337 ctlr = EDMA_CTLR(channel); 1335 ctlr = EDMA_CTLR(channel);
1338 channel = EDMA_CHAN_SLOT(channel); 1336 channel = EDMA_CHAN_SLOT(channel);
1339 1337
1340 if (channel < edma_info[ctlr]->num_channels) { 1338 if (channel < edma_cc[ctlr]->num_channels) {
1341 int j = (channel >> 5); 1339 int j = (channel >> 5);
1342 unsigned int mask = 1 << (channel & 0x1f); 1340 unsigned int mask = BIT(channel & 0x1f);
1343 1341
1344 pr_debug("EDMA: EMR%d %08x\n", j, 1342 pr_debug("EDMA: EMR%d %08x\n", j,
1345 edma_read_array(ctlr, EDMA_EMR, j)); 1343 edma_read_array(ctlr, EDMA_EMR, j));
@@ -1348,7 +1346,7 @@ void edma_clean_channel(unsigned channel)
1348 edma_write_array(ctlr, EDMA_EMCR, j, mask); 1346 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1349 /* Clear any SER */ 1347 /* Clear any SER */
1350 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); 1348 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1351 edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3); 1349 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1352 } 1350 }
1353} 1351}
1354EXPORT_SYMBOL(edma_clean_channel); 1352EXPORT_SYMBOL(edma_clean_channel);
@@ -1365,12 +1363,12 @@ void edma_clear_event(unsigned channel)
1365 ctlr = EDMA_CTLR(channel); 1363 ctlr = EDMA_CTLR(channel);
1366 channel = EDMA_CHAN_SLOT(channel); 1364 channel = EDMA_CHAN_SLOT(channel);
1367 1365
1368 if (channel >= edma_info[ctlr]->num_channels) 1366 if (channel >= edma_cc[ctlr]->num_channels)
1369 return; 1367 return;
1370 if (channel < 32) 1368 if (channel < 32)
1371 edma_write(ctlr, EDMA_ECR, 1 << channel); 1369 edma_write(ctlr, EDMA_ECR, BIT(channel));
1372 else 1370 else
1373 edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32)); 1371 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1374} 1372}
1375EXPORT_SYMBOL(edma_clear_event); 1373EXPORT_SYMBOL(edma_clear_event);
1376 1374
@@ -1402,8 +1400,9 @@ static int __init edma_probe(struct platform_device *pdev)
1402 break; 1400 break;
1403 else 1401 else
1404 return -ENODEV; 1402 return -ENODEV;
1405 } else 1403 } else {
1406 found = 1; 1404 found = 1;
1405 }
1407 1406
1408 len[j] = resource_size(r[j]); 1407 len[j] = resource_size(r[j]);
1409 1408
@@ -1420,38 +1419,37 @@ static int __init edma_probe(struct platform_device *pdev)
1420 goto fail1; 1419 goto fail1;
1421 } 1420 }
1422 1421
1423 edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); 1422 edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
1424 if (!edma_info[j]) { 1423 if (!edma_cc[j]) {
1425 status = -ENOMEM; 1424 status = -ENOMEM;
1426 goto fail1; 1425 goto fail1;
1427 } 1426 }
1428 memset(edma_info[j], 0, sizeof(struct edma)); 1427 memset(edma_cc[j], 0, sizeof(struct edma));
1429 1428
1430 edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel, 1429 edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
1431 EDMA_MAX_DMACH); 1430 EDMA_MAX_DMACH);
1432 edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot, 1431 edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
1433 EDMA_MAX_PARAMENTRY); 1432 EDMA_MAX_PARAMENTRY);
1434 edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, 1433 edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
1435 EDMA_MAX_CC);
1436 1434
1437 edma_info[j]->default_queue = info[j].default_queue; 1435 edma_cc[j]->default_queue = info[j].default_queue;
1438 if (!edma_info[j]->default_queue) 1436 if (!edma_cc[j]->default_queue)
1439 edma_info[j]->default_queue = EVENTQ_1; 1437 edma_cc[j]->default_queue = EVENTQ_1;
1440 1438
1441 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", 1439 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1442 edmacc_regs_base[j]); 1440 edmacc_regs_base[j]);
1443 1441
1444 for (i = 0; i < edma_info[j]->num_slots; i++) 1442 for (i = 0; i < edma_cc[j]->num_slots; i++)
1445 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), 1443 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1446 &dummy_paramset, PARM_SIZE); 1444 &dummy_paramset, PARM_SIZE);
1447 1445
1448 /* Mark all channels as unused */ 1446 /* Mark all channels as unused */
1449 memset(edma_info[j]->edma_unused, 0xff, 1447 memset(edma_cc[j]->edma_unused, 0xff,
1450 sizeof(edma_info[j]->edma_unused)); 1448 sizeof(edma_cc[j]->edma_unused));
1451 1449
1452 sprintf(irq_name, "edma%d", j); 1450 sprintf(irq_name, "edma%d", j);
1453 irq[j] = platform_get_irq_byname(pdev, irq_name); 1451 irq[j] = platform_get_irq_byname(pdev, irq_name);
1454 edma_info[j]->irq_res_start = irq[j]; 1452 edma_cc[j]->irq_res_start = irq[j];
1455 status = request_irq(irq[j], dma_irq_handler, 0, "edma", 1453 status = request_irq(irq[j], dma_irq_handler, 0, "edma",
1456 &pdev->dev); 1454 &pdev->dev);
1457 if (status < 0) { 1455 if (status < 0) {
@@ -1462,7 +1460,7 @@ static int __init edma_probe(struct platform_device *pdev)
1462 1460
1463 sprintf(irq_name, "edma%d_err", j); 1461 sprintf(irq_name, "edma%d_err", j);
1464 err_irq[j] = platform_get_irq_byname(pdev, irq_name); 1462 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1465 edma_info[j]->irq_res_end = err_irq[j]; 1463 edma_cc[j]->irq_res_end = err_irq[j];
1466 status = request_irq(err_irq[j], dma_ccerr_handler, 0, 1464 status = request_irq(err_irq[j], dma_ccerr_handler, 0,
1467 "edma_error", &pdev->dev); 1465 "edma_error", &pdev->dev);
1468 if (status < 0) { 1466 if (status < 0) {
@@ -1475,7 +1473,7 @@ static int __init edma_probe(struct platform_device *pdev)
1475 * specified. This way, long transfers on the low priority queue 1473 * specified. This way, long transfers on the low priority queue
1476 * started by the codec engine will not cause audio defects. 1474 * started by the codec engine will not cause audio defects.
1477 */ 1475 */
1478 for (i = 0; i < edma_info[j]->num_channels; i++) 1476 for (i = 0; i < edma_cc[j]->num_channels; i++)
1479 map_dmach_queue(j, i, EVENTQ_1); 1477 map_dmach_queue(j, i, EVENTQ_1);
1480 1478
1481 queue_tc_mapping = info[j].queue_tc_mapping; 1479 queue_tc_mapping = info[j].queue_tc_mapping;
@@ -1538,7 +1536,7 @@ fail1:
1538 release_mem_region(r[i]->start, len[i]); 1536 release_mem_region(r[i]->start, len[i]);
1539 if (edmacc_regs_base[i]) 1537 if (edmacc_regs_base[i])
1540 iounmap(edmacc_regs_base[i]); 1538 iounmap(edmacc_regs_base[i]);
1541 kfree(edma_info[i]); 1539 kfree(edma_cc[i]);
1542 } 1540 }
1543 return status; 1541 return status;
1544} 1542}
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 744755b53236..bf0ff587e46a 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,46 +20,92 @@
20 20
21#include <asm/mach/irq.h> 21#include <asm/mach/irq.h>
22 22
23static DEFINE_SPINLOCK(gpio_lock); 23struct davinci_gpio_regs {
24 24 u32 dir;
25struct davinci_gpio { 25 u32 out_data;
26 struct gpio_chip chip; 26 u32 set_data;
27 struct gpio_controller *__iomem regs; 27 u32 clr_data;
28 int irq_base; 28 u32 in_data;
29 u32 set_rising;
30 u32 clr_rising;
31 u32 set_falling;
32 u32 clr_falling;
33 u32 intstat;
29}; 34};
30 35
31static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; 36#define chip2controller(chip) \
37 container_of(chip, struct davinci_gpio_controller, chip)
38
39static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
40static void __iomem *gpio_base;
41
42static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
43{
44 void __iomem *ptr;
45
46 if (gpio < 32 * 1)
47 ptr = gpio_base + 0x10;
48 else if (gpio < 32 * 2)
49 ptr = gpio_base + 0x38;
50 else if (gpio < 32 * 3)
51 ptr = gpio_base + 0x60;
52 else if (gpio < 32 * 4)
53 ptr = gpio_base + 0x88;
54 else if (gpio < 32 * 5)
55 ptr = gpio_base + 0xb0;
56 else
57 ptr = NULL;
58 return ptr;
59}
32 60
33/* create a non-inlined version */ 61static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
34static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
35{ 62{
36 return __gpio_to_controller(gpio); 63 struct davinci_gpio_regs __iomem *g;
64
65 g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
66
67 return g;
37} 68}
38 69
39static int __init davinci_gpio_irq_setup(void); 70static int __init davinci_gpio_irq_setup(void);
40 71
41/*--------------------------------------------------------------------------*/ 72/*--------------------------------------------------------------------------*/
42 73
43/* 74/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
44 * board setup code *MUST* set PINMUX0 and PINMUX1 as 75static inline int __davinci_direction(struct gpio_chip *chip,
45 * needed, and enable the GPIO clock. 76 unsigned offset, bool out, int value)
46 */
47
48static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
49{ 77{
50 struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); 78 struct davinci_gpio_controller *d = chip2controller(chip);
51 struct gpio_controller *__iomem g = d->regs; 79 struct davinci_gpio_regs __iomem *g = d->regs;
80 unsigned long flags;
52 u32 temp; 81 u32 temp;
82 u32 mask = 1 << offset;
53 83
54 spin_lock(&gpio_lock); 84 spin_lock_irqsave(&d->lock, flags);
55 temp = __raw_readl(&g->dir); 85 temp = __raw_readl(&g->dir);
56 temp |= (1 << offset); 86 if (out) {
87 temp &= ~mask;
88 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
89 } else {
90 temp |= mask;
91 }
57 __raw_writel(temp, &g->dir); 92 __raw_writel(temp, &g->dir);
58 spin_unlock(&gpio_lock); 93 spin_unlock_irqrestore(&d->lock, flags);
59 94
60 return 0; 95 return 0;
61} 96}
62 97
98static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
99{
100 return __davinci_direction(chip, offset, false, 0);
101}
102
103static int
104davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
105{
106 return __davinci_direction(chip, offset, true, value);
107}
108
63/* 109/*
64 * Read the pin's value (works even if it's set up as output); 110 * Read the pin's value (works even if it's set up as output);
65 * returns zero/nonzero. 111 * returns zero/nonzero.
@@ -69,37 +115,20 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
69 */ 115 */
70static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) 116static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
71{ 117{
72 struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); 118 struct davinci_gpio_controller *d = chip2controller(chip);
73 struct gpio_controller *__iomem g = d->regs; 119 struct davinci_gpio_regs __iomem *g = d->regs;
74 120
75 return (1 << offset) & __raw_readl(&g->in_data); 121 return (1 << offset) & __raw_readl(&g->in_data);
76} 122}
77 123
78static int
79davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
80{
81 struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
82 struct gpio_controller *__iomem g = d->regs;
83 u32 temp;
84 u32 mask = 1 << offset;
85
86 spin_lock(&gpio_lock);
87 temp = __raw_readl(&g->dir);
88 temp &= ~mask;
89 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
90 __raw_writel(temp, &g->dir);
91 spin_unlock(&gpio_lock);
92 return 0;
93}
94
95/* 124/*
96 * Assuming the pin is muxed as a gpio output, set its output value. 125 * Assuming the pin is muxed as a gpio output, set its output value.
97 */ 126 */
98static void 127static void
99davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 128davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
100{ 129{
101 struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); 130 struct davinci_gpio_controller *d = chip2controller(chip);
102 struct gpio_controller *__iomem g = d->regs; 131 struct davinci_gpio_regs __iomem *g = d->regs;
103 132
104 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); 133 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
105} 134}
@@ -109,6 +138,10 @@ static int __init davinci_gpio_setup(void)
109 int i, base; 138 int i, base;
110 unsigned ngpio; 139 unsigned ngpio;
111 struct davinci_soc_info *soc_info = &davinci_soc_info; 140 struct davinci_soc_info *soc_info = &davinci_soc_info;
141 struct davinci_gpio_regs *regs;
142
143 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
144 return 0;
112 145
113 /* 146 /*
114 * The gpio banks conceptually expose a segmented bitmap, 147 * The gpio banks conceptually expose a segmented bitmap,
@@ -124,6 +157,10 @@ static int __init davinci_gpio_setup(void)
124 if (WARN_ON(DAVINCI_N_GPIO < ngpio)) 157 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
125 ngpio = DAVINCI_N_GPIO; 158 ngpio = DAVINCI_N_GPIO;
126 159
160 gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
161 if (WARN_ON(!gpio_base))
162 return -ENOMEM;
163
127 for (i = 0, base = 0; base < ngpio; i++, base += 32) { 164 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
128 chips[i].chip.label = "DaVinci"; 165 chips[i].chip.label = "DaVinci";
129 166
@@ -137,11 +174,20 @@ static int __init davinci_gpio_setup(void)
137 if (chips[i].chip.ngpio > 32) 174 if (chips[i].chip.ngpio > 32)
138 chips[i].chip.ngpio = 32; 175 chips[i].chip.ngpio = 32;
139 176
140 chips[i].regs = gpio2controller(base); 177 spin_lock_init(&chips[i].lock);
178
179 regs = gpio2regs(base);
180 chips[i].regs = regs;
181 chips[i].set_data = &regs->set_data;
182 chips[i].clr_data = &regs->clr_data;
183 chips[i].in_data = &regs->in_data;
141 184
142 gpiochip_add(&chips[i].chip); 185 gpiochip_add(&chips[i].chip);
143 } 186 }
144 187
188 soc_info->gpio_ctlrs = chips;
189 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
190
145 davinci_gpio_irq_setup(); 191 davinci_gpio_irq_setup();
146 return 0; 192 return 0;
147} 193}
@@ -161,7 +207,7 @@ pure_initcall(davinci_gpio_setup);
161 207
162static void gpio_irq_disable(unsigned irq) 208static void gpio_irq_disable(unsigned irq)
163{ 209{
164 struct gpio_controller *__iomem g = get_irq_chip_data(irq); 210 struct davinci_gpio_regs __iomem *g = irq2regs(irq);
165 u32 mask = (u32) get_irq_data(irq); 211 u32 mask = (u32) get_irq_data(irq);
166 212
167 __raw_writel(mask, &g->clr_falling); 213 __raw_writel(mask, &g->clr_falling);
@@ -170,7 +216,7 @@ static void gpio_irq_disable(unsigned irq)
170 216
171static void gpio_irq_enable(unsigned irq) 217static void gpio_irq_enable(unsigned irq)
172{ 218{
173 struct gpio_controller *__iomem g = get_irq_chip_data(irq); 219 struct davinci_gpio_regs __iomem *g = irq2regs(irq);
174 u32 mask = (u32) get_irq_data(irq); 220 u32 mask = (u32) get_irq_data(irq);
175 unsigned status = irq_desc[irq].status; 221 unsigned status = irq_desc[irq].status;
176 222
@@ -186,7 +232,7 @@ static void gpio_irq_enable(unsigned irq)
186 232
187static int gpio_irq_type(unsigned irq, unsigned trigger) 233static int gpio_irq_type(unsigned irq, unsigned trigger)
188{ 234{
189 struct gpio_controller *__iomem g = get_irq_chip_data(irq); 235 struct davinci_gpio_regs __iomem *g = irq2regs(irq);
190 u32 mask = (u32) get_irq_data(irq); 236 u32 mask = (u32) get_irq_data(irq);
191 237
192 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 238 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +261,7 @@ static struct irq_chip gpio_irqchip = {
215static void 261static void
216gpio_irq_handler(unsigned irq, struct irq_desc *desc) 262gpio_irq_handler(unsigned irq, struct irq_desc *desc)
217{ 263{
218 struct gpio_controller *__iomem g = get_irq_chip_data(irq); 264 struct davinci_gpio_regs __iomem *g = irq2regs(irq);
219 u32 mask = 0xffff; 265 u32 mask = 0xffff;
220 266
221 /* we only care about one bank */ 267 /* we only care about one bank */
@@ -253,7 +299,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
253 299
254static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) 300static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
255{ 301{
256 struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); 302 struct davinci_gpio_controller *d = chip2controller(chip);
257 303
258 if (d->irq_base >= 0) 304 if (d->irq_base >= 0)
259 return d->irq_base + offset; 305 return d->irq_base + offset;
@@ -276,7 +322,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
276 322
277static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) 323static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
278{ 324{
279 struct gpio_controller *__iomem g = get_irq_chip_data(irq); 325 struct davinci_gpio_regs __iomem *g = irq2regs(irq);
280 u32 mask = (u32) get_irq_data(irq); 326 u32 mask = (u32) get_irq_data(irq);
281 327
282 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 328 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -305,7 +351,7 @@ static int __init davinci_gpio_irq_setup(void)
305 u32 binten = 0; 351 u32 binten = 0;
306 unsigned ngpio, bank_irq; 352 unsigned ngpio, bank_irq;
307 struct davinci_soc_info *soc_info = &davinci_soc_info; 353 struct davinci_soc_info *soc_info = &davinci_soc_info;
308 struct gpio_controller *__iomem g; 354 struct davinci_gpio_regs __iomem *g;
309 355
310 ngpio = soc_info->gpio_num; 356 ngpio = soc_info->gpio_num;
311 357
@@ -354,7 +400,7 @@ static int __init davinci_gpio_irq_setup(void)
354 gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; 400 gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
355 401
356 /* default trigger: both edges */ 402 /* default trigger: both edges */
357 g = gpio2controller(0); 403 g = gpio2regs(0);
358 __raw_writel(~0, &g->set_falling); 404 __raw_writel(~0, &g->set_falling);
359 __raw_writel(~0, &g->set_rising); 405 __raw_writel(~0, &g->set_rising);
360 406
@@ -362,7 +408,7 @@ static int __init davinci_gpio_irq_setup(void)
362 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { 408 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
363 set_irq_chip(irq, &gpio_irqchip_unbanked); 409 set_irq_chip(irq, &gpio_irqchip_unbanked);
364 set_irq_data(irq, (void *) __gpio_mask(gpio)); 410 set_irq_data(irq, (void *) __gpio_mask(gpio));
365 set_irq_chip_data(irq, g); 411 set_irq_chip_data(irq, (__force void *) g);
366 irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; 412 irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
367 } 413 }
368 414
@@ -379,18 +425,18 @@ static int __init davinci_gpio_irq_setup(void)
379 unsigned i; 425 unsigned i;
380 426
381 /* disabled by default, enabled only as needed */ 427 /* disabled by default, enabled only as needed */
382 g = gpio2controller(gpio); 428 g = gpio2regs(gpio);
383 __raw_writel(~0, &g->clr_falling); 429 __raw_writel(~0, &g->clr_falling);
384 __raw_writel(~0, &g->clr_rising); 430 __raw_writel(~0, &g->clr_rising);
385 431
386 /* set up all irqs in this bank */ 432 /* set up all irqs in this bank */
387 set_irq_chained_handler(bank_irq, gpio_irq_handler); 433 set_irq_chained_handler(bank_irq, gpio_irq_handler);
388 set_irq_chip_data(bank_irq, g); 434 set_irq_chip_data(bank_irq, (__force void *) g);
389 set_irq_data(bank_irq, (void *)irq); 435 set_irq_data(bank_irq, (void *) irq);
390 436
391 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { 437 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
392 set_irq_chip(irq, &gpio_irqchip); 438 set_irq_chip(irq, &gpio_irqchip);
393 set_irq_chip_data(irq, g); 439 set_irq_chip_data(irq, (__force void *) g);
394 set_irq_data(irq, (void *) __gpio_mask(gpio)); 440 set_irq_data(irq, (void *) __gpio_mask(gpio));
395 set_irq_handler(irq, handle_simple_irq); 441 set_irq_handler(irq, handle_simple_irq);
396 set_irq_flags(irq, IRQF_VALID); 442 set_irq_flags(irq, IRQF_VALID);
@@ -403,7 +449,7 @@ done:
403 /* BINTEN -- per-bank interrupt enable. genirq would also let these 449 /* BINTEN -- per-bank interrupt enable. genirq would also let these
404 * bits be set/cleared dynamically. 450 * bits be set/cleared dynamically.
405 */ 451 */
406 __raw_writel(binten, soc_info->gpio_base + 0x08); 452 __raw_writel(binten, gpio_base + 0x08);
407 453
408 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); 454 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
409 455
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 50a955f05ef9..a57cba21e21e 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -12,6 +12,9 @@
12#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H 12#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
13#define __ARCH_ARM_MACH_DAVINCI_COMMON_H 13#define __ARCH_ARM_MACH_DAVINCI_COMMON_H
14 14
15#include <linux/compiler.h>
16#include <linux/types.h>
17
15struct sys_timer; 18struct sys_timer;
16 19
17extern struct sys_timer davinci_timer; 20extern struct sys_timer davinci_timer;
@@ -21,7 +24,7 @@ extern void __iomem *davinci_intc_base;
21extern int davinci_intc_type; 24extern int davinci_intc_type;
22 25
23struct davinci_timer_instance { 26struct davinci_timer_instance {
24 void __iomem *base; 27 u32 base;
25 u32 bottom_irq; 28 u32 bottom_irq;
26 u32 top_irq; 29 u32 top_irq;
27 unsigned long cmp_off; 30 unsigned long cmp_off;
@@ -34,39 +37,54 @@ struct davinci_timer_info {
34 unsigned int clocksource_id; 37 unsigned int clocksource_id;
35}; 38};
36 39
37/* SoC specific init support */ 40struct davinci_gpio_controller;
41
42/*
43 * SoC info passed into common davinci modules.
44 *
45 * Base addresses in this structure should be physical and not virtual.
46 * Modules that take such base addresses, should internally ioremap() them to
47 * use.
48 */
38struct davinci_soc_info { 49struct davinci_soc_info {
39 struct map_desc *io_desc; 50 struct map_desc *io_desc;
40 unsigned long io_desc_num; 51 unsigned long io_desc_num;
41 u32 cpu_id; 52 u32 cpu_id;
42 u32 jtag_id; 53 u32 jtag_id;
43 void __iomem *jtag_id_base; 54 u32 jtag_id_reg;
44 struct davinci_id *ids; 55 struct davinci_id *ids;
45 unsigned long ids_num; 56 unsigned long ids_num;
46 struct clk_lookup *cpu_clks; 57 struct clk_lookup *cpu_clks;
47 void __iomem **psc_bases; 58 u32 *psc_bases;
48 unsigned long psc_bases_num; 59 unsigned long psc_bases_num;
49 void __iomem *pinmux_base; 60 u32 pinmux_base;
50 const struct mux_config *pinmux_pins; 61 const struct mux_config *pinmux_pins;
51 unsigned long pinmux_pins_num; 62 unsigned long pinmux_pins_num;
52 void __iomem *intc_base; 63 u32 intc_base;
53 int intc_type; 64 int intc_type;
54 u8 *intc_irq_prios; 65 u8 *intc_irq_prios;
55 unsigned long intc_irq_num; 66 unsigned long intc_irq_num;
67 u32 *intc_host_map;
56 struct davinci_timer_info *timer_info; 68 struct davinci_timer_info *timer_info;
57 void __iomem *gpio_base; 69 int gpio_type;
70 u32 gpio_base;
58 unsigned gpio_num; 71 unsigned gpio_num;
59 unsigned gpio_irq; 72 unsigned gpio_irq;
60 unsigned gpio_unbanked; 73 unsigned gpio_unbanked;
74 struct davinci_gpio_controller *gpio_ctlrs;
75 int gpio_ctlrs_num;
61 struct platform_device *serial_dev; 76 struct platform_device *serial_dev;
62 struct emac_platform_data *emac_pdata; 77 struct emac_platform_data *emac_pdata;
63 dma_addr_t sram_dma; 78 dma_addr_t sram_dma;
64 unsigned sram_len; 79 unsigned sram_len;
80 struct platform_device *reset_device;
81 void (*reset)(struct platform_device *);
65}; 82};
66 83
67extern struct davinci_soc_info davinci_soc_info; 84extern struct davinci_soc_info davinci_soc_info;
68 85
69extern void davinci_common_init(struct davinci_soc_info *soc_info); 86extern void davinci_common_init(struct davinci_soc_info *soc_info);
87extern void davinci_init_ide(void);
70 88
71/* standard place to map on-chip SRAMs; they *may* support DMA */ 89/* standard place to map on-chip SRAMs; they *may* support DMA */
72#define SRAM_VIRT 0xfffe0000 90#define SRAM_VIRT 0xfffe0000
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index c4d27eec8064..4e8190eed673 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -51,7 +51,6 @@
51#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) 51#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) 52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
53 53
54void __init cp_intc_init(void __iomem *base, unsigned short num_irq, 54void __init cp_intc_init(void);
55 u8 *irq_prio);
56 55
57#endif /* __ASM_HARDWARE_CP_INTC_H */ 56#endif /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 189b1ff13642..cea6b8972043 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -33,6 +33,7 @@ struct davinci_id {
33#define DAVINCI_CPU_ID_DM365 0x03650000 33#define DAVINCI_CPU_ID_DM365 0x03650000
34#define DAVINCI_CPU_ID_DA830 0x08300000 34#define DAVINCI_CPU_ID_DA830 0x08300000
35#define DAVINCI_CPU_ID_DA850 0x08500000 35#define DAVINCI_CPU_ID_DA850 0x08500000
36#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
36 37
37#define IS_DAVINCI_CPU(type, id) \ 38#define IS_DAVINCI_CPU(type, id) \
38static inline int is_davinci_ ##type(void) \ 39static inline int is_davinci_ ##type(void) \
@@ -46,6 +47,7 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
46IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) 47IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
47IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) 48IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
48IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) 49IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
50IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
49 51
50#ifdef CONFIG_ARCH_DAVINCI_DM644x 52#ifdef CONFIG_ARCH_DAVINCI_DM644x
51#define cpu_is_davinci_dm644x() is_davinci_dm644x() 53#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -83,4 +85,10 @@ IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
83#define cpu_is_davinci_da850() 0 85#define cpu_is_davinci_da850() 0
84#endif 86#endif
85 87
88#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
89#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
90#else
91#define cpu_is_davinci_tnetv107x() 0
92#endif
93
86#endif 94#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 03acfd39042b..1b31a9aa8fba 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -64,27 +64,6 @@ extern void __iomem *da8xx_syscfg1_base;
64#define DA8XX_DDR2_CTL_BASE 0xb0000000 64#define DA8XX_DDR2_CTL_BASE 0xb0000000
65#define DA8XX_ARM_RAM_BASE 0xffff0000 65#define DA8XX_ARM_RAM_BASE 0xffff0000
66 66
67#define PINMUX0 0x00
68#define PINMUX1 0x04
69#define PINMUX2 0x08
70#define PINMUX3 0x0c
71#define PINMUX4 0x10
72#define PINMUX5 0x14
73#define PINMUX6 0x18
74#define PINMUX7 0x1c
75#define PINMUX8 0x20
76#define PINMUX9 0x24
77#define PINMUX10 0x28
78#define PINMUX11 0x2c
79#define PINMUX12 0x30
80#define PINMUX13 0x34
81#define PINMUX14 0x38
82#define PINMUX15 0x3c
83#define PINMUX16 0x40
84#define PINMUX17 0x44
85#define PINMUX18 0x48
86#define PINMUX19 0x4c
87
88void __init da830_init(void); 67void __init da830_init(void);
89void __init da850_init(void); 68void __init da850_init(void);
90 69
@@ -108,6 +87,8 @@ extern struct emac_platform_data da8xx_emac_pdata;
108extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; 87extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
109extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; 88extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
110 89
90extern struct platform_device da8xx_wdt_device;
91
111extern const short da830_emif25_pins[]; 92extern const short da830_emif25_pins[];
112extern const short da830_spi0_pins[]; 93extern const short da830_spi0_pins[];
113extern const short da830_spi1_pins[]; 94extern const short da830_spi1_pins[];
@@ -146,10 +127,4 @@ extern const short da850_mmcsd0_pins[];
146extern const short da850_nand_pins[]; 127extern const short da850_nand_pins[];
147extern const short da850_nor_pins[]; 128extern const short da850_nor_pins[];
148 129
149#ifdef CONFIG_DAVINCI_MUX
150int da8xx_pinmux_setup(const short pins[]);
151#else
152static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
153#endif
154
155#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ 130#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
index 85536d8e8336..36dff4a0ce3f 100644
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -15,6 +15,9 @@
15#include <mach/asp.h> 15#include <mach/asp.h>
16#include <media/davinci/vpfe_capture.h> 16#include <media/davinci/vpfe_capture.h>
17 17
18#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000
19#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
20
18#define ASP1_TX_EVT_EN 1 21#define ASP1_TX_EVT_EN 1
19#define ASP1_RX_EVT_EN 2 22#define ASP1_RX_EVT_EN 2
20 23
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 3a37b5a6983c..ea5df3b49ec4 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -36,6 +36,10 @@
36#define DAVINCI_DMA_VC_TX 2 36#define DAVINCI_DMA_VC_TX 2
37#define DAVINCI_DMA_VC_RX 3 37#define DAVINCI_DMA_VC_RX 3
38 38
39#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000
40#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
41#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
42
39void __init dm365_init(void); 43void __init dm365_init(void);
40void __init dm365_init_asp(struct snd_platform_data *pdata); 44void __init dm365_init_asp(struct snd_platform_data *pdata);
41void __init dm365_init_vc(struct snd_platform_data *pdata); 45void __init dm365_init_vc(struct snd_platform_data *pdata);
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 1a8b09ccc3c8..6fca568a0fd2 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -34,6 +34,12 @@
34#define DM644X_EMAC_MDIO_OFFSET (0x4000) 34#define DM644X_EMAC_MDIO_OFFSET (0x4000)
35#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) 35#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
36 36
37#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000
38#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
39#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
40#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
41#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
42
37void __init dm644x_init(void); 43void __init dm644x_init(void);
38void __init dm644x_init_asp(struct snd_platform_data *pdata); 44void __init dm644x_init_asp(struct snd_platform_data *pdata);
39void dm644x_set_vpfe_config(struct vpfe_config *cfg); 45void dm644x_set_vpfe_config(struct vpfe_config *cfg);
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 846da98b619a..add6f794a362 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -25,10 +25,10 @@
25#define DM646X_EMAC_MDIO_OFFSET (0x4000) 25#define DM646X_EMAC_MDIO_OFFSET (0x4000)
26#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) 26#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
27 27
28#define DM646X_ATA_REG_BASE (0x01C66000) 28#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
29#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
29 30
30void __init dm646x_init(void); 31void __init dm646x_init(void);
31void __init dm646x_init_ide(void);
32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); 32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); 33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
34void __init dm646x_board_setup_refclk(struct clk *clk); 34void __init dm646x_board_setup_refclk(struct clk *clk);
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index f3b8ef878158..504cc180a60b 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -14,6 +14,8 @@
14#define __DAVINCI_GPIO_H 14#define __DAVINCI_GPIO_H
15 15
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/spinlock.h>
18
17#include <asm-generic/gpio.h> 19#include <asm-generic/gpio.h>
18 20
19#include <mach/irqs.h> 21#include <mach/irqs.h>
@@ -21,6 +23,10 @@
21 23
22#define DAVINCI_GPIO_BASE 0x01C67000 24#define DAVINCI_GPIO_BASE 0x01C67000
23 25
26enum davinci_gpio_type {
27 GPIO_TYPE_DAVINCI = 0,
28};
29
24/* 30/*
25 * basic gpio routines 31 * basic gpio routines
26 * 32 *
@@ -45,17 +51,14 @@
45/* Convert GPIO signal to GPIO pin number */ 51/* Convert GPIO signal to GPIO pin number */
46#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) 52#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
47 53
48struct gpio_controller { 54struct davinci_gpio_controller {
49 u32 dir; 55 struct gpio_chip chip;
50 u32 out_data; 56 int irq_base;
51 u32 set_data; 57 spinlock_t lock;
52 u32 clr_data; 58 void __iomem *regs;
53 u32 in_data; 59 void __iomem *set_data;
54 u32 set_rising; 60 void __iomem *clr_data;
55 u32 clr_rising; 61 void __iomem *in_data;
56 u32 set_falling;
57 u32 clr_falling;
58 u32 intstat;
59}; 62};
60 63
61/* The __gpio_to_controller() and __gpio_mask() functions inline to constants 64/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
@@ -67,25 +70,16 @@ struct gpio_controller {
67 * 70 *
68 * These are NOT part of the cross-platform GPIO interface 71 * These are NOT part of the cross-platform GPIO interface
69 */ 72 */
70static inline struct gpio_controller *__iomem 73static inline struct davinci_gpio_controller *
71__gpio_to_controller(unsigned gpio) 74__gpio_to_controller(unsigned gpio)
72{ 75{
73 void *__iomem ptr; 76 struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs;
74 void __iomem *base = davinci_soc_info.gpio_base; 77 int index = gpio / 32;
75 78
76 if (gpio < 32 * 1) 79 if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num)
77 ptr = base + 0x10; 80 return NULL;
78 else if (gpio < 32 * 2) 81
79 ptr = base + 0x38; 82 return ctlrs + index;
80 else if (gpio < 32 * 3)
81 ptr = base + 0x60;
82 else if (gpio < 32 * 4)
83 ptr = base + 0x88;
84 else if (gpio < 32 * 5)
85 ptr = base + 0xb0;
86 else
87 ptr = NULL;
88 return ptr;
89} 83}
90 84
91static inline u32 __gpio_mask(unsigned gpio) 85static inline u32 __gpio_mask(unsigned gpio)
@@ -101,16 +95,16 @@ static inline u32 __gpio_mask(unsigned gpio)
101 */ 95 */
102static inline void gpio_set_value(unsigned gpio, int value) 96static inline void gpio_set_value(unsigned gpio, int value)
103{ 97{
104 if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) { 98 if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
105 struct gpio_controller *__iomem g; 99 struct davinci_gpio_controller *ctlr;
106 u32 mask; 100 u32 mask;
107 101
108 g = __gpio_to_controller(gpio); 102 ctlr = __gpio_to_controller(gpio);
109 mask = __gpio_mask(gpio); 103 mask = __gpio_mask(gpio);
110 if (value) 104 if (value)
111 __raw_writel(mask, &g->set_data); 105 __raw_writel(mask, ctlr->set_data);
112 else 106 else
113 __raw_writel(mask, &g->clr_data); 107 __raw_writel(mask, ctlr->clr_data);
114 return; 108 return;
115 } 109 }
116 110
@@ -128,18 +122,18 @@ static inline void gpio_set_value(unsigned gpio, int value)
128 */ 122 */
129static inline int gpio_get_value(unsigned gpio) 123static inline int gpio_get_value(unsigned gpio)
130{ 124{
131 struct gpio_controller *__iomem g; 125 struct davinci_gpio_controller *ctlr;
132 126
133 if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO) 127 if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num)
134 return __gpio_get_value(gpio); 128 return __gpio_get_value(gpio);
135 129
136 g = __gpio_to_controller(gpio); 130 ctlr = __gpio_to_controller(gpio);
137 return __gpio_mask(gpio) & __raw_readl(&g->in_data); 131 return __gpio_mask(gpio) & __raw_readl(ctlr->in_data);
138} 132}
139 133
140static inline int gpio_cansleep(unsigned gpio) 134static inline int gpio_cansleep(unsigned gpio)
141{ 135{
142 if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO) 136 if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num)
143 return 0; 137 return 0;
144 else 138 else
145 return __gpio_cansleep(gpio); 139 return __gpio_cansleep(gpio);
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 354af71798dc..ec76c7775c2e 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -401,6 +401,103 @@
401 401
402#define DA850_N_CP_INTC_IRQ 101 402#define DA850_N_CP_INTC_IRQ 101
403 403
404
405/* TNETV107X specific interrupts */
406#define IRQ_TNETV107X_TDM1_TXDMA 0
407#define IRQ_TNETV107X_EXT_INT_0 1
408#define IRQ_TNETV107X_EXT_INT_1 2
409#define IRQ_TNETV107X_GPIO_INT12 3
410#define IRQ_TNETV107X_GPIO_INT13 4
411#define IRQ_TNETV107X_TIMER_0_TINT12 5
412#define IRQ_TNETV107X_TIMER_1_TINT12 6
413#define IRQ_TNETV107X_UART0 7
414#define IRQ_TNETV107X_TDM1_RXDMA 8
415#define IRQ_TNETV107X_MCDMA_INT0 9
416#define IRQ_TNETV107X_MCDMA_INT1 10
417#define IRQ_TNETV107X_TPCC 11
418#define IRQ_TNETV107X_TPCC_INT0 12
419#define IRQ_TNETV107X_TPCC_INT1 13
420#define IRQ_TNETV107X_TPCC_INT2 14
421#define IRQ_TNETV107X_TPCC_INT3 15
422#define IRQ_TNETV107X_TPTC0 16
423#define IRQ_TNETV107X_TPTC1 17
424#define IRQ_TNETV107X_TIMER_0_TINT34 18
425#define IRQ_TNETV107X_ETHSS 19
426#define IRQ_TNETV107X_TIMER_1_TINT34 20
427#define IRQ_TNETV107X_DSP2ARM_INT0 21
428#define IRQ_TNETV107X_DSP2ARM_INT1 22
429#define IRQ_TNETV107X_ARM_NPMUIRQ 23
430#define IRQ_TNETV107X_USB1 24
431#define IRQ_TNETV107X_VLYNQ 25
432#define IRQ_TNETV107X_UART0_DMATX 26
433#define IRQ_TNETV107X_UART0_DMARX 27
434#define IRQ_TNETV107X_TDM1_TXMCSP 28
435#define IRQ_TNETV107X_SSP 29
436#define IRQ_TNETV107X_MCDMA_INT2 30
437#define IRQ_TNETV107X_MCDMA_INT3 31
438#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
439#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
440#define IRQ_TNETV107X_USB0 34
441#define IRQ_TNETV107X_USB_CDMA 35
442#define IRQ_TNETV107X_LCD 36
443#define IRQ_TNETV107X_KEYPAD 37
444#define IRQ_TNETV107X_KEYPAD_FREE 38
445#define IRQ_TNETV107X_RNG 39
446#define IRQ_TNETV107X_PKA 40
447#define IRQ_TNETV107X_TDM0_TXDMA 41
448#define IRQ_TNETV107X_TDM0_RXDMA 42
449#define IRQ_TNETV107X_TDM0_TXMCSP 43
450#define IRQ_TNETV107X_TDM0_RXMCSP 44
451#define IRQ_TNETV107X_TDM1_RXMCSP 45
452#define IRQ_TNETV107X_SDIO1 46
453#define IRQ_TNETV107X_SDIO0 47
454#define IRQ_TNETV107X_TSC 48
455#define IRQ_TNETV107X_TS 49
456#define IRQ_TNETV107X_UART1 50
457#define IRQ_TNETV107X_MBX_LITE 51
458#define IRQ_TNETV107X_GPIO_INT00 52
459#define IRQ_TNETV107X_GPIO_INT01 53
460#define IRQ_TNETV107X_GPIO_INT02 54
461#define IRQ_TNETV107X_GPIO_INT03 55
462#define IRQ_TNETV107X_UART2 56
463#define IRQ_TNETV107X_UART2_DMATX 57
464#define IRQ_TNETV107X_UART2_DMARX 58
465#define IRQ_TNETV107X_IMCOP_IMX 59
466#define IRQ_TNETV107X_IMCOP_VLCD 60
467#define IRQ_TNETV107X_AES 61
468#define IRQ_TNETV107X_DES 62
469#define IRQ_TNETV107X_SHAMD5 63
470#define IRQ_TNETV107X_TPCC_ERR 68
471#define IRQ_TNETV107X_TPCC_PROT 69
472#define IRQ_TNETV107X_TPTC0_ERR 70
473#define IRQ_TNETV107X_TPTC1_ERR 71
474#define IRQ_TNETV107X_UART0_ERR 72
475#define IRQ_TNETV107X_UART1_ERR 73
476#define IRQ_TNETV107X_AEMIF_ERR 74
477#define IRQ_TNETV107X_DDR_ERR 75
478#define IRQ_TNETV107X_WDTARM_INT0 76
479#define IRQ_TNETV107X_MCDMA_ERR 77
480#define IRQ_TNETV107X_GPIO_ERR 78
481#define IRQ_TNETV107X_MPU_ADDR 79
482#define IRQ_TNETV107X_MPU_PROT 80
483#define IRQ_TNETV107X_IOPU_ADDR 81
484#define IRQ_TNETV107X_IOPU_PROT 82
485#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
486#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
487#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
488#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
489#define IRQ_TNETV107X_PLL_UNLOCK 87
490#define IRQ_TNETV107X_WDTDSP_INT0 88
491#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
492#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
493#define IRQ_TNETV107X_PBIST_CPU 91
494#define IRQ_TNETV107X_WDTARM 92
495#define IRQ_TNETV107X_PSC 93
496#define IRQ_TNETV107X_MMC0 94
497#define IRQ_TNETV107X_MMC1 95
498
499#define TNETV107X_N_CP_INTC_IRQ 96
500
404/* da850 currently has the most gpio pins (144) */ 501/* da850 currently has the most gpio pins (144) */
405#define DAVINCI_N_GPIO 144 502#define DAVINCI_N_GPIO 144
406/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ 503/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 2a68c1d8a24b..de11aac76a80 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -194,11 +194,14 @@ enum davinci_dm365_index {
194 DM365_I2C_SCL, 194 DM365_I2C_SCL,
195 195
196 /* AEMIF */ 196 /* AEMIF */
197 DM365_AEMIF_AR, 197 DM365_AEMIF_AR_A14,
198 DM365_AEMIF_AR_BA0,
198 DM365_AEMIF_A3, 199 DM365_AEMIF_A3,
199 DM365_AEMIF_A7, 200 DM365_AEMIF_A7,
200 DM365_AEMIF_D15_8, 201 DM365_AEMIF_D15_8,
201 DM365_AEMIF_CE0, 202 DM365_AEMIF_CE0,
203 DM365_AEMIF_CE1,
204 DM365_AEMIF_WE_OE,
202 205
203 /* ASP0 function */ 206 /* ASP0 function */
204 DM365_MCBSP0_BDX, 207 DM365_MCBSP0_BDX,
@@ -287,10 +290,19 @@ enum davinci_dm365_index {
287 DM365_SPI4_SDENA0, 290 DM365_SPI4_SDENA0,
288 DM365_SPI4_SDENA1, 291 DM365_SPI4_SDENA1,
289 292
293 /* Clock */
294 DM365_CLKOUT0,
295 DM365_CLKOUT1,
296 DM365_CLKOUT2,
297
290 /* GPIO */ 298 /* GPIO */
291 DM365_GPIO20, 299 DM365_GPIO20,
300 DM365_GPIO30,
301 DM365_GPIO31,
302 DM365_GPIO32,
292 DM365_GPIO33, 303 DM365_GPIO33,
293 DM365_GPIO40, 304 DM365_GPIO40,
305 DM365_GPIO64_57,
294 306
295 /* Video */ 307 /* Video */
296 DM365_VOUT_FIELD, 308 DM365_VOUT_FIELD,
@@ -904,12 +916,288 @@ enum davinci_da850_index {
904 DA850_RTC_ALARM, 916 DA850_RTC_ALARM,
905}; 917};
906 918
919enum davinci_tnetv107x_index {
920 TNETV107X_ASR_A00,
921 TNETV107X_GPIO32,
922 TNETV107X_ASR_A01,
923 TNETV107X_GPIO33,
924 TNETV107X_ASR_A02,
925 TNETV107X_GPIO34,
926 TNETV107X_ASR_A03,
927 TNETV107X_GPIO35,
928 TNETV107X_ASR_A04,
929 TNETV107X_GPIO36,
930 TNETV107X_ASR_A05,
931 TNETV107X_GPIO37,
932 TNETV107X_ASR_A06,
933 TNETV107X_GPIO38,
934 TNETV107X_ASR_A07,
935 TNETV107X_GPIO39,
936 TNETV107X_ASR_A08,
937 TNETV107X_GPIO40,
938 TNETV107X_ASR_A09,
939 TNETV107X_GPIO41,
940 TNETV107X_ASR_A10,
941 TNETV107X_GPIO42,
942 TNETV107X_ASR_A11,
943 TNETV107X_BOOT_STRP_0,
944 TNETV107X_ASR_A12,
945 TNETV107X_BOOT_STRP_1,
946 TNETV107X_ASR_A13,
947 TNETV107X_GPIO43,
948 TNETV107X_ASR_A14,
949 TNETV107X_GPIO44,
950 TNETV107X_ASR_A15,
951 TNETV107X_GPIO45,
952 TNETV107X_ASR_A16,
953 TNETV107X_GPIO46,
954 TNETV107X_ASR_A17,
955 TNETV107X_GPIO47,
956 TNETV107X_ASR_A18,
957 TNETV107X_GPIO48,
958 TNETV107X_SDIO1_DATA3_0,
959 TNETV107X_ASR_A19,
960 TNETV107X_GPIO49,
961 TNETV107X_SDIO1_DATA2_0,
962 TNETV107X_ASR_A20,
963 TNETV107X_GPIO50,
964 TNETV107X_SDIO1_DATA1_0,
965 TNETV107X_ASR_A21,
966 TNETV107X_GPIO51,
967 TNETV107X_SDIO1_DATA0_0,
968 TNETV107X_ASR_A22,
969 TNETV107X_GPIO52,
970 TNETV107X_SDIO1_CMD_0,
971 TNETV107X_ASR_A23,
972 TNETV107X_GPIO53,
973 TNETV107X_SDIO1_CLK_0,
974 TNETV107X_ASR_BA_1,
975 TNETV107X_GPIO54,
976 TNETV107X_SYS_PLL_CLK,
977 TNETV107X_ASR_CS0,
978 TNETV107X_ASR_CS1,
979 TNETV107X_ASR_CS2,
980 TNETV107X_TDM_PLL_CLK,
981 TNETV107X_ASR_CS3,
982 TNETV107X_ETH_PHY_CLK,
983 TNETV107X_ASR_D00,
984 TNETV107X_GPIO55,
985 TNETV107X_ASR_D01,
986 TNETV107X_GPIO56,
987 TNETV107X_ASR_D02,
988 TNETV107X_GPIO57,
989 TNETV107X_ASR_D03,
990 TNETV107X_GPIO58,
991 TNETV107X_ASR_D04,
992 TNETV107X_GPIO59_0,
993 TNETV107X_ASR_D05,
994 TNETV107X_GPIO60_0,
995 TNETV107X_ASR_D06,
996 TNETV107X_GPIO61_0,
997 TNETV107X_ASR_D07,
998 TNETV107X_GPIO62_0,
999 TNETV107X_ASR_D08,
1000 TNETV107X_GPIO63_0,
1001 TNETV107X_ASR_D09,
1002 TNETV107X_GPIO64_0,
1003 TNETV107X_ASR_D10,
1004 TNETV107X_SDIO1_DATA3_1,
1005 TNETV107X_ASR_D11,
1006 TNETV107X_SDIO1_DATA2_1,
1007 TNETV107X_ASR_D12,
1008 TNETV107X_SDIO1_DATA1_1,
1009 TNETV107X_ASR_D13,
1010 TNETV107X_SDIO1_DATA0_1,
1011 TNETV107X_ASR_D14,
1012 TNETV107X_SDIO1_CMD_1,
1013 TNETV107X_ASR_D15,
1014 TNETV107X_SDIO1_CLK_1,
1015 TNETV107X_ASR_OE,
1016 TNETV107X_BOOT_STRP_2,
1017 TNETV107X_ASR_RNW,
1018 TNETV107X_GPIO29_0,
1019 TNETV107X_ASR_WAIT,
1020 TNETV107X_GPIO30_0,
1021 TNETV107X_ASR_WE,
1022 TNETV107X_BOOT_STRP_3,
1023 TNETV107X_ASR_WE_DQM0,
1024 TNETV107X_GPIO31,
1025 TNETV107X_LCD_PD17_0,
1026 TNETV107X_ASR_WE_DQM1,
1027 TNETV107X_ASR_BA0_0,
1028 TNETV107X_VLYNQ_CLK,
1029 TNETV107X_GPIO14,
1030 TNETV107X_LCD_PD19_0,
1031 TNETV107X_VLYNQ_RXD0,
1032 TNETV107X_GPIO15,
1033 TNETV107X_LCD_PD20_0,
1034 TNETV107X_VLYNQ_RXD1,
1035 TNETV107X_GPIO16,
1036 TNETV107X_LCD_PD21_0,
1037 TNETV107X_VLYNQ_TXD0,
1038 TNETV107X_GPIO17,
1039 TNETV107X_LCD_PD22_0,
1040 TNETV107X_VLYNQ_TXD1,
1041 TNETV107X_GPIO18,
1042 TNETV107X_LCD_PD23_0,
1043 TNETV107X_SDIO0_CLK,
1044 TNETV107X_GPIO19,
1045 TNETV107X_SDIO0_CMD,
1046 TNETV107X_GPIO20,
1047 TNETV107X_SDIO0_DATA0,
1048 TNETV107X_GPIO21,
1049 TNETV107X_SDIO0_DATA1,
1050 TNETV107X_GPIO22,
1051 TNETV107X_SDIO0_DATA2,
1052 TNETV107X_GPIO23,
1053 TNETV107X_SDIO0_DATA3,
1054 TNETV107X_GPIO24,
1055 TNETV107X_EMU0,
1056 TNETV107X_EMU1,
1057 TNETV107X_RTCK,
1058 TNETV107X_TRST_N,
1059 TNETV107X_TCK,
1060 TNETV107X_TDI,
1061 TNETV107X_TDO,
1062 TNETV107X_TMS,
1063 TNETV107X_TDM1_CLK,
1064 TNETV107X_TDM1_RX,
1065 TNETV107X_TDM1_TX,
1066 TNETV107X_TDM1_FS,
1067 TNETV107X_KEYPAD_R0,
1068 TNETV107X_KEYPAD_R1,
1069 TNETV107X_KEYPAD_R2,
1070 TNETV107X_KEYPAD_R3,
1071 TNETV107X_KEYPAD_R4,
1072 TNETV107X_KEYPAD_R5,
1073 TNETV107X_KEYPAD_R6,
1074 TNETV107X_GPIO12,
1075 TNETV107X_KEYPAD_R7,
1076 TNETV107X_GPIO10,
1077 TNETV107X_KEYPAD_C0,
1078 TNETV107X_KEYPAD_C1,
1079 TNETV107X_KEYPAD_C2,
1080 TNETV107X_KEYPAD_C3,
1081 TNETV107X_KEYPAD_C4,
1082 TNETV107X_KEYPAD_C5,
1083 TNETV107X_KEYPAD_C6,
1084 TNETV107X_GPIO13,
1085 TNETV107X_TEST_CLK_IN,
1086 TNETV107X_KEYPAD_C7,
1087 TNETV107X_GPIO11,
1088 TNETV107X_SSP0_0,
1089 TNETV107X_SCC_DCLK,
1090 TNETV107X_LCD_PD20_1,
1091 TNETV107X_SSP0_1,
1092 TNETV107X_SCC_CS_N,
1093 TNETV107X_LCD_PD21_1,
1094 TNETV107X_SSP0_2,
1095 TNETV107X_SCC_D,
1096 TNETV107X_LCD_PD22_1,
1097 TNETV107X_SSP0_3,
1098 TNETV107X_SCC_RESETN,
1099 TNETV107X_LCD_PD23_1,
1100 TNETV107X_SSP1_0,
1101 TNETV107X_GPIO25,
1102 TNETV107X_UART2_CTS,
1103 TNETV107X_SSP1_1,
1104 TNETV107X_GPIO26,
1105 TNETV107X_UART2_RD,
1106 TNETV107X_SSP1_2,
1107 TNETV107X_GPIO27,
1108 TNETV107X_UART2_RTS,
1109 TNETV107X_SSP1_3,
1110 TNETV107X_GPIO28,
1111 TNETV107X_UART2_TD,
1112 TNETV107X_UART0_CTS,
1113 TNETV107X_UART0_RD,
1114 TNETV107X_UART0_RTS,
1115 TNETV107X_UART0_TD,
1116 TNETV107X_UART1_RD,
1117 TNETV107X_UART1_TD,
1118 TNETV107X_LCD_AC_NCS,
1119 TNETV107X_LCD_HSYNC_RNW,
1120 TNETV107X_LCD_VSYNC_A0,
1121 TNETV107X_LCD_MCLK,
1122 TNETV107X_LCD_PD16_0,
1123 TNETV107X_LCD_PCLK_E,
1124 TNETV107X_LCD_PD00,
1125 TNETV107X_LCD_PD01,
1126 TNETV107X_LCD_PD02,
1127 TNETV107X_LCD_PD03,
1128 TNETV107X_LCD_PD04,
1129 TNETV107X_LCD_PD05,
1130 TNETV107X_LCD_PD06,
1131 TNETV107X_LCD_PD07,
1132 TNETV107X_LCD_PD08,
1133 TNETV107X_GPIO59_1,
1134 TNETV107X_LCD_PD09,
1135 TNETV107X_GPIO60_1,
1136 TNETV107X_LCD_PD10,
1137 TNETV107X_ASR_BA0_1,
1138 TNETV107X_GPIO61_1,
1139 TNETV107X_LCD_PD11,
1140 TNETV107X_GPIO62_1,
1141 TNETV107X_LCD_PD12,
1142 TNETV107X_GPIO63_1,
1143 TNETV107X_LCD_PD13,
1144 TNETV107X_GPIO64_1,
1145 TNETV107X_LCD_PD14,
1146 TNETV107X_GPIO29_1,
1147 TNETV107X_LCD_PD15,
1148 TNETV107X_GPIO30_1,
1149 TNETV107X_EINT0,
1150 TNETV107X_GPIO08,
1151 TNETV107X_EINT1,
1152 TNETV107X_GPIO09,
1153 TNETV107X_GPIO00,
1154 TNETV107X_LCD_PD20_2,
1155 TNETV107X_TDM_CLK_IN_2,
1156 TNETV107X_GPIO01,
1157 TNETV107X_LCD_PD21_2,
1158 TNETV107X_24M_CLK_OUT_1,
1159 TNETV107X_GPIO02,
1160 TNETV107X_LCD_PD22_2,
1161 TNETV107X_GPIO03,
1162 TNETV107X_LCD_PD23_2,
1163 TNETV107X_GPIO04,
1164 TNETV107X_LCD_PD16_1,
1165 TNETV107X_USB0_RXERR,
1166 TNETV107X_GPIO05,
1167 TNETV107X_LCD_PD17_1,
1168 TNETV107X_TDM_CLK_IN_1,
1169 TNETV107X_GPIO06,
1170 TNETV107X_LCD_PD18,
1171 TNETV107X_24M_CLK_OUT_2,
1172 TNETV107X_GPIO07,
1173 TNETV107X_LCD_PD19_1,
1174 TNETV107X_USB1_RXERR,
1175 TNETV107X_ETH_PLL_CLK,
1176 TNETV107X_MDIO,
1177 TNETV107X_MDC,
1178 TNETV107X_AIC_MUTE_STAT_N,
1179 TNETV107X_TDM0_CLK,
1180 TNETV107X_AIC_HNS_EN_N,
1181 TNETV107X_TDM0_FS,
1182 TNETV107X_AIC_HDS_EN_STAT_N,
1183 TNETV107X_TDM0_TX,
1184 TNETV107X_AIC_HNF_EN_STAT_N,
1185 TNETV107X_TDM0_RX,
1186};
1187
1188#define PINMUX(x) (4 * (x))
1189
907#ifdef CONFIG_DAVINCI_MUX 1190#ifdef CONFIG_DAVINCI_MUX
908/* setup pin muxing */ 1191/* setup pin muxing */
909extern int davinci_cfg_reg(unsigned long reg_cfg); 1192extern int davinci_cfg_reg(unsigned long reg_cfg);
1193extern int davinci_cfg_reg_list(const short pins[]);
910#else 1194#else
911/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ 1195/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
912static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } 1196static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
1197static inline int davinci_cfg_reg_list(const short pins[])
1198{
1199 return 0;
1200}
913#endif 1201#endif
914 1202
915#endif /* __INC_MACH_MUX_H */ 1203#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 651f6d8158fa..983da6e4554c 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -180,6 +180,53 @@
180#define DA8XX_LPSC1_CR_P3_SS 26 180#define DA8XX_LPSC1_CR_P3_SS 26
181#define DA8XX_LPSC1_L3_CBA_RAM 31 181#define DA8XX_LPSC1_L3_CBA_RAM 31
182 182
183/* TNETV107X LPSC Assignments */
184#define TNETV107X_LPSC_ARM 0
185#define TNETV107X_LPSC_GEM 1
186#define TNETV107X_LPSC_DDR2_PHY 2
187#define TNETV107X_LPSC_TPCC 3
188#define TNETV107X_LPSC_TPTC0 4
189#define TNETV107X_LPSC_TPTC1 5
190#define TNETV107X_LPSC_RAM 6
191#define TNETV107X_LPSC_MBX_LITE 7
192#define TNETV107X_LPSC_LCD 8
193#define TNETV107X_LPSC_ETHSS 9
194#define TNETV107X_LPSC_AEMIF 10
195#define TNETV107X_LPSC_CHIP_CFG 11
196#define TNETV107X_LPSC_TSC 12
197#define TNETV107X_LPSC_ROM 13
198#define TNETV107X_LPSC_UART2 14
199#define TNETV107X_LPSC_PKTSEC 15
200#define TNETV107X_LPSC_SECCTL 16
201#define TNETV107X_LPSC_KEYMGR 17
202#define TNETV107X_LPSC_KEYPAD 18
203#define TNETV107X_LPSC_GPIO 19
204#define TNETV107X_LPSC_MDIO 20
205#define TNETV107X_LPSC_SDIO0 21
206#define TNETV107X_LPSC_UART0 22
207#define TNETV107X_LPSC_UART1 23
208#define TNETV107X_LPSC_TIMER0 24
209#define TNETV107X_LPSC_TIMER1 25
210#define TNETV107X_LPSC_WDT_ARM 26
211#define TNETV107X_LPSC_WDT_DSP 27
212#define TNETV107X_LPSC_SSP 28
213#define TNETV107X_LPSC_TDM0 29
214#define TNETV107X_LPSC_VLYNQ 30
215#define TNETV107X_LPSC_MCDMA 31
216#define TNETV107X_LPSC_USB0 32
217#define TNETV107X_LPSC_TDM1 33
218#define TNETV107X_LPSC_DEBUGSS 34
219#define TNETV107X_LPSC_ETHSS_RGMII 35
220#define TNETV107X_LPSC_SYSTEM 36
221#define TNETV107X_LPSC_IMCOP 37
222#define TNETV107X_LPSC_SPARE 38
223#define TNETV107X_LPSC_SDIO1 39
224#define TNETV107X_LPSC_USB1 40
225#define TNETV107X_LPSC_USBSS 41
226#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
227#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
228#define TNETV107X_LPSC_MAX 44
229
183/* PSC register offsets */ 230/* PSC register offsets */
184#define EPCPR 0x070 231#define EPCPR 0x070
185#define PTCMD 0x120 232#define PTCMD 0x120
@@ -189,13 +236,19 @@
189#define MDSTAT 0x800 236#define MDSTAT 0x800
190#define MDCTL 0xA00 237#define MDCTL 0xA00
191 238
239/* PSC module states */
240#define PSC_STATE_SWRSTDISABLE 0
241#define PSC_STATE_SYNCRST 1
242#define PSC_STATE_DISABLE 2
243#define PSC_STATE_ENABLE 3
244
192#define MDSTAT_STATE_MASK 0x1f 245#define MDSTAT_STATE_MASK 0x1f
193 246
194#ifndef __ASSEMBLER__ 247#ifndef __ASSEMBLER__
195 248
196extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); 249extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
197extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, 250extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
198 unsigned int id, char enable); 251 unsigned int id, u32 next_state);
199 252
200#endif 253#endif
201 254
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index a584697a9e70..f6c4f34909a2 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,7 +13,6 @@
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15 15
16#define DAVINCI_MAX_NR_UARTS 3
17#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 16#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 17#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 18#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 5a7d7581b8ce..e65629c20769 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -11,7 +11,7 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H 12#define __ASM_ARCH_SYSTEM_H
13 13
14extern void davinci_watchdog_reset(void); 14#include <mach/common.h>
15 15
16static inline void arch_idle(void) 16static inline void arch_idle(void)
17{ 17{
@@ -20,7 +20,8 @@ static inline void arch_idle(void)
20 20
21static inline void arch_reset(char mode, const char *cmd) 21static inline void arch_reset(char mode, const char *cmd)
22{ 22{
23 davinci_watchdog_reset(); 23 if (davinci_soc_info.reset)
24 davinci_soc_info.reset(davinci_soc_info.reset_device);
24} 25}
25 26
26#endif /* __ASM_ARCH_SYSTEM_H */ 27#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index a1c0b6b99edf..8ea60a8b2495 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -12,19 +12,29 @@
12#include <linux/io.h> 12#include <linux/io.h>
13 13
14#include <asm/tlb.h> 14#include <asm/tlb.h>
15#include <asm/mach/map.h>
15 16
16#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 17#include <mach/common.h>
17#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst)))
18 18
19/* 19/*
20 * Intercept ioremap() requests for addresses in our fixed mapping regions. 20 * Intercept ioremap() requests for addresses in our fixed mapping regions.
21 */ 21 */
22void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type) 22void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
23{ 23{
24 if (BETWEEN(p, IO_PHYS, IO_SIZE)) 24 struct map_desc *desc = davinci_soc_info.io_desc;
25 return XLATE(p, IO_PHYS, IO_VIRT); 25 int desc_num = davinci_soc_info.io_desc_num;
26 int i;
26 27
27 return __arm_ioremap_caller(p, size, type, __builtin_return_address(0)); 28 for (i = 0; i < desc_num; i++, desc++) {
29 unsigned long iophys = __pfn_to_phys(desc->pfn);
30 unsigned long iosize = desc->length;
31
32 if (p >= iophys && (p + size) <= (iophys + iosize))
33 return __io(desc->virtual + p - iophys);
34 }
35
36 return __arm_ioremap_caller(p, size, type,
37 __builtin_return_address(0));
28} 38}
29EXPORT_SYMBOL(davinci_ioremap); 39EXPORT_SYMBOL(davinci_ioremap);
30 40
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index af92ffee8471..784ddf3c5ad4 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -116,6 +116,11 @@ void __init davinci_irq_init(void)
116 unsigned i; 116 unsigned i;
117 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; 117 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
118 118
119 davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
120 davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
121 if (WARN_ON(!davinci_intc_base))
122 return;
123
119 /* Clear all interrupt requests */ 124 /* Clear all interrupt requests */
120 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 125 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
121 davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); 126 davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
@@ -148,7 +153,7 @@ void __init davinci_irq_init(void)
148 } 153 }
149 154
150 /* set up genirq dispatch for ARM INTC */ 155 /* set up genirq dispatch for ARM INTC */
151 for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) { 156 for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
152 set_irq_chip(i, &davinci_irq_chip_0); 157 set_irq_chip(i, &davinci_irq_chip_0);
153 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 158 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
154 if (i != IRQ_TINT1_TINT34) 159 if (i != IRQ_TINT1_TINT34)
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index f757e83415f3..f34a8dcdae2b 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -22,6 +22,8 @@
22#include <mach/mux.h> 22#include <mach/mux.h>
23#include <mach/common.h> 23#include <mach/common.h>
24 24
25static void __iomem *pinmux_base;
26
25/* 27/*
26 * Sets the DAVINCI MUX register based on the table 28 * Sets the DAVINCI MUX register based on the table
27 */ 29 */
@@ -29,14 +31,19 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
29{ 31{
30 static DEFINE_SPINLOCK(mux_spin_lock); 32 static DEFINE_SPINLOCK(mux_spin_lock);
31 struct davinci_soc_info *soc_info = &davinci_soc_info; 33 struct davinci_soc_info *soc_info = &davinci_soc_info;
32 void __iomem *base = soc_info->pinmux_base;
33 unsigned long flags; 34 unsigned long flags;
34 const struct mux_config *cfg; 35 const struct mux_config *cfg;
35 unsigned int reg_orig = 0, reg = 0; 36 unsigned int reg_orig = 0, reg = 0;
36 unsigned int mask, warn = 0; 37 unsigned int mask, warn = 0;
37 38
38 if (!soc_info->pinmux_pins) 39 if (WARN_ON(!soc_info->pinmux_pins))
39 BUG(); 40 return -ENODEV;
41
42 if (!pinmux_base) {
43 pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
44 if (WARN_ON(!pinmux_base))
45 return -ENOMEM;
46 }
40 47
41 if (index >= soc_info->pinmux_pins_num) { 48 if (index >= soc_info->pinmux_pins_num) {
42 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", 49 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
@@ -57,7 +64,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
57 unsigned tmp1, tmp2; 64 unsigned tmp1, tmp2;
58 65
59 spin_lock_irqsave(&mux_spin_lock, flags); 66 spin_lock_irqsave(&mux_spin_lock, flags);
60 reg_orig = __raw_readl(base + cfg->mux_reg); 67 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
61 68
62 mask = (cfg->mask << cfg->mask_offset); 69 mask = (cfg->mask << cfg->mask_offset);
63 tmp1 = reg_orig & mask; 70 tmp1 = reg_orig & mask;
@@ -69,7 +76,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
69 if (tmp1 != tmp2) 76 if (tmp1 != tmp2)
70 warn = 1; 77 warn = 1;
71 78
72 __raw_writel(reg, base + cfg->mux_reg); 79 __raw_writel(reg, pinmux_base + cfg->mux_reg);
73 spin_unlock_irqrestore(&mux_spin_lock, flags); 80 spin_unlock_irqrestore(&mux_spin_lock, flags);
74 } 81 }
75 82
@@ -91,7 +98,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
91} 98}
92EXPORT_SYMBOL(davinci_cfg_reg); 99EXPORT_SYMBOL(davinci_cfg_reg);
93 100
94int da8xx_pinmux_setup(const short pins[]) 101int __init_or_module davinci_cfg_reg_list(const short pins[])
95{ 102{
96 int i, error = -EINVAL; 103 int i, error = -EINVAL;
97 104
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
index adc869413371..5aad1e7dd210 100644
--- a/arch/arm/mach-davinci/mux.h
+++ b/arch/arm/mach-davinci/mux.h
@@ -20,7 +20,7 @@
20 .name = #desc, \ 20 .name = #desc, \
21 .debug = dbg, \ 21 .debug = dbg, \
22 .mux_reg_name = "PINMUX"#muxreg, \ 22 .mux_reg_name = "PINMUX"#muxreg, \
23 .mux_reg = PINMUX##muxreg, \ 23 .mux_reg = PINMUX(muxreg), \
24 .mask_offset = mode_offset, \ 24 .mask_offset = mode_offset, \
25 .mask = mode_mask, \ 25 .mask = mode_mask, \
26 .mode = mux_mode, \ 26 .mode = mux_mode, \
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index adf6b5c7f1e5..1b15dbd0a77b 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -38,8 +38,9 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
38 return 0; 38 return 0;
39 } 39 }
40 40
41 psc_base = soc_info->psc_bases[ctlr]; 41 psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
42 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); 42 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
43 iounmap(psc_base);
43 44
44 /* if clocked, state can be "Enable" or "SyncReset" */ 45 /* if clocked, state can be "Enable" or "SyncReset" */
45 return mdstat & BIT(12); 46 return mdstat & BIT(12);
@@ -47,12 +48,11 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
47 48
48/* Enable or disable a PSC domain */ 49/* Enable or disable a PSC domain */
49void davinci_psc_config(unsigned int domain, unsigned int ctlr, 50void davinci_psc_config(unsigned int domain, unsigned int ctlr,
50 unsigned int id, char enable) 51 unsigned int id, u32 next_state)
51{ 52{
52 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; 53 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
53 void __iomem *psc_base; 54 void __iomem *psc_base;
54 struct davinci_soc_info *soc_info = &davinci_soc_info; 55 struct davinci_soc_info *soc_info = &davinci_soc_info;
55 u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
56 56
57 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { 57 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
58 pr_warning("PSC: Bad psc data: 0x%x[%d]\n", 58 pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
@@ -60,7 +60,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
60 return; 60 return;
61 } 61 }
62 62
63 psc_base = soc_info->psc_bases[ctlr]; 63 psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
64 64
65 mdctl = __raw_readl(psc_base + MDCTL + 4 * id); 65 mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
66 mdctl &= ~MDSTAT_STATE_MASK; 66 mdctl &= ~MDSTAT_STATE_MASK;
@@ -100,4 +100,6 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
100 do { 100 do {
101 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); 101 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
102 } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); 102 } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
103
104 iounmap(psc_base);
103} 105}
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 7ce5ba086575..1875740fe27c 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -35,14 +35,20 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
35 int offset) 35 int offset)
36{ 36{
37 offset <<= up->regshift; 37 offset <<= up->regshift;
38 return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset); 38
39 WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset);
40
41 return (unsigned int)__raw_readl(up->membase + offset);
39} 42}
40 43
41static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, 44static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
42 int value) 45 int value)
43{ 46{
44 offset <<= p->regshift; 47 offset <<= p->regshift;
45 __raw_writel(value, IO_ADDRESS(p->mapbase) + offset); 48
49 WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
50
51 __raw_writel(value, p->membase + offset);
46} 52}
47 53
48static void __init davinci_serial_reset(struct plat_serial8250_port *p) 54static void __init davinci_serial_reset(struct plat_serial8250_port *p)
@@ -77,20 +83,32 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
77 * Make sure the serial ports are muxed on at this point. 83 * Make sure the serial ports are muxed on at this point.
78 * You have to mux them off in device drivers later on if not needed. 84 * You have to mux them off in device drivers later on if not needed.
79 */ 85 */
80 for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) { 86 for (i = 0; p->flags; i++, p++) {
81 if (!(info->enabled_uarts & (1 << i))) 87 if (!(info->enabled_uarts & (1 << i)))
82 continue; 88 continue;
83 89
84 sprintf(name, "uart%d", i); 90 sprintf(name, "uart%d", i);
85 uart_clk = clk_get(dev, name); 91 uart_clk = clk_get(dev, name);
86 if (IS_ERR(uart_clk)) 92 if (IS_ERR(uart_clk)) {
87 printk(KERN_ERR "%s:%d: failed to get UART%d clock\n", 93 printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
88 __func__, __LINE__, i); 94 __func__, __LINE__, i);
89 else { 95 continue;
90 clk_enable(uart_clk);
91 p->uartclk = clk_get_rate(uart_clk);
92 davinci_serial_reset(p);
93 } 96 }
97
98 clk_enable(uart_clk);
99 p->uartclk = clk_get_rate(uart_clk);
100
101 if (!p->membase && p->mapbase) {
102 p->membase = ioremap(p->mapbase, SZ_4K);
103
104 if (p->membase)
105 p->flags &= ~UPF_IOREMAP;
106 else
107 pr_err("uart regs ioremap failed\n");
108 }
109
110 if (p->membase && p->type != PORT_AR7)
111 davinci_serial_reset(p);
94 } 112 }
95 113
96 return platform_device_register(soc_info->serial_dev); 114 return platform_device_register(soc_info->serial_dev);
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 9e0b106b4f5f..0f21c36e65dd 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -197,32 +197,36 @@ static void __init timer_init(void)
197{ 197{
198 struct davinci_soc_info *soc_info = &davinci_soc_info; 198 struct davinci_soc_info *soc_info = &davinci_soc_info;
199 struct davinci_timer_instance *dtip = soc_info->timer_info->timers; 199 struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
200 void __iomem *base[2];
200 int i; 201 int i;
201 202
202 /* Global init of each 64-bit timer as a whole */ 203 /* Global init of each 64-bit timer as a whole */
203 for(i=0; i<2; i++) { 204 for(i=0; i<2; i++) {
204 u32 tgcr; 205 u32 tgcr;
205 void __iomem *base = dtip[i].base; 206
207 base[i] = ioremap(dtip[i].base, SZ_4K);
208 if (WARN_ON(!base[i]))
209 continue;
206 210
207 /* Disabled, Internal clock source */ 211 /* Disabled, Internal clock source */
208 __raw_writel(0, base + TCR); 212 __raw_writel(0, base[i] + TCR);
209 213
210 /* reset both timers, no pre-scaler for timer34 */ 214 /* reset both timers, no pre-scaler for timer34 */
211 tgcr = 0; 215 tgcr = 0;
212 __raw_writel(tgcr, base + TGCR); 216 __raw_writel(tgcr, base[i] + TGCR);
213 217
214 /* Set both timers to unchained 32-bit */ 218 /* Set both timers to unchained 32-bit */
215 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; 219 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
216 __raw_writel(tgcr, base + TGCR); 220 __raw_writel(tgcr, base[i] + TGCR);
217 221
218 /* Unreset timers */ 222 /* Unreset timers */
219 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 223 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
220 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 224 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
221 __raw_writel(tgcr, base + TGCR); 225 __raw_writel(tgcr, base[i] + TGCR);
222 226
223 /* Init both counters to zero */ 227 /* Init both counters to zero */
224 __raw_writel(0, base + TIM12); 228 __raw_writel(0, base[i] + TIM12);
225 __raw_writel(0, base + TIM34); 229 __raw_writel(0, base[i] + TIM34);
226 } 230 }
227 231
228 /* Init of each timer as a 32-bit timer */ 232 /* Init of each timer as a 32-bit timer */
@@ -231,7 +235,9 @@ static void __init timer_init(void)
231 int timer = ID_TO_TIMER(t->id); 235 int timer = ID_TO_TIMER(t->id);
232 u32 irq; 236 u32 irq;
233 237
234 t->base = dtip[timer].base; 238 t->base = base[timer];
239 if (!t->base)
240 continue;
235 241
236 if (IS_TIMER_BOT(t->id)) { 242 if (IS_TIMER_BOT(t->id)) {
237 t->enamode_shift = 6; 243 t->enamode_shift = 6;
@@ -361,13 +367,13 @@ static void __init davinci_timer_init(void)
361 } 367 }
362 } 368 }
363 369
364 /* init timer hw */
365 timer_init();
366
367 timer_clk = clk_get(NULL, "timer0"); 370 timer_clk = clk_get(NULL, "timer0");
368 BUG_ON(IS_ERR(timer_clk)); 371 BUG_ON(IS_ERR(timer_clk));
369 clk_enable(timer_clk); 372 clk_enable(timer_clk);
370 373
374 /* init timer hw */
375 timer_init();
376
371 davinci_clock_tick_rate = clk_get_rate(timer_clk); 377 davinci_clock_tick_rate = clk_get_rate(timer_clk);
372 378
373 /* setup clocksource */ 379 /* setup clocksource */
@@ -399,13 +405,16 @@ struct sys_timer davinci_timer = {
399 405
400 406
401/* reset board using watchdog timer */ 407/* reset board using watchdog timer */
402void davinci_watchdog_reset(void) 408void davinci_watchdog_reset(struct platform_device *pdev)
403{ 409{
404 u32 tgcr, wdtcr; 410 u32 tgcr, wdtcr;
405 struct platform_device *pdev = &davinci_wdt_device; 411 void __iomem *base;
406 void __iomem *base = IO_ADDRESS(pdev->resource[0].start);
407 struct clk *wd_clk; 412 struct clk *wd_clk;
408 413
414 base = ioremap(pdev->resource[0].start, SZ_4K);
415 if (WARN_ON(!base))
416 return;
417
409 wd_clk = clk_get(&pdev->dev, NULL); 418 wd_clk = clk_get(&pdev->dev, NULL);
410 if (WARN_ON(IS_ERR(wd_clk))) 419 if (WARN_ON(IS_ERR(wd_clk)))
411 return; 420 return;
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6a1303759432..50ac047cd136 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -620,6 +620,16 @@ config RTC_DRV_NUC900
620 620
621comment "on-CPU RTC drivers" 621comment "on-CPU RTC drivers"
622 622
623config RTC_DRV_DAVINCI
624 tristate "TI DaVinci RTC"
625 depends on ARCH_DAVINCI_DM365
626 help
627 If you say yes here you get support for the RTC on the
628 DaVinci platforms (DM365).
629
630 This driver can also be built as a module. If so, the module
631 will be called rtc-davinci.
632
623config RTC_DRV_OMAP 633config RTC_DRV_OMAP
624 tristate "TI OMAP1" 634 tristate "TI OMAP1"
625 depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX 635 depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 44ef194a9573..245311a1348f 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
27obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o 27obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
28obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o 28obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o
29obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o 29obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o
30obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
30obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o 31obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
31obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o 32obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
32obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o 33obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o
diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
new file mode 100644
index 000000000000..92a8f6cacda9
--- /dev/null
+++ b/drivers/rtc/rtc-davinci.c
@@ -0,0 +1,673 @@
1/*
2 * DaVinci Power Management and Real Time Clock Driver for TI platforms
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc
5 *
6 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/spinlock.h>
28#include <linux/rtc.h>
29#include <linux/bcd.h>
30#include <linux/platform_device.h>
31#include <linux/io.h>
32
33/*
34 * The DaVinci RTC is a simple RTC with the following
35 * Sec: 0 - 59 : BCD count
36 * Min: 0 - 59 : BCD count
37 * Hour: 0 - 23 : BCD count
38 * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
39 */
40
41/* PRTC interface registers */
42#define DAVINCI_PRTCIF_PID 0x00
43#define PRTCIF_CTLR 0x04
44#define PRTCIF_LDATA 0x08
45#define PRTCIF_UDATA 0x0C
46#define PRTCIF_INTEN 0x10
47#define PRTCIF_INTFLG 0x14
48
49/* PRTCIF_CTLR bit fields */
50#define PRTCIF_CTLR_BUSY BIT(31)
51#define PRTCIF_CTLR_SIZE BIT(25)
52#define PRTCIF_CTLR_DIR BIT(24)
53#define PRTCIF_CTLR_BENU_MSB BIT(23)
54#define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
55#define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
56#define PRTCIF_CTLR_BENU_LSB BIT(20)
57#define PRTCIF_CTLR_BENU_MASK (0x00F00000)
58#define PRTCIF_CTLR_BENL_MSB BIT(19)
59#define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
60#define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
61#define PRTCIF_CTLR_BENL_LSB BIT(16)
62#define PRTCIF_CTLR_BENL_MASK (0x000F0000)
63
64/* PRTCIF_INTEN bit fields */
65#define PRTCIF_INTEN_RTCSS BIT(1)
66#define PRTCIF_INTEN_RTCIF BIT(0)
67#define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
68 | PRTCIF_INTEN_RTCIF)
69
70/* PRTCIF_INTFLG bit fields */
71#define PRTCIF_INTFLG_RTCSS BIT(1)
72#define PRTCIF_INTFLG_RTCIF BIT(0)
73#define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
74 | PRTCIF_INTFLG_RTCIF)
75
76/* PRTC subsystem registers */
77#define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
78#define PRTCSS_RTC_CTRL (0x10)
79#define PRTCSS_RTC_WDT (0x11)
80#define PRTCSS_RTC_TMR0 (0x12)
81#define PRTCSS_RTC_TMR1 (0x13)
82#define PRTCSS_RTC_CCTRL (0x14)
83#define PRTCSS_RTC_SEC (0x15)
84#define PRTCSS_RTC_MIN (0x16)
85#define PRTCSS_RTC_HOUR (0x17)
86#define PRTCSS_RTC_DAY0 (0x18)
87#define PRTCSS_RTC_DAY1 (0x19)
88#define PRTCSS_RTC_AMIN (0x1A)
89#define PRTCSS_RTC_AHOUR (0x1B)
90#define PRTCSS_RTC_ADAY0 (0x1C)
91#define PRTCSS_RTC_ADAY1 (0x1D)
92#define PRTCSS_RTC_CLKC_CNT (0x20)
93
94/* PRTCSS_RTC_INTC_EXTENA1 */
95#define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
96
97/* PRTCSS_RTC_CTRL bit fields */
98#define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
99#define PRTCSS_RTC_CTRL_WEN BIT(6)
100#define PRTCSS_RTC_CTRL_WDRT BIT(5)
101#define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
102#define PRTCSS_RTC_CTRL_TE BIT(3)
103#define PRTCSS_RTC_CTRL_TIEN BIT(2)
104#define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
105#define PRTCSS_RTC_CTRL_TMMD BIT(0)
106
107/* PRTCSS_RTC_CCTRL bit fields */
108#define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
109#define PRTCSS_RTC_CCTRL_DAEN BIT(5)
110#define PRTCSS_RTC_CCTRL_HAEN BIT(4)
111#define PRTCSS_RTC_CCTRL_MAEN BIT(3)
112#define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
113#define PRTCSS_RTC_CCTRL_AIEN BIT(1)
114#define PRTCSS_RTC_CCTRL_CAEN BIT(0)
115
116static DEFINE_SPINLOCK(davinci_rtc_lock);
117
118struct davinci_rtc {
119 struct rtc_device *rtc;
120 void __iomem *base;
121 resource_size_t pbase;
122 size_t base_size;
123 int irq;
124};
125
126static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
127 u32 val, u32 addr)
128{
129 writel(val, davinci_rtc->base + addr);
130}
131
132static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
133{
134 return readl(davinci_rtc->base + addr);
135}
136
137static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
138{
139 while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
140 cpu_relax();
141}
142
143static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
144 unsigned long val, u8 addr)
145{
146 rtcif_wait(davinci_rtc);
147
148 rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
149 rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
150
151 rtcif_wait(davinci_rtc);
152}
153
154static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
155{
156 rtcif_wait(davinci_rtc);
157
158 rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
159 PRTCIF_CTLR);
160
161 rtcif_wait(davinci_rtc);
162
163 return rtcif_read(davinci_rtc, PRTCIF_LDATA);
164}
165
166static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
167{
168 while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
169 PRTCSS_RTC_CCTRL_CALBUSY)
170 cpu_relax();
171}
172
173static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
174{
175 struct davinci_rtc *davinci_rtc = class_dev;
176 unsigned long events = 0;
177 u32 irq_flg;
178 u8 alm_irq, tmr_irq;
179 u8 rtc_ctrl, rtc_cctrl;
180 int ret = IRQ_NONE;
181
182 irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
183 PRTCIF_INTFLG_RTCSS;
184
185 alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
186 PRTCSS_RTC_CCTRL_ALMFLG;
187
188 tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
189 PRTCSS_RTC_CTRL_TMRFLG;
190
191 if (irq_flg) {
192 if (alm_irq) {
193 events |= RTC_IRQF | RTC_AF;
194 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
195 rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
196 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
197 } else if (tmr_irq) {
198 events |= RTC_IRQF | RTC_PF;
199 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
200 rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
201 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
202 }
203
204 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
205 PRTCIF_INTFLG);
206 rtc_update_irq(davinci_rtc->rtc, 1, events);
207
208 ret = IRQ_HANDLED;
209 }
210
211 return ret;
212}
213
214static int
215davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
216{
217 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
218 u8 rtc_ctrl;
219 unsigned long flags;
220 int ret = 0;
221
222 spin_lock_irqsave(&davinci_rtc_lock, flags);
223
224 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
225
226 switch (cmd) {
227 case RTC_WIE_ON:
228 rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
229 break;
230 case RTC_WIE_OFF:
231 rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
232 break;
233 case RTC_UIE_OFF:
234 case RTC_UIE_ON:
235 ret = -ENOTTY;
236 break;
237 default:
238 ret = -ENOIOCTLCMD;
239 }
240
241 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
242
243 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
244
245 return ret;
246}
247
248static int convertfromdays(u16 days, struct rtc_time *tm)
249{
250 int tmp_days, year, mon;
251
252 for (year = 2000;; year++) {
253 tmp_days = rtc_year_days(1, 12, year);
254 if (days >= tmp_days)
255 days -= tmp_days;
256 else {
257 for (mon = 0;; mon++) {
258 tmp_days = rtc_month_days(mon, year);
259 if (days >= tmp_days) {
260 days -= tmp_days;
261 } else {
262 tm->tm_year = year - 1900;
263 tm->tm_mon = mon;
264 tm->tm_mday = days + 1;
265 break;
266 }
267 }
268 break;
269 }
270 }
271 return 0;
272}
273
274static int convert2days(u16 *days, struct rtc_time *tm)
275{
276 int i;
277 *days = 0;
278
279 /* epoch == 1900 */
280 if (tm->tm_year < 100 || tm->tm_year > 199)
281 return -EINVAL;
282
283 for (i = 2000; i < 1900 + tm->tm_year; i++)
284 *days += rtc_year_days(1, 12, i);
285
286 *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
287
288 return 0;
289}
290
291static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
292{
293 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
294 u16 days = 0;
295 u8 day0, day1;
296 unsigned long flags;
297
298 spin_lock_irqsave(&davinci_rtc_lock, flags);
299
300 davinci_rtcss_calendar_wait(davinci_rtc);
301 tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
302
303 davinci_rtcss_calendar_wait(davinci_rtc);
304 tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
305
306 davinci_rtcss_calendar_wait(davinci_rtc);
307 tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
308
309 davinci_rtcss_calendar_wait(davinci_rtc);
310 day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
311
312 davinci_rtcss_calendar_wait(davinci_rtc);
313 day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
314
315 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
316
317 days |= day1;
318 days <<= 8;
319 days |= day0;
320
321 if (convertfromdays(days, tm) < 0)
322 return -EINVAL;
323
324 return 0;
325}
326
327static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
328{
329 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
330 u16 days;
331 u8 rtc_cctrl;
332 unsigned long flags;
333
334 if (convert2days(&days, tm) < 0)
335 return -EINVAL;
336
337 spin_lock_irqsave(&davinci_rtc_lock, flags);
338
339 davinci_rtcss_calendar_wait(davinci_rtc);
340 rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
341
342 davinci_rtcss_calendar_wait(davinci_rtc);
343 rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
344
345 davinci_rtcss_calendar_wait(davinci_rtc);
346 rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
347
348 davinci_rtcss_calendar_wait(davinci_rtc);
349 rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
350
351 davinci_rtcss_calendar_wait(davinci_rtc);
352 rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
353
354 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
355 rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
356 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
357
358 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
359
360 return 0;
361}
362
363static int davinci_rtc_alarm_irq_enable(struct device *dev,
364 unsigned int enabled)
365{
366 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
367 unsigned long flags;
368 u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
369
370 spin_lock_irqsave(&davinci_rtc_lock, flags);
371
372 if (enabled)
373 rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
374 PRTCSS_RTC_CCTRL_HAEN |
375 PRTCSS_RTC_CCTRL_MAEN |
376 PRTCSS_RTC_CCTRL_ALMFLG |
377 PRTCSS_RTC_CCTRL_AIEN;
378 else
379 rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
380
381 davinci_rtcss_calendar_wait(davinci_rtc);
382 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
383
384 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
385
386 return 0;
387}
388
389static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
390{
391 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
392 u16 days = 0;
393 u8 day0, day1;
394 unsigned long flags;
395
396 spin_lock_irqsave(&davinci_rtc_lock, flags);
397
398 davinci_rtcss_calendar_wait(davinci_rtc);
399 alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
400
401 davinci_rtcss_calendar_wait(davinci_rtc);
402 alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
403
404 davinci_rtcss_calendar_wait(davinci_rtc);
405 day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
406
407 davinci_rtcss_calendar_wait(davinci_rtc);
408 day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
409
410 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
411 days |= day1;
412 days <<= 8;
413 days |= day0;
414
415 if (convertfromdays(days, &alm->time) < 0)
416 return -EINVAL;
417
418 alm->pending = !!(rtcss_read(davinci_rtc,
419 PRTCSS_RTC_CCTRL) &
420 PRTCSS_RTC_CCTRL_AIEN);
421 alm->enabled = alm->pending && device_may_wakeup(dev);
422
423 return 0;
424}
425
426static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
427{
428 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
429 unsigned long flags;
430 u16 days;
431
432 if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
433 && alm->time.tm_year < 0) {
434 struct rtc_time tm;
435 unsigned long now, then;
436
437 davinci_rtc_read_time(dev, &tm);
438 rtc_tm_to_time(&tm, &now);
439
440 alm->time.tm_mday = tm.tm_mday;
441 alm->time.tm_mon = tm.tm_mon;
442 alm->time.tm_year = tm.tm_year;
443 rtc_tm_to_time(&alm->time, &then);
444
445 if (then < now) {
446 rtc_time_to_tm(now + 24 * 60 * 60, &tm);
447 alm->time.tm_mday = tm.tm_mday;
448 alm->time.tm_mon = tm.tm_mon;
449 alm->time.tm_year = tm.tm_year;
450 }
451 }
452
453 if (convert2days(&days, &alm->time) < 0)
454 return -EINVAL;
455
456 spin_lock_irqsave(&davinci_rtc_lock, flags);
457
458 davinci_rtcss_calendar_wait(davinci_rtc);
459 rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
460
461 davinci_rtcss_calendar_wait(davinci_rtc);
462 rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
463
464 davinci_rtcss_calendar_wait(davinci_rtc);
465 rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
466
467 davinci_rtcss_calendar_wait(davinci_rtc);
468 rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
469
470 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
471
472 return 0;
473}
474
475static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
476{
477 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
478 unsigned long flags;
479 u8 rtc_ctrl;
480
481 spin_lock_irqsave(&davinci_rtc_lock, flags);
482
483 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
484
485 if (enabled) {
486 while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
487 & PRTCSS_RTC_CTRL_WDTBUS)
488 cpu_relax();
489
490 rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
491 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
492
493 rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
494
495 rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
496 PRTCSS_RTC_CTRL_TMMD |
497 PRTCSS_RTC_CTRL_TMRFLG;
498 } else
499 rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
500
501 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
502
503 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
504
505 return 0;
506}
507
508static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
509{
510 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
511 unsigned long flags;
512 u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
513
514 spin_lock_irqsave(&davinci_rtc_lock, flags);
515
516 rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
517 rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
518
519 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
520
521 return 0;
522}
523
524static struct rtc_class_ops davinci_rtc_ops = {
525 .ioctl = davinci_rtc_ioctl,
526 .read_time = davinci_rtc_read_time,
527 .set_time = davinci_rtc_set_time,
528 .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
529 .read_alarm = davinci_rtc_read_alarm,
530 .set_alarm = davinci_rtc_set_alarm,
531 .irq_set_state = davinci_rtc_irq_set_state,
532 .irq_set_freq = davinci_rtc_irq_set_freq,
533};
534
535static int __init davinci_rtc_probe(struct platform_device *pdev)
536{
537 struct device *dev = &pdev->dev;
538 struct davinci_rtc *davinci_rtc;
539 struct resource *res, *mem;
540 int ret = 0;
541
542 davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
543 if (!davinci_rtc) {
544 dev_dbg(dev, "could not allocate memory for private data\n");
545 return -ENOMEM;
546 }
547
548 davinci_rtc->irq = platform_get_irq(pdev, 0);
549 if (davinci_rtc->irq < 0) {
550 dev_err(dev, "no RTC irq\n");
551 ret = davinci_rtc->irq;
552 goto fail1;
553 }
554
555 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
556 if (!res) {
557 dev_err(dev, "no mem resource\n");
558 ret = -EINVAL;
559 goto fail1;
560 }
561
562 davinci_rtc->pbase = res->start;
563 davinci_rtc->base_size = resource_size(res);
564
565 mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
566 pdev->name);
567 if (!mem) {
568 dev_err(dev, "RTC registers at %08x are not free\n",
569 davinci_rtc->pbase);
570 ret = -EBUSY;
571 goto fail1;
572 }
573
574 davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
575 if (!davinci_rtc->base) {
576 dev_err(dev, "unable to ioremap MEM resource\n");
577 ret = -ENOMEM;
578 goto fail2;
579 }
580
581 davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
582 &davinci_rtc_ops, THIS_MODULE);
583 if (IS_ERR(davinci_rtc->rtc)) {
584 dev_err(dev, "unable to register RTC device, err %ld\n",
585 PTR_ERR(davinci_rtc->rtc));
586 goto fail3;
587 }
588
589 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
590 rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
591 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
592
593 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
594 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
595
596 ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
597 IRQF_DISABLED, "davinci_rtc", davinci_rtc);
598 if (ret < 0) {
599 dev_err(dev, "unable to register davinci RTC interrupt\n");
600 goto fail4;
601 }
602
603 /* Enable interrupts */
604 rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
605 rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
606 PRTCSS_RTC_INTC_EXTENA1);
607
608 rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
609
610 platform_set_drvdata(pdev, davinci_rtc);
611
612 device_init_wakeup(&pdev->dev, 0);
613
614 return 0;
615
616fail4:
617 rtc_device_unregister(davinci_rtc->rtc);
618fail3:
619 iounmap(davinci_rtc->base);
620fail2:
621 release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
622fail1:
623 kfree(davinci_rtc);
624
625 return ret;
626}
627
628static int __devexit davinci_rtc_remove(struct platform_device *pdev)
629{
630 struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
631
632 device_init_wakeup(&pdev->dev, 0);
633
634 rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
635
636 free_irq(davinci_rtc->irq, davinci_rtc);
637
638 rtc_device_unregister(davinci_rtc->rtc);
639
640 iounmap(davinci_rtc->base);
641 release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
642
643 platform_set_drvdata(pdev, NULL);
644
645 kfree(davinci_rtc);
646
647 return 0;
648}
649
650static struct platform_driver davinci_rtc_driver = {
651 .probe = davinci_rtc_probe,
652 .remove = __devexit_p(davinci_rtc_remove),
653 .driver = {
654 .name = "rtc_davinci",
655 .owner = THIS_MODULE,
656 },
657};
658
659static int __init rtc_init(void)
660{
661 return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
662}
663module_init(rtc_init);
664
665static void __exit rtc_exit(void)
666{
667 platform_driver_unregister(&davinci_rtc_driver);
668}
669module_exit(rtc_exit);
670
671MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
672MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
673MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-12 05:45:55 -0500