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-rw-r--r--arch/arm/boot/dts/socfpga.dtsi16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 0207a6af5fd2..6d09b8d42fdd 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -147,7 +147,7 @@
147 reg = <0x58>; 147 reg = <0x58>;
148 }; 148 };
149 149
150 cfg_s2f_usr0_clk: cfg_s2f_usr0_clk { 150 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
151 #clock-cells = <0>; 151 #clock-cells = <0>;
152 compatible = "altr,socfpga-perip-clk"; 152 compatible = "altr,socfpga-perip-clk";
153 clocks = <&main_pll>; 153 clocks = <&main_pll>;
@@ -198,7 +198,7 @@
198 reg = <0x98>; 198 reg = <0x98>;
199 }; 199 };
200 200
201 s2f_usr1_clk: s2f_usr1_clk { 201 h2f_usr1_clk: h2f_usr1_clk {
202 #clock-cells = <0>; 202 #clock-cells = <0>;
203 compatible = "altr,socfpga-perip-clk"; 203 compatible = "altr,socfpga-perip-clk";
204 clocks = <&periph_pll>; 204 clocks = <&periph_pll>;
@@ -235,7 +235,7 @@
235 reg = <0xD0>; 235 reg = <0xD0>;
236 }; 236 };
237 237
238 s2f_usr2_clk: s2f_usr2_clk { 238 h2f_usr2_clk: h2f_usr2_clk {
239 #clock-cells = <0>; 239 #clock-cells = <0>;
240 compatible = "altr,socfpga-perip-clk"; 240 compatible = "altr,socfpga-perip-clk";
241 clocks = <&sdram_pll>; 241 clocks = <&sdram_pll>;
@@ -335,14 +335,14 @@
335 cfg_clk: cfg_clk { 335 cfg_clk: cfg_clk {
336 #clock-cells = <0>; 336 #clock-cells = <0>;
337 compatible = "altr,socfpga-gate-clk"; 337 compatible = "altr,socfpga-gate-clk";
338 clocks = <&cfg_s2f_usr0_clk>; 338 clocks = <&cfg_h2f_usr0_clk>;
339 clk-gate = <0x60 8>; 339 clk-gate = <0x60 8>;
340 }; 340 };
341 341
342 s2f_user0_clk: s2f_user0_clk { 342 h2f_user0_clk: h2f_user0_clk {
343 #clock-cells = <0>; 343 #clock-cells = <0>;
344 compatible = "altr,socfpga-gate-clk"; 344 compatible = "altr,socfpga-gate-clk";
345 clocks = <&cfg_s2f_usr0_clk>; 345 clocks = <&cfg_h2f_usr0_clk>;
346 clk-gate = <0x60 9>; 346 clk-gate = <0x60 9>;
347 }; 347 };
348 348
@@ -400,10 +400,10 @@
400 div-reg = <0xa8 0 24>; 400 div-reg = <0xa8 0 24>;
401 }; 401 };
402 402
403 s2f_user1_clk: s2f_user1_clk { 403 h2f_user1_clk: h2f_user1_clk {
404 #clock-cells = <0>; 404 #clock-cells = <0>;
405 compatible = "altr,socfpga-gate-clk"; 405 compatible = "altr,socfpga-gate-clk";
406 clocks = <&s2f_usr1_clk>; 406 clocks = <&h2f_usr1_clk>;
407 clk-gate = <0xa0 7>; 407 clk-gate = <0xa0 7>;
408 }; 408 };
409 409