diff options
27 files changed, 140 insertions, 59 deletions
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 13798733f2db..ace016b17036 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c | |||
| @@ -63,16 +63,19 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 63 | { | 63 | { |
| 64 | .mapbase = 0xf8400000, | 64 | .mapbase = 0xf8400000, |
| 65 | .flags = UPF_BOOT_AUTOCONF, | 65 | .flags = UPF_BOOT_AUTOCONF, |
| 66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 66 | .type = PORT_SCIF, | 67 | .type = PORT_SCIF, |
| 67 | .irqs = { 88, 88, 88, 88 }, | 68 | .irqs = { 88, 88, 88, 88 }, |
| 68 | }, { | 69 | }, { |
| 69 | .mapbase = 0xf8410000, | 70 | .mapbase = 0xf8410000, |
| 70 | .flags = UPF_BOOT_AUTOCONF, | 71 | .flags = UPF_BOOT_AUTOCONF, |
| 72 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 71 | .type = PORT_SCIF, | 73 | .type = PORT_SCIF, |
| 72 | .irqs = { 92, 92, 92, 92 }, | 74 | .irqs = { 92, 92, 92, 92 }, |
| 73 | }, { | 75 | }, { |
| 74 | .mapbase = 0xf8420000, | 76 | .mapbase = 0xf8420000, |
| 75 | .flags = UPF_BOOT_AUTOCONF, | 77 | .flags = UPF_BOOT_AUTOCONF, |
| 78 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 76 | .type = PORT_SCIF, | 79 | .type = PORT_SCIF, |
| 77 | .irqs = { 96, 96, 96, 96 }, | 80 | .irqs = { 96, 96, 96, 96 }, |
| 78 | }, { | 81 | }, { |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index 869c2da4820b..7ec658ce14f8 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c | |||
| @@ -211,6 +211,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 211 | { | 211 | { |
| 212 | .mapbase = 0xff804000, | 212 | .mapbase = 0xff804000, |
| 213 | .flags = UPF_BOOT_AUTOCONF, | 213 | .flags = UPF_BOOT_AUTOCONF, |
| 214 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 214 | .type = PORT_SCIF, | 215 | .type = PORT_SCIF, |
| 215 | .irqs = { 220, 220, 220, 220 }, | 216 | .irqs = { 220, 220, 220, 220 }, |
| 216 | }, { | 217 | }, { |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index d8febe128066..2a2ac222f9c7 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c | |||
| @@ -181,41 +181,49 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 181 | { | 181 | { |
| 182 | .mapbase = 0xfffe8000, | 182 | .mapbase = 0xfffe8000, |
| 183 | .flags = UPF_BOOT_AUTOCONF, | 183 | .flags = UPF_BOOT_AUTOCONF, |
| 184 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 184 | .type = PORT_SCIF, | 185 | .type = PORT_SCIF, |
| 185 | .irqs = { 180, 180, 180, 180 } | 186 | .irqs = { 180, 180, 180, 180 } |
| 186 | }, { | 187 | }, { |
| 187 | .mapbase = 0xfffe8800, | 188 | .mapbase = 0xfffe8800, |
| 188 | .flags = UPF_BOOT_AUTOCONF, | 189 | .flags = UPF_BOOT_AUTOCONF, |
| 190 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 189 | .type = PORT_SCIF, | 191 | .type = PORT_SCIF, |
| 190 | .irqs = { 184, 184, 184, 184 } | 192 | .irqs = { 184, 184, 184, 184 } |
| 191 | }, { | 193 | }, { |
| 192 | .mapbase = 0xfffe9000, | 194 | .mapbase = 0xfffe9000, |
| 193 | .flags = UPF_BOOT_AUTOCONF, | 195 | .flags = UPF_BOOT_AUTOCONF, |
| 196 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 194 | .type = PORT_SCIF, | 197 | .type = PORT_SCIF, |
| 195 | .irqs = { 188, 188, 188, 188 } | 198 | .irqs = { 188, 188, 188, 188 } |
| 196 | }, { | 199 | }, { |
| 197 | .mapbase = 0xfffe9800, | 200 | .mapbase = 0xfffe9800, |
| 198 | .flags = UPF_BOOT_AUTOCONF, | 201 | .flags = UPF_BOOT_AUTOCONF, |
| 202 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 199 | .type = PORT_SCIF, | 203 | .type = PORT_SCIF, |
| 200 | .irqs = { 192, 192, 192, 192 } | 204 | .irqs = { 192, 192, 192, 192 } |
| 201 | }, { | 205 | }, { |
| 202 | .mapbase = 0xfffea000, | 206 | .mapbase = 0xfffea000, |
| 203 | .flags = UPF_BOOT_AUTOCONF, | 207 | .flags = UPF_BOOT_AUTOCONF, |
| 208 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 204 | .type = PORT_SCIF, | 209 | .type = PORT_SCIF, |
| 205 | .irqs = { 196, 196, 196, 196 } | 210 | .irqs = { 196, 196, 196, 196 } |
| 206 | }, { | 211 | }, { |
| 207 | .mapbase = 0xfffea800, | 212 | .mapbase = 0xfffea800, |
| 208 | .flags = UPF_BOOT_AUTOCONF, | 213 | .flags = UPF_BOOT_AUTOCONF, |
| 214 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 209 | .type = PORT_SCIF, | 215 | .type = PORT_SCIF, |
| 210 | .irqs = { 200, 200, 200, 200 } | 216 | .irqs = { 200, 200, 200, 200 } |
| 211 | }, { | 217 | }, { |
| 212 | .mapbase = 0xfffeb000, | 218 | .mapbase = 0xfffeb000, |
| 213 | .flags = UPF_BOOT_AUTOCONF, | 219 | .flags = UPF_BOOT_AUTOCONF, |
| 220 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 214 | .type = PORT_SCIF, | 221 | .type = PORT_SCIF, |
| 215 | .irqs = { 204, 204, 204, 204 } | 222 | .irqs = { 204, 204, 204, 204 } |
| 216 | }, { | 223 | }, { |
| 217 | .mapbase = 0xfffeb800, | 224 | .mapbase = 0xfffeb800, |
| 218 | .flags = UPF_BOOT_AUTOCONF, | 225 | .flags = UPF_BOOT_AUTOCONF, |
| 226 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 219 | .type = PORT_SCIF, | 227 | .type = PORT_SCIF, |
| 220 | .irqs = { 208, 208, 208, 208 } | 228 | .irqs = { 208, 208, 208, 208 } |
| 221 | }, { | 229 | }, { |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index 62e3039d2398..2c9f3ababfd7 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c | |||
| @@ -177,21 +177,25 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 177 | { | 177 | { |
| 178 | .mapbase = 0xfffe8000, | 178 | .mapbase = 0xfffe8000, |
| 179 | .flags = UPF_BOOT_AUTOCONF, | 179 | .flags = UPF_BOOT_AUTOCONF, |
| 180 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 180 | .type = PORT_SCIF, | 181 | .type = PORT_SCIF, |
| 181 | .irqs = { 192, 192, 192, 192 }, | 182 | .irqs = { 192, 192, 192, 192 }, |
| 182 | }, { | 183 | }, { |
| 183 | .mapbase = 0xfffe8800, | 184 | .mapbase = 0xfffe8800, |
| 184 | .flags = UPF_BOOT_AUTOCONF, | 185 | .flags = UPF_BOOT_AUTOCONF, |
| 186 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 185 | .type = PORT_SCIF, | 187 | .type = PORT_SCIF, |
| 186 | .irqs = { 196, 196, 196, 196 }, | 188 | .irqs = { 196, 196, 196, 196 }, |
| 187 | }, { | 189 | }, { |
| 188 | .mapbase = 0xfffe9000, | 190 | .mapbase = 0xfffe9000, |
| 189 | .flags = UPF_BOOT_AUTOCONF, | 191 | .flags = UPF_BOOT_AUTOCONF, |
| 192 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 190 | .type = PORT_SCIF, | 193 | .type = PORT_SCIF, |
| 191 | .irqs = { 200, 200, 200, 200 }, | 194 | .irqs = { 200, 200, 200, 200 }, |
| 192 | }, { | 195 | }, { |
| 193 | .mapbase = 0xfffe9800, | 196 | .mapbase = 0xfffe9800, |
| 194 | .flags = UPF_BOOT_AUTOCONF, | 197 | .flags = UPF_BOOT_AUTOCONF, |
| 198 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 195 | .type = PORT_SCIF, | 199 | .type = PORT_SCIF, |
| 196 | .irqs = { 204, 204, 204, 204 }, | 200 | .irqs = { 204, 204, 204, 204 }, |
| 197 | }, { | 201 | }, { |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index 3e6f3d7a58be..5a47987f3902 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c | |||
| @@ -137,21 +137,25 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 137 | { | 137 | { |
| 138 | .mapbase = 0xfffe8000, | 138 | .mapbase = 0xfffe8000, |
| 139 | .flags = UPF_BOOT_AUTOCONF, | 139 | .flags = UPF_BOOT_AUTOCONF, |
| 140 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 140 | .type = PORT_SCIF, | 141 | .type = PORT_SCIF, |
| 141 | .irqs = { 240, 240, 240, 240 }, | 142 | .irqs = { 240, 240, 240, 240 }, |
| 142 | }, { | 143 | }, { |
| 143 | .mapbase = 0xfffe8800, | 144 | .mapbase = 0xfffe8800, |
| 144 | .flags = UPF_BOOT_AUTOCONF, | 145 | .flags = UPF_BOOT_AUTOCONF, |
| 146 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 145 | .type = PORT_SCIF, | 147 | .type = PORT_SCIF, |
| 146 | .irqs = { 244, 244, 244, 244 }, | 148 | .irqs = { 244, 244, 244, 244 }, |
| 147 | }, { | 149 | }, { |
| 148 | .mapbase = 0xfffe9000, | 150 | .mapbase = 0xfffe9000, |
| 149 | .flags = UPF_BOOT_AUTOCONF, | 151 | .flags = UPF_BOOT_AUTOCONF, |
| 152 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 150 | .type = PORT_SCIF, | 153 | .type = PORT_SCIF, |
| 151 | .irqs = { 248, 248, 248, 248 }, | 154 | .irqs = { 248, 248, 248, 248 }, |
| 152 | }, { | 155 | }, { |
| 153 | .mapbase = 0xfffe9800, | 156 | .mapbase = 0xfffe9800, |
| 154 | .flags = UPF_BOOT_AUTOCONF, | 157 | .flags = UPF_BOOT_AUTOCONF, |
| 158 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 155 | .type = PORT_SCIF, | 159 | .type = PORT_SCIF, |
| 156 | .irqs = { 252, 252, 252, 252 }, | 160 | .irqs = { 252, 252, 252, 252 }, |
| 157 | }, { | 161 | }, { |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 88f742fed9ed..28de53b281f3 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c | |||
| @@ -71,11 +71,14 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 71 | { | 71 | { |
| 72 | .mapbase = 0xa4410000, | 72 | .mapbase = 0xa4410000, |
| 73 | .flags = UPF_BOOT_AUTOCONF, | 73 | .flags = UPF_BOOT_AUTOCONF, |
| 74 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | | ||
| 75 | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, | ||
| 74 | .type = PORT_SCIF, | 76 | .type = PORT_SCIF, |
| 75 | .irqs = { 56, 56, 56 }, | 77 | .irqs = { 56, 56, 56 }, |
| 76 | }, { | 78 | }, { |
| 77 | .mapbase = 0xa4400000, | 79 | .mapbase = 0xa4400000, |
| 78 | .flags = UPF_BOOT_AUTOCONF, | 80 | .flags = UPF_BOOT_AUTOCONF, |
| 81 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, | ||
| 79 | .type = PORT_SCIF, | 82 | .type = PORT_SCIF, |
| 80 | .irqs = { 52, 52, 52 }, | 83 | .irqs = { 52, 52, 52 }, |
| 81 | }, { | 84 | }, { |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index c56306798584..50ac42836dc7 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c | |||
| @@ -110,6 +110,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 110 | { | 110 | { |
| 111 | .mapbase = 0xfffffe80, | 111 | .mapbase = 0xfffffe80, |
| 112 | .flags = UPF_BOOT_AUTOCONF, | 112 | .flags = UPF_BOOT_AUTOCONF, |
| 113 | .scscr = SCSCR_TE | SCSCR_RE, | ||
| 113 | .type = PORT_SCI, | 114 | .type = PORT_SCI, |
| 114 | .irqs = { 23, 23, 23, 0 }, | 115 | .irqs = { 23, 23, 23, 0 }, |
| 115 | }, | 116 | }, |
| @@ -119,6 +120,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 119 | { | 120 | { |
| 120 | .mapbase = 0xa4000150, | 121 | .mapbase = 0xa4000150, |
| 121 | .flags = UPF_BOOT_AUTOCONF, | 122 | .flags = UPF_BOOT_AUTOCONF, |
| 123 | .scscr = SCSCR_TE | SCSCR_RE, | ||
| 122 | .type = PORT_SCIF, | 124 | .type = PORT_SCIF, |
| 123 | .irqs = { 56, 56, 56, 56 }, | 125 | .irqs = { 56, 56, 56, 56 }, |
| 124 | }, | 126 | }, |
| @@ -128,6 +130,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 128 | { | 130 | { |
| 129 | .mapbase = 0xa4000140, | 131 | .mapbase = 0xa4000140, |
| 130 | .flags = UPF_BOOT_AUTOCONF, | 132 | .flags = UPF_BOOT_AUTOCONF, |
| 133 | .scscr = SCSCR_TE | SCSCR_RE, | ||
| 131 | .type = PORT_IRDA, | 134 | .type = PORT_IRDA, |
| 132 | .irqs = { 52, 52, 52, 52 }, | 135 | .irqs = { 52, 52, 52, 52 }, |
| 133 | }, | 136 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index efa76c8148f4..007627ecb7c8 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c | |||
| @@ -100,11 +100,15 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 100 | { | 100 | { |
| 101 | .mapbase = 0xa4400000, | 101 | .mapbase = 0xa4400000, |
| 102 | .flags = UPF_BOOT_AUTOCONF, | 102 | .flags = UPF_BOOT_AUTOCONF, |
| 103 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | | ||
| 104 | SCSCR_CKE1 | SCSCR_CKE0, | ||
| 103 | .type = PORT_SCIF, | 105 | .type = PORT_SCIF, |
| 104 | .irqs = { 52, 52, 52, 52 }, | 106 | .irqs = { 52, 52, 52, 52 }, |
| 105 | }, { | 107 | }, { |
| 106 | .mapbase = 0xa4410000, | 108 | .mapbase = 0xa4410000, |
| 107 | .flags = UPF_BOOT_AUTOCONF, | 109 | .flags = UPF_BOOT_AUTOCONF, |
| 110 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | | ||
| 111 | SCSCR_CKE1 | SCSCR_CKE0, | ||
| 108 | .type = PORT_SCIF, | 112 | .type = PORT_SCIF, |
| 109 | .irqs = { 56, 56, 56, 56 }, | 113 | .irqs = { 56, 56, 56, 56 }, |
| 110 | }, { | 114 | }, { |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index 5b2107798edb..1fc3d9089199 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * SH7720 Setup | 2 | * Setup code for SH7720, SH7721. |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007 Markus Brunner, Mark Jonas | 4 | * Copyright (C) 2007 Markus Brunner, Mark Jonas |
| 5 | * Copyright (C) 2009 Paul Mundt | 5 | * Copyright (C) 2009 Paul Mundt |
| @@ -52,15 +52,16 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 52 | { | 52 | { |
| 53 | .mapbase = 0xa4430000, | 53 | .mapbase = 0xa4430000, |
| 54 | .flags = UPF_BOOT_AUTOCONF, | 54 | .flags = UPF_BOOT_AUTOCONF, |
| 55 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 55 | .type = PORT_SCIF, | 56 | .type = PORT_SCIF, |
| 56 | .irqs = { 80, 80, 80, 80 }, | 57 | .irqs = { 80, 80, 80, 80 }, |
| 57 | }, { | 58 | }, { |
| 58 | .mapbase = 0xa4438000, | 59 | .mapbase = 0xa4438000, |
| 59 | .flags = UPF_BOOT_AUTOCONF, | 60 | .flags = UPF_BOOT_AUTOCONF, |
| 61 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 60 | .type = PORT_SCIF, | 62 | .type = PORT_SCIF, |
| 61 | .irqs = { 81, 81, 81, 81 }, | 63 | .irqs = { 81, 81, 81, 81 }, |
| 62 | }, { | 64 | }, { |
| 63 | |||
| 64 | .flags = 0, | 65 | .flags = 0, |
| 65 | } | 66 | } |
| 66 | }; | 67 | }; |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c index 6d088d123591..9aa6fa3ca4e6 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c | |||
| @@ -19,6 +19,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 19 | { | 19 | { |
| 20 | .mapbase = 0xffe80000, | 20 | .mapbase = 0xffe80000, |
| 21 | .flags = UPF_BOOT_AUTOCONF, | 21 | .flags = UPF_BOOT_AUTOCONF, |
| 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 22 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
| 23 | .irqs = { 40, 41, 43, 42 }, | 24 | .irqs = { 40, 41, 43, 42 }, |
| 24 | }, { | 25 | }, { |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 851672d15cf4..2159c439dce9 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 15 | #include <linux/sh_timer.h> | 15 | #include <linux/sh_timer.h> |
| 16 | #include <linux/serial_sci.h> | 16 | #include <linux/serial_sci.h> |
| 17 | #include <asm/machtypes.h> | ||
| 17 | 18 | ||
| 18 | static struct resource rtc_resources[] = { | 19 | static struct resource rtc_resources[] = { |
| 19 | [0] = { | 20 | [0] = { |
| @@ -35,32 +36,36 @@ static struct platform_device rtc_device = { | |||
| 35 | .resource = rtc_resources, | 36 | .resource = rtc_resources, |
| 36 | }; | 37 | }; |
| 37 | 38 | ||
| 38 | static struct plat_sci_port sci_platform_data[] = { | 39 | static struct plat_sci_port sci_platform_data = { |
| 39 | { | 40 | .mapbase = 0xffe00000, |
| 40 | #ifndef CONFIG_SH_RTS7751R2D | 41 | .flags = UPF_BOOT_AUTOCONF, |
| 41 | .mapbase = 0xffe00000, | 42 | .type = PORT_SCI, |
| 42 | .flags = UPF_BOOT_AUTOCONF, | 43 | .scscr = SCSCR_TE | SCSCR_RE, |
| 43 | .type = PORT_SCI, | 44 | .irqs = { 23, 23, 23, 0 }, |
| 44 | .irqs = { 23, 23, 23, 0 }, | ||
| 45 | }, { | ||
| 46 | #endif | ||
| 47 | .mapbase = 0xffe80000, | ||
| 48 | .flags = UPF_BOOT_AUTOCONF, | ||
| 49 | .type = PORT_SCIF, | ||
| 50 | .irqs = { 40, 40, 40, 40 }, | ||
| 51 | }, { | ||
| 52 | .flags = 0, | ||
| 53 | } | ||
| 54 | }; | 45 | }; |
| 55 | 46 | ||
| 56 | static struct platform_device sci_device = { | 47 | static struct platform_device sci_device = { |
| 57 | .name = "sh-sci", | 48 | .name = "sh-sci", |
| 58 | .id = -1, | ||
| 59 | .dev = { | 49 | .dev = { |
| 60 | .platform_data = sci_platform_data, | 50 | .platform_data = sci_platform_data, |
| 61 | }, | 51 | }, |
| 62 | }; | 52 | }; |
| 63 | 53 | ||
| 54 | static struct plat_sci_port scif_platform_data = { | ||
| 55 | .mapbase = 0xffe80000, | ||
| 56 | .flags = UPF_BOOT_AUTOCONF, | ||
| 57 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, | ||
| 58 | .type = PORT_SCIF, | ||
| 59 | .irqs = { 40, 40, 40, 40 }, | ||
| 60 | }; | ||
| 61 | |||
| 62 | static struct platform_device scif_device = { | ||
| 63 | .name = "sh-sci", | ||
| 64 | .dev = { | ||
| 65 | .platform_data = scif_platform_data, | ||
| 66 | }, | ||
| 67 | }; | ||
| 68 | |||
| 64 | static struct sh_timer_config tmu0_platform_data = { | 69 | static struct sh_timer_config tmu0_platform_data = { |
| 65 | .name = "TMU0", | 70 | .name = "TMU0", |
| 66 | .channel_offset = 0x04, | 71 | .channel_offset = 0x04, |
| @@ -222,7 +227,6 @@ static struct platform_device tmu4_device = { | |||
| 222 | 227 | ||
| 223 | static struct platform_device *sh7750_devices[] __initdata = { | 228 | static struct platform_device *sh7750_devices[] __initdata = { |
| 224 | &rtc_device, | 229 | &rtc_device, |
| 225 | &sci_device, | ||
| 226 | &tmu0_device, | 230 | &tmu0_device, |
| 227 | &tmu1_device, | 231 | &tmu1_device, |
| 228 | &tmu2_device, | 232 | &tmu2_device, |
| @@ -236,6 +240,14 @@ static struct platform_device *sh7750_devices[] __initdata = { | |||
| 236 | 240 | ||
| 237 | static int __init sh7750_devices_setup(void) | 241 | static int __init sh7750_devices_setup(void) |
| 238 | { | 242 | { |
| 243 | if (mach_is_rts7751r2d()) { | ||
| 244 | scif_platform_data.scscr |= SCSCR_CKE1; | ||
| 245 | platform_register_device(&scif_device); | ||
| 246 | } else { | ||
| 247 | platform_register_device(&sci_device); | ||
| 248 | platform_register_device(&scif_device); | ||
| 249 | } | ||
| 250 | |||
| 239 | return platform_add_devices(sh7750_devices, | 251 | return platform_add_devices(sh7750_devices, |
| 240 | ARRAY_SIZE(sh7750_devices)); | 252 | ARRAY_SIZE(sh7750_devices)); |
| 241 | } | 253 | } |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 5b822519bd90..74b5e994724d 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c | |||
| @@ -130,21 +130,25 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 130 | { | 130 | { |
| 131 | .mapbase = 0xfe600000, | 131 | .mapbase = 0xfe600000, |
| 132 | .flags = UPF_BOOT_AUTOCONF, | 132 | .flags = UPF_BOOT_AUTOCONF, |
| 133 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 133 | .type = PORT_SCIF, | 134 | .type = PORT_SCIF, |
| 134 | .irqs = { 52, 53, 55, 54 }, | 135 | .irqs = { 52, 53, 55, 54 }, |
| 135 | }, { | 136 | }, { |
| 136 | .mapbase = 0xfe610000, | 137 | .mapbase = 0xfe610000, |
| 137 | .flags = UPF_BOOT_AUTOCONF, | 138 | .flags = UPF_BOOT_AUTOCONF, |
| 139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 138 | .type = PORT_SCIF, | 140 | .type = PORT_SCIF, |
| 139 | .irqs = { 72, 73, 75, 74 }, | 141 | .irqs = { 72, 73, 75, 74 }, |
| 140 | }, { | 142 | }, { |
| 141 | .mapbase = 0xfe620000, | 143 | .mapbase = 0xfe620000, |
| 142 | .flags = UPF_BOOT_AUTOCONF, | 144 | .flags = UPF_BOOT_AUTOCONF, |
| 145 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 143 | .type = PORT_SCIF, | 146 | .type = PORT_SCIF, |
| 144 | .irqs = { 76, 77, 79, 78 }, | 147 | .irqs = { 76, 77, 79, 78 }, |
| 145 | }, { | 148 | }, { |
| 146 | .mapbase = 0xfe480000, | 149 | .mapbase = 0xfe480000, |
| 147 | .flags = UPF_BOOT_AUTOCONF, | 150 | .flags = UPF_BOOT_AUTOCONF, |
| 151 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 148 | .type = PORT_SCI, | 152 | .type = PORT_SCI, |
| 149 | .irqs = { 80, 81, 82, 0 }, | 153 | .irqs = { 80, 81, 82, 0 }, |
| 150 | }, { | 154 | }, { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 6307e087c864..09fb5814d925 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c | |||
| @@ -269,24 +269,28 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 269 | { | 269 | { |
| 270 | .mapbase = 0xffe00000, | 270 | .mapbase = 0xffe00000, |
| 271 | .flags = UPF_BOOT_AUTOCONF, | 271 | .flags = UPF_BOOT_AUTOCONF, |
| 272 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
| 272 | .type = PORT_SCIF, | 273 | .type = PORT_SCIF, |
| 273 | .irqs = { 80, 80, 80, 80 }, | 274 | .irqs = { 80, 80, 80, 80 }, |
| 274 | .clk = "scif0", | 275 | .clk = "scif0", |
| 275 | }, { | 276 | }, { |
| 276 | .mapbase = 0xffe10000, | 277 | .mapbase = 0xffe10000, |
| 277 | .flags = UPF_BOOT_AUTOCONF, | 278 | .flags = UPF_BOOT_AUTOCONF, |
| 279 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
| 278 | .type = PORT_SCIF, | 280 | .type = PORT_SCIF, |
| 279 | .irqs = { 81, 81, 81, 81 }, | 281 | .irqs = { 81, 81, 81, 81 }, |
| 280 | .clk = "scif1", | 282 | .clk = "scif1", |
| 281 | }, { | 283 | }, { |
| 282 | .mapbase = 0xffe20000, | 284 | .mapbase = 0xffe20000, |
| 283 | .flags = UPF_BOOT_AUTOCONF, | 285 | .flags = UPF_BOOT_AUTOCONF, |
| 286 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
| 284 | .type = PORT_SCIF, | 287 | .type = PORT_SCIF, |
| 285 | .irqs = { 82, 82, 82, 82 }, | 288 | .irqs = { 82, 82, 82, 82 }, |
| 286 | .clk = "scif2", | 289 | .clk = "scif2", |
| 287 | }, { | 290 | }, { |
| 288 | .mapbase = 0xffe30000, | 291 | .mapbase = 0xffe30000, |
| 289 | .flags = UPF_BOOT_AUTOCONF, | 292 | .flags = UPF_BOOT_AUTOCONF, |
| 293 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
| 290 | .type = PORT_SCIF, | 294 | .type = PORT_SCIF, |
| 291 | .irqs = { 83, 83, 83, 83 }, | 295 | .irqs = { 83, 83, 83, 83 }, |
| 292 | .clk = "scif3", | 296 | .clk = "scif3", |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index c18f7d09281b..307777cf04cc 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c | |||
| @@ -280,6 +280,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 280 | { | 280 | { |
| 281 | .mapbase = 0xffe00000, | 281 | .mapbase = 0xffe00000, |
| 282 | .flags = UPF_BOOT_AUTOCONF, | 282 | .flags = UPF_BOOT_AUTOCONF, |
| 283 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 283 | .type = PORT_SCIF, | 284 | .type = PORT_SCIF, |
| 284 | .irqs = { 80, 80, 80, 80 }, | 285 | .irqs = { 80, 80, 80, 80 }, |
| 285 | .clk = "scif0", | 286 | .clk = "scif0", |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index ea524a2da3e4..ffc69bc95932 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c | |||
| @@ -305,25 +305,25 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 305 | { | 305 | { |
| 306 | .mapbase = 0xffe00000, | 306 | .mapbase = 0xffe00000, |
| 307 | .flags = UPF_BOOT_AUTOCONF, | 307 | .flags = UPF_BOOT_AUTOCONF, |
| 308 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 308 | .type = PORT_SCIF, | 309 | .type = PORT_SCIF, |
| 309 | .irqs = { 80, 80, 80, 80 }, | 310 | .irqs = { 80, 80, 80, 80 }, |
| 310 | .clk = "scif0", | 311 | .clk = "scif0", |
| 311 | }, | 312 | }, { |
| 312 | { | ||
| 313 | .mapbase = 0xffe10000, | 313 | .mapbase = 0xffe10000, |
| 314 | .flags = UPF_BOOT_AUTOCONF, | 314 | .flags = UPF_BOOT_AUTOCONF, |
| 315 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 315 | .type = PORT_SCIF, | 316 | .type = PORT_SCIF, |
| 316 | .irqs = { 81, 81, 81, 81 }, | 317 | .irqs = { 81, 81, 81, 81 }, |
| 317 | .clk = "scif1", | 318 | .clk = "scif1", |
| 318 | }, | 319 | }, { |
| 319 | { | ||
| 320 | .mapbase = 0xffe20000, | 320 | .mapbase = 0xffe20000, |
| 321 | .flags = UPF_BOOT_AUTOCONF, | 321 | .flags = UPF_BOOT_AUTOCONF, |
| 322 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 322 | .type = PORT_SCIF, | 323 | .type = PORT_SCIF, |
| 323 | .irqs = { 82, 82, 82, 82 }, | 324 | .irqs = { 82, 82, 82, 82 }, |
| 324 | .clk = "scif2", | 325 | .clk = "scif2", |
| 325 | }, | 326 | }, { |
| 326 | { | ||
| 327 | .flags = 0, | 327 | .flags = 0, |
| 328 | } | 328 | } |
| 329 | }; | 329 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index e1bb80b2a27b..6ce331a8f1bd 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
| @@ -321,36 +321,42 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 321 | { | 321 | { |
| 322 | .mapbase = 0xffe00000, | 322 | .mapbase = 0xffe00000, |
| 323 | .flags = UPF_BOOT_AUTOCONF, | 323 | .flags = UPF_BOOT_AUTOCONF, |
| 324 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 324 | .type = PORT_SCIF, | 325 | .type = PORT_SCIF, |
| 325 | .irqs = { 80, 80, 80, 80 }, | 326 | .irqs = { 80, 80, 80, 80 }, |
| 326 | .clk = "scif0", | 327 | .clk = "scif0", |
| 327 | },{ | 328 | },{ |
| 328 | .mapbase = 0xffe10000, | 329 | .mapbase = 0xffe10000, |
| 329 | .flags = UPF_BOOT_AUTOCONF, | 330 | .flags = UPF_BOOT_AUTOCONF, |
| 331 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 330 | .type = PORT_SCIF, | 332 | .type = PORT_SCIF, |
| 331 | .irqs = { 81, 81, 81, 81 }, | 333 | .irqs = { 81, 81, 81, 81 }, |
| 332 | .clk = "scif1", | 334 | .clk = "scif1", |
| 333 | },{ | 335 | },{ |
| 334 | .mapbase = 0xffe20000, | 336 | .mapbase = 0xffe20000, |
| 335 | .flags = UPF_BOOT_AUTOCONF, | 337 | .flags = UPF_BOOT_AUTOCONF, |
| 338 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 336 | .type = PORT_SCIF, | 339 | .type = PORT_SCIF, |
| 337 | .irqs = { 82, 82, 82, 82 }, | 340 | .irqs = { 82, 82, 82, 82 }, |
| 338 | .clk = "scif2", | 341 | .clk = "scif2", |
| 339 | },{ | 342 | },{ |
| 340 | .mapbase = 0xa4e30000, | 343 | .mapbase = 0xa4e30000, |
| 341 | .flags = UPF_BOOT_AUTOCONF, | 344 | .flags = UPF_BOOT_AUTOCONF, |
| 345 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 342 | .type = PORT_SCIFA, | 346 | .type = PORT_SCIFA, |
| 343 | .irqs = { 56, 56, 56, 56 }, | 347 | .irqs = { 56, 56, 56, 56 }, |
| 344 | .clk = "scif3", | 348 | .clk = "scif3", |
| 345 | },{ | 349 | },{ |
| 346 | .mapbase = 0xa4e40000, | 350 | .mapbase = 0xa4e40000, |
| 347 | .flags = UPF_BOOT_AUTOCONF, | 351 | .flags = UPF_BOOT_AUTOCONF, |
| 352 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 348 | .type = PORT_SCIFA, | 353 | .type = PORT_SCIFA, |
| 349 | .irqs = { 88, 88, 88, 88 }, | 354 | .irqs = { 88, 88, 88, 88 }, |
| 350 | .clk = "scif4", | 355 | .clk = "scif4", |
| 351 | },{ | 356 | },{ |
| 352 | .mapbase = 0xa4e50000, | 357 | .mapbase = 0xa4e50000, |
| 353 | .flags = UPF_BOOT_AUTOCONF, | 358 | .flags = UPF_BOOT_AUTOCONF, |
| 359 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 354 | .type = PORT_SCIFA, | 360 | .type = PORT_SCIFA, |
| 355 | .irqs = { 109, 109, 109, 109 }, | 361 | .irqs = { 109, 109, 109, 109 }, |
| 356 | .clk = "scif5", | 362 | .clk = "scif5", |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index e5ac9eb11c63..4bf03c1ec8d6 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c | |||
| @@ -28,36 +28,42 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 28 | { | 28 | { |
| 29 | .mapbase = 0xffe00000, | 29 | .mapbase = 0xffe00000, |
| 30 | .flags = UPF_BOOT_AUTOCONF, | 30 | .flags = UPF_BOOT_AUTOCONF, |
| 31 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 31 | .type = PORT_SCIF, | 32 | .type = PORT_SCIF, |
| 32 | .irqs = { 80, 80, 80, 80 }, | 33 | .irqs = { 80, 80, 80, 80 }, |
| 33 | .clk = "scif0", | 34 | .clk = "scif0", |
| 34 | }, { | 35 | }, { |
| 35 | .mapbase = 0xffe10000, | 36 | .mapbase = 0xffe10000, |
| 36 | .flags = UPF_BOOT_AUTOCONF, | 37 | .flags = UPF_BOOT_AUTOCONF, |
| 38 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 37 | .type = PORT_SCIF, | 39 | .type = PORT_SCIF, |
| 38 | .irqs = { 81, 81, 81, 81 }, | 40 | .irqs = { 81, 81, 81, 81 }, |
| 39 | .clk = "scif1", | 41 | .clk = "scif1", |
| 40 | }, { | 42 | }, { |
| 41 | .mapbase = 0xffe20000, | 43 | .mapbase = 0xffe20000, |
| 42 | .flags = UPF_BOOT_AUTOCONF, | 44 | .flags = UPF_BOOT_AUTOCONF, |
| 45 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 43 | .type = PORT_SCIF, | 46 | .type = PORT_SCIF, |
| 44 | .irqs = { 82, 82, 82, 82 }, | 47 | .irqs = { 82, 82, 82, 82 }, |
| 45 | .clk = "scif2", | 48 | .clk = "scif2", |
| 46 | }, { | 49 | }, { |
| 47 | .mapbase = 0xa4e30000, | 50 | .mapbase = 0xa4e30000, |
| 48 | .flags = UPF_BOOT_AUTOCONF, | 51 | .flags = UPF_BOOT_AUTOCONF, |
| 52 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 49 | .type = PORT_SCIFA, | 53 | .type = PORT_SCIFA, |
| 50 | .irqs = { 56, 56, 56, 56 }, | 54 | .irqs = { 56, 56, 56, 56 }, |
| 51 | .clk = "scif3", | 55 | .clk = "scif3", |
| 52 | }, { | 56 | }, { |
| 53 | .mapbase = 0xa4e40000, | 57 | .mapbase = 0xa4e40000, |
| 54 | .flags = UPF_BOOT_AUTOCONF, | 58 | .flags = UPF_BOOT_AUTOCONF, |
| 59 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 55 | .type = PORT_SCIFA, | 60 | .type = PORT_SCIFA, |
| 56 | .irqs = { 88, 88, 88, 88 }, | 61 | .irqs = { 88, 88, 88, 88 }, |
| 57 | .clk = "scif4", | 62 | .clk = "scif4", |
| 58 | }, { | 63 | }, { |
| 59 | .mapbase = 0xa4e50000, | 64 | .mapbase = 0xa4e50000, |
| 60 | .flags = UPF_BOOT_AUTOCONF, | 65 | .flags = UPF_BOOT_AUTOCONF, |
| 66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 61 | .type = PORT_SCIFA, | 67 | .type = PORT_SCIFA, |
| 62 | .irqs = { 109, 109, 109, 109 }, | 68 | .irqs = { 109, 109, 109, 109 }, |
| 63 | .clk = "scif5", | 69 | .clk = "scif5", |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index f1e0c0d36da7..76339c6da01e 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c | |||
| @@ -40,16 +40,19 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 40 | { | 40 | { |
| 41 | .mapbase = 0xffe00000, | 41 | .mapbase = 0xffe00000, |
| 42 | .flags = UPF_BOOT_AUTOCONF, | 42 | .flags = UPF_BOOT_AUTOCONF, |
| 43 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 43 | .type = PORT_SCIF, | 44 | .type = PORT_SCIF, |
| 44 | .irqs = { 40, 40, 40, 40 }, | 45 | .irqs = { 40, 40, 40, 40 }, |
| 45 | }, { | 46 | }, { |
| 46 | .mapbase = 0xffe08000, | 47 | .mapbase = 0xffe08000, |
| 47 | .flags = UPF_BOOT_AUTOCONF, | 48 | .flags = UPF_BOOT_AUTOCONF, |
| 49 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 48 | .type = PORT_SCIF, | 50 | .type = PORT_SCIF, |
| 49 | .irqs = { 76, 76, 76, 76 }, | 51 | .irqs = { 76, 76, 76, 76 }, |
| 50 | }, { | 52 | }, { |
| 51 | .mapbase = 0xffe10000, | 53 | .mapbase = 0xffe10000, |
| 52 | .flags = UPF_BOOT_AUTOCONF, | 54 | .flags = UPF_BOOT_AUTOCONF, |
| 55 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 53 | .type = PORT_SCIF, | 56 | .type = PORT_SCIF, |
| 54 | .irqs = { 104, 104, 104, 104 }, | 57 | .irqs = { 104, 104, 104, 104 }, |
| 55 | }, { | 58 | }, { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 1e86209db284..07a41ff20504 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c | |||
| @@ -18,51 +18,61 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 18 | { | 18 | { |
| 19 | .mapbase = 0xff923000, | 19 | .mapbase = 0xff923000, |
| 20 | .flags = UPF_BOOT_AUTOCONF, | 20 | .flags = UPF_BOOT_AUTOCONF, |
| 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 21 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
| 22 | .irqs = { 61, 61, 61, 61 }, | 23 | .irqs = { 61, 61, 61, 61 }, |
| 23 | }, { | 24 | }, { |
| 24 | .mapbase = 0xff924000, | 25 | .mapbase = 0xff924000, |
| 25 | .flags = UPF_BOOT_AUTOCONF, | 26 | .flags = UPF_BOOT_AUTOCONF, |
| 27 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 26 | .type = PORT_SCIF, | 28 | .type = PORT_SCIF, |
| 27 | .irqs = { 62, 62, 62, 62 }, | 29 | .irqs = { 62, 62, 62, 62 }, |
| 28 | }, { | 30 | }, { |
| 29 | .mapbase = 0xff925000, | 31 | .mapbase = 0xff925000, |
| 30 | .flags = UPF_BOOT_AUTOCONF, | 32 | .flags = UPF_BOOT_AUTOCONF, |
| 33 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 31 | .type = PORT_SCIF, | 34 | .type = PORT_SCIF, |
| 32 | .irqs = { 63, 63, 63, 63 }, | 35 | .irqs = { 63, 63, 63, 63 }, |
| 33 | }, { | 36 | }, { |
| 34 | .mapbase = 0xff926000, | 37 | .mapbase = 0xff926000, |
| 35 | .flags = UPF_BOOT_AUTOCONF, | 38 | .flags = UPF_BOOT_AUTOCONF, |
| 39 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 36 | .type = PORT_SCIF, | 40 | .type = PORT_SCIF, |
| 37 | .irqs = { 64, 64, 64, 64 }, | 41 | .irqs = { 64, 64, 64, 64 }, |
| 38 | }, { | 42 | }, { |
| 39 | .mapbase = 0xff927000, | 43 | .mapbase = 0xff927000, |
| 40 | .flags = UPF_BOOT_AUTOCONF, | 44 | .flags = UPF_BOOT_AUTOCONF, |
| 45 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 41 | .type = PORT_SCIF, | 46 | .type = PORT_SCIF, |
| 42 | .irqs = { 65, 65, 65, 65 }, | 47 | .irqs = { 65, 65, 65, 65 }, |
| 43 | }, { | 48 | }, { |
| 44 | .mapbase = 0xff928000, | 49 | .mapbase = 0xff928000, |
| 45 | .flags = UPF_BOOT_AUTOCONF, | 50 | .flags = UPF_BOOT_AUTOCONF, |
| 51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 46 | .type = PORT_SCIF, | 52 | .type = PORT_SCIF, |
| 47 | .irqs = { 66, 66, 66, 66 }, | 53 | .irqs = { 66, 66, 66, 66 }, |
| 48 | }, { | 54 | }, { |
| 49 | .mapbase = 0xff929000, | 55 | .mapbase = 0xff929000, |
| 50 | .flags = UPF_BOOT_AUTOCONF, | 56 | .flags = UPF_BOOT_AUTOCONF, |
| 57 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 51 | .type = PORT_SCIF, | 58 | .type = PORT_SCIF, |
| 52 | .irqs = { 67, 67, 67, 67 }, | 59 | .irqs = { 67, 67, 67, 67 }, |
| 53 | }, { | 60 | }, { |
| 54 | .mapbase = 0xff92a000, | 61 | .mapbase = 0xff92a000, |
| 55 | .flags = UPF_BOOT_AUTOCONF, | 62 | .flags = UPF_BOOT_AUTOCONF, |
| 63 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 56 | .type = PORT_SCIF, | 64 | .type = PORT_SCIF, |
| 57 | .irqs = { 68, 68, 68, 68 }, | 65 | .irqs = { 68, 68, 68, 68 }, |
| 58 | }, { | 66 | }, { |
| 59 | .mapbase = 0xff92b000, | 67 | .mapbase = 0xff92b000, |
| 60 | .flags = UPF_BOOT_AUTOCONF, | 68 | .flags = UPF_BOOT_AUTOCONF, |
| 69 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 61 | .type = PORT_SCIF, | 70 | .type = PORT_SCIF, |
| 62 | .irqs = { 69, 69, 69, 69 }, | 71 | .irqs = { 69, 69, 69, 69 }, |
| 63 | }, { | 72 | }, { |
| 64 | .mapbase = 0xff92c000, | 73 | .mapbase = 0xff92c000, |
| 65 | .flags = UPF_BOOT_AUTOCONF, | 74 | .flags = UPF_BOOT_AUTOCONF, |
| 75 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
| 66 | .type = PORT_SCIF, | 76 | .type = PORT_SCIF, |
| 67 | .irqs = { 70, 70, 70, 70 }, | 77 | .irqs = { 70, 70, 70, 70 }, |
| 68 | }, { | 78 | }, { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index 715e05b431e5..2b355b67a33d 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c | |||
| @@ -220,11 +220,13 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 220 | { | 220 | { |
| 221 | .mapbase = 0xffe00000, | 221 | .mapbase = 0xffe00000, |
| 222 | .flags = UPF_BOOT_AUTOCONF, | 222 | .flags = UPF_BOOT_AUTOCONF, |
| 223 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 223 | .type = PORT_SCIF, | 224 | .type = PORT_SCIF, |
| 224 | .irqs = { 40, 40, 40, 40 }, | 225 | .irqs = { 40, 40, 40, 40 }, |
| 225 | }, { | 226 | }, { |
| 226 | .mapbase = 0xffe10000, | 227 | .mapbase = 0xffe10000, |
| 227 | .flags = UPF_BOOT_AUTOCONF, | 228 | .flags = UPF_BOOT_AUTOCONF, |
| 229 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 228 | .type = PORT_SCIF, | 230 | .type = PORT_SCIF, |
| 229 | .irqs = { 76, 76, 76, 76 }, | 231 | .irqs = { 76, 76, 76, 76 }, |
| 230 | }, { | 232 | }, { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index af561402570b..acd4b1d1b813 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c | |||
| @@ -202,36 +202,42 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 202 | { | 202 | { |
| 203 | .mapbase = 0xffea0000, | 203 | .mapbase = 0xffea0000, |
| 204 | .flags = UPF_BOOT_AUTOCONF, | 204 | .flags = UPF_BOOT_AUTOCONF, |
| 205 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 205 | .type = PORT_SCIF, | 206 | .type = PORT_SCIF, |
| 206 | .irqs = { 40, 40, 40, 40 }, | 207 | .irqs = { 40, 40, 40, 40 }, |
| 207 | .clk = "scif_fck", | 208 | .clk = "scif_fck", |
| 208 | }, { | 209 | }, { |
| 209 | .mapbase = 0xffeb0000, | 210 | .mapbase = 0xffeb0000, |
| 210 | .flags = UPF_BOOT_AUTOCONF, | 211 | .flags = UPF_BOOT_AUTOCONF, |
| 212 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 211 | .type = PORT_SCIF, | 213 | .type = PORT_SCIF, |
| 212 | .irqs = { 44, 44, 44, 44 }, | 214 | .irqs = { 44, 44, 44, 44 }, |
| 213 | .clk = "scif_fck", | 215 | .clk = "scif_fck", |
| 214 | }, { | 216 | }, { |
| 215 | .mapbase = 0xffec0000, | 217 | .mapbase = 0xffec0000, |
| 216 | .flags = UPF_BOOT_AUTOCONF, | 218 | .flags = UPF_BOOT_AUTOCONF, |
| 219 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 217 | .type = PORT_SCIF, | 220 | .type = PORT_SCIF, |
| 218 | .irqs = { 60, 60, 60, 60 }, | 221 | .irqs = { 60, 60, 60, 60 }, |
| 219 | .clk = "scif_fck", | 222 | .clk = "scif_fck", |
| 220 | }, { | 223 | }, { |
| 221 | .mapbase = 0xffed0000, | 224 | .mapbase = 0xffed0000, |
| 222 | .flags = UPF_BOOT_AUTOCONF, | 225 | .flags = UPF_BOOT_AUTOCONF, |
| 226 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 223 | .type = PORT_SCIF, | 227 | .type = PORT_SCIF, |
| 224 | .irqs = { 61, 61, 61, 61 }, | 228 | .irqs = { 61, 61, 61, 61 }, |
| 225 | .clk = "scif_fck", | 229 | .clk = "scif_fck", |
| 226 | }, { | 230 | }, { |
| 227 | .mapbase = 0xffee0000, | 231 | .mapbase = 0xffee0000, |
| 228 | .flags = UPF_BOOT_AUTOCONF, | 232 | .flags = UPF_BOOT_AUTOCONF, |
| 233 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 229 | .type = PORT_SCIF, | 234 | .type = PORT_SCIF, |
| 230 | .irqs = { 62, 62, 62, 62 }, | 235 | .irqs = { 62, 62, 62, 62 }, |
| 231 | .clk = "scif_fck", | 236 | .clk = "scif_fck", |
| 232 | }, { | 237 | }, { |
| 233 | .mapbase = 0xffef0000, | 238 | .mapbase = 0xffef0000, |
| 234 | .flags = UPF_BOOT_AUTOCONF, | 239 | .flags = UPF_BOOT_AUTOCONF, |
| 240 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 235 | .type = PORT_SCIF, | 241 | .type = PORT_SCIF, |
| 236 | .irqs = { 63, 63, 63, 63 }, | 242 | .irqs = { 63, 63, 63, 63 }, |
| 237 | .clk = "scif_fck", | 243 | .clk = "scif_fck", |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index b70049470a0b..347ce88de570 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c | |||
| @@ -27,6 +27,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 27 | { | 27 | { |
| 28 | .mapbase = 0xffea0000, | 28 | .mapbase = 0xffea0000, |
| 29 | .flags = UPF_BOOT_AUTOCONF, | 29 | .flags = UPF_BOOT_AUTOCONF, |
| 30 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 30 | .type = PORT_SCIF, | 31 | .type = PORT_SCIF, |
| 31 | .irqs = { 40, 41, 43, 42 }, | 32 | .irqs = { 40, 41, 43, 42 }, |
| 32 | }, | 33 | }, |
| @@ -36,26 +37,31 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 36 | { | 37 | { |
| 37 | .mapbase = 0xffeb0000, | 38 | .mapbase = 0xffeb0000, |
| 38 | .flags = UPF_BOOT_AUTOCONF, | 39 | .flags = UPF_BOOT_AUTOCONF, |
| 40 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 39 | .type = PORT_SCIF, | 41 | .type = PORT_SCIF, |
| 40 | .irqs = { 44, 44, 44, 44 }, | 42 | .irqs = { 44, 44, 44, 44 }, |
| 41 | }, { | 43 | }, { |
| 42 | .mapbase = 0xffec0000, | 44 | .mapbase = 0xffec0000, |
| 43 | .flags = UPF_BOOT_AUTOCONF, | 45 | .flags = UPF_BOOT_AUTOCONF, |
| 46 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 44 | .type = PORT_SCIF, | 47 | .type = PORT_SCIF, |
| 45 | .irqs = { 50, 50, 50, 50 }, | 48 | .irqs = { 50, 50, 50, 50 }, |
| 46 | }, { | 49 | }, { |
| 47 | .mapbase = 0xffed0000, | 50 | .mapbase = 0xffed0000, |
| 48 | .flags = UPF_BOOT_AUTOCONF, | 51 | .flags = UPF_BOOT_AUTOCONF, |
| 52 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 49 | .type = PORT_SCIF, | 53 | .type = PORT_SCIF, |
| 50 | .irqs = { 51, 51, 51, 51 }, | 54 | .irqs = { 51, 51, 51, 51 }, |
| 51 | }, { | 55 | }, { |
| 52 | .mapbase = 0xffee0000, | 56 | .mapbase = 0xffee0000, |
| 53 | .flags = UPF_BOOT_AUTOCONF, | 57 | .flags = UPF_BOOT_AUTOCONF, |
| 58 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 54 | .type = PORT_SCIF, | 59 | .type = PORT_SCIF, |
| 55 | .irqs = { 52, 52, 52, 52 }, | 60 | .irqs = { 52, 52, 52, 52 }, |
| 56 | }, { | 61 | }, { |
| 57 | .mapbase = 0xffef0000, | 62 | .mapbase = 0xffef0000, |
| 58 | .flags = UPF_BOOT_AUTOCONF, | 63 | .flags = UPF_BOOT_AUTOCONF, |
| 64 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | ||
| 59 | .type = PORT_SCIF, | 65 | .type = PORT_SCIF, |
| 60 | .irqs = { 53, 53, 53, 53 }, | 66 | .irqs = { 53, 53, 53, 53 }, |
| 61 | }, { | 67 | }, { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 53c65fd9ccef..eef94934f542 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c | |||
| @@ -19,21 +19,25 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 19 | { | 19 | { |
| 20 | .mapbase = 0xffc30000, | 20 | .mapbase = 0xffc30000, |
| 21 | .flags = UPF_BOOT_AUTOCONF, | 21 | .flags = UPF_BOOT_AUTOCONF, |
| 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 22 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
| 23 | .irqs = { 40, 41, 43, 42 }, | 24 | .irqs = { 40, 41, 43, 42 }, |
| 24 | }, { | 25 | }, { |
| 25 | .mapbase = 0xffc40000, | 26 | .mapbase = 0xffc40000, |
| 26 | .flags = UPF_BOOT_AUTOCONF, | 27 | .flags = UPF_BOOT_AUTOCONF, |
| 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 27 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
| 28 | .irqs = { 44, 45, 47, 46 }, | 30 | .irqs = { 44, 45, 47, 46 }, |
| 29 | }, { | 31 | }, { |
| 30 | .mapbase = 0xffc50000, | 32 | .mapbase = 0xffc50000, |
| 31 | .flags = UPF_BOOT_AUTOCONF, | 33 | .flags = UPF_BOOT_AUTOCONF, |
| 34 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 32 | .type = PORT_SCIF, | 35 | .type = PORT_SCIF, |
| 33 | .irqs = { 48, 49, 51, 50 }, | 36 | .irqs = { 48, 49, 51, 50 }, |
| 34 | }, { | 37 | }, { |
| 35 | .mapbase = 0xffc60000, | 38 | .mapbase = 0xffc60000, |
| 36 | .flags = UPF_BOOT_AUTOCONF, | 39 | .flags = UPF_BOOT_AUTOCONF, |
| 40 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 37 | .type = PORT_SCIF, | 41 | .type = PORT_SCIF, |
| 38 | .irqs = { 52, 53, 55, 54 }, | 42 | .irqs = { 52, 53, 55, 54 }, |
| 39 | }, { | 43 | }, { |
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c index f5ff1ac57fc2..26fa10c560de 100644 --- a/arch/sh/kernel/cpu/sh5/setup-sh5.c +++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c | |||
| @@ -20,6 +20,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
| 20 | { | 20 | { |
| 21 | .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, | 21 | .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, |
| 22 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | 22 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
| 23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
| 23 | .type = PORT_SCIF, | 24 | .type = PORT_SCIF, |
| 24 | .irqs = { 39, 40, 42, 0 }, | 25 | .irqs = { 39, 40, 42, 0 }, |
| 25 | }, { | 26 | }, { |
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c index 66f52674ca0c..3a13e58e9c5d 100644 --- a/drivers/serial/sh-sci.c +++ b/drivers/serial/sh-sci.c | |||
| @@ -79,6 +79,9 @@ struct sci_port { | |||
| 79 | struct timer_list break_timer; | 79 | struct timer_list break_timer; |
| 80 | int break_flag; | 80 | int break_flag; |
| 81 | 81 | ||
| 82 | /* SCSCR initialization */ | ||
| 83 | unsigned int scscr; | ||
| 84 | |||
| 82 | #ifdef CONFIG_HAVE_CLK | 85 | #ifdef CONFIG_HAVE_CLK |
| 83 | /* Interface clock */ | 86 | /* Interface clock */ |
| 84 | struct clk *iclk; | 87 | struct clk *iclk; |
| @@ -928,6 +931,7 @@ static void sci_shutdown(struct uart_port *port) | |||
| 928 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, | 931 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
| 929 | struct ktermios *old) | 932 | struct ktermios *old) |
| 930 | { | 933 | { |
| 934 | struct sci_port *s = to_sci_port(port); | ||
| 931 | unsigned int status, baud, smr_val; | 935 | unsigned int status, baud, smr_val; |
| 932 | int t = -1; | 936 | int t = -1; |
| 933 | 937 | ||
| @@ -972,7 +976,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, | |||
| 972 | sci_init_pins(port, termios->c_cflag); | 976 | sci_init_pins(port, termios->c_cflag); |
| 973 | sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0); | 977 | sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0); |
| 974 | 978 | ||
| 975 | sci_out(port, SCSCR, SCSCR_INIT(port)); | 979 | sci_out(port, SCSCR, s->scscr); |
| 976 | 980 | ||
| 977 | if ((termios->c_cflag & CREAD) != 0) | 981 | if ((termios->c_cflag & CREAD) != 0) |
| 978 | sci_start_rx(port, 0); | 982 | sci_start_rx(port, 0); |
| @@ -1097,6 +1101,7 @@ static void __devinit sci_init_single(struct platform_device *dev, | |||
| 1097 | sci_port->port.mapbase = p->mapbase; | 1101 | sci_port->port.mapbase = p->mapbase; |
| 1098 | sci_port->port.membase = p->membase; | 1102 | sci_port->port.membase = p->membase; |
| 1099 | 1103 | ||
| 1104 | sci_port->scscr = p->scscr; | ||
| 1100 | sci_port->port.irq = p->irqs[SCIx_TXI_IRQ]; | 1105 | sci_port->port.irq = p->irqs[SCIx_TXI_IRQ]; |
| 1101 | sci_port->port.flags = p->flags; | 1106 | sci_port->port.flags = p->flags; |
| 1102 | sci_port->port.dev = &dev->dev; | 1107 | sci_port->port.dev = &dev->dev; |
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 38072c15b845..4aa0ac8e67dd 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 15 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ | 16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
| 17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | 17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ |
| 18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | ||
| 19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | 18 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
| 20 | # define SCIF0 0xA4400000 | 19 | # define SCIF0 0xA4400000 |
| 21 | # define SCIF2 0xA4410000 | 20 | # define SCIF2 0xA4410000 |
| @@ -23,15 +22,8 @@ | |||
| 23 | # define IRDA_SCIF SCIF0 | 22 | # define IRDA_SCIF SCIF0 |
| 24 | # define SCPCR 0xA4000116 | 23 | # define SCPCR 0xA4000116 |
| 25 | # define SCPDR 0xA4000136 | 24 | # define SCPDR 0xA4000136 |
| 26 | |||
| 27 | /* Set the clock source, | ||
| 28 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | ||
| 29 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | ||
| 30 | */ | ||
| 31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | ||
| 32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 25 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 33 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 26 | defined(CONFIG_CPU_SUBTYPE_SH7721) |
| 34 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | ||
| 35 | # define PORT_PTCR 0xA405011EUL | 27 | # define PORT_PTCR 0xA405011EUL |
| 36 | # define PORT_PVCR 0xA4050122UL | 28 | # define PORT_PVCR 0xA4050122UL |
| 37 | # define SCIF_ORER 0x0200 /* overrun error bit */ | 29 | # define SCIF_ORER 0x0200 /* overrun error bit */ |
| @@ -39,7 +31,6 @@ | |||
| 39 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ | 31 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ |
| 40 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | 32 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
| 41 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 33 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 42 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 43 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | 34 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 44 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 35 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
| 45 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 36 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
| @@ -49,39 +40,31 @@ | |||
| 49 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ | 40 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
| 50 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | 41 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
| 51 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 42 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 52 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | ||
| 53 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | ||
| 54 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | ||
| 55 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | 43 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
| 56 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ | 44 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
| 57 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | 45 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ |
| 58 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | 46 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ |
| 59 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 47 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 60 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 61 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | 48 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| 62 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ | 49 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
| 63 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 50 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 64 | # define PACR 0xa4050100 | 51 | # define PACR 0xa4050100 |
| 65 | # define PBCR 0xa4050102 | 52 | # define PBCR 0xa4050102 |
| 66 | # define SCSCR_INIT(port) 0x3B | ||
| 67 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) | 53 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 68 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | 54 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ |
| 69 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | 55 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ |
| 70 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | 56 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ |
| 71 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | 57 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ |
| 72 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | ||
| 73 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) | 58 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 74 | # define PADR 0xA4050120 | 59 | # define PADR 0xA4050120 |
| 75 | # define PSDR 0xA405013e | 60 | # define PSDR 0xA405013e |
| 76 | # define PWDR 0xA4050166 | 61 | # define PWDR 0xA4050166 |
| 77 | # define PSCR 0xA405011E | 62 | # define PSCR 0xA405011E |
| 78 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 63 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 79 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 80 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) | 64 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
| 81 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | 65 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ |
| 82 | # define SCSPTR0 SCPDR0 | 66 | # define SCSPTR0 SCPDR0 |
| 83 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 67 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 84 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 85 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) | 68 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| 86 | # define SCSPTR0 0xa4050160 | 69 | # define SCSPTR0 0xa4050160 |
| 87 | # define SCSPTR1 0xa405013e | 70 | # define SCSPTR1 0xa405013e |
| @@ -90,45 +73,34 @@ | |||
| 90 | # define SCSPTR4 0xa4050128 | 73 | # define SCSPTR4 0xa4050128 |
| 91 | # define SCSPTR5 0xa4050128 | 74 | # define SCSPTR5 0xa4050128 |
| 92 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 75 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 93 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 94 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | 76 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
| 95 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 77 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 96 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 97 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | 78 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 98 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | 79 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
| 99 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 80 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 100 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 101 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | 81 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
| 102 | # define SCIF_BASE_ADDR 0x01030000 | ||
| 103 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | ||
| 104 | # define SCIF_PTR2_OFFS 0x0000020 | 82 | # define SCIF_PTR2_OFFS 0x0000020 |
| 105 | # define SCIF_LSR2_OFFS 0x0000024 | 83 | # define SCIF_LSR2_OFFS 0x0000024 |
| 106 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ | 84 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
| 107 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | 85 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ |
| 108 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ | ||
| 109 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | 86 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
| 110 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | ||
| 111 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | 87 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
| 112 | #elif defined(CONFIG_H8S2678) | 88 | #elif defined(CONFIG_H8S2678) |
| 113 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | ||
| 114 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | 89 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
| 115 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | 90 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 116 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | 91 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
| 117 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | 92 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ |
| 118 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ | 93 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
| 119 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 94 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 120 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 121 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) | 95 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 122 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | 96 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ |
| 123 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | 97 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ |
| 124 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | 98 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ |
| 125 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 99 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 126 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | ||
| 127 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | 100 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
| 128 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | 101 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
| 129 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | 102 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ |
| 130 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | 103 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| 131 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 132 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | 104 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
| 133 | defined(CONFIG_CPU_SUBTYPE_SH7786) | 105 | defined(CONFIG_CPU_SUBTYPE_SH7786) |
| 134 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | 106 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ |
| @@ -138,7 +110,6 @@ | |||
| 138 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | 110 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ |
| 139 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | 111 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ |
| 140 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | 112 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| 141 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 142 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ | 113 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ |
| 143 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | 114 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ |
| 144 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ | 115 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
| @@ -153,20 +124,17 @@ | |||
| 153 | # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ | 124 | # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ |
| 154 | # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ | 125 | # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ |
| 155 | # endif | 126 | # endif |
| 156 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 157 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | 127 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
| 158 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | 128 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ |
| 159 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | 129 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ |
| 160 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | 130 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ |
| 161 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 131 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 162 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 163 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) | 132 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
| 164 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | 133 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ |
| 165 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | 134 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ |
| 166 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ | 135 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ |
| 167 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | 136 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ |
| 168 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | 137 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| 169 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
| 170 | #else | 138 | #else |
| 171 | # error CPU subtype not defined | 139 | # error CPU subtype not defined |
| 172 | #endif | 140 | #endif |
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h index 1c297ddc9d5a..f722a2275add 100644 --- a/include/linux/serial_sci.h +++ b/include/linux/serial_sci.h | |||
| @@ -7,6 +7,15 @@ | |||
| 7 | * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) | 7 | * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #define SCSCR_TIE (1 << 7) | ||
| 11 | #define SCSCR_RIE (1 << 6) | ||
| 12 | #define SCSCR_TE (1 << 5) | ||
| 13 | #define SCSCR_RE (1 << 4) | ||
| 14 | #define SCSCR_REIE (1 << 3) | ||
| 15 | #define SCSCR_TOIE (1 << 2) /* not supported by all parts */ | ||
| 16 | #define SCSCR_CKE1 (1 << 1) | ||
| 17 | #define SCSCR_CKE0 (1 << 0) | ||
| 18 | |||
| 10 | /* Offsets into the sci_port->irqs array */ | 19 | /* Offsets into the sci_port->irqs array */ |
| 11 | enum { | 20 | enum { |
| 12 | SCIx_ERI_IRQ, | 21 | SCIx_ERI_IRQ, |
| @@ -26,6 +35,8 @@ struct plat_sci_port { | |||
| 26 | unsigned int type; /* SCI / SCIF / IRDA */ | 35 | unsigned int type; /* SCI / SCIF / IRDA */ |
| 27 | upf_t flags; /* UPF_* flags */ | 36 | upf_t flags; /* UPF_* flags */ |
| 28 | char *clk; /* clock string */ | 37 | char *clk; /* clock string */ |
| 38 | |||
| 39 | unsigned int scscr; /* SCSCR initialization */ | ||
| 29 | }; | 40 | }; |
| 30 | 41 | ||
| 31 | #endif /* __LINUX_SERIAL_SCI_H */ | 42 | #endif /* __LINUX_SERIAL_SCI_H */ |
