11 files changed, 160 insertions, 21 deletions

diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index fc8b223bad4f..f3b48f841d84 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -64,6 +64,9 @@
 
 #define S3C64XX_PA_USBHOST      (0x74300000)
 
+#define S3C64XX_PA_USB_HSPHY    (0x7C100000)
+#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
+
 /* place VICs close together */
 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x00)
 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
@@ -79,5 +82,6 @@
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
+#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
 
 #endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
index b42bdd0f2138..d876ee503671 100644
--- a/arch/arm/mach-s3c6400/s3c6400.c
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -45,6 +45,7 @@ void __init s3c6400_map_io(void)
 
         s3c6400_default_sdhci0();
         s3c6400_default_sdhci1();
+        s3c6400_default_sdhci2();
 
         /* the i2c devices are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index 9b67c663d9d8..522c08691952 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -58,6 +58,7 @@ void __init s3c6410_map_io(void)
         /* initialise device information early */
         s3c6410_default_sdhci0();
         s3c6410_default_sdhci1();
+        s3c6410_default_sdhci2();
 
         /* the i2c devices are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 9f1a21462620..480d297c1de2 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -25,6 +25,7 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/smsc911x.h>
+#include <linux/regulator/fixed.h>
 
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -184,6 +185,43 @@ static struct platform_device smdk6410_smsc911x = {
         },
 };
 
+#ifdef CONFIG_REGULATOR
+static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
+        {
+                /* WM8580 */
+                .supply = "PVDD",
+                .dev_name = "0-001b",
+        },
+        {
+                /* WM8580 */
+                .supply = "AVDD",
+                .dev_name = "0-001b",
+        },
+};
+
+static struct regulator_init_data smdk6410_b_pwr_5v_data = {
+        .constraints = {
+                .always_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
+        .consumer_supplies = smdk6410_b_pwr_5v_consumers,
+};
+
+static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
+        .supply_name = "B_PWR_5V",
+        .microvolts = 5000000,
+        .init_data = &smdk6410_b_pwr_5v_data,
+};
+
+static struct platform_device smdk6410_b_pwr_5v = {
+        .name          = "reg-fixed-voltage",
+        .id            = -1,
+        .dev = {
+                .platform_data = &smdk6410_b_pwr_5v_pdata,
+        },
+};
+#endif
+
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -198,6 +236,10 @@ static struct platform_device *smdk6410_devices[] __initdata = {
         &s3c_device_fb,
         &s3c_device_usb,
         &s3c_device_usb_hsotg,
+
+#ifdef CONFIG_REGULATOR
+        &smdk6410_b_pwr_5v,
+#endif
         &smdk6410_lcd_powerdev,
 
         &smdk6410_smsc911x,
@@ -232,6 +274,14 @@ static struct regulator_init_data wm8350_dcdc3_data = {
 };
 
 /* USB, EXT, PCM, ADC/DAC, USB, MMC */
+static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
+        {
+                /* WM8580 */
+                .supply = "DVDD",
+                .dev_name = "0-001b",
+        },
+};
+
 static struct regulator_init_data wm8350_dcdc4_data = {
         .constraints = {
                 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
@@ -239,6 +289,8 @@ static struct regulator_init_data wm8350_dcdc4_data = {
                 .max_uV = 3000000,
                 .always_on = 1,
         },
+        .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
+        .consumer_supplies = wm8350_dcdc4_consumers,
 };
 
 /* ARM core */
diff --git a/arch/arm/plat-s3c/dev-hsmmc2.c b/arch/arm/plat-s3c/dev-hsmmc2.c
index 082e55a78ad7..824580bc0e06 100644
--- a/arch/arm/plat-s3c/dev-hsmmc2.c
+++ b/arch/arm/plat-s3c/dev-hsmmc2.c
@@ -1,6 +1,10 @@
 /* linux/arch/arm/plat-s3c/dev-hsmmc2.c
  *
  * Copyright (c) 2009 Samsung Electronics
+ * Copyright (c) 2009 Maurus Cuelenaere
+ *
+ * Based on arch/arm/plat-s3c/dev-hsmmc1.c
+ * original file Copyright (c) 2008 Simtec Electronics
  *
  * S3C series device definition for hsmmc device 2
  *
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
index c71d07861840..53198673b6bd 100644
--- a/arch/arm/plat-s3c/include/plat/sdhci.h
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -74,6 +74,7 @@ extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 
 /* S3C6400 SDHCI setup */
 
@@ -108,6 +109,17 @@ static inline void s3c6400_default_sdhci1(void)
 static inline void s3c6400_default_sdhci1(void) { }
 #endif /* CONFIG_S3C_DEV_HSMMC1 */
 
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s3c6400_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6400_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
+
 #else
 static inline void s3c6400_default_sdhci0(void) { }
 static inline void s3c6400_default_sdhci1(void) { }
@@ -145,6 +157,17 @@ static inline void s3c6410_default_sdhci1(void)
 static inline void s3c6410_default_sdhci1(void) { }
 #endif /* CONFIG_S3C_DEV_HSMMC1 */
 
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s3c6410_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s3c6410_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
+
 #else
 static inline void s3c6410_default_sdhci0(void) { }
 static inline void s3c6410_default_sdhci1(void) { }
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
index b1fdd83940a6..49796d2db86d 100644
--- a/arch/arm/plat-s3c64xx/cpu.c
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -107,6 +107,11 @@ static struct map_desc s3c_iodesc[] __initdata = {
                 .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
+                .length         = SZ_1K,
+                .type           = MT_DEVICE,
         },
 };
 
diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
index e6e0843215df..74c0e8347de5 100644
--- a/arch/arm/plat-s3c64xx/cpufreq.c
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -19,6 +19,7 @@
 
 static struct clk *armclk;
 static struct regulator *vddarm;
+static unsigned long regulator_latency;
 
 #ifdef CONFIG_CPU_S3C6410
 struct s3c64xx_dvfs {
@@ -27,11 +28,10 @@ struct s3c64xx_dvfs {
 };
 
 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
-        [0] = { 1000000, 1000000 },
-        [1] = { 1000000, 1050000 },
-        [2] = { 1050000, 1100000 },
-        [3] = { 1050000, 1150000 },
-        [4] = { 1250000, 1350000 },
+        [0] = { 1000000, 1150000 },
+        [1] = { 1050000, 1150000 },
+        [2] = { 1100000, 1150000 },
+        [3] = { 1200000, 1350000 },
 };
 
 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
@@ -41,9 +41,9 @@ static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
         { 1, 266000 },
         { 2, 333000 },
         { 2, 400000 },
-        { 3, 532000 },
-        { 3, 533000 },
-        { 4, 667000 },
+        { 2, 532000 },
+        { 2, 533000 },
+        { 3, 667000 },
         { 0, CPUFREQ_TABLE_END },
 };
 #endif
@@ -141,7 +141,7 @@ err:
 }
 
 #ifdef CONFIG_REGULATOR
-static void __init s3c64xx_cpufreq_constrain_voltages(void)
+static void __init s3c64xx_cpufreq_config_regulator(void)
 {
         int count, v, i, found;
         struct cpufreq_frequency_table *freq;
@@ -150,11 +150,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
         count = regulator_count_voltages(vddarm);
         if (count < 0) {
                 pr_err("cpufreq: Unable to check supported voltages\n");
-                return;
         }
 
         freq = s3c64xx_freq_table;
-        while (freq->frequency != CPUFREQ_TABLE_END) {
+        while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
                 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
                         continue;
 
@@ -175,6 +174,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
 
                 freq++;
         }
+
+        /* Guess based on having to do an I2C/SPI write; in future we
+         * will be able to query the regulator performance here. */
+        regulator_latency = 1 * 1000 * 1000;
 }
 #endif
 
@@ -206,7 +209,7 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
                 pr_err("cpufreq: Only frequency scaling available\n");
                 vddarm = NULL;
         } else {
-                s3c64xx_cpufreq_constrain_voltages();
+                s3c64xx_cpufreq_config_regulator();
         }
 #endif
 
@@ -217,8 +220,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
                 /* Check for frequencies we can generate */
                 r = clk_round_rate(armclk, freq->frequency * 1000);
                 r /= 1000;
-                if (r != freq->frequency)
+                if (r != freq->frequency) {
+                        pr_debug("cpufreq: %dkHz unsupported by clock\n",
+                                 freq->frequency);
                         freq->frequency = CPUFREQ_ENTRY_INVALID;
+                }
 
                 /* If we have no regulator then assume startup
                  * frequency is the maximum we can support. */
@@ -230,9 +236,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 
         policy->cur = clk_get_rate(armclk) / 1000;
 
-        /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI
-         * write plus clock reprogramming. */
-        policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
+        /* Datasheet says PLL stabalisation time (if we were to use
+         * the PLLs, which we don't currently) is ~300us worst case,
+         * but add some fudge.
+         */
+        policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
 
         ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
         if (ret != 0) {
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index 92859290ea33..778560457277 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -213,6 +213,11 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
         .get_pull       = s3c_gpio_getpull_updown,
 };
 
+int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
+{
+        return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
+}
+
 static struct s3c_gpio_chip gpio_4bit[] = {
         {
                 .base   = S3C64XX_GPA_BASE,
@@ -269,10 +274,16 @@ static struct s3c_gpio_chip gpio_4bit[] = {
                         .base   = S3C64XX_GPM(0),
                         .ngpio  = S3C64XX_GPIO_M_NR,
                         .label  = "GPM",
+                        .to_irq = s3c64xx_gpio2int_gpm,
                 },
         },
 };
 
+int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
+{
+        return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
+}
+
 static struct s3c_gpio_chip gpio_4bit2[] = {
         {
                 .base   = S3C64XX_GPH_BASE + 0x4,
@@ -297,6 +308,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = {
                         .base   = S3C64XX_GPL(0),
                         .ngpio  = S3C64XX_GPIO_L_NR,
                         .label  = "GPL",
+                        .to_irq = s3c64xx_gpio2int_gpl,
                 },
         },
 };
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index f81b7b818ba0..ebdf183a0911 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -65,7 +65,7 @@ static void s3c_irq_eint_maskack(unsigned int irq)
 static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 {
         int offs = eint_offset(irq);
-        int pin;
+        int pin, pin_val;
         int shift;
         u32 ctrl, mask;
         u32 newvalue = 0;
@@ -109,7 +109,10 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
                 return -1;
         }
 
-        shift = (offs / 2) * 4;
+        if (offs <= 15)
+                shift = (offs / 2) * 4;
+        else
+                shift = ((offs - 16) / 2) * 4;
         mask = 0x7 << shift;
 
         ctrl = __raw_readl(reg);
@@ -119,12 +122,18 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 
         /* set the GPIO pin appropriately */
 
-        if (offs < 23)
+        if (offs < 16) {
                 pin = S3C64XX_GPN(offs);
-        else
+                pin_val = S3C_GPIO_SFN(2);
+        } else if (offs < 23) {
+                pin = S3C64XX_GPL(offs + 8 - 16);
+                pin_val = S3C_GPIO_SFN(3);
+        } else {
                 pin = S3C64XX_GPM(offs - 23);
+                pin_val = S3C_GPIO_SFN(3);
+        }
 
-        s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
+        s3c_gpio_cfgpin(pin, pin_val);
 
         return 0;
 }
diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
index 5417123b0ac1..a58c0cc7ba5e 100644
--- a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
@@ -53,3 +53,23 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
         s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
         s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
 }
+
+void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+
+        end = S3C64XX_GPH(6 + width);
+
+        /* Set all the necessary GPH pins to special-function 1 */
+        for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        /* Set all the necessary GPC pins to special-function 1 */
+        for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+}