206 files changed, 18954 insertions, 1886 deletions

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 1e097037349c..5da38c5ed476 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,9 @@ Optional Properties:
         - pclkN, clkN: Pairs of parent of input clock and input clock to the
                 devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
                 are supported currently.
+        - asbN: Clocks required by asynchronous bridges (ASB) present in
+                the power domain. These clock should be enabled during power
+                domain on/off operations.
 - power-domains: phandle pointing to the parent power domain, for more details
                  see Documentation/devicetree/bindings/power/power_domain.txt
 
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 1e0d21201d3a..2da059a4790c 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -18,6 +18,8 @@ Main node required properties:
         "arm,arm11mp-gic"
         "brcm,brahma-b15-gic"
         "arm,arm1176jzf-devchip-gic"
+        "qcom,msm-8660-qgic"
+        "qcom,msm-qgic2"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.
diff --git a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
index 925ecbf6e7b7..4f40ff3fee4b 100644
--- a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
@@ -42,6 +42,7 @@ board. Currently known boards are:
 "lacie,cloudbox"
 "lacie,inetspace_v2"
 "lacie,laplug"
+"lacie,nas2big"
 "lacie,netspace_lite_v2"
 "lacie,netspace_max_v2"
 "lacie,netspace_mini_v2"
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
new file mode 100644
index 000000000000..06df04cc827a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
@@ -0,0 +1,84 @@
+QCOM Idle States for cpuidle driver
+
+ARM provides idle-state node to define the cpuidle states, as defined in [1].
+cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
+states. Idle states have different enter/exit latency and residency values.
+The idle states supported by the QCOM SoC are defined as -
+
+    * Standby
+    * Retention
+    * Standalone Power Collapse (Standalone PC or SPC)
+    * Power Collapse (PC)
+
+Standby: Standby does a little more in addition to architectural clock gating.
+When the WFI instruction is executed the ARM core would gate its internal
+clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
+trigger to execute the SPM state machine. The SPM state machine waits for the
+interrupt to trigger the core back in to active. This triggers the cache
+hierarchy to enter standby states, when all cpus are idle. An interrupt brings
+the SPM state machine out of its wait, the next step is to ensure that the
+cache hierarchy is also out of standby, and then the cpu is allowed to resume
+execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
+driver and is not defined in the DT. The SPM state machine should be
+configured to execute this state by default and after executing every other
+state below.
+
+Retention: Retention is a low power state where the core is clock gated and
+the memory and the registers associated with the core are retained. The
+voltage may be reduced to the minimum value needed to keep the processor
+registers active. The SPM should be configured to execute the retention
+sequence and would wait for interrupt, before restoring the cpu to execution
+state. Retention may have a slightly higher latency than Standby.
+
+Standalone PC: A cpu can power down and warmboot if there is a sufficient time
+between the time it enters idle and the next known wake up. SPC mode is used
+to indicate a core entering a power down state without consulting any other
+cpu or the system resources. This helps save power only on that core.  The SPM
+sequence for this idle state is programmed to power down the supply to the
+core, wait for the interrupt, restore power to the core, and ensure the
+system state including cache hierarchy is ready before allowing core to
+resume. Applying power and resetting the core causes the core to warmboot
+back into Elevation Level (EL) which trampolines the control back to the
+kernel. Entering a power down state for the cpu, needs to be done by trapping
+into a EL. Failing to do so, would result in a crash enforced by the warm boot
+code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
+be flushed in s/w, before powering down the core.
+
+Power Collapse: This state is similar to the SPC mode, but distinguishes
+itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
+modes. In a hierarchical power domain SoC, this means L2 and other caches can
+be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
+voltages reduced, provided all cpus enter this state.  Since the span of low
+power modes possible at this state is vast, the exit latency and the residency
+of this low power mode would be considered high even though at a cpu level,
+this essentially is cpu power down. The SPM in this state also may handshake
+with the Resource power manager (RPM) processor in the SoC to indicate a
+complete application processor subsystem shut down.
+
+The idle-state for QCOM SoCs are distinguished by the compatible property of
+the idle-states device node.
+
+The devicetree representation of the idle state should be -
+
+Required properties:
+
+- compatible: Must be one of -
+                        "qcom,idle-state-ret",
+                        "qcom,idle-state-spc",
+                        "qcom,idle-state-pc",
+                and "arm,idle-state".
+
+Other required and optional properties are specified in [1].
+
+Example:
+
+        idle-states {
+                CPU_SPC: spc {
+                        compatible = "qcom,idle-state-spc", "arm,idle-state";
+                        entry-latency-us = <150>;
+                        exit-latency-us = <200>;
+                        min-residency-us = <2000>;
+                };
+        };
+
+[1]. Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
index 1505fb8e131a..ae4afc6dcfe0 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -2,22 +2,31 @@ SPM AVS Wrapper 2 (SAW2)
 
 The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
 Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
-micro-controller that transitions a piece of hardware (like a processor or
+power-controller that transitions a piece of hardware (like a processor or
 subsystem) into and out of low power modes via a direct connection to
 the PMIC. It can also be wired up to interact with other processors in the
 system, notifying them when a low power state is entered or exited.
 
+Multiple revisions of the SAW hardware are supported using these Device Nodes.
+SAW2 revisions differ in the register offset and configuration data. Also, the
+same revision of the SAW in different SoCs may have different configuration
+data due the the differences in hardware capabilities. Hence the SoC name, the
+version of the SAW hardware in that SoC and the distinction between cpu (big
+or Little) or cache, may be needed to uniquely identify the SAW register
+configuration and initialization data. The compatible string is used to
+indicate this parameter.
+
 PROPERTIES
 
 - compatible:
         Usage: required
         Value type: <string>
-        Definition: shall contain "qcom,saw2". A more specific value should be
-                    one of:
-                         "qcom,saw2-v1"
-                         "qcom,saw2-v1.1"
-                         "qcom,saw2-v2"
-                         "qcom,saw2-v2.1"
+        Definition: Must have
+                        "qcom,saw2"
+                    A more specific value could be one of:
+                        "qcom,apq8064-saw2-v1.1-cpu"
+                        "qcom,msm8974-saw2-v2.1-cpu"
+                        "qcom,apq8084-saw2-v2.1-cpu"
 
 - reg:
         Usage: required
@@ -26,10 +35,23 @@ PROPERTIES
                     the register region. An optional second element specifies
                     the base address and size of the alias register region.
 
+- regulator:
+        Usage: optional
+        Value type: boolean
+        Definition: Indicates that this SPM device acts as a regulator device
+                        device for the core (CPU or Cache) the SPM is attached
+                        to.
 
-Example:
+Example 1:
 
-        regulator@2099000 {
+        power-controller@2099000 {
                 compatible = "qcom,saw2";
                 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+                regulator;
+        };
+
+Example 2:
+        saw0: power-controller@f9089000 {
+                compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
         };
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 6809e4e51ed2..60d4a1e0a9b5 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -22,3 +22,7 @@ Rockchip platforms device tree bindings
       - compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
     or
       - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";
+
+- ChipSPARK PopMetal-RK3288 board:
+    Required root node properties:
+      - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt
new file mode 100644
index 000000000000..ea670a5d7ee3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt
@@ -0,0 +1,32 @@
+NVIDIA Tegra Activity Monitor
+
+The activity monitor block collects statistics about the behaviour of other
+components in the system. This information can be used to derive the rate at
+which the external memory needs to be clocked in order to serve all requests
+from the monitored clients.
+
+Required properties:
+- compatible: should be "nvidia,tegra<chip>-actmon"
+- reg: offset and length of the register set for the device
+- interrupts: standard interrupt property
+- clocks: Must contain a phandle and clock specifier pair for each entry in
+clock-names. See ../../clock/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - actmon
+  - emc
+- resets: Must contain an entry for each entry in reset-names. See
+../../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - actmon
+
+Example:
+        actmon@6000c800 {
+                compatible = "nvidia,tegra124-actmon";
+                reg = <0x0 0x6000c800 0x0 0x400>;
+                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
+                         <&tegra_car TEGRA124_CLK_EMC>;
+                clock-names = "actmon", "emc";
+                resets = <&tegra_car 119>;
+                reset-names = "actmon";
+        };
diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.txt b/Documentation/devicetree/bindings/media/ti,omap3isp.txt
new file mode 100644
index 000000000000..ac23de855641
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/ti,omap3isp.txt
@@ -0,0 +1,71 @@
+OMAP 3 ISP Device Tree bindings
+===============================
+
+The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
+
+Required properties
+===================
+
+compatible      : must contain "ti,omap3-isp"
+
+reg             : the two registers sets (physical address and length) for the
+                  ISP. The first set contains the core ISP registers up to
+                  the end of the SBL block. The second set contains the
+                  CSI PHYs and receivers registers.
+interrupts      : the ISP interrupt specifier
+iommus          : phandle and IOMMU specifier for the IOMMU that serves the ISP
+syscon          : the phandle and register offset to the Complex I/O or CSI-PHY
+                  register
+ti,phy-type     : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
+                  1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
+#clock-cells    : Must be 1 --- the ISP provides two external clocks,
+                  cam_xclka and cam_xclkb, at indices 0 and 1,
+                  respectively. Please find more information on common
+                  clock bindings in ../clock/clock-bindings.txt.
+
+Port nodes (optional)
+---------------------
+
+More documentation on these bindings is available in
+video-interfaces.txt in the same directory.
+
+reg             : The interface:
+                  0 - parallel (CCDC)
+                  1 - CSIPHY1 -- CSI2C / CCP2B on 3630;
+                      CSI1 -- CSIb on 3430
+                  2 - CSIPHY2 -- CSI2A / CCP2B on 3630;
+                      CSI2 -- CSIa on 3430
+
+Optional properties
+===================
+
+vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
+vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
+
+Endpoint nodes
+--------------
+
+lane-polarities : lane polarity (required on CSI-2)
+                  0 -- not inverted; 1 -- inverted
+data-lanes      : an array of data lanes from 1 to 3. The length can
+                  be either 1 or 2. (required on CSI-2)
+clock-lanes     : the clock lane (from 1 to 3). (required on CSI-2)
+
+
+Example
+=======
+
+                isp@480bc000 {
+                        compatible = "ti,omap3-isp";
+                        reg = <0x480bc000 0x12fc
+                               0x480bd800 0x0600>;
+                        interrupts = <24>;
+                        iommus = <&mmu_isp>;
+                        syscon = <&scm_conf 0x2f0>;
+                        ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+                        #clock-cells = <1>;
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
new file mode 100644
index 000000000000..e90519d566a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
@@ -0,0 +1,22 @@
+QCOM Top Control and Status Register
+
+Qualcomm devices have a set of registers that provide various control and status
+functions for their peripherals.  This node is intended to allow access to these
+registers via syscon.
+
+Required properties:
+- compatible:   Should contain:
+                "qcom,tcsr-ipq8064", "syscon" for IPQ8064
+                "qcom,tcsr-apq8064", "syscon" for APQ8064
+                "qcom,tcsr-msm8660", "syscon" for MSM8660
+                "qcom,tcsr-msm8960", "syscon" for MSM8960
+                "qcom,tcsr-msm8974", "syscon" for MSM8974
+                "qcom,tcsr-apq8084", "syscon" for APQ8084
+                "qcom,tcsr-msm8916", "syscon" for MSM8916
+- reg: Address range for TCSR registers
+
+Example:
+        tcsr: syscon@1a400000 {
+                compatible = "qcom,tcsr-msm8960", "syscon";
+                reg = <0x1a400000 0x100>;
+        };
diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt
new file mode 100644
index 000000000000..2a3d90de18ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt
@@ -0,0 +1,47 @@
+TI Wilink 6/7/8 (wl12xx/wl18xx) SDIO devices
+
+This node provides properties for controlling the wilink wireless device. The
+node is expected to be specified as a child node to the SDIO controller that
+connects the device to the system.
+
+Required properties:
+ - compatible: should be one of the following:
+    * "ti,wl1271"
+    * "ti,wl1273"
+    * "ti,wl1281"
+    * "ti,wl1283"
+    * "ti,wl1801"
+    * "ti,wl1805"
+    * "ti,wl1807"
+    * "ti,wl1831"
+    * "ti,wl1835"
+    * "ti,wl1837"
+ - interrupts : specifies attributes for the out-of-band interrupt.
+
+Optional properties:
+ - interrupt-parent : the phandle for the interrupt controller to which the
+        device interrupts are connected.
+ - ref-clock-frequency : ref clock frequency in Hz
+ - tcxo-clock-frequency : tcxo clock frequency in Hz
+
+Note: the *-clock-frequency properties assume internal clocks. In case of external
+clock, new bindings (for parsing the clock nodes) have to be added.
+
+Example:
+
+&mmc3 {
+        status = "okay";
+        vmmc-supply = <&wlan_en_reg>;
+        bus-width = <4>;
+        cap-power-off-card;
+        keep-power-in-suspend;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1835";
+                reg = <2>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt
index 342eedd10050..54c2a155c783 100644
--- a/Documentation/devicetree/bindings/serial/omap_serial.txt
+++ b/Documentation/devicetree/bindings/serial/omap_serial.txt
@@ -4,7 +4,27 @@ Required properties:
 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- reg : address and length of the register space
+- interrupts or interrupts-extended : Should contain the uart interrupt
+                                      specifier or both the interrupt
+                                      controller phandle and interrupt
+                                      specifier.
 - ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
 
 Optional properties:
 - clock-frequency : frequency of the clock input to the UART
+- dmas : DMA specifier, consisting of a phandle to the DMA controller
+         node and a DMA channel number.
+- dma-names : "rx" for receive channel, "tx" for transmit channel.
+
+Example:
+
+                uart4: serial@49042000 {
+                        compatible = "ti,omap3-uart";
+                        reg = <0x49042000 0x400>;
+                        interrupts = <80>;
+                        dmas = <&sdma 81 &sdma 82>;
+                        dma-names = "tx", "rx";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
new file mode 100644
index 000000000000..ddeb5b6a53c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
@@ -0,0 +1,58 @@
+MediaTek PMIC Wrapper Driver
+
+This document describes the binding for the MediaTek PMIC wrapper.
+
+On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface
+is not directly visible to the CPU, but only through the PMIC wrapper
+inside the SoC. The communication between the SoC and the PMIC can
+optionally be encrypted. Also a non standard Dual IO SPI mode can be
+used to increase speed.
+
+IP Pairing
+
+on MT8135 the pins of some SoC internal peripherals can be on the PMIC.
+The signals of these pins are routed over the SPI bus using the pwrap
+bridge. In the binding description below the properties needed for bridging
+are marked with "IP Pairing". These are optional on SoCs which do not support
+IP Pairing
+
+Required properties in pwrap device node.
+- compatible:
+        "mediatek,mt8135-pwrap" for MT8135 SoCs
+        "mediatek,mt8173-pwrap" for MT8173 SoCs
+- interrupts: IRQ for pwrap in SOC
+- reg-names: Must include the following entries:
+  "pwrap": Main registers base
+  "pwrap-bridge": bridge base (IP Pairing)
+- reg: Must contain an entry for each entry in reg-names.
+- reset-names: Must include the following entries:
+  "pwrap"
+  "pwrap-bridge" (IP Pairing)
+- resets: Must contain an entry for each entry in reset-names.
+- clock-names: Must include the following entries:
+  "spi": SPI bus clock
+  "wrap": Main module clock
+- clocks: Must contain an entry for each entry in clock-names.
+
+Optional properities:
+- pmic: Mediatek PMIC MFD is the child device of pwrap
+  See the following for child node definitions:
+  Documentation/devicetree/bindings/mfd/mt6397.txt
+
+Example:
+        pwrap: pwrap@1000f000 {
+                compatible = "mediatek,mt8135-pwrap";
+                reg = <0 0x1000f000 0 0x1000>,
+                        <0 0x11017000 0 0x1000>;
+                reg-names = "pwrap", "pwrap-bridge";
+                interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+                resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
+                                <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+                reset-names = "pwrap", "pwrap-bridge";
+                clocks = <&clk26m>, <&clk26m>;
+                clock-names = "spi", "wrap";
+
+                pmic {
+                        compatible = "mediatek,mt6397";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
index 1ab6bc8404d5..f6a715e4ef43 100644
--- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt
+++ b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
@@ -4,9 +4,9 @@ Required properties:
 - compatible: "ti,omap-twl4030"
 - ti,model: Name of the sound card (for example "omap3beagle")
 - ti,mcbsp: phandle for the McBSP node
-- ti,codec: phandle for the twl4030 audio node
 
 Optional properties:
+- ti,codec: phandle for the twl4030 audio node
 - ti,mcbsp-voice: phandle for the McBSP node connected to the voice port of twl
 - ti, jack-det-gpio: Jack detect GPIO
 - ti,audio-routing: List of connections between audio components.
@@ -59,5 +59,4 @@ sound {
         ti,model = "omap3beagle";
 
         ti,mcbsp = <&mcbsp2>;
-        ti,codec = <&twl_audio>;
 };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 54c1d5790358..83737a3403d7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -84,6 +84,7 @@ globalscale	Globalscale Technologies, Inc.
 gmt     Global Mixed-mode Technology, Inc.
 goodix  Shenzhen Huiding Technology Co., Ltd.
 google  Google, Inc.
+grinn   Grinn
 gumstix Gumstix, Inc.
 gw      Gateworks Corporation
 hannstar        HannStar Display Corporation
diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
index f059dd0b3d28..ecb8da063d07 100644
--- a/Documentation/devicetree/bindings/video/atmel,lcdc.txt
+++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
@@ -10,7 +10,9 @@ Required properties:
         "atmel,at91sam9g45es-lcdc" ,
         "atmel,at91sam9rl-lcdc" ,
         "atmel,at32ap-lcdc"
-- reg : Should contain 1 register ranges(address and length)
+- reg : Should contain 1 register ranges(address and length).
+        Can contain an additional register range(address and length)
+        for fixed framebuffer memory. Useful for dedicated memories.
 - interrupts : framebuffer controller interrupt
 - display: a phandle pointing to the display node
 
@@ -38,6 +40,14 @@ Example:
 
         };
 
+Example for fixed framebuffer memory:
+
+        fb0: fb@0x00500000 {
+                compatible = "atmel,at91sam9263-lcdc";
+                reg = <0x00700000 0x1000 0x70000000 0x200000>;
+                [...]
+        };
+
 Atmel LCDC Display
 -----------------------------------------------------
 Required properties (as per of_videomode_helper):
diff --git a/MAINTAINERS b/MAINTAINERS
index e85dbd350c0c..fadb73c40e28 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7132,6 +7132,7 @@ OMAP IMAGING SUBSYSTEM (OMAP3 ISP and OMAP4 ISS)
 M:      Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 L:      linux-media@vger.kernel.org
 S:      Maintained
+F:      Documentation/devicetree/bindings/media/ti,omap3isp.txt
 F:      drivers/media/platform/omap3isp/
 F:      drivers/staging/media/omap4iss/
 
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b8dcec..d0c219dfa0a7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,5 +1,7 @@
 ifeq ($(CONFIG_OF),y)
 
+dtb-$(CONFIG_ARCH_ALPINE) += \
+        alpine-db.dtb
 dtb-$(CONFIG_MACH_ASM9260) += \
         alphascale-asm9260-devkit.dtb
 # Keep at91 dtb files sorted alphabetically for each SoC
@@ -42,6 +44,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
         sama5d34ek.dtb \
         sama5d35ek.dtb \
         sama5d36ek.dtb \
+        at91-sama5d4_xplained.dtb \
         at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += \
         atlas6-evb.dtb
@@ -59,13 +62,15 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
         bcm4708-netgear-r6300-v2.dtb \
         bcm47081-asus-rt-n18u.dtb \
         bcm47081-buffalo-wzr-600dhp2.dtb \
-        bcm47081-buffalo-wzr-900dhp.dtb
+        bcm47081-buffalo-wzr-900dhp.dtb \
+        bcm4709-netgear-r8000.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += \
         bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
         bcm911360_entphn.dtb \
         bcm911360k.dtb \
-        bcm958300k.dtb
+        bcm958300k.dtb \
+        bcm958305k.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
         bcm28155-ap.dtb \
         bcm21664-garnet.dtb
@@ -165,6 +170,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
         kirkwood-lsxhl.dtb \
         kirkwood-mplcec4.dtb \
         kirkwood-mv88f6281gtw-ge.dtb \
+        kirkwood-nas2big.dtb \
         kirkwood-net2big.dtb \
         kirkwood-net5big.dtb \
         kirkwood-netgear_readynas_duo_v2.dtb \
@@ -199,6 +205,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \
         ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_MACH_MESON6) += \
         meson6-atv1200.dtb
+dtb-$(CONFIG_MACH_MESON8) += \
+        meson8-minix-neo-x8.dtb
 dtb-$(CONFIG_ARCH_MMP) += \
         pxa168-aspenite.dtb \
         pxa910-dkb.dtb \
@@ -386,6 +394,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
         omap3-overo-storm-tobi.dtb \
         omap3-overo-summit.dtb \
         omap3-overo-tobi.dtb \
+        omap3-pandora-600mhz.dtb \
+        omap3-pandora-1ghz.dtb \
         omap3-sbc-t3517.dtb \
         omap3-sbc-t3530.dtb \
         omap3-sbc-t3730.dtb \
@@ -401,7 +411,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \
         am335x-evmsk.dtb \
         am335x-nano.dtb \
         am335x-pepper.dtb \
-        am335x-lxm.dtb
+        am335x-lxm.dtb \
+        am335x-chiliboard.dtb
 dtb-$(CONFIG_ARCH_OMAP4) += \
         omap4-duovero-parlor.dtb \
         omap4-panda.dtb \
@@ -577,6 +588,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
 dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
         tegra124-jetson-tk1.dtb \
         tegra124-nyan-big.dtb \
+        tegra124-nyan-blaze.dtb \
         tegra124-venice2.dtb
 dtb-$(CONFIG_ARCH_U300) += \
         ste-u300.dtb
@@ -624,11 +636,14 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
         armada-388-db.dtb \
         armada-388-gp.dtb \
         armada-388-rd.dtb
+dtb-$(CONFIG_MACH_ARMADA_39X) += \
+        armada-398-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_XP) += \
         armada-xp-axpwifiap.dtb \
         armada-xp-db.dtb \
         armada-xp-gp.dtb \
         armada-xp-lenovo-ix4-300d.dtb \
+        armada-xp-linksys-mamba.dtb \
         armada-xp-matrix.dtb \
         armada-xp-netgear-rn2120.dtb \
         armada-xp-openblocks-ax3-4.dtb \
diff --git a/arch/arm/boot/dts/alpine-db.dts b/arch/arm/boot/dts/alpine-db.dts
new file mode 100644
index 000000000000..dfb5a0802273
--- /dev/null
+++ b/arch/arm/boot/dts/alpine-db.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2015 Annapurna Labs Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * Alternatively, redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   *   Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *   *   Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/dts-v1/;
+
+#include "alpine.dtsi"
+
+/ {
+        model = "Annapurna Labs Alpine Dev Board";
+        /* no need for anything outside SOC */
+};
+
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
new file mode 100644
index 000000000000..9af2d60e9a7f
--- /dev/null
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2015 Annapurna Labs Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * Alternatively, redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   *   Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *   *   Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton64.dtsi"
+
+/ {
+        /* SOC compatibility */
+        compatible = "al,alpine";
+
+        /* CPU Configuration */
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "al,alpine-smp";
+
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <1>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <2>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <3>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+        };
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                arch-timer {
+                        compatible = "arm,cortex-a15-timer",
+                                     "arm,armv7-timer";
+                        interrupts =
+                                <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+
+                /* Interrupt Controller */
+                gic: gic@fb001000 {
+                        compatible = "arm,cortex-a15-gic";
+                        #interrupt-cells = <3>;
+                        #size-cells = <0>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x0 0xfb001000 0x0 0x1000>,
+                              <0x0 0xfb002000 0x0 0x2000>,
+                              <0x0 0xfb004000 0x0 0x1000>,
+                              <0x0 0xfb006000 0x0 0x2000>;
+                        interrupts =
+                                <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                };
+
+                /* CPU Resume registers */
+                cpu-resume@fbff5ec0 {
+                        compatible = "al,alpine-cpu-resume";
+                        reg = <0x0 0xfbff5ec0 0x0 0x30>;
+                };
+
+                /* North Bridge Service Registers */
+                sysfabric-service@fb070000 {
+                        compatible = "al,alpine-sysfabric-service", "syscon";
+                        reg = <0x0 0xfb070000 0x0 0x10000>;
+                };
+
+                /* Performance Monitor Unit */
+                pmu {
+                        compatible = "arm,cortex-a15-pmu";
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                uart0:uart@fd883000 {
+                        compatible = "ns16550a";
+                        reg = <0x0 0xfd883000 0x0 0x1000>;
+                        clock-frequency = <0>; /* Filled by loader */
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                uart1:uart@0xfd884000 {
+                        compatible = "ns16550a";
+                        reg = <0x0 0xfd884000 0x0 0x1000>;
+                        clock-frequency = <0>; /* Filled by loader */
+                        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                /* Internal PCIe Controller */
+                pcie-internal@0xfbc00000 {
+                        compatible = "pci-host-ecam-generic";
+                        device_type = "pci";
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        #interrupt-cells = <1>;
+                        reg = <0x0 0xfbc00000 0x0 0x100000>;
+                        interrupt-map-mask = <0xf800 0 0 7>;
+                        /* Add legacy interrupts for SATA devices only */
+                        interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
+                                        <0x4800 0 0 1 &gic 0 44 4>;
+
+                        /* 32 bit non prefetchable memory space */
+                        ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
+
+                        bus-range = <0x00 0x00>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts
new file mode 100644
index 000000000000..310da20a8aa7
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Author: Rostislav Lisovy <lisovy@jablotron.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "am335x-chilisom.dtsi"
+
+/ {
+        model = "AM335x Chiliboard";
+        compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
+                     "ti,am33xx";
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_gpio_pins>;
+
+                led0 {
+                        label = "led0";
+                        gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                        linux,default-trigger = "heartbeat";
+                };
+
+                led1 {
+                        label = "led1";
+                        gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                };
+        };
+};
+
+&am33xx_pinmux {
+        usb1_drvvbus: usb1_drvvbus {
+                pinctrl-single,pins = <
+                        0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
+                >;
+        };
+
+        sd_pins: pinmux_sd_card {
+                pinctrl-single,pins = <
+                        0xf0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+                        0xf4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+                        0xf8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+                        0xfc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+                        0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+                        0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+                        0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                >;
+        };
+
+        led_gpio_pins: led_gpio_pins {
+                pinctrl-single,pins = <
+                        0x1e4 (PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
+                        0x1e8 (PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
+                >;
+        };
+};
+
+&ldo4_reg {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+};
+
+/* Ethernet */
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "rmii";
+};
+
+&phy_sel {
+        rmii-clock-ext;
+};
+
+/* USB */
+&usb {
+        status = "okay";
+};
+
+&usb_ctrl_mod {
+        status = "okay";
+};
+
+&usb1_phy {
+        status = "okay";
+};
+
+&usb1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_drvvbus>;
+
+        status = "okay";
+        dr_mode = "host";
+};
+
+&cppi41dma  {
+        status = "okay";
+};
+
+/* microSD */
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd_pins>;
+        vmmc-supply = <&ldo4_reg>;
+        bus-width = <0x4>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi
new file mode 100644
index 000000000000..7e9a34dffe21
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-chilisom.dtsi
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Author: Rostislav Lisovy <lisovy@jablotron.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "am33xx.dtsi"
+
+/ {
+        model = "Grinn AM335x ChiliSOM";
+        compatible = "grinn,am335x-chilisom", "ti,am33xx";
+
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&dcdc2_reg>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+};
+
+&am33xx_pinmux {
+        pinctrl-names = "default";
+
+        i2c0_pins: pinmux_i2c0_pins {
+                pinctrl-single,pins = <
+                        0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                        0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                >;
+        };
+
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                        0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                >;
+        };
+
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
+                        0x110 (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxerr.rmii1_rxerr */
+                        0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
+                        0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+                        0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+                        0x13c (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd1.rmii1_rxd1 */
+                        0x140 (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd0.rmii1_rxd0 */
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_ref_clk.rmii_ref_clk */
+                >;
+        };
+
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 reset value */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* mdio_data.mdio_data */
+                        0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+                        /* mdio_clk.mdio_clk */
+                        0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                >;
+        };
+
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        /* MDIO reset value */
+                        0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        nandflash_pins: nandflash_pins {
+                pinctrl-single,pins = <
+                        0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
+                        0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
+                        0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
+                        0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
+                        0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
+                        0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
+                        0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
+                        0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
+
+                        0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                        0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_csn0.gpmc_csn0 */
+                        0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_advn_ale.gpmc_advn_ale */
+                        0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_oen_ren.gpmc_oen_ren */
+                        0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_wen.gpmc_wen */
+                        0x9c (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_be0n_cle.gpmc_be0n_cle */
+                >;
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+
+        status = "okay";
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tps: tps@24 {
+                reg = <0x24>;
+        };
+
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+        regulators {
+                dcdc1_reg: regulator@0 {
+                        regulator-name = "vdds_dpr";
+                        regulator-always-on;
+                };
+
+                dcdc2_reg: regulator@1 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1325000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                dcdc3_reg: regulator@2 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo1_reg: regulator@3 {
+                        regulator-name = "vio,vrtc,vdds";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo2_reg: regulator@4 {
+                        regulator-name = "vdd_3v3aux";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo3_reg: regulator@5 {
+                        regulator-name = "vdd_1v8";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo4_reg: regulator@6 {
+                        regulator-name = "vdd_3v3d";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+        };
+};
+
+/* Ethernet MAC */
+&mac {
+        slaves = <1>;
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        status = "okay";
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
+};
+
+/* NAND Flash */
+&elm {
+        status = "okay";
+};
+
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nandflash_pins>;
+        ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
+        nand@0,0 {
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <8>;
+                gpmc,device-width = <1>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-on-ns = <0>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wait-on-read = "true";
+                gpmc,wait-on-write = "true";
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index df5fee6b6b4b..87fc7a35e802 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -15,6 +15,7 @@
 
 #include "am33xx.dtsi"
 #include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "TI AM335x EVM-SK";
@@ -647,6 +648,16 @@
         cap-power-off-card;
         pinctrl-names = "default";
         pinctrl-0 = <&mmc2_pins>;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 
 &mcasp1 {
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts
index a3466455b171..5ed4ca6eaf55 100644
--- a/arch/arm/boot/dts/am335x-nano.dts
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -213,7 +213,9 @@
         pinctrl-0 = <&i2c0_pins>;
 
         gpio@20 {
-                compatible = "mcp,mcp23017";
+                compatible = "microchip,mcp23017";
+                gpio-controller;
+                #gpio-cells = <2>;
                 reg = <0x20>;
         };
 
@@ -222,7 +224,7 @@
         };
 
         eeprom@53 {
-                compatible = "mcp,24c02";
+                compatible = "microchip,24c02";
                 reg = <0x53>;
                 pagesize = <8>;
         };
@@ -297,8 +299,8 @@
                 |            |-->0x004FFFFF-> Kernel end
                 |            |-->0x00500000-> File system start
                 |            |
-                |            |-->0x014FFFFF-> File system end
-                |            |-->0x01500000-> User data start
+                |            |-->0x01FFFFFF-> File system end
+                |            |-->0x02000000-> User data start
                 |            |
                 |            |-->0x03FFFFFF-> User data end
                 |            |-->0x04000000-> Data storage start
@@ -327,12 +329,12 @@
 
                 partition@4 {
                         label = "rootfs";
-                        reg = <0x00500000 0x01000000>; /* 16MB */
+                        reg = <0x00500000 0x01b00000>; /* 27MB */
                 };
 
                 partition@5 {
                         label = "user";
-                        reg = <0x01500000 0x02b00000>; /* 43MB */
+                        reg = <0x02000000 0x02000000>; /* 32MB */
                 };
 
                 partition@6 {
@@ -343,7 +345,7 @@
 };
 
 &mac {
-        dual_emac = <1>;
+        dual_emac;
         status = "okay";
 };
 
@@ -353,11 +355,13 @@
 
 &cpsw_emac0 {
         phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "mii";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
         phy_id = <&davinci_mdio>, <1>;
+        phy-mode = "mii";
         dual_emac_res_vlan = <2>;
 };
 
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index ebe4fa691860..1b7bda8c14b1 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -893,7 +893,7 @@
                 };
 
                 hdq: hdq@48347000 {
-                        compatible = "ti,am43xx-hdq";
+                        compatible = "ti,am4372-hdq";
                         reg = <0x48347000 0x1000>;
                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&func_12m_clk>;
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index 0198f5a62b96..378344271746 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -133,6 +133,20 @@
                 >;
         };
 
+        i2c2_pins_default: i2c2_pins_default {
+                pinctrl-single,pins = <
+                        0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
+                        0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
+                >;
+        };
+
+        i2c2_pins_sleep: i2c2_pins_sleep {
+                pinctrl-single,pins = <
+                        0x1e8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x1ec (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
         mmc1_pins_default: pinmux_mmc1_pins_default {
                 pinctrl-single,pins = <
                         0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
@@ -263,6 +277,14 @@
         };
 };
 
+&i2c2 {
+        status = "okay";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&i2c2_pins_default>;
+        pinctrl-1 = <&i2c2_pins_sleep>;
+        clock-frequency = <100000>;
+};
+
 &epwmss0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index e580f4ffbde0..15f198e4864d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -8,7 +8,6 @@
 /dts-v1/;
 
 #include "dra74x.dtsi"
-#include <dt-bindings/clk/ti-dra7-atl.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
@@ -550,6 +549,14 @@
         pinctrl-0 = <&usb1_pins>;
 };
 
+&omap_dwc3_1 {
+        extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+        extcon = <&extcon_usb2>;
+};
+
 &usb2 {
         dr_mode = "peripheral";
 };
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e993c46bd472..19f3bf271915 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -45,6 +45,15 @@
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
  */
 
 /dts-v1/;
@@ -55,7 +64,7 @@
         compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
@@ -64,7 +73,7 @@
         };
 
         soc {
-                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
                           MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
 
                 internal-regs {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index b10ceb488efe..0f40d5da28c3 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -51,7 +51,7 @@
         compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 3f8cc3845a5e..a31207860f34 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -53,7 +53,7 @@
         compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 99eb8a014ac6..00540f292979 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -53,7 +53,7 @@
         compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 6ae36a38beb2..19475e68b8e9 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -64,7 +64,7 @@
         compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
index 59f74e66963f..b42b767763aa 100644
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -67,8 +67,7 @@
                      "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
-                stdout-path = &uart0;
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 8a322ad57e5f..ec96f0b36346 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -59,8 +59,8 @@
         compatible = "marvell,armada-370-xp";
 
         aliases {
-                eth0 = &eth0;
-                eth1 = &eth1;
+                serial0 = &uart0;
+                serial1 = &uart1;
         };
 
         cpus {
@@ -73,6 +73,11 @@
                 };
         };
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts-extended = <&mpic 3>;
+        };
+
         soc {
                 #address-cells = <2>;
                 #size-cells = <1>;
@@ -223,7 +228,7 @@
                                       <0x20250 0x8>;
                         };
 
-                        mpic: interrupt-controller@20000 {
+                        mpic: interrupt-controller@20a00 {
                                 compatible = "marvell,mpic";
                                 #interrupt-cells = <1>;
                                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 27397f151def..00b50db57c9c 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -129,6 +129,7 @@
                                 compatible = "marvell,aurora-outer-cache";
                                 reg = <0x08000 0x1000>;
                                 cache-id-part = <0x100>;
+                                cache-level = <2>;
                                 cache-unified;
                                 wt-override;
                         };
@@ -232,7 +233,7 @@
                                 reg = <0x18330 0x4>;
                         };
 
-                        interrupt-controller@20000 {
+                        interrupt-controller@20a00 {
                                 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
                         };
 
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 0440891425c0..4eabc9c21f8d 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -55,7 +55,7 @@
         compatible = "marvell,a375-db", "marvell,armada375";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index ba3c57e0af72..c675257f2377 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -60,8 +60,8 @@
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
                 gpio2 = &gpio2;
-                ethernet0 = &eth0;
-                ethernet1 = &eth1;
+                serial0 = &uart0;
+                serial1 = &uart1;
         };
 
         clocks {
@@ -96,6 +96,11 @@
                 };
         };
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts-extended = <&mpic 3>;
+        };
+
         soc {
                 compatible = "marvell,armada375-mbus", "simple-bus";
                 #address-cells = <2>;
@@ -276,7 +281,7 @@
                                 status = "disabled";
                         };
 
-                        serial@12000 {
+                        uart0: serial@12000 {
                                 compatible = "snps,dw-apb-uart";
                                 reg = <0x12000 0x100>;
                                 reg-shift = <2>;
@@ -286,7 +291,7 @@
                                 status = "disabled";
                         };
 
-                        serial@12100 {
+                        uart1: serial@12100 {
                                 compatible = "snps,dw-apb-uart";
                                 reg = <0x12100 0x100>;
                                 reg-shift = <2>;
@@ -394,7 +399,7 @@
                                 reg = <0x20000 0x100>, <0x20180 0x20>;
                         };
 
-                        mpic: interrupt-controller@20000 {
+                        mpic: interrupt-controller@20a00 {
                                 compatible = "marvell,mpic";
                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                                 #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
index 57b9119fb3e0..7219ac3a3d90 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -49,8 +49,7 @@
         compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
 
         chosen {
-                bootargs = "console=ttyS0,115200";
-                stdout-path = &uart1;
+                stdout-path = "serial1:115200n8";
         };
 
         memory {
@@ -126,6 +125,13 @@
                                 status = "okay";
                         };
 
+                        pinctrl@18000 {
+                                xhci0_vbus_pins: xhci0-vbus-pins {
+                                        marvell,pins = "mpp44";
+                                        marvell,function = "gpio";
+                                };
+                        };
+
                         ethernet@30000 {
                                 status = "okay";
                                 phy = <&phy2>;
@@ -150,6 +156,24 @@
                                 phy = <&phy0>;
                                 phy-mode = "rgmii-id";
                         };
+
+                        nfc: flash@d0000 {
+                                status = "okay";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                num-cs = <1>;
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                        };
+
+                        usb3@f0000 {
+                                status = "okay";
+                                usb-phy = <&usb3_phy>;
+                        };
                 };
 
                 pcie-controller {
@@ -175,4 +199,20 @@
                         };
                 };
         };
+
+        usb3_phy: usb3_phy {
+                compatible = "usb-nop-xceiv";
+                vcc-supply = <&reg_xhci0_vbus>;
+        };
+
+        reg_xhci0_vbus: xhci0-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&xhci0_vbus_pins>;
+                regulator-name = "xhci0-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+        };
 };
diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index 16512efcd32c..51d1623de53e 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -54,7 +54,7 @@
                 "marvell,armada385", "marvell,armada380";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
@@ -99,7 +99,7 @@
                                 phy-mode = "rgmii-id";
                         };
 
-                        usb@50000 {
+                        usb@58000 {
                                 status = "ok";
                         };
 
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 590b383db323..78514ab0b47a 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -48,8 +48,7 @@
         compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
 
         chosen {
-                bootargs = "console=ttyS0,115200";
-                stdout-path = &uart0;
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
@@ -135,7 +134,7 @@
                         };
 
                         /* CON4 */
-                        usb@50000 {
+                        usb@58000 {
                                 vcc-supply = <&reg_usb2_0_vbus>;
                                 status = "okay";
                         };
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index d99baac72081..1dc6e2341cc2 100644
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -55,7 +55,7 @@
                 "marvell,armada385","marvell,armada380";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
@@ -85,6 +85,16 @@
                                 clock-frequency = <100000>;
                         };
 
+                        sdhci@d8000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&sdhci_pins>;
+                                broken-cd;
+                                no-1-8-v;
+                                wp-inverted;
+                                bus-width = <8>;
+                                status = "okay";
+                        };
+
                         serial@12000 {
                                 status = "okay";
                         };
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 1dff30a81e24..ed2dd8ba4080 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -59,9 +59,13 @@
         aliases {
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
-                ethernet0 = &eth0;
-                ethernet1 = &eth1;
-                ethernet2 = &eth2;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts-extended = <&mpic 3>;
         };
 
         soc {
@@ -216,7 +220,7 @@
                                 status = "disabled";
                         };
 
-                        serial@12100 {
+                        uart1: serial@12100 {
                                 compatible = "snps,dw-apb-uart";
                                 reg = <0x12100 0x100>;
                                 reg-shift = <2>;
@@ -368,7 +372,7 @@
                                 reg = <0x20000 0x100>, <0x20180 0x20>;
                         };
 
-                        mpic: interrupt-controller@20000 {
+                        mpic: interrupt-controller@20a00 {
                                 compatible = "marvell,mpic";
                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                                 #interrupt-cells = <1>;
@@ -435,7 +439,7 @@
                                 status = "disabled";
                         };
 
-                        usb@50000 {
+                        usb@58000 {
                                 compatible = "marvell,orion-ehci";
                                 reg = <0x58000 0x500>;
                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -548,8 +552,11 @@
 
                         sdhci@d8000 {
                                 compatible = "marvell,armada-380-sdhci";
-                                reg = <0xd8000 0x1000>, <0xdc000 0x100>;
-                                interrupts = <0 25 0x4>;
+                                reg-names = "sdhci", "mbus", "conf-sdio3";
+                                reg = <0xd8000 0x1000>,
+                                        <0xdc000 0x100>,
+                                        <0x18454 0x4>;
+                                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&gateclk 17>;
                                 mrvl,clk-delay-cycles = <0x1F>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi
new file mode 100644
index 000000000000..094e39c66039
--- /dev/null
+++ b/arch/arm/boot/dts/armada-390.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada 390 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-39x.dtsi"
+
+/ {
+        soc {
+                internal-regs {
+                        pinctrl@18000 {
+                                compatible = "marvell,mv88f6920-pinctrl";
+                                reg = <0x18000 0x20>;
+                        };
+                };
+};
diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
new file mode 100644
index 000000000000..bbf83756c43c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-398-db.dts
@@ -0,0 +1,153 @@
+/*
+ * Device Tree Include file for Marvell Armada 398 Development Board
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-398.dtsi"
+
+/ {
+        model = "Marvell Armada 398 Development Board";
+        compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>; /* 2 GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+                internal-regs {
+                        spi@10680 {
+                                status = "okay";
+                                pinctrl-0 = <&spi1_pins>;
+                                pinctrl-names = "default";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "n25q128a13";
+                                        reg = <0>;
+                                        spi-max-frequency = <108000000>;
+
+                                        partition@0 {
+                                                label = "U-Boot";
+                                                reg = <0 0x400000>;
+                                        };
+
+                                        partition@400000 {
+                                                label = "Filesystem";
+                                                reg = <0x400000 0x1000000>;
+                                        };
+                                };
+                        };
+
+                        i2c@11000 {
+                                pinctrl-0 = <&i2c0_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                clock-frequency = <100000>;
+                        };
+
+                        serial@12000 {
+                                pinctrl-0 = <&uart0_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                        };
+
+                        serial@12100 {
+                                pinctrl-0 = <&uart1_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                        };
+
+                        flash@d0000 {
+                                status = "okay";
+                                pinctrl-0 = <&nand_pins>;
+                                pinctrl-names = "default";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                                nand-ecc-strength = <8>;
+                                nand-ecc-step-size = <512>;
+
+                                partition@0 {
+                                        label = "U-Boot";
+                                        reg = <0 0x800000>;
+                                };
+                                partition@800000 {
+                                        label = "Linux";
+                                        reg = <0x800000 0x800000>;
+                                };
+                                partition@1000000 {
+                                        label = "Filesystem";
+                                        reg = <0x1000000 0x3f000000>;
+                                };
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+
+                        pcie@3,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi
new file mode 100644
index 000000000000..fdc25914e3a3
--- /dev/null
+++ b/arch/arm/boot/dts/armada-398.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Device Tree Include file for Marvell Armada 398 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-39x.dtsi"
+
+/ {
+        compatible = "marvell,armada398", "marvell,armada390";
+
+        soc {
+                internal-regs {
+                        pinctrl@18000 {
+                                compatible = "marvell,mv88f6928-pinctrl";
+                                reg = <0x18000 0x20>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
new file mode 100644
index 000000000000..0e85fc15ceda
--- /dev/null
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -0,0 +1,508 @@
+/*
+ * Device Tree Include file for Marvell Armada 39x family of SoCs.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+/ {
+        model = "Marvell Armada 39x family SoC";
+        compatible = "marvell,armada390";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "marvell,armada-390-smp";
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+
+        soc {
+                compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
+                             "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+                interrupt-parent = <&gic>;
+                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-io-aperture  = <0xe8000000 0x100000>;
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
+                };
+
+                internal-regs {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+                        L2: cache-controller@8000 {
+                                compatible = "arm,pl310-cache";
+                                reg = <0x8000 0x1000>;
+                                cache-unified;
+                                cache-level = <2>;
+                        };
+
+                        scu@c000 {
+                                compatible = "arm,cortex-a9-scu";
+                                reg = <0xc000 0x100>;
+                        };
+
+                        timer@c600 {
+                                compatible = "arm,cortex-a9-twd-timer";
+                                reg = <0xc600 0x20>;
+                                interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+                                clocks = <&coreclk 2>;
+                        };
+
+                        gic: interrupt-controller@d000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                #size-cells = <0>;
+                                interrupt-controller;
+                                reg = <0xd000 0x1000>,
+                                      <0xc100 0x100>;
+                        };
+
+                        spi0: spi@10600 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10600 0x50>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        spi1: spi@10680 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10680 0x50>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11000 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@11100 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11100 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@11200 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11200 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        i2c3: i2c@11300 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11300 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        uart0: serial@12000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12000 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        uart1: serial@12100 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12100 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        uart2: serial@12200 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12200 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        uart3: serial@12300 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12300 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        pinctrl@18000 {
+                                i2c0_pins: i2c0-pins {
+                                        marvell,pins = "mpp2", "mpp3";
+                                        marvell,function = "i2c0";
+                                };
+
+                                uart0_pins: uart0-pins {
+                                        marvell,pins = "mpp0", "mpp1";
+                                        marvell,function = "ua0";
+                                };
+
+                                uart1_pins: uart1-pins {
+                                        marvell,pins = "mpp19", "mpp20";
+                                        marvell,function = "ua1";
+                                };
+
+                                spi1_pins: spi1-pins {
+                                        marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
+                                        marvell,function = "spi1";
+                                };
+
+                                nand_pins: nand-pins {
+                                        marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
+                                                       "mpp38", "mpp28", "mpp40", "mpp42",
+                                                       "mpp35", "mpp36", "mpp25", "mpp30",
+                                                       "mpp32";
+                                        marvell,function = "dev";
+                                };
+                        };
+
+                        system-controller@18200 {
+                                compatible = "marvell,armada-390-system-controller",
+                                             "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x100>;
+                        };
+
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,armada-390-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
+                        };
+
+                        coreclk: mvebu-sar@18600 {
+                                compatible = "marvell,armada-390-core-clock";
+                                reg = <0x18600 0x04>;
+                                #clock-cells = <1>;
+                        };
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
+                        };
+
+                        mpic: interrupt-controller@20a00 {
+                                compatible = "marvell,mpic";
+                                reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+                                #interrupt-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                msi-controller;
+                                interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        timer@20300 {
+                                compatible = "marvell,armada-380-timer",
+                                             "marvell,armada-xp-timer";
+                                reg = <0x20300 0x30>, <0x21040 0x30>;
+                                interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&mpic 5>,
+                                                      <&mpic 6>;
+                                clocks = <&coreclk 2>, <&coreclk 5>;
+                                clock-names = "nbclk", "fixed";
+                        };
+
+                        cpurst@20800 {
+                                compatible = "marvell,armada-370-cpu-reset";
+                                reg = <0x20800 0x10>;
+                        };
+
+                        pmsu@22000 {
+                                compatible = "marvell,armada-390-pmsu",
+                                             "marvell,armada-380-pmsu";
+                                reg = <0x22000 0x1000>;
+                        };
+
+                        xor@60800 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60800 0x100
+                                       0x60a00 0x100>;
+                                clocks = <&gateclk 22>;
+                                status = "okay";
+
+                                xor00 {
+                                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor01 {
+                                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
+                        };
+
+                        xor@60900 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60900 0x100
+                                       0x60b00 0x100>;
+                                clocks = <&gateclk 28>;
+                                status = "okay";
+
+                                xor10 {
+                                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor11 {
+                                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
+                        };
+
+                        flash@d0000 {
+                                compatible = "marvell,armada370-nand";
+                                reg = <0xd0000 0x54>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coredivclk 0>;
+                                status = "disabled";
+                        };
+
+                        sdhci@d8000 {
+                                compatible = "marvell,armada-380-sdhci";
+                                reg = <0xd8000 0x1000>, <0xdc000 0x100>;
+                                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 17>;
+                                mrvl,clk-delay-cycles = <0x1F>;
+                                status = "disabled";
+                        };
+
+                        coredivclk: clock@e4250 {
+                                compatible = "marvell,armada-390-corediv-clock",
+                                             "marvell,armada-380-corediv-clock";
+                                reg = <0xe4250 0xc>;
+                                #clock-cells = <1>;
+                                clocks = <&mainpll>;
+                                clock-output-names = "nand";
+                        };
+                };
+
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        msi-parent = <&mpic>;
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                                0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
+                                0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+                                0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
+                                0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
+                                0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
+
+                        /*
+                         * This port can be either x4 or x1. When
+                         * configured in x4 by the bootloader, then
+                         * pcie@4,0 is not available.
+                         */
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        /* x1 port */
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        /* x1 port */
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        /*
+                         * x1 port only available when pcie@1,0 is
+                         * configured as a x1 port
+                         */
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+                };
+        };
+
+        clocks {
+                /* 2 GHz fixed main PLL */
+                mainpll: mainpll {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <2000000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index c1fbab243609..dfd782b44e50 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -59,7 +59,7 @@
         compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 48bdafe17526..103782407618 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -64,7 +64,7 @@
         compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 206aebba01be..565227eacf06 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -65,7 +65,7 @@
         compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 5fb3c8b687cf..06a6a6c1fdf7 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -54,8 +54,7 @@
                      "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
-                stdout-path = &uart0;
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
new file mode 100644
index 000000000000..a2cf2154dcdb
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -0,0 +1,393 @@
+/*
+ * Device Tree file for the Linksys WRT1900AC (Mamba).
+ *
+ * Note: this board is shipped with a new generation boot loader that
+ * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
+ * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be
+ * used.
+ *
+ * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on armada-xp-axpwifiap.dts:
+ *
+ *     Copyright (C) 2013 Marvell
+ *
+ *     Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+        model = "Linksys WRT1900AC";
+        compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
+                     "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Etron EJ168 USB 3.0 controller */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* First mini-PCIe port */
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+
+                        /* Second mini-PCIe port */
+                        pcie@3,0 {
+                                /* Port 0, Lane 3 */
+                                status = "okay";
+                        };
+                };
+
+                internal-regs {
+
+                        /* J10: VCC, NC, RX, NC, TX, GND  */
+                        serial@12000 {
+                                status = "okay";
+                        };
+
+                        sata@a0000 {
+                                nr-ports = <1>;
+                                status = "okay";
+                        };
+
+                        ethernet@70000 {
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy-mode = "rgmii-id";
+                                fixed-link {
+                                        speed = <1000>;
+                                        full-duplex;
+                                };
+                        };
+
+                        ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy-mode = "rgmii-id";
+                                fixed-link {
+                                        speed = <1000>;
+                                        full-duplex;
+                                };
+                        };
+
+                        /* USB part of the eSATA/USB 2.0 port */
+                        usb@50000 {
+                                status = "okay";
+                        };
+
+                        i2c@11000 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+
+                                tmp421@4c {
+                                        compatible = "ti,tmp421";
+                                        reg = <0x4c>;
+                                };
+
+                                tlc59116@68 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #gpio-cells = <2>;
+                                        compatible = "ti,tlc59116";
+                                        reg = <0x68>;
+
+                                        wan_amber@0 {
+                                                label = "mamba:amber:wan";
+                                                reg = <0x0>;
+                                        };
+
+                                        wan_white@1 {
+                                                label = "mamba:white:wan";
+                                                reg = <0x1>;
+                                        };
+
+                                        wlan_2g@2 {
+                                                label = "mamba:white:wlan_2g";
+                                                reg = <0x2>;
+                                        };
+
+                                        wlan_5g@3 {
+                                                label = "mamba:white:wlan_5g";
+                                                reg = <0x3>;
+                                        };
+
+                                        esata@4 {
+                                                label = "mamba:white:esata";
+                                                reg = <0x4>;
+                                        };
+
+                                        usb2@5 {
+                                                label = "mamba:white:usb2";
+                                                reg = <0x5>;
+                                        };
+
+                                        usb3_1@6 {
+                                                label = "mamba:white:usb3_1";
+                                                reg = <0x6>;
+                                        };
+
+                                        usb3_2@7 {
+                                                label = "mamba:white:usb3_2";
+                                                reg = <0x7>;
+                                        };
+
+                                        wps_white@8 {
+                                                label = "mamba:white:wps";
+                                                reg = <0x8>;
+                                        };
+
+                                        wps_amber@9 {
+                                                label = "mamba:amber:wps";
+                                                reg = <0x9>;
+                                        };
+                                };
+                        };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
+
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0000000 0x100000>;  /* 1MB */
+                                        read-only;
+                                };
+
+                                partition@100000 {
+                                        label = "u_env";
+                                        reg = <0x100000 0x40000>;    /* 256KB */
+                                };
+
+                                partition@140000 {
+                                        label = "s_env";
+                                        reg = <0x140000 0x40000>;    /* 256KB */
+                                };
+
+                                partition@900000 {
+                                        label = "devinfo";
+                                        reg = <0x900000 0x100000>;   /* 1MB */
+                                        read-only;
+                                };
+
+                                /* kernel1 overlaps with rootfs1 by design */
+                                partition@a00000 {
+                                        label = "kernel1";
+                                        reg = <0xa00000 0x2800000>;  /* 40MB */
+                                };
+
+                                partition@d00000 {
+                                        label = "rootfs1";
+                                        reg = <0xd00000 0x2500000>;  /* 37MB */
+                                };
+
+                                /* kernel2 overlaps with rootfs2 by design */
+                                partition@3200000 {
+                                        label = "kernel2";
+                                        reg = <0x3200000 0x2800000>; /* 40MB */
+                                };
+
+                                partition@3500000 {
+                                        label = "rootfs2";
+                                        reg = <0x3500000 0x2500000>; /* 37MB */
+                                };
+
+                                /*
+                                 * 38MB, last MB is for the BBT, not writable
+                                 */
+                                partition@5a00000 {
+                                        label = "syscfg";
+                                        reg = <0x5a00000 0x2600000>;
+                                };
+
+                                /*
+                                 * Unused area between "s_env" and "devinfo".
+                                 * Moved here because otherwise the renumbered
+                                 * partitions would break the bootloader
+                                 * supplied bootargs
+                                 */
+                                partition@180000 {
+                                        label = "unused_area";
+                                        reg = <0x180000 0x780000>;   /* 7.5MB */
+                                };
+                        };
+
+                        spi0: spi@10600 {
+                                status = "okay";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "everspin,mr25h256";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <40000000>;
+                                };
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&keys_pin>;
+                pinctrl-names = "default";
+
+                button@1 {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+                };
+
+                button@2 {
+                        label = "Factory Reset Button";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&power_led_pin>;
+                pinctrl-names = "default";
+
+                power {
+                        label = "mamba:white:power";
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+        };
+
+        gpio_fan {
+                /* SUNON HA4010V4-0000-C99 */
+                compatible = "gpio-fan";
+                gpios = <&gpio0 24 0>;
+
+                gpio-fan,speed-map = <0    0
+                                      4500 1>;
+        };
+
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                dsa,ethernet = <&eth0>;
+                dsa,mii-bus = <&mdio>;
+
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0>;  /* MDIO address 0, switch 0 in tree */
+
+                        port@0 {
+                                reg = <0>;
+                                label = "lan4";
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                label = "lan3";
+                        };
+
+                        port@2 {
+                                reg = <2>;
+                                label = "lan2";
+                        };
+
+                        port@3 {
+                                reg = <3>;
+                                label = "lan1";
+                        };
+
+                        port@4 {
+                                reg = <4>;
+                                label = "internet";
+                        };
+
+                        port@5 {
+                                reg = <5>;
+                                label = "cpu";
+                        };
+                };
+        };
+};
+
+&pinctrl {
+
+        keys_pin: keys-pin {
+                marvell,pins = "mpp32", "mpp33";
+                marvell,function = "gpio";
+        };
+
+        power_led_pin: power-led-pin {
+                marvell,pins = "mpp40";
+                marvell,function = "gpio";
+        };
+
+        gpio_fan_pin: gpio-fan-pin {
+                marvell,pins = "mpp24";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index 56f958eb1ede..f894bc83e957 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -52,7 +52,7 @@
         compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 4a7cbed79b07..8479fdc9e9c2 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -57,7 +57,6 @@
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
                 gpio2 = &gpio2;
-                eth3 = &eth3;
         };
 
         cpus {
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 36ce63a96cc9..661d54c81580 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -57,7 +57,6 @@
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
                 gpio2 = &gpio2;
-                eth3 = &eth3;
         };
 
 
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 99cb9a8401b4..1516fc2627f9 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -53,7 +53,7 @@
         compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 0c76d9f05fd0..e3b08fb959e5 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -54,7 +54,7 @@
         compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index e9fb225169aa..6063428fa6a0 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -67,8 +67,7 @@
                      "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
-                stdout-path = &uart0;
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 82917236a2fb..013d63f69e36 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -57,7 +57,8 @@
         compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
         aliases {
-                eth2 = &eth2;
+                serial2 = &uart2;
+                serial3 = &uart3;
         };
 
         soc {
@@ -78,6 +79,7 @@
                                 compatible = "marvell,aurora-system-cache";
                                 reg = <0x08000 0x1000>;
                                 cache-id-part = <0x100>;
+                                cache-level = <2>;
                                 cache-unified;
                                 wt-override;
                         };
@@ -149,11 +151,11 @@
                         cpuclk: clock-complex@18700 {
                                 #clock-cells = <1>;
                                 compatible = "marvell,armada-xp-cpu-clock";
-                                reg = <0x18700 0xA0>, <0x1c054 0x10>;
+                                reg = <0x18700 0x24>, <0x1c054 0x10>;
                                 clocks = <&coreclk 1>;
                         };
 
-                        interrupt-controller@20000 {
+                        interrupt-controller@20a00 {
                               reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                         };
 
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index 6c4bc53cbf4e..9991240b7438 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -194,6 +194,11 @@
                                                         <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
                                         };
 
+                                        pinctrl_key_gpio: key_gpio_0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+
                                         pinctrl_mmc0_cd: mmc0_cd {
                                                 atmel,pins =
                                                         <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
@@ -282,6 +287,9 @@
         gpio_keys {
                 compatible = "gpio-keys";
 
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_key_gpio>;
+
                 bp3 {
                         label = "PB_USER";
                         gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
new file mode 100644
index 000000000000..c740e1a2a3a5
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
@@ -0,0 +1,241 @@
+/*
+ * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
+ *
+ *  Copyright (C) 2015 Atmel,
+ *                2015 Josh Wu <josh.wu@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+        model = "Atmel SAMA5D4 Xplained";
+        compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
+        };
+
+        memory {
+                reg = <0x20000000 0x20000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+
+                slow_xtal {
+                        clock-frequency = <32768>;
+                };
+
+                main_xtal {
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        spi0: spi@f8010000 {
+                                cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
+                                status = "okay";
+                                m25p80@0 {
+                                        compatible = "atmel,at25df321a";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
+
+                        i2c0: i2c@f8014000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f8020000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+
+                                phy0: ethernet-phy@1 {
+                                        interrupt-parent = <&pioE>;
+                                        interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                                        reg = <1>;
+                                };
+                        };
+
+                        mmc1: mmc@fc000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioE 3 0>;
+                                };
+                        };
+
+                        usart3: serial@fc00c000 {
+                                status = "okay";
+                        };
+
+                        usart4: serial@fc010000 {
+                                status = "okay";
+                        };
+
+                        adc0: adc@fc034000 {
+                                atmel,adc-vref = <3300>;
+                                status = "okay";
+                        };
+
+                        watchdog@fc068640 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fc06a000 {
+                                board {
+                                        pinctrl_mmc1_cd: mmc1_cd {
+                                                atmel,pins =
+                                                        <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+                                        pinctrl_usba_vbus: usba_vbus {
+                                                atmel,pins =
+                                                        <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+                                        };
+                                        pinctrl_key_gpio: key_gpio_0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+                                };
+                        };
+                };
+
+                usb0: gadget@00400000 {
+                        atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usba_vbus>;
+                        status = "okay";
+                };
+
+                usb1: ohci@00500000 {
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <0
+                                           &pioE 11 GPIO_ACTIVE_HIGH
+                                           &pioE 14 GPIO_ACTIVE_HIGH
+                                          >;
+                        status = "okay";
+                };
+
+                usb2: ehci@00600000 {
+                        status = "okay";
+                };
+
+                nand0: nand@80000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        nand-on-flash-bbt;
+                        atmel,has-pmecc;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_key_gpio>;
+
+                pb_user1 {
+                        label = "pb_user1";
+                        gpios = <&pioE 8 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x100>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                status = "okay";
+
+                d8 {
+                        label = "d8";
+                        gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
+                        status = "disabled";
+                };
+
+                d10 {
+                        label = "d10";
+                        gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
index 9198b719d0ef..89ef4a540db5 100644
--- a/arch/arm/boot/dts/at91-sama5d4ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -115,6 +115,10 @@
                                 };
                         };
 
+                        ssc0: ssc@f8008000 {
+                                status = "okay";
+                        };
+
                         spi0: spi@f8010000 {
                                 cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
                                 status = "okay";
@@ -127,6 +131,13 @@
 
                         i2c0: i2c@f8014000 {
                                 status = "okay";
+
+                                wm8904: codec@1a {
+                                        compatible = "wlf,wm8904";
+                                        reg = <0x1a>;
+                                        clocks = <&pck2>;
+                                        clock-names = "mclk";
+                                };
                         };
 
                         macb0: ethernet@f8020000 {
@@ -171,6 +182,10 @@
                                                 atmel,pins =
                                                         <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
                                         };
+                                        pinctrl_pck2_as_audio_mck: pck2_as_audio_mck {
+                                                atmel,pins =
+                                                        <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
                                         pinctrl_usba_vbus: usba_vbus {
                                                 atmel,pins =
                                                         <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
@@ -244,8 +259,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_key_gpio>;
@@ -257,4 +270,42 @@
                         gpio-key,wakeup;
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+                status = "okay";
+
+                d8 {
+                        label = "d8";
+                        /* PE28, conflicts with usart4 rts pin */
+                        gpios = <&pioE 28 GPIO_ACTIVE_LOW>;
+                };
+
+                d9 {
+                        label = "d9";
+                        gpios = <&pioE 9 GPIO_ACTIVE_HIGH>;
+                };
+
+                d10 {
+                        label = "d10";
+                        gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        sound {
+                compatible = "atmel,asoc-wm8904";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pck2_as_audio_mck>;
+
+                atmel,model = "wm8904 @ SAMA5D4EK";
+                atmel,audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "IN1L", "Line In Jack",
+                        "IN1R", "Line In Jack";
+
+                atmel,ssc-controller = <&ssc0>;
+                atmel,audio-codec = <&wm8904>;
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 17b879990914..a7da0dd0c98f 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_isi.dtsi"
 #include "at91sam9x5_usart3.dtsi"
 #include "at91sam9x5_macb0.dtsi"
 
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 1e4c49c584d3..707fd4ea58f5 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -16,10 +16,28 @@
 
         ahb {
                 apb {
+                        spi0: spi@f0000000 {
+                                status = "disabled";
+                        };
+
+                        mmc1: mmc@f000c000 {
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@f8010000 {
+                                ov2640: camera@0x30 {
+                                        status = "okay";
+                                };
+                        };
+
                         macb0: ethernet@f802c000 {
                                 phy-mode = "rmii";
                                 status = "okay";
                         };
+
+                        isi: isi@f8048000 {
+                                status = "okay";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index ea0af0f6ec7d..a9e35dfc12d9 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -912,6 +912,15 @@
                                 clocks = <&pwm_clk>;
                                 status = "disabled";
                         };
+
+                        usb1: gadget@f803c000 {
+                                compatible = "atmel,at91sam9260-udc";
+                                reg = <0xf803c000 0x4000>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
+                                clocks = <&udphs_clk>, <&udpck>;
+                                clock-names = "pclk", "hclk";
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 9575c0d895c9..6e067c8a3502 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -108,6 +108,13 @@
                                                         <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                         };
                                 };
+
+                                usb1 {
+                                        pinctrl_usb1_vbus_sense: usb1_vbus_sense {
+                                                atmel,pins =
+                                                        <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;  /* PB16 gpio usb vbus sense, no pull up and deglitch */
+                                        };
+                                };
                         };
 
                         spi0: spi@f0000000 {
@@ -120,9 +127,20 @@
                                 };
                         };
 
+                        usb1: gadget@f803c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usb1_vbus_sense>;
+                                atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
                         watchdog@fffffe40 {
                                 status = "okay";
                         };
+
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
index 98bc877a68ef..8fc45ca4dcb5 100644
--- a/arch/arm/boot/dts/at91sam9x5_isi.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
@@ -13,6 +13,37 @@
 / {
         ahb {
                 apb {
+                        pinctrl@fffff400 {
+                                isi {
+                                        pinctrl_isi_data_0_7: isi-0-data-0-7 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 0 AT91_PERIPH_B AT91_PINCTRL_NONE    /* ISI_D0, conflicts with LCDDAT0 */
+                                                        AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D1, conflicts with LCDDAT1 */
+                                                        AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D2, conflicts with LCDDAT2 */
+                                                        AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D3, conflicts with LCDDAT3 */
+                                                        AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D4, conflicts with LCDDAT4 */
+                                                        AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D5, conflicts with LCDDAT5 */
+                                                        AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D6, conflicts with LCDDAT6 */
+                                                        AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D7, conflicts with LCDDAT7 */
+                                                        AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE    /* ISI_PCK, conflicts with LCDDAT12 */
+                                                        AT91_PIOC 14 AT91_PERIPH_B AT91_PINCTRL_NONE    /* ISI_HSYNC, conflicts with LCDDAT14 */
+                                                        AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* ISI_VSYNC, conflicts with LCDDAT13 */
+                                        };
+
+                                        pinctrl_isi_data_8_9: isi-0-data-8-9 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE    /* ISI_D8, conflicts with LCDDAT8 */
+                                                        AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;   /* ISI_D9, conflicts with LCDDAT9 */
+                                        };
+
+                                        pinctrl_isi_data_10_11: isi-0-data-10-11 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE   /* ISI_D10, conflicts with LCDDAT10 */
+                                                        AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* ISI_D11, conflicts with LCDDAT11 */
+                                        };
+                                };
+                        };
+
                         pmc: pmc@fffffc00 {
                                 periphck {
                                         isi_clk: isi_clk {
@@ -21,6 +52,21 @@
                                         };
                                 };
                         };
+
+                        isi: isi@f8048000 {
+                                compatible = "atmel,at91sam9g45-isi";
+                                reg = <0xf8048000 0x4000>;
+                                interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_isi_data_0_7>;
+                                clocks = <&isi_clk>;
+                                clock-names = "isi_clk";
+                                status = "disabled";
+                                port {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 229d6c24a9c4..26112ebd15fc 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -42,6 +42,10 @@
                                         };
                                 };
                         };
+
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index bd16bd360272..cc83a37a7311 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -59,6 +59,16 @@
                                 status = "okay";
                         };
 
+                        isi: isi@f8048000 {
+                                status = "disabled";
+                                port {
+                                        isi_0: endpoint@0 {
+                                                remote-endpoint = <&ov2640_0>;
+                                                bus-width = <8>;
+                                        };
+                                };
+                        };
+
                         i2c0: i2c@f8010000 {
                                 status = "okay";
 
@@ -66,9 +76,47 @@
                                         compatible = "wm8731";
                                         reg = <0x1a>;
                                 };
+
+                                ov2640: camera@0x30 {
+                                        compatible = "ovti,ov2640";
+                                        reg = <0x30>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
+                                        resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
+                                        pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
+                                        clocks = <&pck0>;
+                                        clock-names = "xvclk";
+                                        assigned-clocks = <&pck0>;
+                                        assigned-clock-rates = <25000000>;
+                                        status = "disabled";
+
+                                        port {
+                                                ov2640_0: endpoint {
+                                                        remote-endpoint = <&isi_0>;
+                                                        bus-width = <8>;
+                                                };
+                                        };
+                                };
                         };
 
                         pinctrl@fffff400 {
+                                camera_sensor {
+                                        pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_MCK */
+                                        };
+
+                                        pinctrl_sensor_power: sensor_power-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_sensor_reset: sensor_reset-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
                                 mmc0 {
                                         pinctrl_board_mmc0: mmc0-board {
                                                 atmel,pins =
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index ff5fb6ab0b97..7b52c33ea69a 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -54,6 +54,42 @@
 
         /include/ "bcm-cygnus-clock.dtsi"
 
+        pinctrl: pinctrl@0x0301d0c8 {
+                compatible = "brcm,cygnus-pinmux";
+                reg = <0x0301d0c8 0x30>,
+                      <0x0301d24c 0x2c>;
+        };
+
+        gpio_crmu: gpio@03024800 {
+                compatible = "brcm,cygnus-crmu-gpio";
+                reg = <0x03024800 0x50>,
+                      <0x03024008 0x18>;
+                #gpio-cells = <2>;
+                gpio-controller;
+        };
+
+        gpio_ccm: gpio@1800a000 {
+                compatible = "brcm,cygnus-ccm-gpio";
+                reg = <0x1800a000 0x50>,
+                      <0x0301d164 0x20>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-controller;
+        };
+
+        gpio_asiu: gpio@180a5000 {
+                compatible = "brcm,cygnus-asiu-gpio";
+                reg = <0x180a5000 0x668>;
+                #gpio-cells = <2>;
+                gpio-controller;
+
+                pinmux = <&pinctrl>;
+
+                interrupt-controller;
+                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -90,6 +126,48 @@
                 status = "disabled";
         };
 
+        pcie0: pcie@18012000 {
+                compatible = "brcm,iproc-pcie";
+                reg = <0x18012000 0x1000>;
+
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
+
+                linux,pci-domain = <0>;
+
+                bus-range = <0x00 0xff>;
+
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x81000000 0 0          0x28000000 0 0x00010000
+                          0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
+
+                status = "disabled";
+        };
+
+        pcie1: pcie@18013000 {
+                compatible = "brcm,iproc-pcie";
+                reg = <0x18013000 0x1000>;
+
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
+
+                linux,pci-domain = <1>;
+
+                bus-range = <0x00 0xff>;
+
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x81000000 0 0          0x48000000 0 0x00010000
+                          0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
+
+                status = "disabled";
+        };
+
         uart0: serial@18020000 {
                 compatible = "snps,dw-apb-uart";
                 reg = <0x18020000 0x100>;
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index f18c9d9b2f2c..2ed9e5794785 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -45,13 +45,13 @@
                 power0 {
                         label = "bcm53xx:green:power";
                         gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
+                        linux,default-trigger = "default-on";
                 };
 
                 power1 {
                         label = "bcm53xx:amber:power";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-on";
+                        linux,default-trigger = "default-off";
                 };
 
                 usb {
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
new file mode 100644
index 000000000000..ea26dd3ec03a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
@@ -0,0 +1,77 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Netgear R8000
+ *
+ * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+        compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708";
+        model = "Netgear R8000 (BCM4709)";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                power0 {
+                        label = "bcm53xx:white:power";
+                        gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                power1 {
+                        label = "bcm53xx:amber:power";
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+
+                5ghz-1 {
+                        label = "bcm53xx:white:5ghz-1";
+                        gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+
+                2ghz {
+                        label = "bcm53xx:white:2ghz";
+                        gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                rfkill {
+                        label = "WiFi";
+                        linux,code = <KEY_RFKILL>;
+                        gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+                };
+
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
+                };
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
index 0ca0f4e523d0..39ac7840d7ee 100644
--- a/arch/arm/boot/dts/bcm7445.dtsi
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -76,7 +76,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                        clock-frequency = <0x4d3f640>;
+                        clock-frequency = <81000000>;
                 };
 
                 sun_top_ctrl: syscon@404000 {
@@ -96,6 +96,18 @@
                                      "syscon";
                         reg = <0x452000 0x100>;
                 };
+
+                irq0_intc: interrupt-controller@40a780 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        interrupt-parent = <&gic>;
+                        #interrupt-cells = <1>;
+                        reg = <0x40a780 0x8>;
+                        interrupt-controller;
+                        interrupts = <GIC_SPI 0x45 0x0>,
+                                     <GIC_SPI 0x43 0x0>;
+                        brcm,int-map-mask = <0x25c>, <0x7000000>;
+                        brcm,int-fwd-mask = <0x70000>;
+                };
         };
 
         smpboot {
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
index d2ee95280548..7db484323fd6 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -33,6 +33,7 @@
 /dts-v1/;
 
 #include "bcm-cygnus.dtsi"
+#include "dt-bindings/input/input.h"
 
 / {
         model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
@@ -50,4 +51,16 @@
         uart3: serial@18023000 {
                 status = "okay";
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                hook {
+                        label = "HOOK";
+                        linux,code = <KEY_O>;
+                        gpios = <&gpio_asiu 48 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index f1bb36f3975c..c9eb8565eac5 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -47,6 +47,14 @@
                 bootargs = "console=ttyS0,115200";
         };
 
+        pcie0: pcie@18012000 {
+                status = "okay";
+        };
+
+        pcie1: pcie@18013000 {
+                status = "okay";
+        };
+
         uart3: serial@18023000 {
                 status = "okay";
         };
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
new file mode 100644
index 000000000000..56b429abbedb
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -0,0 +1,53 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+        model = "Cygnus Wireless Audio (BCM958305K)";
+        compatible = "brcm,bcm58305", "brcm,cygnus";
+
+        aliases {
+                serial0 = &uart3;
+        };
+
+        chosen {
+                stdout-path = &uart3;
+                bootargs = "console=ttyS0,115200";
+        };
+
+        uart3: serial@18023000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index afe678f6d2e9..169a85578fc9 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -29,10 +29,10 @@
 &dm816x_pinmux {
         mcspi1_pins: pinmux_mcspi1_pins {
                 pinctrl-single,pins = <
-                        DM816X_IOPAD(0x0a94, PIN_INPUT | MUX_MODE0)     /* SPI_SCLK */
-                        DM816X_IOPAD(0x0a98, PIN_OUTPUT | MUX_MODE0)    /* SPI_SCS0 */
-                        DM816X_IOPAD(0x0aa8, PIN_INPUT | MUX_MODE0)     /* SPI_D0 */
-                        DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0)     /* SPI_D1 */
+                        DM816X_IOPAD(0x0a94, MUX_MODE0)                 /* SPI_SCLK */
+                        DM816X_IOPAD(0x0a98, MUX_MODE0)                 /* SPI_SCS0 */
+                        DM816X_IOPAD(0x0aa8, MUX_MODE0)                 /* SPI_D0 */
+                        DM816X_IOPAD(0x0aac, MUX_MODE0)                 /* SPI_D1 */
                 >;
         };
 
@@ -52,13 +52,13 @@
 
         usb0_pins: pinmux_usb0_pins {
                 pinctrl-single,pins = <
-                        DM816X_IOPAD(0x0d00, MUX_MODE0)                 /* USB0_DRVVBUS */
+                        DM816X_IOPAD(0x0d04, MUX_MODE0)                 /* USB0_DRVVBUS */
                 >;
         };
 
-        usb1_pins: pinmux_usb0_pins {
+        usb1_pins: pinmux_usb1_pins {
                 pinctrl-single,pins = <
-                        DM816X_IOPAD(0x0d04, MUX_MODE0)                 /* USB1_DRVVBUS */
+                        DM816X_IOPAD(0x0d08, MUX_MODE0)                 /* USB1_DRVVBUS */
                 >;
         };
 };
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index f35715bc6992..de8427be830a 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -396,6 +396,29 @@
                                 mentor,num-eps = <16>;
                                 mentor,ram-bits = <12>;
                                 mentor,power = <500>;
+
+                                dmas = <&cppi41dma  0 0 &cppi41dma  1 0
+                                        &cppi41dma  2 0 &cppi41dma  3 0
+                                        &cppi41dma  4 0 &cppi41dma  5 0
+                                        &cppi41dma  6 0 &cppi41dma  7 0
+                                        &cppi41dma  8 0 &cppi41dma  9 0
+                                        &cppi41dma 10 0 &cppi41dma 11 0
+                                        &cppi41dma 12 0 &cppi41dma 13 0
+                                        &cppi41dma 14 0 &cppi41dma  0 1
+                                        &cppi41dma  1 1 &cppi41dma  2 1
+                                        &cppi41dma  3 1 &cppi41dma  4 1
+                                        &cppi41dma  5 1 &cppi41dma  6 1
+                                        &cppi41dma  7 1 &cppi41dma  8 1
+                                        &cppi41dma  9 1 &cppi41dma 10 1
+                                        &cppi41dma 11 1 &cppi41dma 12 1
+                                        &cppi41dma 13 1 &cppi41dma 14 1>;
+                                dma-names =
+                                        "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                        "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                        "rx14", "rx15",
+                                        "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                        "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                        "tx14", "tx15";
                         };
 
                         usb1: usb@47401800 {
@@ -413,6 +436,43 @@
                                 mentor,num-eps = <16>;
                                 mentor,ram-bits = <12>;
                                 mentor,power = <500>;
+
+                                dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+                                        &cppi41dma 17 0 &cppi41dma 18 0
+                                        &cppi41dma 19 0 &cppi41dma 20 0
+                                        &cppi41dma 21 0 &cppi41dma 22 0
+                                        &cppi41dma 23 0 &cppi41dma 24 0
+                                        &cppi41dma 25 0 &cppi41dma 26 0
+                                        &cppi41dma 27 0 &cppi41dma 28 0
+                                        &cppi41dma 29 0 &cppi41dma 15 1
+                                        &cppi41dma 16 1 &cppi41dma 17 1
+                                        &cppi41dma 18 1 &cppi41dma 19 1
+                                        &cppi41dma 20 1 &cppi41dma 21 1
+                                        &cppi41dma 22 1 &cppi41dma 23 1
+                                        &cppi41dma 24 1 &cppi41dma 25 1
+                                        &cppi41dma 26 1 &cppi41dma 27 1
+                                        &cppi41dma 28 1 &cppi41dma 29 1>;
+                                dma-names =
+                                        "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                        "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                        "rx14", "rx15",
+                                        "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                        "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                        "tx14", "tx15";
+                        };
+
+                        cppi41dma: dma-controller@47402000 {
+                                compatible = "ti,am3359-cppi41";
+                                reg =  <0x47400000 0x1000
+                                        0x47402000 0x1000
+                                        0x47403000 0x1000
+                                        0x47404000 0x4000>;
+                                reg-names = "glue", "controller", "scheduler", "queuemgr";
+                                interrupts = <17>;
+                                interrupt-names = "glue";
+                                #dma-cells = <2>;
+                                #dma-channels = <30>;
+                                #dma-requests = <256>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index a5441d5482a6..9ad829523a13 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -1,5 +1,8 @@
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
 / {
@@ -61,7 +64,7 @@
                                   0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0   /* Port 1.0 Mem */
                                   0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
 
-                        pcie-port@0 {
+                        pcie0: pcie-port@0 {
                                 device_type = "pci";
                                 status = "disabled";
                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
@@ -79,7 +82,7 @@
                                 interrupt-map = <0 0 0 0 &intc 16>;
                         };
 
-                        pcie-port@1 {
+                        pcie1: pcie-port@1 {
                                 device_type = "pci";
                                 status = "disabled";
                                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
@@ -154,7 +157,7 @@
 
                         uart2: serial@12200 {
                                 compatible = "ns16550a";
-                                reg = <0x12000 0x100>;
+                                reg = <0x12200 0x100>;
                                 reg-shift = <2>;
                                 interrupts = <9>;
                                 clocks = <&core_clk 0>;
@@ -163,7 +166,7 @@
 
                         uart3: serial@12300 {
                                 compatible = "ns16550a";
-                                reg = <0x12100 0x100>;
+                                reg = <0x12300 0x100>;
                                 reg-shift = <2>;
                                 interrupts = <10>;
                                 clocks = <&core_clk 0>;
@@ -448,6 +451,11 @@
                                         marvell,function = "gpio";
                                 };
 
+                                pmx_pcie1_clkreq: pmx-pcie1-clkreq {
+                                        marvell,pins = "mpp9";
+                                        marvell,function = "pex1";
+                                };
+
                                 pmx_gpio_10: pmx-gpio-10 {
                                         marvell,pins = "mpp10";
                                         marvell,function = "gpio";
@@ -458,6 +466,11 @@
                                         marvell,function = "gpio";
                                 };
 
+                                pmx_pcie0_clkreq: pmx-pcie0-clkreq {
+                                        marvell,pins = "mpp11";
+                                        marvell,function = "pex0";
+                                };
+
                                 pmx_gpio_12: pmx-gpio-12 {
                                         marvell,pins = "mpp12";
                                         marvell,function = "gpio";
@@ -563,6 +576,18 @@
                                         marvell,function = "gpio";
                                 };
 
+                                pmx_spi1_4_7: pmx-spi1-4-7 {
+                                        marvell,pins = "mpp4", "mpp5",
+                                                "mpp6", "mpp7";
+                                        marvell,function = "spi1";
+                                };
+
+                                pmx_spi1_20_23: pmx-spi1-20-23 {
+                                        marvell,pins = "mpp20", "mpp21",
+                                                "mpp22", "mpp23";
+                                        marvell,function = "spi1";
+                                };
+
                                 pmx_uart1: pmx-uart1 {
                                         marvell,pins = "mpp_uart1";
                                         marvell,function = "uart1";
@@ -582,6 +607,36 @@
                                         marvell,pins = "mpp_nand";
                                         marvell,function = "gpo";
                                 };
+
+                                pmx_i2c1: pmx-i2c1 {
+                                        marvell,pins = "mpp17", "mpp19";
+                                        marvell,function = "twsi";
+                                };
+
+                                pmx_i2c2: pmx-i2c2 {
+                                        marvell,pins = "mpp_audio1";
+                                        marvell,function = "twsi";
+                                };
+
+                                pmx_ssp_i2c2: pmx-ssp-i2c2 {
+                                        marvell,pins = "mpp_audio1";
+                                        marvell,function = "ssp/twsi";
+                                };
+
+                                pmx_i2cmux_0: pmx-i2cmux-0 {
+                                        marvell,pins = "twsi";
+                                        marvell,function = "twsi-opt1";
+                                };
+
+                                pmx_i2cmux_1: pmx-i2cmux-1 {
+                                        marvell,pins = "twsi";
+                                        marvell,function = "twsi-opt2";
+                                };
+
+                                pmx_i2cmux_2: pmx-i2cmux-2 {
+                                        marvell,pins = "twsi";
+                                        marvell,function = "twsi-opt3";
+                                };
                         };
 
                         core_clk: core-clocks@d0214 {
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index b1bd06c6c2a8..aa465904f6cc 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -541,6 +541,14 @@
         };
 };
 
+&omap_dwc3_1 {
+        extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+        extcon = <&extcon_usb2>;
+};
+
 &usb1 {
         dr_mode = "peripheral";
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index fe55938bc978..082882c616e8 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -678,7 +678,6 @@
                         reg = <0x48820000 0x80>;
                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer5";
-                        ti,timer-dsp;
                 };
 
                 timer6: timer@48822000 {
@@ -686,8 +685,6 @@
                         reg = <0x48822000 0x80>;
                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer6";
-                        ti,timer-dsp;
-                        ti,timer-pwm;
                 };
 
                 timer7: timer@48824000 {
@@ -695,7 +692,6 @@
                         reg = <0x48824000 0x80>;
                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer7";
-                        ti,timer-dsp;
                 };
 
                 timer8: timer@48826000 {
@@ -703,8 +699,6 @@
                         reg = <0x48826000 0x80>;
                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer8";
-                        ti,timer-dsp;
-                        ti,timer-pwm;
                 };
 
                 timer9: timer@4803e000 {
@@ -726,7 +720,6 @@
                         reg = <0x48088000 0x80>;
                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer11";
-                        ti,timer-pwm;
                 };
 
                 timer13: timer@48828000 {
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index daf28110d487..ce0390f081d9 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -377,6 +377,14 @@
         phy-supply = <&ldo4_reg>;
 };
 
+&omap_dwc3_1 {
+        extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+        extcon = <&extcon_usb2>;
+};
+
 &usb1 {
         dr_mode = "peripheral";
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 99b09a44e269..3b933f74d000 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1493,6 +1493,14 @@
                 ti,dividers = <1>, <8>;
         };
 
+        clkout2_clk: clkout2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkoutmux2_clk_mux>;
+                ti,bit-shift = <8>;
+                reg = <0x06b0>;
+        };
+
         l3init_960m_gfclk: l3init_960m_gfclk {
                 #clock-cells = <0>;
                 compatible = "ti,gate-clock";
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 667d323e80a3..19446273e4a7 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -94,3 +94,16 @@
                 vdd33a-supply = <&reg_3p3v>;
         };
 };
+
+&pfc {
+        uart1_pins: uart@e1030000 {
+                renesas,groups = "uart1_ctrl", "uart1_data";
+                renesas,function = "uart1";
+        };
+};
+
+&uart1 {
+        pinctrl-0 = <&uart1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index cc7bfe0ba40a..bb45694d91bc 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -169,12 +169,18 @@
                 clock-names = "sclk";
         };
 
+        pfc: pfc@e0140200 {
+                compatible = "renesas,pfc-emev2";
+                reg = <0xe0140200 0x100>;
+        };
+
         gpio0: gpio@e0050000 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
                 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
                              <0 68 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
+                gpio-ranges = <&pfc 0 0 32>;
                 #gpio-cells = <2>;
                 ngpios = <32>;
                 interrupt-controller;
@@ -186,6 +192,7 @@
                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
                              <0 70 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
+                gpio-ranges = <&pfc 0 32 32>;
                 #gpio-cells = <2>;
                 ngpios = <32>;
                 interrupt-controller;
@@ -197,6 +204,7 @@
                 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
                              <0 72 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
+                gpio-ranges = <&pfc 0 64 32>;
                 #gpio-cells = <2>;
                 ngpios = <32>;
                 interrupt-controller;
@@ -208,6 +216,7 @@
                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
                              <0 74 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
+                gpio-ranges = <&pfc 0 96 32>;
                 #gpio-cells = <2>;
                 ngpios = <32>;
                 interrupt-controller;
@@ -219,6 +228,7 @@
                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
                              <0 76 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
+                gpio-ranges = <&pfc 0 128 31>;
                 #gpio-cells = <2>;
                 ngpios = <31>;
                 interrupt-controller;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 14ab515aa83c..e3bfb11c6ef8 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -176,6 +176,10 @@
                         compatible = "samsung,exynos3250-cmu";
                         reg = <0x10030000 0x20000>;
                         #clock-cells = <1>;
+                        assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
+                                          <&cmu CLK_MOUT_ACLK_266_SUB>;
+                        assigned-clock-parents = <&cmu CLK_FIN_PLL>,
+                                                 <&cmu CLK_FIN_PLL>;
                 };
 
                 cmu_dmc: clock-controller@105C0000 {
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index adb4f6a97a1d..8de12af7c276 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -75,10 +75,18 @@
                 };
         };
 
+        emmc_pwrseq: pwrseq {
+                pinctrl-0 = <&sd1_cd>;
+                pinctrl-names = "default";
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&gpk1 2 1>;
+        };
+
         mmc@12550000 {
                 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
                 pinctrl-names = "default";
                 vmmc-supply = <&ldo20_reg &buck8_reg>;
+                mmc-pwrseq = <&emmc_pwrseq>;
                 status = "okay";
 
                 num-slots = <1>;
@@ -472,6 +480,12 @@
         };
 };
 
+/* RSTN signal for eMMC */
+&sd1_cd {
+        samsung,pin-pud = <0>;
+        samsung,pin-drv = <0>;
+};
+
 &pinctrl_1 {
         gpio_power_key: power_key {
                 samsung,pins = "gpx1-3";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index b9aeec430527..2657e842e5a5 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -29,6 +29,7 @@
 
         chosen {
                 bootargs = "console=tty1";
+                stdout-path = "serial3:115200n8";
         };
 
         gpio-keys {
@@ -183,7 +184,20 @@
                         powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
                         reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
                         edid-emulation = <5>;
-                        panel = <&panel>;
+
+                        ports {
+                                port@0 {
+                                        bridge_out: endpoint {
+                                                remote-endpoint = <&panel_in>;
+                                        };
+                                };
+
+                                port@1 {
+                                        bridge_in: endpoint {
+                                                remote-endpoint = <&dp_out>;
+                                        };
+                                };
+                        };
                 };
         };
 
@@ -228,6 +242,20 @@
                 compatible = "auo,b116xw03";
                 power-supply = <&fet6>;
                 backlight = <&backlight>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&bridge_out>;
+                        };
+                };
+        };
+
+        mmc3_pwrseq: mmc3_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */
+                              <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+                clocks = <&max77686 MAX77686_CLK_PMIC>;
+                clock-names = "ext_clock";
         };
 };
 
@@ -242,7 +270,14 @@
         samsung,link-rate = <0x0a>;
         samsung,lane-count = <2>;
         samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
-        bridge = <&ptn3460>;
+
+        ports {
+                port@0 {
+                        dp_out: endpoint {
+                                remote-endpoint = <&bridge_in>;
+                        };
+                };
+        };
 };
 
 &ehci {
@@ -531,17 +566,33 @@
         status = "okay";
         num-slots = <1>;
         broken-cd;
+        cap-sdio-irq;
         card-detect-delay = <200>;
         samsung,dw-mshc-ciu-div = <3>;
         samsung,dw-mshc-sdr-timing = <2 3>;
         samsung,dw-mshc-ddr-timing = <1 2>;
         pinctrl-names = "default";
-        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
+        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>;
         bus-width = <4>;
         cap-sd-highspeed;
+        mmc-pwrseq = <&mmc3_pwrseq>;
 };
 
 &pinctrl_0 {
+        wifi_en: wifi-en {
+                samsung,pins = "gpx0-1";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        wifi_rst: wifi-rst {
+                samsung,pins = "gpx0-2";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
         power_key_irq: power-key-irq {
                 samsung,pins = "gpx1-3";
                 samsung,pin-function = <0xf>;
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index d075a68ac078..d03f9b8d376d 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -25,6 +25,7 @@
 
         chosen {
                 bootargs = "console=tty1";
+                stdout-path = "serial3:115200n8";
         };
 
         gpio-keys {
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 77f656eb8e6b..257e2f10525d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -143,7 +143,7 @@
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x101C0000 0x800>;
                 interrupt-controller;
-                #interrups-cells = <2>;
+                #interrupt-cells = <2>;
                 interrupt-parent = <&mct_map>;
                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
                              <4 0>, <5 0>;
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index db2c1c4cd900..b82b6fa15f48 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -55,7 +55,7 @@
                 samsung,dw-mshc-sdr-timing = <0 4>;
                 samsung,dw-mshc-ddr-timing = <0 2>;
                 pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
                 vmmc-supply = <&ldo10_reg>;
                 bus-width = <8>;
                 cap-mmc-highspeed;
@@ -68,7 +68,7 @@
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
                 pinctrl-names = "default";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
                 vmmc-supply = <&ldo19_reg>;
                 vqmmc-supply = <&ldo13_reg>;
                 bus-width = <4>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index c47bb70665c1..0788d08fb43e 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -43,6 +43,10 @@
                 pinctrl-names = "default";
         };
 
+        chosen {
+                stdout-path = "serial3:115200n8";
+        };
+
         fixed-rate-clocks {
                 oscclk {
                         compatible = "samsung,exynos5420-oscclk";
@@ -118,6 +122,19 @@
                 compatible = "auo,b116xw03";
                 power-supply = <&tps65090_fet6>;
                 backlight = <&backlight>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&bridge_out>;
+                        };
+                };
+        };
+
+        mmc1_pwrseq: mmc1_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+                clocks = <&max77802 MAX77802_CLK_32K_CP>;
+                clock-names = "ext_clock";
         };
 };
 
@@ -137,7 +154,14 @@
         samsung,link-rate = <0x06>;
         samsung,lane-count = <2>;
         samsung,hpd-gpio = <&gpx2 6 0>;
-        bridge = <&ps8625>;
+
+        ports {
+                port@0 {
+                        dp_out: endpoint {
+                                remote-endpoint = <&bridge_in>;
+                        };
+                };
+        };
 };
 
 &fimd {
@@ -581,6 +605,8 @@
                 interrupt-parent = <&gpx0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&max98090_irq>;
+                clocks = <&pmu_system_controller 0>;
+                clock-names = "mclk";
         };
 
         light-sensor@44 {
@@ -595,8 +621,22 @@
                 sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
                 reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
                 lane-count = <2>;
-                panel = <&panel>;
                 use-external-pwm;
+
+                ports {
+                        port@0 {
+                                bridge_out: endpoint {
+                                        remote-endpoint = <&panel_in>;
+                                };
+                        };
+
+                        port@1 {
+                                bridge_in: endpoint {
+                                        remote-endpoint = <&dp_out>;
+                                };
+                        };
+                };
+
         };
 };
 
@@ -659,11 +699,32 @@
         samsung,dw-mshc-ciu-div = <3>;
         samsung,dw-mshc-sdr-timing = <0 4>;
         samsung,dw-mshc-ddr-timing = <0 2>;
+        samsung,dw-mshc-hs400-timing = <0 2>;
+        samsung,read-strobe-delay = <90>;
         pinctrl-names = "default";
-        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
         bus-width = <8>;
 };
 
+&mmc_1 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        cap-sdio-irq;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <1>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>,
+                    <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>;
+        bus-width = <4>;
+        cap-sd-highspeed;
+        mmc-pwrseq = <&mmc1_pwrseq>;
+        vqmmc-supply = <&buck10_reg>;
+};
+
 &mmc_2 {
         status = "okay";
         num-slots = <1>;
@@ -674,7 +735,7 @@
         samsung,dw-mshc-sdr-timing = <2 3>;
         samsung,dw-mshc-ddr-timing = <1 2>;
         pinctrl-names = "default";
-        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
         bus-width = <4>;
 };
 
@@ -683,6 +744,13 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mask_tpm_reset>;
 
+        wifi_en: wifi-en {
+                samsung,pins = "gpx0-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
         max98090_irq: max98090-irq {
                 samsung,pins = "gpx0-2";
                 samsung,pin-function = <0>;
@@ -770,6 +838,29 @@
         };
 };
 
+&pinctrl_1 {
+        /* Adjust WiFi drive strengths lower for EMI */
+        sd1_clk: sd1-clk {
+                samsung,pin-drv = <2>;
+        };
+
+        sd1_cmd: sd1-cmd {
+                samsung,pin-drv = <2>;
+        };
+
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pin-drv = <2>;
+        };
+
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pin-drv = <2>;
+        };
+
+        sd1_bus8: sd1-bus-width8 {
+                samsung,pin-drv = <2>;
+        };
+};
+
 &pinctrl_2 {
         pmic_dvs_2: pmic-dvs-2 {
                 samsung,pins = "gpj4-2";
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index ba686e40eac7..8b153166ebdb 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -201,6 +201,13 @@
                         samsung,pin-drv = <3>;
                 };
 
+                sd0_rclk: sd0-rclk {
+                        samsung,pins = "gpc0-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <1>;
+                        samsung,pin-drv = <3>;
+                };
+
                 sd1_cmd: sd1-cmd {
                         samsung,pins = "gpc1-1";
                         samsung,pin-function = <2>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 8be3d7b489ff..9103f2381a6d 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -80,8 +80,11 @@
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <0 4>;
                 samsung,dw-mshc-ddr-timing = <0 2>;
+                samsung,dw-mshc-hs400-timing = <0 2>;
+                samsung,read-strobe-delay = <90>;
                 pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8
+                             &sd0_rclk>;
                 bus-width = <8>;
                 cap-mmc-highspeed;
         };
@@ -93,7 +96,7 @@
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
                 pinctrl-names = "default";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
                 bus-width = <4>;
                 cap-sd-highspeed;
         };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index b3d2d53820e3..f67b23f303c3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -221,7 +221,7 @@
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x101C0000 0x800>;
                 interrupt-controller;
-                #interrups-cells = <1>;
+                #interrupt-cells = <1>;
                 interrupt-parent = <&mct_map>;
                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
                                 <8>, <9>, <10>, <11>;
@@ -251,6 +251,8 @@
                 compatible = "samsung,exynos4210-pd";
                 reg = <0x10044000 0x20>;
                 #power-domain-cells = <0>;
+                clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
+                clock-names = "asb0", "asb1";
         };
 
         isp_pd: power-domain@10044020 {
@@ -283,9 +285,11 @@
                          <&clock CLK_MOUT_SW_ACLK300>,
                          <&clock CLK_MOUT_USER_ACLK300_DISP1>,
                          <&clock CLK_MOUT_SW_ACLK400>,
-                         <&clock CLK_MOUT_USER_ACLK400_DISP1>;
+                         <&clock CLK_MOUT_USER_ACLK400_DISP1>,
+                         <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
                 clock-names = "oscclk", "pclk0", "clk0",
-                              "pclk1", "clk1", "pclk2", "clk2";
+                              "pclk1", "clk1", "pclk2", "clk2",
+                              "asb0", "asb1";
         };
 
         pinctrl_0: pinctrl@13400000 {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index a519c863248d..edc25cf1d717 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -264,6 +264,13 @@
                 };
         };
 
+        emmc_pwrseq: pwrseq {
+                pinctrl-0 = <&emmc_nrst_pin>;
+                pinctrl-names = "default";
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&gpd1 0 1>;
+        };
+
         i2c_2: i2c@12C80000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
@@ -298,13 +305,14 @@
 
 &mmc_0 {
         status = "okay";
+        mmc-pwrseq = <&emmc_pwrseq>;
         broken-cd;
         card-detect-delay = <200>;
         samsung,dw-mshc-ciu-div = <3>;
         samsung,dw-mshc-sdr-timing = <0 4>;
         samsung,dw-mshc-ddr-timing = <0 2>;
         pinctrl-names = "default";
-        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
         bus-width = <8>;
         cap-mmc-highspeed;
 };
@@ -316,7 +324,7 @@
         samsung,dw-mshc-sdr-timing = <0 4>;
         samsung,dw-mshc-ddr-timing = <0 2>;
         pinctrl-names = "default";
-        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
         bus-width = <4>;
         cap-sd-highspeed;
 };
@@ -330,6 +338,15 @@
         };
 };
 
+&pinctrl_1 {
+        emmc_nrst_pin: emmc-nrst {
+                samsung,pins = "gpd1-0";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+
 &usbdrd_dwc3_0 {
         dr_mode = "host";
 };
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 06737c60d333..412f41d62686 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -42,6 +42,10 @@
                 pinctrl-names = "default";
         };
 
+        chosen {
+                stdout-path = "serial3:115200n8";
+        };
+
         fixed-rate-clocks {
                 oscclk {
                         compatible = "samsung,exynos5420-oscclk";
@@ -119,6 +123,13 @@
                 power-supply = <&tps65090_fet6>;
                 backlight = <&backlight>;
         };
+
+        mmc1_pwrseq: mmc1_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+                clocks = <&max77802 MAX77802_CLK_32K_CP>;
+                clock-names = "ext_clock";
+        };
 };
 
 &adc {
@@ -581,6 +592,8 @@
                 interrupt-parent = <&gpx0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&max98091_irq>;
+                clocks = <&pmu_system_controller 0>;
+                clock-names = "mclk";
         };
 
         light-sensor@44 {
@@ -641,18 +654,40 @@
         num-slots = <1>;
         broken-cd;
         mmc-hs200-1_8v;
+        mmc-hs400-1_8v;
         cap-mmc-highspeed;
         non-removable;
         card-detect-delay = <200>;
-        clock-frequency = <400000000>;
+        clock-frequency = <800000000>;
         samsung,dw-mshc-ciu-div = <3>;
         samsung,dw-mshc-sdr-timing = <0 4>;
         samsung,dw-mshc-ddr-timing = <0 2>;
+        samsung,dw-mshc-hs400-timing = <0 2>;
+        samsung,read-strobe-delay = <90>;
         pinctrl-names = "default";
-        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
         bus-width = <8>;
 };
 
+&mmc_1 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        cap-sdio-irq;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <1>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>,
+                    <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>;
+        bus-width = <4>;
+        cap-sd-highspeed;
+        mmc-pwrseq = <&mmc1_pwrseq>;
+        vqmmc-supply = <&buck10_reg>;
+};
+
 &mmc_2 {
         status = "okay";
         num-slots = <1>;
@@ -663,7 +698,7 @@
         samsung,dw-mshc-sdr-timing = <2 3>;
         samsung,dw-mshc-ddr-timing = <1 2>;
         pinctrl-names = "default";
-        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
         bus-width = <4>;
 };
 
@@ -672,6 +707,13 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mask_tpm_reset>;
 
+        wifi_en: wifi-en {
+                samsung,pins = "gpx0-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
         max98091_irq: max98091-irq {
                 samsung,pins = "gpx0-2";
                 samsung,pin-function = <0>;
@@ -759,6 +801,29 @@
         };
 };
 
+&pinctrl_1 {
+        /* Adjust WiFi drive strengths lower for EMI */
+        sd1_clk: sd1-clk {
+                samsung,pin-drv = <2>;
+        };
+
+        sd1_cmd: sd1-cmd {
+                samsung,pin-drv = <2>;
+        };
+
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pin-drv = <2>;
+        };
+
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pin-drv = <2>;
+        };
+
+        sd1_bus8: sd1-bus-width8 {
+                samsung,pin-drv = <2>;
+        };
+};
+
 &pinctrl_2 {
         pmic_dvs_2: pmic-dvs-2 {
                 samsung,pins = "gpj4-2";
diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts
new file mode 100644
index 000000000000..7427ec50b829
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nas2big.dts
@@ -0,0 +1,143 @@
+/*
+ * Device Tree file for LaCie 2Big NAS
+ *
+ * Copyright (C) 2015 Seagate
+ *
+ * Author: Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+/dts-v1/;
+
+#include "kirkwood-netxbig.dtsi"
+
+/ {
+        model = "LaCie 2Big NAS";
+        compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
+        };
+
+        mbus {
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ocp@f1000000 {
+                rtc@10300 {
+                        /* The on-chip RTC is not powered (no supercap). */
+                        status = "disabled";
+                };
+                spi@10600 {
+                        /*
+                         * A NAND flash is used instead of an SPI flash for
+                         * the other netxbig-compatible boards.
+                         */
+                        status = "disabled";
+                };
+        };
+
+        fan {
+                /*
+                 * An I2C fan controller (GMT G762) is used but alarm is
+                 * wired to a separate GPIO.
+                 */
+                compatible = "gpio-fan";
+                alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+        };
+
+        regulators: regulators {
+                status = "okay";
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "hdd1power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+                };
+                clocks {
+                        g762_clk: g762-oscillator {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-frequency = <32768>;
+                        };
+                };
+        };
+};
+
+&mdio {
+        status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+        status = "okay";
+
+        /*
+         * An external I2C RTC (Dallas DS1337S+) is used. This allows
+         * to power-up the board on an RTC alarm. The external RTC can
+         * be kept powered, even when the SoC is off.
+         */
+        rtc@68 {
+                compatible = "dallas,ds1307";
+                reg = <0x68>;
+                interrupts = <43>;
+        };
+        g762@3e {
+                compatible = "gmt,g762";
+                reg = <0x3e>;
+                clocks = <&g762_clk>;
+        };
+};
+
+&nand {
+        chip-delay = <50>;
+        status = "okay";
+
+        partition@0 {
+                label = "U-Boot";
+                reg = <0x0 0x100000>;
+        };
+
+        partition@100000 {
+                label = "uImage";
+                reg = <0x100000 0x1000000>;
+        };
+
+        partition@1100000 {
+                label = "root";
+                reg = <0x1100000 0x8000000>;
+        };
+
+        partition@9100000 {
+                label = "unused";
+                reg = <0x9100000 0x6f00000>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts
index 53dc37a3b687..13a44773b6df 100644
--- a/arch/arm/boot/dts/kirkwood-net2big.dts
+++ b/arch/arm/boot/dts/kirkwood-net2big.dts
@@ -27,6 +27,11 @@
                 device_type = "memory";
                 reg = <0x00000000 0x10000000>;
         };
+
+        fan {
+                compatible = "gpio-fan";
+                alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+        };
 };
 
 &regulators {
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index b67ede515bcd..548441384d2a 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -150,5 +150,25 @@
                         interrupts = <0 15 1>;
                         status = "disabled";
                 };
+
+                spifc: spi@c1108c80 {
+                        compatible = "amlogic,meson6-spifc";
+                        reg = <0xc1108c80 0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clk81>;
+                        status = "disabled";
+                };
+
+                ethmac: ethernet@c9410000 {
+                        compatible = "amlogic,meson6-dwmac", "snps,dwmac";
+                        reg = <0xc9410000 0x10000
+                               0xc1108108 0x4>;
+                        interrupts = <0 8 1>;
+                        interrupt-names = "macirq";
+                        clocks = <&clk81>;
+                        clock-names = "stmmaceth";
+                        status = "disabled";
+                };
         };
 }; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index d7d351a68944..1237faa63ce6 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -64,3 +64,7 @@
 &uart_AO {
         status = "okay";
 };
+
+&ethmac {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
new file mode 100644
index 000000000000..4f536bb1f002
--- /dev/null
+++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2014 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "meson8.dtsi"
+
+/ {
+        model = "MINIX NEO-X8";
+        compatible = "minix,neo-x8", "amlogic,meson8";
+
+        aliases {
+                serial0 = &uart_AO;
+        };
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                blue {
+                        label = "x8:blue:power";
+                        gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&uart_AO {
+        status = "okay";
+        pinctrl-0 = <&uart_ao_a_pins>;
+        pinctrl-names = "default";
+};
+
+&i2c_AO {
+        status = "okay";
+        pinctrl-0 = <&i2c_ao_pins>;
+        pinctrl-names = "default";
+
+        pmic@32 {
+                compatible = "ricoh,rn5t618";
+                reg = <0x32>;
+
+                regulators {
+                };
+        };
+
+        rtc@51 {
+                compatible = "nxp,pcf8563";
+                reg = <0x51>;
+        };
+};
+
+&spifc {
+        status = "okay";
+        pinctrl-0 = <&spi_nor_pins>;
+        pinctrl-names = "default";
+
+        spi-flash@0 {
+                compatible = "mxicy,mx25l1606e";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0>;
+                spi-max-frequency = <30000000>;
+
+                partition@0 {
+                        label = "boot";
+                        reg = <0x0 0x100000>;
+                };
+
+                partition@100000 {
+                        label = "env";
+                        reg = <0x100000 0x10000>;
+                };
+        };
+};
+
+&ir_receiver {
+        status = "okay";
+        pinctrl-0 = <&ir_recv_pins>;
+        pinctrl-names = "default";
+};
+
+&ethmac {
+        status = "okay";
+        pinctrl-0 = <&eth_pins>;
+        pnictrl-names = "default";
+};
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 1f442a7fe03b..a2ddcb8c545a 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -43,6 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/gpio/meson8-gpio.h>
 /include/ "meson.dtsi"
 
 / {
@@ -89,4 +90,71 @@
                 compatible = "fixed-clock";
                 clock-frequency = <141666666>;
         };
+
+        pinctrl: pinctrl@c1109880 {
+                compatible = "amlogic,meson8-pinctrl";
+                reg = <0xc1109880 0x10>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                gpio: banks@c11080b0 {
+                        reg = <0xc11080b0 0x28>,
+                              <0xc11080e8 0x18>,
+                              <0xc1108120 0x18>,
+                              <0xc1108030 0x30>;
+                        reg-names = "mux", "pull", "pull-enable", "gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpio_ao: ao-bank@c1108030 {
+                        reg = <0xc8100014 0x4>,
+                              <0xc810002c 0x4>,
+                              <0xc8100024 0x8>;
+                        reg-names = "mux", "pull", "gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                uart_ao_a_pins: uart_ao_a {
+                        mux {
+                                groups = "uart_tx_ao_a", "uart_rx_ao_a";
+                                function = "uart_ao";
+                        };
+                };
+
+                i2c_ao_pins: i2c_mst_ao {
+                        mux {
+                                groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
+                                function = "i2c_mst_ao";
+                        };
+                };
+
+                spi_nor_pins: nor {
+                        mux {
+                                groups = "nor_d", "nor_q", "nor_c", "nor_cs";
+                                function = "nor";
+                        };
+                };
+
+                ir_recv_pins: remote {
+                        mux {
+                                groups = "remote_input";
+                                function = "remote";
+                        };
+                };
+
+                eth_pins: ethernet {
+                        mux {
+                                groups = "eth_tx_clk_50m", "eth_tx_en",
+                                         "eth_txd1", "eth_txd0",
+                                         "eth_rx_clk_in", "eth_rx_dv",
+                                         "eth_rxd1", "eth_rxd0", "eth_mdio",
+                                         "eth_mdc";
+                                function = "ethernet";
+                        };
+                };
+        };
+
 }; /* end of / */
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index 106b61b10030..88b3cb128698 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -138,5 +138,10 @@
                         clocks = <&uart_clk>;
                         status = "disabled";
                 };
+
+                wdt: watchdog@010000000 {
+                        compatible = "mediatek,mt6589-wdt";
+                        reg = <0x10000000 0x44>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
index 9565199bce7a..4907c5085d4b 100644
--- a/arch/arm/boot/dts/nspire-classic.dtsi
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -51,6 +51,11 @@
         compatible = "lsi,nspire-classic-ahb-divider";
 };
 
+
+&vbus_reg {
+        gpio = <&gpio 5 0>;
+};
+
 / {
         memory {
                 device_type = "memory";
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
index 375b924f60d8..08e0b81b3385 100644
--- a/arch/arm/boot/dts/nspire-cx.dts
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -69,6 +69,10 @@
         0x0709001d      0x070a0033      >;
 };
 
+&vbus_reg {
+        gpio = <&gpio 2 0>;
+};
+
 / {
         model = "TI-NSPIRE CX";
         compatible = "ti,nspire-cx";
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
index a22ffe633b49..390c91aea16d 100644
--- a/arch/arm/boot/dts/nspire.dtsi
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -54,6 +54,20 @@
                 clocks = <&ahb_clk>;
         };
 
+        usb_phy: usb_phy {
+                compatible = "usb-nop-xceiv";
+        };
+
+        vbus_reg: vbus_reg {
+                compatible = "regulator-fixed";
+
+                regulator-name = "USB VBUS output";
+                regulator-type = "voltage";
+
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
         ahb {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -65,8 +79,12 @@
                 };
 
                 usb0: usb@B0000000 {
+                        compatible = "lsi,zevio-usb";
                         reg = <0xB0000000 0x1000>;
                         interrupts = <8>;
+
+                        usb-phy = <&usb_phy>;
+                        vbus-supply = <&vbus_reg>;
                 };
 
                 usb1: usb@B4000000 {
@@ -105,8 +123,11 @@
                         ranges;
 
                         gpio: gpio@90000000 {
+                                compatible = "lsi,zevio-gpio";
                                 reg = <0x90000000 0x1000>;
                                 interrupts = <7>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                         };
 
                         fast_timer: timer@90010000 {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 8cdca51b6984..7c4dca122a91 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -60,7 +60,6 @@
                 ti,model = "omap3beagle";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         gpio_keys {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6d4c46be8c39..a5474113cd50 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -71,7 +71,6 @@
                 ti,model = "omap3beagle";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         gpio_keys {
@@ -378,3 +377,55 @@
                 };
         };
 };
+
+&gpmc {
+        status = "ok";
+        ranges = <0 0 0x30000000 0x1000000>;    /* CS0 space, 16MB */
+
+        /* Chip select 0 */
+        nand@0,0 {
+                reg = <0 0 4>;          /* NAND I/O window, 4 bytes */
+                interrupts = <20>;
+                ti,nand-ecc-opt = "ham1";
+                nand-bus-width = <16>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                gpmc,device-width = <2>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <36>;
+                gpmc,cs-wr-off-ns = <36>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <24>;
+                gpmc,adv-wr-off-ns = <36>;
+                gpmc,oe-on-ns = <6>;
+                gpmc,oe-off-ns = <48>;
+                gpmc,we-on-ns = <6>;
+                gpmc,we-off-ns = <30>;
+                gpmc,rd-cycle-ns = <72>;
+                gpmc,wr-cycle-ns = <72>;
+                gpmc,access-ns = <54>;
+                gpmc,wr-access-ns = <30>;
+
+                partition@0 {
+                        label = "X-Loader";
+                        reg = <0 0x80000>;
+                };
+                partition@80000 {
+                        label = "U-Boot";
+                        reg = <0x80000 0x1e0000>;
+                };
+                partition@1c0000 {
+                        label = "U-Boot Env";
+                        reg = <0x260000 0x20000>;
+                };
+                partition@280000 {
+                        label = "Kernel";
+                        reg = <0x280000 0x400000>;
+                };
+                partition@780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0xf980000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index 0ab748cf7749..f5b5a1d96cd7 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -133,6 +133,16 @@
         non-removable;
         bus-width = <4>;
         cap-power-off-card;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 145 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 
 &dss {
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index 46eadb21b5ef..2294f5b0aa10 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -73,6 +73,16 @@
         non-removable;
         bus-width = <4>;
         cap-power-off-card;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 
 &dss {
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index d9e92b654f85..046cd7733c4f 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -16,7 +16,6 @@
                 ti,model = "cm-t35";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 };
 
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 169037e5ff53..134d3f27a8ec 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -48,7 +48,6 @@
                 ti,model = "devkit8000";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
                 ti,audio-routing =
                         "Ext Spk", "PREDRIVEL",
                         "Ext Spk", "PREDRIVER",
diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi
index 127f3e7c10c4..346552b94d9f 100644
--- a/arch/arm/boot/dts/omap3-evm-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-common.dtsi
@@ -106,6 +106,16 @@
         non-removable;
         bus-width = <4>;
         cap-power-off-card;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 
 &twl_gpio {
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index fb3a69604ed5..b9f68817bd6e 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -46,7 +46,6 @@
                 ti,model = "gta04";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         spi_lcd {
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 8a63ad2286aa..d5e5cd449b16 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -22,7 +22,6 @@
                 compatible = "ti,omap-twl4030";
                 ti,model = "igep2";
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         vdd33: regulator-vdd33 {
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
index cc8bd0cd8cf8..72f7cdc091fb 100644
--- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -42,4 +42,13 @@
         vmmc-supply = <&lbep5clwmc_wlen>;
         bus-width = <4>;
         non-removable;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1835";
+                reg = <2>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 177 */
+        };
 };
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
index 9326b282c94a..b899e341874a 100644
--- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -64,4 +64,13 @@
         vmmc-supply = <&lbep5clwmc_wlen>;
         bus-width = <4>;
         non-removable;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1835";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */
+        };
 };
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index e81fb651d5d0..e63133304a34 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -38,7 +38,6 @@
                 ti,model = "lilly-a83x";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         reg_vcc3: vcc3 {
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index 9938b5dc1909..f2e213931e09 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -16,3 +16,40 @@
         model = "Nokia N9";
         compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
 };
+
+&i2c2 {
+        smia_1: camera@10 {
+                compatible = "nokia,smia";
+                reg = <0x10>;
+                /* No reset gpio */
+                vana-supply = <&vaux3>;
+                clocks = <&isp 0>;
+                clock-frequency = <9600000>;
+                nokia,nvm-size = <(16 * 64)>;
+                port {
+                        smia_1_1: endpoint {
+                                link-frequencies = /bits/ 64 <199200000 210000000 499200000>;
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                                remote-endpoint = <&csi2a_ep>;
+                        };
+                };
+        };
+};
+
+&isp {
+        vdd-csiphy1-supply = <&vaux2>;
+        vdd-csiphy2-supply = <&vaux2>;
+        ports {
+                port@2 {
+                        reg = <2>;
+                        csi2a_ep: endpoint {
+                                remote-endpoint = <&smia_1_1>;
+                                clock-lanes = <2>;
+                                data-lanes = <1 3>;
+                                crc = <1>;
+                                lane-polarities = <1 1 1>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 2cab149b191c..a29315833ecd 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -9,9 +9,23 @@
 
 /dts-v1/;
 
-#include "omap34xx-hs.dtsi"
+#include "omap34xx.dtsi"
 #include <dt-bindings/input/input.h>
 
+/*
+ * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
+ * for omap AES HW crypto support. When linux kernel try to access memory of AES
+ * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
+ * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
+ * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
+ * There is "unofficial" version of bootloader which enables AES in L3 firewall
+ * but it is not widely used and to prevent kernel crash rather AES is disabled.
+ * There is also no runtime detection code if AES is disabled in L3 firewall...
+ */
+&aes {
+        status = "disabled";
+};
+
 / {
         model = "Nokia N900";
         compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index c41db94ee9c2..800b379d368d 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 
-#include "omap36xx-hs.dtsi"
+#include "omap36xx.dtsi"
 
 / {
         cpus {
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
index 261c5589bfa3..0885b34d5d7d 100644
--- a/arch/arm/boot/dts/omap3-n950.dts
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -16,3 +16,40 @@
         model = "Nokia N950";
         compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
 };
+
+&i2c2 {
+        smia_1: camera@10 {
+                compatible = "nokia,smia";
+                reg = <0x10>;
+                /* No reset gpio */
+                vana-supply = <&vaux3>;
+                clocks = <&isp 0>;
+                clock-frequency = <9600000>;
+                nokia,nvm-size = <(16 * 64)>;
+                port {
+                        smia_1_1: endpoint {
+                                link-frequencies = /bits/ 64 <210000000 333600000 398400000>;
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                                remote-endpoint = <&csi2a_ep>;
+                        };
+                };
+        };
+};
+
+&isp {
+        vdd-csiphy1-supply = <&vaux2>;
+        vdd-csiphy2-supply = <&vaux2>;
+        ports {
+                port@2 {
+                        reg = <2>;
+                        csi2a_ep: endpoint {
+                                remote-endpoint = <&smia_1_1>;
+                                clock-lanes = <2>;
+                                data-lanes = <3 1>;
+                                crc = <1>;
+                                lane-polarities = <1 1 1>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi
index d36bf0250a05..18e1649681c1 100644
--- a/arch/arm/boot/dts/omap3-overo-base.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-base.dtsi
@@ -27,7 +27,6 @@
                 ti,model = "overo";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         /* HS USB Port 2 Power */
diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
new file mode 100644
index 000000000000..9619a28dfd7d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * device tree for OpenPandora 1GHz with DM3730
+ */
+
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "omap3-pandora-common.dtsi"
+
+/ {
+        model = "Pandora Handheld Console 1GHz";
+
+        compatible = "ti,omap36xx", "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusb2_2_pins
+                &control_pins
+        >;
+
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
+
+        mmc3_pins: pinmux_mmc3_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_clk.sdmmc3_clk */
+                        OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_ctl.sdmmc3_cmd */
+                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d3.sdmmc3_dat3 */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d4.sdmmc3_dat0 */
+                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d5.sdmmc3_dat1 */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d6.sdmmc3_dat2 */
+                >;
+        };
+
+        control_pins: pinmux_control_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4)    /* etk_d0.gpio_14 =  HP_SHUTDOWN */
+                        OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4)            /* etk_d1.gpio_15 =  BT_SHUTDOWN */
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)            /* etk_d2.gpio_16 =  RESET_USB_HOST */
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4)             /* etk_d7.gpio_21 =  WIFI IRQ */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)            /* etk_d8.gpio_22 =  MSECURE */
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4)            /* etk_d9.gpio_23 =  WIFI_POWER */
+                        OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4)                 /* reserved.gpio_127 = MMC2_WP */
+                        OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4)                 /* reserved.gpio_126 = MMC1_WP */
+                        OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4)                /* reserved.gpio_128 = LED_MMC1 */
+                        OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4)                /* reserved.gpio_129 = LED_MMC2 */
+
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/omap3-pandora-600mhz.dts
new file mode 100644
index 000000000000..fb803a70a2bb
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-600mhz.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * device tree for OpenPandora with OMAP3530
+ */
+
+/dts-v1/;
+
+#include "omap34xx.dtsi"
+#include "omap3-pandora-common.dtsi"
+
+/ {
+        model = "Pandora Handheld Console";
+
+        compatible = "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusb2_2_pins
+                &control_pins
+        >;
+
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
+
+        mmc3_pins: pinmux_mmc3_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_clk.sdmmc3_clk */
+                        OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_ctl.sdmmc3_cmd */
+                        OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d3.sdmmc3_dat3 */
+                        OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d4.sdmmc3_dat0 */
+                        OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d5.sdmmc3_dat1 */
+                        OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d6.sdmmc3_dat2 */
+                >;
+        };
+
+        control_pins: pinmux_control_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4)    /* etk_d0.gpio_14 =  HP_SHUTDOWN */
+                        OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4)            /* etk_d1.gpio_15 =  BT_SHUTDOWN */
+                        OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)            /* etk_d2.gpio_16 =  RESET_USB_HOST */
+                        OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4)             /* etk_d7.gpio_21 =  WIFI IRQ */
+                        OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)            /* etk_d8.gpio_22 =  MSECURE */
+                        OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4)            /* etk_d9.gpio_23 =  WIFI_POWER */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi
new file mode 100644
index 000000000000..782ab1ff1d08
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi
@@ -0,0 +1,640 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * Common device tree include for OpenPandora devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vcc>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+
+        aliases {
+                display0 = &lcd;
+        };
+
+        tv: connector@1 {
+                compatible = "connector-analog-tv";
+                label = "tv";
+
+                port {
+                        tv_connector_in: endpoint {
+                                remote-endpoint = <&venc_out>;
+                        };
+                };
+        };
+
+        gpio-leds {
+
+                compatible = "gpio-leds";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+
+                led@1 {
+                        label = "pandora::sd1";
+                        gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;    /* GPIO_128 */
+                        linux,default-trigger = "mmc0";
+                        default-state = "off";
+                };
+
+                led@2 {
+                        label = "pandora::sd2";
+                        gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;    /* GPIO_129 */
+                        linux,default-trigger = "mmc1";
+                        default-state = "off";
+                };
+
+                led@3 {
+                        label = "pandora::bluetooth";
+                        gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;   /* GPIO_158 */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+
+                led@4 {
+                        label = "pandora::wifi";
+                        gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;   /* GPIO_159 */
+                        linux,default-trigger = "mmc2";
+                        default-state = "off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&button_pins>;
+
+                up-button {
+                        label = "up";
+                        linux,code = <KEY_UP>;
+                        gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;    /* GPIO_110 */
+                        gpio-key,wakeup;
+                };
+
+                down-button {
+                        label = "down";
+                        linux,code = <KEY_DOWN>;
+                        gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;     /* GPIO_103 */
+                        gpio-key,wakeup;
+                };
+
+                left-button {
+                        label = "left";
+                        linux,code = <KEY_LEFT>;
+                        gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;     /* GPIO_96 */
+                        gpio-key,wakeup;
+                };
+
+                right-button {
+                        label = "right";
+                        linux,code = <KEY_RIGHT>;
+                        gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;     /* GPIO_98 */
+                        gpio-key,wakeup;
+                };
+
+                pageup-button {
+                        label = "game 1";
+                        linux,code = <KEY_PAGEUP>;
+                        gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;    /* GPIO_109 */
+                        gpio-key,wakeup;
+                };
+
+                pagedown-button {
+                        label = "game 3";
+                        linux,code = <KEY_PAGEDOWN>;
+                        gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;    /* GPIO_106 */
+                        gpio-key,wakeup;
+                };
+
+                home-button {
+                        label = "game 4";
+                        linux,code = <KEY_HOME>;
+                        gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;     /* GPIO_101 */
+                        gpio-key,wakeup;
+                };
+
+                end-button {
+                        label = "game 2";
+                        linux,code = <KEY_END>;
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;    /* GPIO_111 */
+                        gpio-key,wakeup;
+                };
+
+                right-shift {
+                        label = "l";
+                        linux,code = <KEY_RIGHTSHIFT>;
+                        gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;     /* GPIO_102 */
+                        gpio-key,wakeup;
+                };
+
+                kp-plus {
+                        label = "l2";
+                        linux,code = <KEY_KPPLUS>;
+                        gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;     /* GPIO_97 */
+                        gpio-key,wakeup;
+                };
+
+                right-ctrl {
+                        label = "r";
+                        linux,code = <KEY_RIGHTCTRL>;
+                        gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;     /* GPIO_105 */
+                        gpio-key,wakeup;
+                };
+
+                kp-minus {
+                        label = "r2";
+                        linux,code = <KEY_KPMINUS>;
+                        gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;    /* GPIO_107 */
+                        gpio-key,wakeup;
+                };
+
+                left-ctrl {
+                        label = "ctrl";
+                        linux,code = <KEY_LEFTCTRL>;
+                        gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;     /* GPIO_104 */
+                        gpio-key,wakeup;
+                };
+
+                menu {
+                        label = "menu";
+                        linux,code = <KEY_MENU>;
+                        gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;     /* GPIO_99 */
+                        gpio-key,wakeup;
+                };
+
+                hold {
+                        label = "hold";
+                        linux,code = <KEY_COFFEE>;
+                        gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;    /* GPIO_176 */
+                        gpio-key,wakeup;
+                };
+
+                left-alt {
+                        label = "alt";
+                        linux,code = <KEY_LEFTALT>;
+                        gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;    /* GPIO_100 */
+                        gpio-key,wakeup;
+                };
+
+                lid {
+                        label = "lid";
+                        linux,code = <0x00>;    /* SW_LID lid shut */
+                        linux,input-type = <0x05>;    /* EV_SW */
+                        gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;   /* GPIO_108 */
+                };
+        };
+};
+
+&omap3_pmx_core {
+
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat3.sdmmc1_dat3 */
+                >;
+        };
+
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat3.sdmmc2_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat4.sdmmc2_dirdat0 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat5.sdmmc2_dirdat1 */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat6.sdmmc2_dircmd */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1)         /* sdmmc2_dat7.sdmmc2_clkin */
+                >;
+        };
+
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)       /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)       /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)       /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)       /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)       /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)       /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)       /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)       /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)       /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)       /* dss_data5.dss_data5 */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)       /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)       /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)       /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)       /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)       /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)       /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)       /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)       /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)       /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)       /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)       /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)       /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)       /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)       /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)       /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)       /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)       /* dss_data23.dss_data23 */
+                        OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4)       /* GPIO_157 = lcd reset */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+
+        led_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4)       /* GPIO_128 */
+                        OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4)       /* GPIO_129 */
+                        OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4)       /* GPIO_158 */
+                        OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4)       /* GPIO_159 */
+                >;
+        };
+
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4)        /* GPIO_96 */
+                        OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4)        /* GPIO_97 */
+                        OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4)        /* GPIO_98 */
+                        OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4)        /* GPIO_99 */
+                        OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4)        /* GPIO_100 */
+                        OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4)        /* GPIO_101 */
+                        OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4)        /* GPIO_102 */
+                        OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4)        /* GPIO_103 */
+                        OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4)        /* GPIO_104 */
+                        OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4)        /* GPIO_105 */
+                        OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4)        /* GPIO_106 */
+                        OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4)        /* GPIO_107 */
+                        OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4)        /* GPIO_108 */
+                        OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4)        /* GPIO_109 */
+                        OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4)        /* GPIO_110 */
+                        OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4)        /* GPIO_111 */
+                        OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4)        /* GPIO_176 */
+                >;
+        };
+
+        penirq_pins: pinmux_penirq_pins {
+                pinctrl-single,pins = <
+                        /* here we could enable to wakeup the cpu from suspend by a pen touch */
+                        OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4)        /* GPIO_94 */
+                >;
+        };
+
+};
+
+&omap3_pmx_core2 {
+        /* define in CPU specific file that includes this one
+         * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD()
+         */
+};
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+
+                twl_power: power {
+                        compatible = "ti,twl4030-power-reset";
+                        ti,use_poweroff;
+                };
+
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+
+                        codec {
+                                ti,ramp_delay_value = <3>;
+                        };
+                };
+        };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&twl_keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <6>;
+        linux,keymap = <
+                MATRIX_KEY(0, 0, KEY_9)
+                MATRIX_KEY(0, 1, KEY_8)
+                MATRIX_KEY(0, 2, KEY_I)
+                MATRIX_KEY(0, 3, KEY_J)
+                MATRIX_KEY(0, 4, KEY_N)
+                MATRIX_KEY(0, 5, KEY_M)
+                MATRIX_KEY(1, 0, KEY_0)
+                MATRIX_KEY(1, 1, KEY_7)
+                MATRIX_KEY(1, 2, KEY_U)
+                MATRIX_KEY(1, 3, KEY_H)
+                MATRIX_KEY(1, 4, KEY_B)
+                MATRIX_KEY(1, 5, KEY_SPACE)
+                MATRIX_KEY(2, 0, KEY_BACKSPACE)
+                MATRIX_KEY(2, 1, KEY_6)
+                MATRIX_KEY(2, 2, KEY_Y)
+                MATRIX_KEY(2, 3, KEY_G)
+                MATRIX_KEY(2, 4, KEY_V)
+                MATRIX_KEY(2, 5, KEY_FN)
+                MATRIX_KEY(3, 0, KEY_O)
+                MATRIX_KEY(3, 1, KEY_5)
+                MATRIX_KEY(3, 2, KEY_T)
+                MATRIX_KEY(3, 3, KEY_F)
+                MATRIX_KEY(3, 4, KEY_C)
+                MATRIX_KEY(4, 0, KEY_P)
+                MATRIX_KEY(4, 1, KEY_4)
+                MATRIX_KEY(4, 2, KEY_R)
+                MATRIX_KEY(4, 3, KEY_D)
+                MATRIX_KEY(4, 4, KEY_X)
+                MATRIX_KEY(5, 0, KEY_K)
+                MATRIX_KEY(5, 1, KEY_3)
+                MATRIX_KEY(5, 2, KEY_E)
+                MATRIX_KEY(5, 3, KEY_S)
+                MATRIX_KEY(5, 4, KEY_Z)
+                MATRIX_KEY(6, 0, KEY_L)
+                MATRIX_KEY(6, 1, KEY_2)
+                MATRIX_KEY(6, 2, KEY_W)
+                MATRIX_KEY(6, 3, KEY_A)
+                MATRIX_KEY(6, 4, KEY_RIGHTBRACE)
+                MATRIX_KEY(7, 0, KEY_ENTER)
+                MATRIX_KEY(7, 1, KEY_1)
+                MATRIX_KEY(7, 2, KEY_Q)
+                MATRIX_KEY(7, 3, KEY_LEFTSHIFT)
+                MATRIX_KEY(7, 4, KEY_LEFTBRACE )
+         >;
+};
+
+/* backup battery charger */
+&charger {
+        ti,bb-uvolt = <3200000>;
+        ti,bb-uamp = <150>;
+};
+
+/* MMC2 */
+&vmmc2 {
+        regulator-min-microvolt = <1850000>;
+        regulator-max-microvolt = <3150000>;
+};
+
+/* LCD */
+&vaux1 {
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+};
+
+/* USB Host PHY */
+&vaux2 {
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+};
+
+/* available on expansion connector */
+&vaux3 {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+
+/* ADS7846 and nubs */
+&vaux4 {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+
+/* power audio DAC and LID sensor */
+&vsim {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+        regulator-always-on;
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        /* no clients so we should disable clock */
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+
+        bq27500@55 {
+                compatible = "ti,bq27500";
+                reg = <0x55>;
+        };
+
+};
+
+&usb_otg_hs {
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        phys = <&usb2_phy>;
+        phy-names = "usb2-phy";
+        mode = <3>;
+        power = <50>;
+};
+
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+        cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; /* GPIO_126 */
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&vmmc2>;
+        bus-width = <4>;
+        cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* GPIO_127 */
+};
+
+/* bluetooth*/
+&uart1 {
+};
+
+/* spare (expansion connector) */
+&uart2 {
+};
+
+/* console (expansion connector) */
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+};
+
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+
+&gpmc {
+        ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
+
+        nand@0,0 {
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "sw";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,device-width = <2>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */
+
+                x-loader@0 {
+                        label = "xloader";
+                        reg = <0 0x80000>;
+                };
+
+                bootloaders@80000 {
+                        label = "uboot";
+                        reg = <0x80000 0x1e0000>;
+                };
+
+                bootloaders_env@260000 {
+                        label = "uboot-env";
+                        reg = <0x260000 0x20000>;
+                };
+
+                kernel@280000 {
+                        label = "boot";
+                        reg = <0x280000 0xa00000>;
+                };
+
+                filesystem@680000 {
+                        label = "rootfs";
+                        reg = <0xc80000 0>;     /* 0 = MTDPART_SIZ_FULL */
+                };
+        };
+};
+
+&mcspi1 {
+        tsc2046@0 {
+                reg = <0>;      /* CS0 */
+                compatible = "ti,tsc2046";
+                spi-max-frequency = <1000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&penirq_pins>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <30 0>;    /* GPIO_94 */
+                pendown-gpio = <&gpio3 30 0>;
+                vcc-supply = <&vaux4>;
+
+                ti,x-min = /bits/ 16 <0>;
+                ti,x-max = /bits/ 16 <8000>;
+                ti,y-min = /bits/ 16 <0>;
+                ti,y-max = /bits/ 16 <4800>;
+                ti,x-plate-ohms = /bits/ 16 <40>;
+                ti,pressure-max = /bits/ 16 <255>;
+
+                linux,wakeup;
+        };
+
+        lcd: lcd@1 {
+                reg = <1>;      /* CS1 */
+                compatible =    "omapdss,tpo,td043mtea1";
+                spi-max-frequency = <100000>;
+                spi-cpol;
+                spi-cpha;
+
+                label = "lcd";
+                reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;      /* GPIO_157 */
+                vcc-supply = <&vaux1>;
+
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&dpi_out>;
+                        };
+                };
+        };
+
+
+};
+
+/* n/a - used as GPIOs */
+&mcbsp1 {
+};
+
+/* audio DAC */
+&mcbsp2 {
+};
+
+/* bluetooth */
+&mcbsp3 {
+};
+
+/* to twl4030*/
+&mcbsp4 {
+};
+
+&venc {
+        status = "ok";
+
+        vdda-supply = <&vdac>;
+
+        port {
+                venc_out: endpoint {
+                        remote-endpoint = <&tv_connector_in>;
+                        ti,channels = <2>;
+                };
+        };
+};
+
+&dss {
+        pinctrl-names = "default";
+        pinctrl-0 = < &dss_dpi_pins >;
+
+        status = "ok";
+        vdds_dsi-supply = <&vpll2>;
+
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&lcd_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index e89820a6776e..7bd8d9a4f67f 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -8,7 +8,16 @@
  */
 /dts-v1/;
 
-#include "omap34xx-hs.dtsi"
+#include "omap34xx.dtsi"
+
+/* Secure omaps have some devices inaccessible depending on the firmware */
+&aes {
+        status = "disabled";
+};
+
+&sham {
+        status = "disabled";
+};
 
 / {
         cpus {
@@ -45,7 +54,6 @@
 
                 /* McBSP2 is used for onboard sound, same as on beagle */
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         /* Regulator to enable/switch the vcc of the Wifi module */
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
index 6644f516a42b..131448d86e67 100644
--- a/arch/arm/boot/dts/omap3-zoom3.dts
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -195,6 +195,16 @@
         cap-power-off-card;
         pinctrl-names = "default";
         pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */
+                ref-clock-frequency = <26000000>;
+        };
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/omap34xx-hs.dtsi b/arch/arm/boot/dts/omap34xx-hs.dtsi
deleted file mode 100644
index 1ff626489546..000000000000
--- a/arch/arm/boot/dts/omap34xx-hs.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Disabled modules for secure omaps */
-
-#include "omap34xx.dtsi"
-
-/* Secure omaps have some devices inaccessible depending on the firmware */
-&aes {
-        status = "disabled";
-};
-
-&sham {
-        status = "disabled";
-};
-
-&timer12 {
-        status = "disabled";
-};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 3819c1e91591..7bc8c0f72ddb 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/media/omap3-isp.h>
+
 #include "omap3.dtsi"
 
 / {
@@ -37,6 +39,21 @@
                         pinctrl-single,register-width = <16>;
                         pinctrl-single,function-mask = <0xff1f>;
                 };
+
+                isp: isp@480bc000 {
+                        compatible = "ti,omap3-isp";
+                        reg = <0x480bc000 0x12fc
+                               0x480bd800 0x017c>;
+                        interrupts = <24>;
+                        iommus = <&mmu_isp>;
+                        syscon = <&omap3_scm_general 0xdc>;
+                        ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
+                        #clock-cells = <1>;
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/omap36xx-hs.dtsi b/arch/arm/boot/dts/omap36xx-hs.dtsi
deleted file mode 100644
index 2c7febb0e016..000000000000
--- a/arch/arm/boot/dts/omap36xx-hs.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Disabled modules for secure omaps */
-
-#include "omap36xx.dtsi"
-
-/* Secure omaps have some devices inaccessible depending on the firmware */
-&aes {
-        status = "disabled";
-};
-
-&sham {
-        status = "disabled";
-};
-
-&timer12 {
-        status = "disabled";
-};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 541704a59a5a..3502fe00ec7d 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/media/omap3-isp.h>
+
 #include "omap3.dtsi"
 
 / {
@@ -69,6 +71,21 @@
                         pinctrl-single,register-width = <16>;
                         pinctrl-single,function-mask = <0xff1f>;
                 };
+
+                isp: isp@480bc000 {
+                        compatible = "ti,omap3-isp";
+                        reg = <0x480bc000 0x12fc
+                               0x480bd800 0x0600>;
+                        interrupts = <24>;
+                        iommus = <&mmu_isp>;
+                        syscon = <&omap3_scm_general 0x2f0>;
+                        ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+                        #clock-cells = <1>;
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 7c15fb2e2fe4..f1507bc8737e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -448,6 +448,16 @@
         non-removable;
         bus-width = <4>;
         cap-power-off-card;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 
 &emif1 {
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 8aca8dae968a..dac86ed7481f 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -485,6 +485,17 @@
         non-removable;
         bus-width = <4>;
         cap-power-off-card;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1281";
+                reg = <2>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
+                ref-clock-frequency = <26000000>;
+                tcxo-clock-frequency = <26000000>;
+        };
 };
 
 &emif1 {
diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
index cc66af419236..9bceeb7e1f03 100644
--- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
+++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
@@ -65,4 +65,14 @@
         bus-width = <4>;
         cap-power-off-card;
         status = "okay";
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
+                ref-clock-frequency = <38400000>;
+        };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c071652..6c1511263a55 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -23,6 +23,7 @@
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc0>;
                         qcom,saw = <&saw0>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@1 {
@@ -33,6 +34,7 @@
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc1>;
                         qcom,saw = <&saw1>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@2 {
@@ -43,6 +45,7 @@
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc2>;
                         qcom,saw = <&saw2>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@3 {
@@ -53,12 +56,23 @@
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc3>;
                         qcom,saw = <&saw3>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 L2: l2-cache {
                         compatible = "cache";
                         cache-level = <2>;
                 };
+
+                idle-states {
+                        CPU_SPC: spc {
+                                compatible = "qcom,idle-state-spc",
+                                                "arm,idle-state";
+                                entry-latency-us = <400>;
+                                exit-latency-us = <900>;
+                                min-residency-us = <3000>;
+                        };
+                };
         };
 
         cpu-pmu {
@@ -139,26 +153,26 @@
                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
                 };
 
-                saw0: regulator@2089000 {
-                        compatible = "qcom,saw2";
+                saw0: power-controller@2089000 {
+                        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
                         regulator;
                 };
 
-                saw1: regulator@2099000 {
-                        compatible = "qcom,saw2";
+                saw1: power-controller@2099000 {
+                        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
                         regulator;
                 };
 
-                saw2: regulator@20a9000 {
-                        compatible = "qcom,saw2";
+                saw2: power-controller@20a9000 {
+                        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
                         regulator;
                 };
 
-                saw3: regulator@20b9000 {
-                        compatible = "qcom,saw2";
+                saw3: power-controller@20b9000 {
+                        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
                         regulator;
                 };
@@ -166,6 +180,7 @@
                 gsbi1: gsbi@12440000 {
                         status = "disabled";
                         compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <1>;
                         reg = <0x12440000 0x100>;
                         clocks = <&gcc GSBI1_H_CLK>;
                         clock-names = "iface";
@@ -173,6 +188,8 @@
                         #size-cells = <1>;
                         ranges;
 
+                        syscon-tcsr = <&tcsr>;
+
                         i2c1: i2c@12460000 {
                                 compatible = "qcom,i2c-qup-v1.1.1";
                                 reg = <0x12460000 0x1000>;
@@ -187,6 +204,7 @@
                 gsbi2: gsbi@12480000 {
                         status = "disabled";
                         compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <2>;
                         reg = <0x12480000 0x100>;
                         clocks = <&gcc GSBI2_H_CLK>;
                         clock-names = "iface";
@@ -194,6 +212,8 @@
                         #size-cells = <1>;
                         ranges;
 
+                        syscon-tcsr = <&tcsr>;
+
                         i2c2: i2c@124a0000 {
                                 compatible = "qcom,i2c-qup-v1.1.1";
                                 reg = <0x124a0000 0x1000>;
@@ -208,6 +228,7 @@
                 gsbi7: gsbi@16600000 {
                         status = "disabled";
                         compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <7>;
                         reg = <0x16600000 0x100>;
                         clocks = <&gcc GSBI7_H_CLK>;
                         clock-names = "iface";
@@ -215,6 +236,8 @@
                         #size-cells = <1>;
                         ranges;
 
+                        syscon-tcsr = <&tcsr>;
+
                         serial@16640000 {
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x16640000 0x1000>,
@@ -239,6 +262,13 @@
                         #reset-cells = <1>;
                 };
 
+                lcc: clock-controller@28000000 {
+                        compatible = "qcom,lcc-apq8064";
+                        reg = <0x28000000 0x1000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+
                 mmcc: clock-controller@4000000 {
                         compatible = "qcom,mmcc-apq8064";
                         reg = <0x4000000 0x1000>;
@@ -349,5 +379,10 @@
                                 pinctrl-0 = <&sdc4_gpios>;
                         };
                 };
+
+                tcsr: syscon@1a400000 {
+                        compatible = "qcom,tcsr-apq8064", "syscon";
+                        reg = <0x1a400000 0x100>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 47370494d0f8..d484d08163e9 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -1,4 +1,6 @@
 #include "qcom-msm8974.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
 
 / {
         model = "Qualcomm APQ8074 Dragonboard";
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index c9ff10821ad9..f7725b96612c 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -1,4 +1,5 @@
 #include "qcom-apq8084.dtsi"
+#include "qcom-pma8084.dtsi"
 
 / {
         model = "Qualcomm APQ8084/IFC6540";
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
index 8ecec58a9ff6..cb43acfc5d1d 100644
--- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -1,4 +1,5 @@
 #include "qcom-apq8084.dtsi"
+#include "qcom-pma8084.dtsi"
 
 / {
         model = "Qualcomm APQ 8084-MTP";
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 1f130bc16858..7084010ee61b 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -21,6 +21,8 @@
                         enable-method = "qcom,kpss-acc-v2";
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc0>;
+                        qcom,saw = <&saw0>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@1 {
@@ -30,6 +32,8 @@
                         enable-method = "qcom,kpss-acc-v2";
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc1>;
+                        qcom,saw = <&saw1>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@2 {
@@ -39,6 +43,8 @@
                         enable-method = "qcom,kpss-acc-v2";
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc2>;
+                        qcom,saw = <&saw2>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@3 {
@@ -48,6 +54,8 @@
                         enable-method = "qcom,kpss-acc-v2";
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc3>;
+                        qcom,saw = <&saw3>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 L2: l2-cache {
@@ -55,6 +63,16 @@
                         cache-level = <2>;
                         qcom,saw = <&saw_l2>;
                 };
+
+                idle-states {
+                        CPU_SPC: spc {
+                                compatible = "qcom,idle-state-spc",
+                                                "arm,idle-state";
+                                entry-latency-us = <150>;
+                                exit-latency-us = <200>;
+                                min-residency-us = <2000>;
+                        };
+                };
         };
 
         cpu-pmu {
@@ -144,7 +162,27 @@
                         };
                 };
 
-                saw_l2: regulator@f9012000 {
+                saw0: power-controller@f9089000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw1: power-controller@f9099000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw2: power-controller@f90a9000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw3: power-controller@f90b9000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw_l2: power-controller@f9012000 {
                         compatible = "qcom,saw2";
                         reg = <0xf9012000 0x1000>;
                         regulator;
@@ -226,5 +264,21 @@
                         clock-names = "core", "iface";
                         status = "disabled";
                 };
+
+                spmi_bus: spmi@fc4cf000 {
+                        compatible = "qcom,spmi-pmic-arb";
+                        reg-names = "core", "intr", "cnfg";
+                        reg = <0xfc4cf000 0x1000>,
+                              <0xfc4cb000 0x1000>,
+                              <0xfc4ca000 0x1000>;
+                        interrupt-names = "periph_irq";
+                        interrupts = <0 190 0>;
+                        qcom,ee = <0>;
+                        qcom,channel = <0>;
+                        #address-cells = <2>;
+                        #size-cells = <0>;
+                        interrupt-controller;
+                        #interrupt-cells = <4>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index cb225dafe97c..1bc5fdd0e4b3 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
 
 / {
@@ -66,6 +67,21 @@
                 ranges;
                 compatible = "simple-bus";
 
+                lpass@28100000 {
+                        compatible = "qcom,lpass-cpu";
+                        status = "disabled";
+                        clocks = <&lcc AHBIX_CLK>,
+                                        <&lcc MI2S_OSR_CLK>,
+                                        <&lcc MI2S_BIT_CLK>;
+                        clock-names = "ahbix-clk",
+                                        "mi2s-osr-clk",
+                                        "mi2s-bit-clk";
+                        interrupts = <0 85 1>;
+                        interrupt-names = "lpass-irq-lpaif";
+                        reg = <0x28100000 0x10000>;
+                        reg-names = "lpass-lpaif";
+                };
+
                 qcom_pinmux: pinmux@800000 {
                         compatible = "qcom,ipq8064-pinctrl";
                         reg = <0x800000 0x4000>;
@@ -120,6 +136,7 @@
 
                 gsbi2: gsbi@12480000 {
                         compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <2>;
                         reg = <0x12480000 0x100>;
                         clocks = <&gcc GSBI2_H_CLK>;
                         clock-names = "iface";
@@ -128,6 +145,8 @@
                         ranges;
                         status = "disabled";
 
+                        syscon-tcsr = <&tcsr>;
+
                         serial@12490000 {
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x12490000 0x1000>,
@@ -155,6 +174,7 @@
 
                 gsbi4: gsbi@16300000 {
                         compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <4>;
                         reg = <0x16300000 0x100>;
                         clocks = <&gcc GSBI4_H_CLK>;
                         clock-names = "iface";
@@ -163,6 +183,8 @@
                         ranges;
                         status = "disabled";
 
+                        syscon-tcsr = <&tcsr>;
+
                         serial@16340000 {
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x16340000 0x1000>,
@@ -189,6 +211,7 @@
 
                 gsbi5: gsbi@1a200000 {
                         compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <5>;
                         reg = <0x1a200000 0x100>;
                         clocks = <&gcc GSBI5_H_CLK>;
                         clock-names = "iface";
@@ -197,6 +220,8 @@
                         ranges;
                         status = "disabled";
 
+                        syscon-tcsr = <&tcsr>;
+
                         serial@1a240000 {
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x1a240000 0x1000>,
@@ -279,5 +304,18 @@
                         #clock-cells = <1>;
                         #reset-cells = <1>;
                 };
+
+                tcsr: syscon@1a400000 {
+                        compatible = "qcom,tcsr-ipq8064", "syscon";
+                        reg = <0x1a400000 0x100>;
+                };
+
+                lcc: clock-controller@28000000 {
+                        compatible = "qcom,lcc-ipq8064";
+                        reg = <0x28000000 0x1000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+
         };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 0affd6193f56..20bbd19b996e 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -82,6 +82,7 @@
 
                 gsbi12: gsbi@19c00000 {
                         compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <12>;
                         reg = <0x19c00000 0x100>;
                         clocks = <&gcc GSBI12_H_CLK>;
                         clock-names = "iface";
@@ -89,6 +90,8 @@
                         #size-cells = <1>;
                         ranges;
 
+                        syscon-tcsr = <&tcsr>;
+
                         serial@19c40000 {
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x19c40000 0x1000>,
@@ -196,6 +199,11 @@
                                 vmmc-supply = <&vsdcc_fixed>;
                         };
                 };
+
+                tcsr: syscon@1a400000 {
+                        compatible = "qcom,tcsr-msm8660", "syscon";
+                        reg = <0x1a400000 0x100>;
+                };
         };
 
 };
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index e1b0d5cd9e3c..a02b984cc68d 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -91,6 +91,13 @@
                         reg = <0x900000 0x4000>;
                 };
 
+                lcc: clock-controller@28000000 {
+                        compatible = "qcom,lcc-msm8960";
+                        reg = <0x28000000 0x1000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+
                 clock-controller@4000000 {
                         compatible = "qcom,mmcc-msm8960";
                         reg = <0x4000000 0x1000>;
@@ -122,6 +129,7 @@
 
                 gsbi5: gsbi@16400000 {
                         compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <5>;
                         reg = <0x16400000 0x100>;
                         clocks = <&gcc GSBI5_H_CLK>;
                         clock-names = "iface";
@@ -129,6 +137,8 @@
                         #size-cells = <1>;
                         ranges;
 
+                        syscon-tcsr = <&tcsr>;
+
                         serial@16440000 {
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x16440000 0x1000>,
@@ -238,5 +248,10 @@
                                 vmmc-supply = <&vsdcc_fixed>;
                         };
                 };
+
+                tcsr: syscon@1a400000 {
+                        compatible = "qcom,tcsr-msm8960", "syscon";
+                        reg = <0x1a400000 0x100>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
index cccc21b7c8fd..bd35b0674ff6 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
@@ -1,4 +1,6 @@
 #include "qcom-msm8974.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
 
 / {
         model = "Sony Xperia Z1";
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index e265ec16a787..37b47b5538b8 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -21,6 +21,8 @@
                         reg = <0>;
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc0>;
+                        qcom,saw = <&saw0>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@1 {
@@ -30,6 +32,8 @@
                         reg = <1>;
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc1>;
+                        qcom,saw = <&saw1>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@2 {
@@ -39,6 +43,8 @@
                         reg = <2>;
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc2>;
+                        qcom,saw = <&saw2>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@3 {
@@ -48,6 +54,8 @@
                         reg = <3>;
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc3>;
+                        qcom,saw = <&saw3>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 L2: l2-cache {
@@ -55,6 +63,16 @@
                         cache-level = <2>;
                         qcom,saw = <&saw_l2>;
                 };
+
+                idle-states {
+                        CPU_SPC: spc {
+                                compatible = "qcom,idle-state-spc",
+                                                "arm,idle-state";
+                                entry-latency-us = <150>;
+                                exit-latency-us = <200>;
+                                min-residency-us = <2000>;
+                        };
+                };
         };
 
         cpu-pmu {
@@ -144,7 +162,27 @@
                         };
                 };
 
-                saw_l2: regulator@f9012000 {
+                saw0: power-controller@f9089000 {
+                        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw1: power-controller@f9099000 {
+                        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw2: power-controller@f90a9000 {
+                        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw3: power-controller@f90b9000 {
+                        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw_l2: power-controller@f9012000 {
                         compatible = "qcom,saw2";
                         reg = <0xf9012000 0x1000>;
                         regulator;
@@ -247,5 +285,21 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                 };
+
+                spmi_bus: spmi@fc4cf000 {
+                        compatible = "qcom,spmi-pmic-arb";
+                        reg-names = "core", "intr", "cnfg";
+                        reg = <0xfc4cf000 0x1000>,
+                              <0xfc4cb000 0x1000>,
+                              <0xfc4ca000 0x1000>;
+                        interrupt-names = "periph_irq";
+                        interrupts = <0 190 0>;
+                        qcom,ee = <0>;
+                        qcom,channel = <0>;
+                        #address-cells = <2>;
+                        #size-cells = <0>;
+                        interrupt-controller;
+                        #interrupt-cells = <4>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi
new file mode 100644
index 000000000000..73813cc118f9
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+        usid4: pm8841@4 {
+                compatible = "qcom,spmi-pmic";
+                reg = <0x4 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        usid5: pm8841@5 {
+                compatible = "qcom,spmi-pmic";
+                reg = <0x5 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
new file mode 100644
index 000000000000..24c5088acea2
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+        usid0: pm8941@0 {
+                compatible ="qcom,spmi-pmic";
+                reg = <0x0 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        usid1: pm8941@1 {
+                compatible ="qcom,spmi-pmic";
+                reg = <0x1 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi
new file mode 100644
index 000000000000..a5a4fe695a46
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+        usid0: pma8084@0 {
+                compatible = "qcom,spmi-pmic";
+                reg = <0x0 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        usid1: pma8084@1 {
+                compatible = "qcom,spmi-pmic";
+                reg = <0x1 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 0d50bef01234..d1b6a07253ae 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -95,27 +95,27 @@
         leds {
                 compatible = "gpio-leds";
                 led1 {
-                        gpios = <&pfc 28 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 28 GPIO_ACTIVE_HIGH>;
                         label = "GNSS_EN";
                 };
                 led2 {
-                        gpios = <&pfc 126 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 126 GPIO_ACTIVE_HIGH>;
                         label = "NFC_NRST";
                 };
                 led3 {
-                        gpios = <&pfc 132 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 132 GPIO_ACTIVE_HIGH>;
                         label = "GNSS_NRST";
                 };
                 led4 {
-                        gpios = <&pfc 232 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 232 GPIO_ACTIVE_HIGH>;
                         label = "BT_WAKEUP";
                 };
                 led5 {
-                        gpios = <&pfc 250 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 250 GPIO_ACTIVE_HIGH>;
                         label = "STROBE";
                 };
                 led6 {
-                        gpios = <&pfc 288 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 288 GPIO_ACTIVE_HIGH>;
                         label = "BBRESETOUT";
                 };
         };
@@ -123,10 +123,14 @@
         keyboard {
                 compatible = "gpio-keys";
 
+                pinctrl-names = "default";
+                pinctrl-0 = <&keyboard_pins>;
+
                 zero-key {
                         gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_0>;
                         label = "S16";
+                        gpio-key,wakeup;
                 };
 
                 menu-key {
@@ -208,6 +212,12 @@
                 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
                 renesas,function = "sdhi1";
         };
+
+        keyboard_pins: keyboard {
+                renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327",
+                               "PORT328", "PORT329";
+                bias-pull-up;
+        };
 };
 
 &mmcif0 {
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 8a092605d641..83c1c3ca1b8f 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -431,6 +431,18 @@
                         clock-frequency = <27000000>;
                         clock-output-names = "dv";
                 };
+                fmsick_clk: fmsick_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "fmsick";
+                };
+                fmsock_clk: fmsock_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "fmsock";
+                };
                 fsiack_clk: fsiack_clk {
                         compatible = "fixed-clock";
                         #clock-cells = <0>;
@@ -459,13 +471,78 @@
                 };
 
                 /* Variable factor clocks (DIV6) */
+                vclk1_clk: vclk1_clk@e6150008 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150008 4>;
+                        clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
+                                 <&cpg_clocks R8A7740_CLK_USB24S>,
+                                 <&extal1_div2_clk>, <&extalr_clk>, <0>,
+                                 <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk1";
+                };
+                vclk2_clk: vclk2_clk@e615000c {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615000c 4>;
+                        clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
+                                 <&cpg_clocks R8A7740_CLK_USB24S>,
+                                 <&extal1_div2_clk>, <&extalr_clk>, <0>,
+                                 <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk2";
+                };
+                fmsi_clk: fmsi_clk@e6150010 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150010 4>;
+                        clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fmsi";
+                };
+                fmso_clk: fmso_clk@e6150014 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150014 4>;
+                        clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fmso";
+                };
+                fsia_clk: fsia_clk@e6150018 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150018 4>;
+                        clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fsia";
+                };
                 sub_clk: sub_clk@e6150080 {
                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150080 4>;
-                        clocks = <&pllc1_div2_clk>;
+                        clocks = <&pllc1_div2_clk>,
+                                 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "sub";
                 };
+                spu_clk: spu_clk@e6150084 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150084 4>;
+                        clocks = <&pllc1_div2_clk>,
+                                 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "spu";
+                };
+                vou_clk: vou_clk@e6150088 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150088 4>;
+                        clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
+                                 <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vou";
+                };
+                stpro_clk: stpro_clk@e615009c {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615009c 4>;
+                        clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "stpro";
+                };
 
                 /* Fixed factor clocks */
                 pllc1_div2_clk: pllc1_div2_clk {
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index e83d40e24bcd..540756cdf391 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -122,6 +122,12 @@
                         };
                 };
         };
+
+        x3_clk: x3-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <65000000>;
+        };
 };
 
 &du {
@@ -129,6 +135,9 @@
         pinctrl-names = "default";
         status = "okay";
 
+        clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
+        clock-names = "du", "dclkin.0";
+
         ports {
                 port@0 {
                         endpoint {
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 2a0f895c48d0..aaa4f258e279 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -222,6 +222,29 @@
                         };
                 };
         };
+
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con: endpoint {
+                                remote-endpoint = <&adv7511_out>;
+                        };
+                };
+        };
+
+        x2_clk: x2-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
+
+        x13_clk: x13-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
 };
 
 &du {
@@ -229,12 +252,26 @@
         pinctrl-names = "default";
         status = "okay";
 
+        clocks = <&mstp7_clks R8A7790_CLK_DU0>,
+                 <&mstp7_clks R8A7790_CLK_DU1>,
+                 <&mstp7_clks R8A7790_CLK_DU2>,
+                 <&mstp7_clks R8A7790_CLK_LVDS0>,
+                 <&mstp7_clks R8A7790_CLK_LVDS1>,
+                 <&x13_clk>, <&x2_clk>;
+        clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
+                      "dclkin.0", "dclkin.1";
+
         ports {
                 port@0 {
                         endpoint {
                                 remote-endpoint = <&adv7123_in>;
                         };
                 };
+                port@1 {
+                        endpoint {
+                                remote-endpoint = <&adv7511_in>;
+                        };
+                };
                 port@2 {
                         lvds_connector: endpoint {
                         };
@@ -506,6 +543,38 @@
                         };
                 };
         };
+
+        hdmi@39 {
+                compatible = "adi,adv7511w";
+                reg = <0x39>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&du_out_lvds0>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con>;
+                                };
+                        };
+                };
+        };
 };
 
 &iic3 {
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 4b38fc920114..4bb2f4c17321 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1,6 +1,7 @@
 /*
  * Device Tree Source for the r8a7790 SoC
  *
+ * Copyright (C) 2015 Renesas Electronics Corporation
  * Copyright (C) 2013-2014 Renesas Solutions Corp.
  * Copyright (C) 2014 Cogent Embedded Inc.
  *
@@ -369,13 +370,6 @@
                 dma-channels = <13>;
         };
 
-        audmapp: dma-controller@ec740000 {
-                compatible = "renesas,rcar-audmapp";
-                #dma-cells = <1>;
-
-                reg = <0 0xec740000 0 0x200>;
-        };
-
         i2c0: i2c@e6508000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -493,17 +487,21 @@
 
         sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-r8a7790";
-                reg = <0 0xee100000 0 0x200>;
+                reg = <0 0xee100000 0 0x328>;
                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
+                dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
         sdhi1: sd@ee120000 {
                 compatible = "renesas,sdhi-r8a7790";
-                reg = <0 0xee120000 0 0x200>;
+                reg = <0 0xee120000 0 0x328>;
                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
+                dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -512,6 +510,8 @@
                 reg = <0 0xee140000 0 0x100>;
                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
+                dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -520,6 +520,8 @@
                 reg = <0 0xee160000 0 0x100>;
                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
+                dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -792,6 +794,26 @@
                 };
         };
 
+        can0: can@e6e80000 {
+                compatible = "renesas,can-r8a7790";
+                reg = <0 0xe6e80000 0 0x1000>;
+                interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
+                         <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
+
+        can1: can@e6e88000 {
+                compatible = "renesas,can-r8a7790";
+                reg = <0 0xe6e88000 0 0x1000>;
+                interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
+                         <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
+
         clocks {
                 #address-cells = <2>;
                 #size-cells = <2>;
@@ -838,16 +860,34 @@
                         clock-output-names = "audio_clk_c";
                 };
 
+                /* External USB clock - can be overridden by the board */
+                usb_extal_clk: usb_extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <48000000>;
+                        clock-output-names = "usb_extal";
+                };
+
+                /* External CAN clock */
+                can_clk: can_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overridden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "can_clk";
+                        status = "disabled";
+                };
+
                 /* Special CPG clocks */
                 cpg_clocks: cpg_clocks@e6150000 {
                         compatible = "renesas,r8a7790-cpg-clocks",
                                      "renesas,rcar-gen2-cpg-clocks";
                         reg = <0 0xe6150000 0 0x1000>;
-                        clocks = <&extal_clk>;
+                        clocks = <&extal_clk &usb_extal_clk>;
                         #clock-cells = <1>;
                         clock-output-names = "main", "pll0", "pll1", "pll3",
                                              "lb", "qspi", "sdh", "sd0", "sd1",
-                                             "z";
+                                             "z", "rcan", "adsp";
                 };
 
                 /* Variable factor clocks */
@@ -1121,18 +1161,21 @@
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-                        clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
+                        clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
+                                 <&extal_clk>, <&p_clk>;
                         #clock-cells = <1>;
                         clock-indices = <
                                 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
-                                R8A7790_CLK_THERMAL R8A7790_CLK_PWM
+                                R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
+                                R8A7790_CLK_PWM
                         >;
-                        clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
+                        clock-output-names = "audmac0", "audmac1", "adsp_mod",
+                                             "thermal", "pwm";
                 };
                 mstp7_clks: mstp7_clks@e615014c {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
-                        clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+                        clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
                                  <&zx_clk>;
                         #clock-cells = <1>;
@@ -1410,7 +1453,10 @@
                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
                         <0 0xec5a0000 0 0x100>,  /* ADG */
                         <0 0xec540000 0 0x1000>, /* SSIU */
-                        <0 0xec541000 0 0x1280>; /* SSI */
+                        <0 0xec541000 0 0x1280>, /* SSI */
+                        <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
@@ -1435,34 +1481,171 @@
                 status = "disabled";
 
                 rcar_sound,dvc {
-                        dvc0: dvc@0 { };
-                        dvc1: dvc@1 { };
+                        dvc0: dvc@0 {
+                                dmas = <&audma0 0xbc>;
+                                dma-names = "tx";
+                        };
+                        dvc1: dvc@1 {
+                                dmas = <&audma0 0xbe>;
+                                dma-names = "tx";
+                        };
                 };
 
                 rcar_sound,src {
-                        src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
-                        src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
-                        src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
-                        src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
-                        src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
-                        src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
-                        src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
-                        src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
-                        src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
-                        src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
+                        src0: src@0 {
+                                interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x85>, <&audma1 0x9a>;
+                                dma-names = "rx", "tx";
+                        };
+                        src1: src@1 {
+                                interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x87>, <&audma1 0x9c>;
+                                dma-names = "rx", "tx";
+                        };
+                        src2: src@2 {
+                                interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                dma-names = "rx", "tx";
+                        };
+                        src3: src@3 {
+                                interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                dma-names = "rx", "tx";
+                        };
+                        src4: src@4 {
+                                interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                dma-names = "rx", "tx";
+                        };
+                        src5: src@5 {
+                                interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                dma-names = "rx", "tx";
+                        };
+                        src6: src@6 {
+                                interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                dma-names = "rx", "tx";
+                        };
+                        src7: src@7 {
+                                interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                dma-names = "rx", "tx";
+                        };
+                        src8: src@8 {
+                                interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                dma-names = "rx", "tx";
+                        };
+                        src9: src@9 {
+                                interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                dma-names = "rx", "tx";
+                        };
                 };
 
                 rcar_sound,ssi {
-                        ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi0: ssi@0 {
+                                interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi1: ssi@1 {
+                                 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi2: ssi@2 {
+                                interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi3: ssi@3 {
+                                interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi4: ssi@4 {
+                                interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi5: ssi@5 {
+                                interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi6: ssi@6 {
+                                interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi7: ssi@7 {
+                                interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi8: ssi@8 {
+                                interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi9: ssi@9 {
+                                interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
                 };
         };
+
+        ipmmu_sy0: mmu@e6280000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6280000 0 0x1000>;
+                interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 224 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_sy1: mmu@e6290000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6290000 0 0x1000>;
+                interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_ds: mmu@e6740000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6740000 0 0x1000>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_mp: mmu@ec680000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xec680000 0 0x1000>;
+                interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_mx: mmu@fe951000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xfe951000 0 0x1000>;
+                interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 221 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_rt: mmu@ffc80000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xffc80000 0 0x1000>;
+                interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index d2ebf11f9881..e33e4047b0b0 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -141,6 +141,11 @@
                 renesas,groups = "vin0_data8", "vin0_clk";
                 renesas,function = "vin0";
         };
+
+        can0_pins: can0 {
+                renesas,groups = "can0_data";
+                renesas,function = "can0";
+        };
 };
 
 &scif0 {
@@ -307,3 +312,9 @@
                 };
         };
 };
+
+&can0 {
+        pinctrl-0 = <&can0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index b2dcf640d583..74c3212f1f11 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -258,6 +258,29 @@
                         system-clock-frequency = <11289600>;
                 };
         };
+
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con: endpoint {
+                                remote-endpoint = <&adv7511_out>;
+                        };
+                };
+        };
+
+        x2_clk: x2-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
+
+        x13_clk: x13-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
 };
 
 &du {
@@ -265,7 +288,19 @@
         pinctrl-names = "default";
         status = "okay";
 
+        clocks = <&mstp7_clks R8A7791_CLK_DU0>,
+                 <&mstp7_clks R8A7791_CLK_DU1>,
+                 <&mstp7_clks R8A7791_CLK_LVDS0>,
+                 <&x13_clk>, <&x2_clk>;
+        clock-names = "du.0", "du.1", "lvds.0",
+                      "dclkin.0", "dclkin.1";
+
         ports {
+                port@0 {
+                        endpoint {
+                                remote-endpoint = <&adv7511_in>;
+                        };
+                };
                 port@1 {
                         lvds_connector: endpoint {
                         };
@@ -284,7 +319,7 @@
         };
 
         du_pins: du {
-                renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0";
+                renesas,groups = "du_rgb666", "du_sync", "du_disp", "du_clk_out_0";
                 renesas,function = "du";
         };
 
@@ -506,6 +541,38 @@
                 };
         };
 
+        hdmi@39 {
+                compatible = "adi,adv7511w";
+                reg = <0x39>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con>;
+                                };
+                        };
+                };
+        };
+
         eeprom@50 {
                 compatible = "renesas,24c02";
                 reg = <0x50>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e35812a0d8d4..4696062f6dde 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for the r8a7791 SoC
  *
- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2015 Renesas Electronics Corporation
  * Copyright (C) 2013-2014 Renesas Solutions Corp.
  * Copyright (C) 2014 Cogent Embedded Inc.
  *
@@ -357,13 +357,6 @@
                 dma-channels = <13>;
         };
 
-        audmapp: dma-controller@ec740000 {
-                compatible = "renesas,rcar-audmapp";
-                #dma-cells = <1>;
-
-                reg = <0 0xec740000 0 0x200>;
-        };
-
         /* The memory map in the User's Manual maps the cores to bus numbers */
         i2c0: i2c@e6508000 {
                 #address-cells = <1>;
@@ -482,9 +475,11 @@
 
         sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-r8a7791";
-                reg = <0 0xee100000 0 0x200>;
+                reg = <0 0xee100000 0 0x328>;
                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
+                dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -493,6 +488,8 @@
                 reg = <0 0xee140000 0 0x100>;
                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
+                dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -501,6 +498,8 @@
                 reg = <0 0xee160000 0 0x100>;
                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
+                dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -816,6 +815,26 @@
                 };
         };
 
+        can0: can@e6e80000 {
+                compatible = "renesas,can-r8a7791";
+                reg = <0 0xe6e80000 0 0x1000>;
+                interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
+                         <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
+
+        can1: can@e6e88000 {
+                compatible = "renesas,can-r8a7791";
+                reg = <0 0xe6e88000 0 0x1000>;
+                interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
+                         <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
+
         clocks {
                 #address-cells = <2>;
                 #size-cells = <2>;
@@ -862,31 +881,50 @@
                         status = "disabled";
                 };
 
+                /* External USB clock - can be overridden by the board */
+                usb_extal_clk: usb_extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <48000000>;
+                        clock-output-names = "usb_extal";
+                };
+
+                /* External CAN clock */
+                can_clk: can_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overridden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "can_clk";
+                        status = "disabled";
+                };
+
                 /* Special CPG clocks */
                 cpg_clocks: cpg_clocks@e6150000 {
                         compatible = "renesas,r8a7791-cpg-clocks",
                                      "renesas,rcar-gen2-cpg-clocks";
                         reg = <0 0xe6150000 0 0x1000>;
-                        clocks = <&extal_clk>;
+                        clocks = <&extal_clk &usb_extal_clk>;
                         #clock-cells = <1>;
                         clock-output-names = "main", "pll0", "pll1", "pll3",
-                                             "lb", "qspi", "sdh", "sd0", "z";
+                                             "lb", "qspi", "sdh", "sd0", "z",
+                                             "rcan", "adsp";
                 };
 
                 /* Variable factor clocks */
-                sd1_clk: sd2_clk@e6150078 {
+                sd2_clk: sd2_clk@e6150078 {
                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0 0xe6150078 0 4>;
                         clocks = <&pll1_div2_clk>;
                         #clock-cells = <0>;
-                        clock-output-names = "sd1";
+                        clock-output-names = "sd2";
                 };
-                sd2_clk: sd3_clk@e615026c {
+                sd3_clk: sd3_clk@e615026c {
                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0 0xe615026c 0 4>;
                         clocks = <&pll1_div2_clk>;
                         #clock-cells = <0>;
-                        clock-output-names = "sd2";
+                        clock-output-names = "sd3";
                 };
                 mmc0_clk: mmc0_clk@e6150240 {
                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
@@ -1107,7 +1145,7 @@
                 mstp3_clks: mstp3_clks@e615013c {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-                        clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
+                        clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
                                  <&hp_clk>, <&hp_clk>;
                         #clock-cells = <1>;
@@ -1125,18 +1163,21 @@
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-                        clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
+                        clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
+                                 <&extal_clk>, <&p_clk>;
                         #clock-cells = <1>;
                         clock-indices = <
                                 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
-                                R8A7791_CLK_THERMAL R8A7791_CLK_PWM
+                                R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
+                                R8A7791_CLK_PWM
                         >;
-                        clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
+                        clock-output-names = "audmac0", "audmac1", "adsp_mod",
+                                             "thermal", "pwm";
                 };
                 mstp7_clks: mstp7_clks@e615014c {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
-                        clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+                        clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
                         #clock-cells = <1>;
@@ -1154,7 +1195,7 @@
                 mstp8_clks: mstp8_clks@e6150990 {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-                        clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
+                        clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
                                  <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
                         #clock-cells = <1>;
                         clock-indices = <
@@ -1384,6 +1425,66 @@
                 status = "disabled";
         };
 
+        ipmmu_sy0: mmu@e6280000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6280000 0 0x1000>;
+                interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 224 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_sy1: mmu@e6290000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6290000 0 0x1000>;
+                interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_ds: mmu@e6740000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6740000 0 0x1000>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_mp: mmu@ec680000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xec680000 0 0x1000>;
+                interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_mx: mmu@fe951000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xfe951000 0 0x1000>;
+                interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 221 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_rt: mmu@ffc80000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xffc80000 0 0x1000>;
+                interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_gp: mmu@e62a0000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe62a0000 0 0x1000>;
+                interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 261 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
         rcar_sound: rcar_sound@ec500000 {
                 /*
                  * #sound-dai-cells is required
@@ -1395,7 +1496,10 @@
                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
                         <0 0xec5a0000 0 0x100>,  /* ADG */
                         <0 0xec540000 0 0x1000>, /* SSIU */
-                        <0 0xec541000 0 0x1280>; /* SSI */
+                        <0 0xec541000 0 0x1280>, /* SSI */
+                        <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
@@ -1420,34 +1524,120 @@
                 status = "disabled";
 
                 rcar_sound,dvc {
-                        dvc0: dvc@0 { };
-                        dvc1: dvc@1 { };
+                        dvc0: dvc@0 {
+                                dmas = <&audma0 0xbc>;
+                                dma-names = "tx";
+                        };
+                        dvc1: dvc@1 {
+                                dmas = <&audma0 0xbe>;
+                                dma-names = "tx";
+                        };
                 };
 
                 rcar_sound,src {
-                        src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
-                        src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
-                        src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
-                        src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
-                        src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
-                        src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
-                        src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
-                        src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
-                        src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
-                        src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
+                        src0: src@0 {
+                                interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x85>, <&audma1 0x9a>;
+                                dma-names = "rx", "tx";
+                        };
+                        src1: src@1 {
+                                interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x87>, <&audma1 0x9c>;
+                                dma-names = "rx", "tx";
+                        };
+                        src2: src@2 {
+                                interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                dma-names = "rx", "tx";
+                        };
+                        src3: src@3 {
+                                interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                dma-names = "rx", "tx";
+                        };
+                        src4: src@4 {
+                                interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                dma-names = "rx", "tx";
+                        };
+                        src5: src@5 {
+                                interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                dma-names = "rx", "tx";
+                        };
+                        src6: src@6 {
+                                interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                dma-names = "rx", "tx";
+                        };
+                        src7: src@7 {
+                                interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                dma-names = "rx", "tx";
+                        };
+                        src8: src@8 {
+                                interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                dma-names = "rx", "tx";
+                        };
+                        src9: src@9 {
+                                interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                dma-names = "rx", "tx";
+                        };
                 };
 
                 rcar_sound,ssi {
-                        ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi0: ssi@0 {
+                                interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi1: ssi@1 {
+                                 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi2: ssi@2 {
+                                interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi3: ssi@3 {
+                                interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi4: ssi@4 {
+                                interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi5: ssi@5 {
+                                interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi6: ssi@6 {
+                                interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi7: ssi@7 {
+                                interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi8: ssi@8 {
+                                interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi9: ssi@9 {
+                                interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 0d848e605071..928cfa641475 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -43,6 +43,19 @@
         status = "okay";
 };
 
+&ether {
+        phy-handle = <&phy1>;
+        renesas,ether-link-active-low;
+        status = "okay";
+
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+                micrel,led-mode = <1>;
+        };
+};
+
 &scif2 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 8f78da5ef10b..7a3ffa51a8bf 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -107,6 +107,66 @@
                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
         };
 
+        dmac0: dma-controller@e6700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6700000 0 0x20000>;
+                interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
+                              0 200 IRQ_TYPE_LEVEL_HIGH
+                              0 201 IRQ_TYPE_LEVEL_HIGH
+                              0 202 IRQ_TYPE_LEVEL_HIGH
+                              0 203 IRQ_TYPE_LEVEL_HIGH
+                              0 204 IRQ_TYPE_LEVEL_HIGH
+                              0 205 IRQ_TYPE_LEVEL_HIGH
+                              0 206 IRQ_TYPE_LEVEL_HIGH
+                              0 207 IRQ_TYPE_LEVEL_HIGH
+                              0 208 IRQ_TYPE_LEVEL_HIGH
+                              0 209 IRQ_TYPE_LEVEL_HIGH
+                              0 210 IRQ_TYPE_LEVEL_HIGH
+                              0 211 IRQ_TYPE_LEVEL_HIGH
+                              0 212 IRQ_TYPE_LEVEL_HIGH
+                              0 213 IRQ_TYPE_LEVEL_HIGH
+                              0 214 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
+
+        dmac1: dma-controller@e6720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6720000 0 0x20000>;
+                interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+                              0 216 IRQ_TYPE_LEVEL_HIGH
+                              0 217 IRQ_TYPE_LEVEL_HIGH
+                              0 218 IRQ_TYPE_LEVEL_HIGH
+                              0 219 IRQ_TYPE_LEVEL_HIGH
+                              0 308 IRQ_TYPE_LEVEL_HIGH
+                              0 309 IRQ_TYPE_LEVEL_HIGH
+                              0 310 IRQ_TYPE_LEVEL_HIGH
+                              0 311 IRQ_TYPE_LEVEL_HIGH
+                              0 312 IRQ_TYPE_LEVEL_HIGH
+                              0 313 IRQ_TYPE_LEVEL_HIGH
+                              0 314 IRQ_TYPE_LEVEL_HIGH
+                              0 315 IRQ_TYPE_LEVEL_HIGH
+                              0 316 IRQ_TYPE_LEVEL_HIGH
+                              0 317 IRQ_TYPE_LEVEL_HIGH
+                              0 318 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
+
         scifa0: serial@e6c40000 {
                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
                 reg = <0 0xe6c40000 0 64>;
@@ -269,6 +329,41 @@
                 status = "disabled";
         };
 
+        ether: ethernet@ee700000 {
+                compatible = "renesas,ether-r8a7794";
+                reg = <0 0xee700000 0 0x400>;
+                interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
+                phy-mode = "rmii";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        sdhi0: sd@ee100000 {
+                compatible = "renesas,sdhi-r8a7794";
+                reg = <0 0xee100000 0 0x200>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
+                status = "disabled";
+        };
+
+        sdhi1: sd@ee140000 {
+                compatible = "renesas,sdhi-r8a7794";
+                reg = <0 0xee140000 0 0x100>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
+                status = "disabled";
+        };
+
+        sdhi2: sd@ee160000 {
+                compatible = "renesas,sdhi-r8a7794";
+                reg = <0 0xee160000 0 0x100>;
+                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
+                status = "disabled";
+        };
+
         clocks {
                 #address-cells = <2>;
                 #size-cells = <2>;
@@ -294,19 +389,19 @@
                                              "lb", "qspi", "sdh", "sd0", "z";
                 };
                 /* Variable factor clocks */
-                sd1_clk: sd2_clk@e6150078 {
+                sd2_clk: sd2_clk@e6150078 {
                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0 0xe6150078 0 4>;
                         clocks = <&pll1_div2_clk>;
                         #clock-cells = <0>;
-                        clock-output-names = "sd1";
+                        clock-output-names = "sd2";
                 };
-                sd2_clk: sd3_clk@e615007c {
+                sd3_clk: sd3_clk@e615026c {
                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
-                        reg = <0 0xe615007c 0 4>;
+                        reg = <0 0xe615026c 0 4>;
                         clocks = <&pll1_div2_clk>;
                         #clock-cells = <0>;
-                        clock-output-names = "sd2";
+                        clock-output-names = "sd3";
                 };
                 mmc0_clk: mmc0_clk@e6150240 {
                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
@@ -518,7 +613,7 @@
                 mstp3_clks: mstp3_clks@e615013c {
                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-                        clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
+                        clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
                                  <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
                         #clock-cells = <1>;
                         clock-indices = <
@@ -585,4 +680,54 @@
                         clock-output-names = "scifa3", "scifa4", "scifa5";
                 };
         };
+
+        ipmmu_sy0: mmu@e6280000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6280000 0 0x1000>;
+                interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 224 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_sy1: mmu@e6290000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6290000 0 0x1000>;
+                interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_ds: mmu@e6740000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6740000 0 0x1000>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+        };
+
+        ipmmu_mp: mmu@ec680000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xec680000 0 0x1000>;
+                interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+
+        ipmmu_mx: mmu@fe951000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xfe951000 0 0x1000>;
+                interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 221 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+        };
+
+        ipmmu_gp: mmu@e62a0000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe62a0000 0 0x1000>;
+                interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 261 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 9a09579b8309..bdf85701987d 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -103,6 +103,14 @@
                 regulator-always-on;
                 regulator-boot-on;
         };
+
+        vsys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vsys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
 };
 
 &emac {
@@ -148,6 +156,14 @@
                 pinctrl-names = "default";
                 pinctrl-0 = <&act8846_dvs0_ctl>;
 
+                vp1-supply = <&vsys>;
+                vp2-supply = <&vsys>;
+                vp3-supply = <&vsys>;
+                vp4-supply = <&vsys>;
+                inl1-supply = <&vcc_io>;
+                inl2-supply = <&vsys>;
+                inl3-supply = <&vsys>;
+
                 regulators {
                         vcc_ddr: REG1 {
                                 regulator-name = "VCC_DDR";
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index d7b8bbc0c25f..1687e8336994 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -33,6 +33,7 @@
                 regulator-max-microvolt = <1350000>;
                 regulator-always-on;
                 regulator-boot-on;
+                vin-supply = <&vcc_sys>;
         };
 
         vdd_gpu: syr828@41 {
@@ -43,6 +44,7 @@
                 regulator-min-microvolt = <850000>;
                 regulator-max-microvolt = <1350000>;
                 regulator-always-on;
+                vin-supply = <&vcc_sys>;
         };
 
         hym8563@51 {
@@ -64,6 +66,14 @@
                 reg = <0x5a>;
                 status = "okay";
 
+                vp1-supply = <&vcc_sys>;
+                vp2-supply = <&vcc_sys>;
+                vp3-supply = <&vcc_sys>;
+                vp4-supply = <&vcc_sys>;
+                inl1-supply = <&vcc_io>;
+                inl2-supply = <&vcc_sys>;
+                inl3-supply = <&vcc_20>;
+
                 regulators {
                         vcc_ddr: REG1 {
                                 regulator-name = "VCC_DDR";
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index a1c294bf7fed..f62ea78754a9 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -43,9 +43,16 @@
                 #clock-cells = <1>;
                 clock-output-names = "xin32k", "rk808-clkout2";
 
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc6-supply = <&vcc_sys>;
+                vcc7-supply = <&vcc_sys>;
                 vcc8-supply = <&vcc_18>;
                 vcc9-supply = <&vcc_io>;
                 vcc10-supply = <&vcc_io>;
+                vcc11-supply = <&vcc_sys>;
                 vcc12-supply = <&vcc_io>;
                 vddio-supply = <&vccio_pmu>;
 
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 5e895a514a0b..4a457518d861 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -103,6 +103,15 @@
                 regulator-always-on;
                 regulator-boot-on;
         };
+
+        vcc_sys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
 };
 
 &emmc {
@@ -238,6 +247,10 @@
         };
 };
 
+&usbphy {
+        status = "okay";
+};
+
 &usb_host0_ehci {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index e6f873abbe0d..b54dd78580c1 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -179,6 +179,22 @@
         status = "okay";
 };
 
+&gmac {
+        assigned-clocks = <&cru SCLK_MAC>;
+        assigned-clock-parents = <&ext_gmac>;
+        clock_in_out = "input";
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+        phy-supply = <&vcc_lan>;
+        phy-mode = "rgmii";
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+        tx_delay = <0x30>;
+        rx_delay = <0x10>;
+        status = "ok";
+};
+
 &hdmi {
         ddc-i2c-bus = <&i2c5>;
         status = "okay";
@@ -459,6 +475,10 @@
         status = "okay";
 };
 
+&usbphy {
+        status = "okay";
+};
+
 &usb_host1 {
         pinctrl-names = "default";
         pinctrl-0 = <&usbhub_rst>;
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
new file mode 100644
index 000000000000..d081f0e0da36
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2014, 2015 Andy Yan <andy.yan@rock-chips.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3288.dtsi"
+
+/ {
+        model = "PopMetal-RK3288";
+        compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
+
+        memory{
+                reg = <0 0x80000000>;
+        };
+
+        ext_gmac: external-gmac-clock {
+                compatible = "fixed-clock";
+                clock-frequency = <125000000>;
+                clock-output-names = "ext_gmac";
+                #clock-cells = <0>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwrbtn>;
+
+                button@0 {
+                        gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+                        linux,code = <116>;
+                        label = "GPIO Key Power";
+                        linux,input-type = <1>;
+                        gpio-key,wakeup = <1>;
+                        debounce-interval = <100>;
+                };
+        };
+
+        ir: ir-receiver {
+                compatible = "gpio-ir-receiver";
+                gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&ir_int>;
+        };
+
+        vcc_sys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+
+&cpu0 {
+        cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+        broken-cd;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        disable-wp;
+        non-removable;
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+        status = "okay";
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        card-detect-delay = <200>;
+        disable-wp;                     /* wp not hooked up */
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+        status = "okay";
+};
+
+&gmac {
+        phy-supply = <&vcc_lan>;
+        phy-mode = "rgmii";
+        clock_in_out = "input";
+        snps,reset-gpio = <&gpio4 7 0>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        assigned-clocks = <&cru SCLK_MAC>;
+        assigned-clock-parents = <&ext_gmac>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        tx_delay = <0x30>;
+        rx_delay = <0x10>;
+        status = "ok";
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c5>;
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                reg = <0x1b>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int &global_pwroff>;
+                rockchip,system-power-controller;
+                wakeup-source;
+                #clock-cells = <1>;
+                clock-output-names = "xin32k", "rk808-clkout2";
+
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc6-supply = <&vcc_sys>;
+                vcc7-supply = <&vcc_sys>;
+                vcc8-supply = <&vcc_18>;
+                vcc9-supply = <&vcc_io>;
+                vcc10-supply = <&vcc_io>;
+                vcc11-supply = <&vcc_sys>;
+                vcc12-supply = <&vcc_io>;
+                vddio-supply = <&vcc_io>;
+
+                regulators {
+                        vdd_cpu: DCDC_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-name = "vdd_arm";
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_gpu: DCDC_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1250000>;
+                                regulator-name = "vdd_gpu";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_ddr";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc_io: DCDC_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_io";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vcc_lan: LDO_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_lan";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vccio_sd: LDO_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vccio_sd";
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_10: LDO_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd_10";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc18_lcd: LDO_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        ldo5: LDO_REG5 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "ldo5";
+                        };
+
+                        vdd10_lcd: LDO_REG6 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd10_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc_18: LDO_REG7 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc_18";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcca_codec: LDO_REG8 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcca_codec";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vcc_wl: SWITCH_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_wl";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc_lcd: SWITCH_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        ak8963: ak8963@0d {
+                compatible = "asahi-kasei,ak8975";
+                reg = <0x0d>;
+                interrupt-parent = <&gpio8>;
+                interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&comp_int>;
+        };
+
+        l3g4200d: l3g4200d@68 {
+                compatible = "st,l3g4200d-gyro";
+                st,drdy-int-pin = <2>;
+                reg = <0x6b>;
+        };
+
+        mma8452: mma8452@1d {
+                compatible = "fsl,mma8452";
+                reg = <0x1d>;
+                interrupt-parent = <&gpio8>;
+                interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&gsensor_int>;
+        };
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c3 {
+        status = "okay";
+};
+
+&i2c4 {
+        status = "okay";
+};
+
+&i2c5 {
+        status = "okay";
+};
+
+&pinctrl {
+        ak8963 {
+                comp_int: comp-int {
+                        rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        buttons {
+                pwrbtn: pwrbtn {
+                        rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        ir {
+                ir_int: ir-int {
+                        rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        mma8452 {
+                gsensor_int: gsensor-int {
+                        rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        pmic {
+                pmic_int: pmic-int {
+                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+};
+
+&vopb {
+        status = "okay";
+};
+
+&vopb_mmu {
+        status = "okay";
+};
+
+&vopl {
+        status = "okay";
+};
+
+&vopl_mmu {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&uart4 {
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index eccc78d3220b..165968d51d8f 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -420,6 +420,8 @@
                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_USBHOST0>;
                 clock-names = "usbhost";
+                phys = <&usbphy1>;
+                phy-names = "usb";
                 status = "disabled";
         };
 
@@ -432,6 +434,8 @@
                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_USBHOST1>;
                 clock-names = "otg";
+                phys = <&usbphy2>;
+                phy-names = "usb2-phy";
                 status = "disabled";
         };
 
@@ -442,6 +446,8 @@
                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_OTG0>;
                 clock-names = "otg";
+                phys = <&usbphy0>;
+                phy-names = "usb2-phy";
                 status = "disabled";
         };
 
@@ -698,6 +704,35 @@
                 interrupts = <GIC_PPI 9 0xf04>;
         };
 
+        usbphy: phy {
+                compatible = "rockchip,rk3288-usb-phy";
+                rockchip,grf = <&grf>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+
+                usbphy0: usb-phy0 {
+                        #phy-cells = <0>;
+                        reg = <0x320>;
+                        clocks = <&cru SCLK_OTGPHY0>;
+                        clock-names = "phyclk";
+                };
+
+                usbphy1: usb-phy1 {
+                        #phy-cells = <0>;
+                        reg = <0x334>;
+                        clocks = <&cru SCLK_OTGPHY1>;
+                        clock-names = "phyclk";
+                };
+
+                usbphy2: usb-phy2 {
+                        #phy-cells = <0>;
+                        reg = <0x348>;
+                        clocks = <&cru SCLK_OTGPHY2>;
+                        clock-names = "phyclk";
+                };
+        };
+
         pinctrl: pinctrl {
                 compatible = "rockchip,rk3288-pinctrl";
                 rockchip,grf = <&grf>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index c0a8dfcf8380..57ab8587f7b9 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -26,6 +26,7 @@
                 serial2 = &usart1;
                 serial3 = &usart2;
                 serial4 = &usart3;
+                serial5 = &uart0;
                 gpio0 = &pioA;
                 gpio1 = &pioB;
                 gpio2 = &pioC;
@@ -206,6 +207,17 @@
                                 status = "disabled";
                         };
 
+                        uart0: serial@f0024000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf0024000 0x100>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
+                                clocks = <&uart0_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+
                         pwm0: pwm@f002c000 {
                                 compatible = "atmel,sama5d3-pwm";
                                 reg = <0xf002c000 0x300>;
@@ -764,6 +776,22 @@
                                         };
                                 };
 
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* conflicts with PWMFI2, ISI_D8 */
+                                                         AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* conflicts with ISI_PCK */
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* conflicts with TWD0, ISI_VSYNC */
+                                                         AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* conflicts with TWCK0, ISI_HSYNC */
+                                        };
+                                };
+
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
@@ -1098,6 +1126,12 @@
                                                 atmel,clk-output-range = <0 66000000>;
                                         };
 
+                                        uart0_clk: uart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
                                         twi0_clk: twi0_clk {
                                                 reg = <18>;
                                                 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index 9089c7c6cea8..d9a9aca1ccfd 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -44,8 +44,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 pb_user1 {
                         label = "pb_user1";
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index eaf41451ad0c..c5a3772741bf 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
  * CAN support
  *
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
index b4544cf11bad..7cb235ef0fb6 100644
--- a/arch/arm/boot/dts/sama5d3_emac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with
  * Ethernet.
  *
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
index de5ed59fb446..23f225fbb756 100644
--- a/arch/arm/boot/dts/sama5d3_gmac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with
  * Gigabit Ethernet.
  *
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 85d302701565..be7cfefc6c31 100644
--- a/arch/arm/boot/dts/sama5d3_lcd.dtsi
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
  * LCD support
  *
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
@@ -13,40 +13,183 @@
 / {
         ahb {
                 apb {
+                        hlcdc: hlcdc@f0030000 {
+                                compatible = "atmel,sama5d3-hlcdc";
+                                reg = <0xf0030000 0x2000>;
+                                interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+                                clock-names = "periph_clk","sys_clk", "slow_clk";
+                                status = "disabled";
+
+                                hlcdc-display-controller {
+                                        compatible = "atmel,hlcdc-display-controller";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        port@0 {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                reg = <0>;
+                                        };
+                                };
+
+                                hlcdc_pwm: hlcdc-pwm {
+                                        compatible = "atmel,hlcdc-pwm";
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_lcd_pwm>;
+                                        #pwm-cells = <3>;
+                                };
+                        };
+
                         pinctrl@fffff200 {
                                 lcd {
-                                        pinctrl_lcd: lcd-0 {
+                                        pinctrl_lcd_base: lcd-base-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDVSYNC */
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDHSYNC */
+                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDISP */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDEN */
+                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
+                                        };
+
+                                        pinctrl_lcd_pwm: lcd-pwm-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;    /* LCDPWM */
+                                        };
+
+                                        pinctrl_lcd_rgb444: lcd-rgb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
+                                        };
+
+                                        pinctrl_lcd_rgb565: lcd-rgb-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
+                                        };
+
+                                        pinctrl_lcd_rgb666: lcd-rgb-2 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
+                                        };
+
+                                        pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* LCDD17 pin */
+                                        };
+
+                                        pinctrl_lcd_rgb888: lcd-rgb-3 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+                                        };
+
+                                        pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt {
                                                 atmel,pins =
-                                                        <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA24 periph A LCDPWM */
-                                                         AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA26 periph A LCDVSYNC */
-                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA27 periph A LCDHSYNC */
-                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA25 periph A LCDDISP */
-                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA29 periph A LCDDEN */
-                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA28 periph A LCDPCK */
-                                                         AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A LCDD0 pin */
-                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A LCDD1 pin */
-                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA2 periph A LCDD2 pin */
-                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA3 periph A LCDD3 pin */
-                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA4 periph A LCDD4 pin */
-                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA5 periph A LCDD5 pin */
-                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA6 periph A LCDD6 pin */
-                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA7 periph A LCDD7 pin */
-                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA8 periph A LCDD8 pin */
-                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A LCDD9 pin */
-                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A LCDD10 pin */
-                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A LCDD11 pin */
-                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A LCDD12 pin */
-                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A LCDD13 pin */
-                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A LCDD14 pin */
-                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A LCDD15 pin */
-                                                         AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC14 periph C LCDD16 pin */
-                                                         AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC13 periph C LCDD17 pin */
-                                                         AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC12 periph C LCDD18 pin */
-                                                         AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC11 periph C LCDD19 pin */
-                                                         AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC10 periph C LCDD20 pin */
-                                                         AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC15 periph C LCDD21 pin */
-                                                         AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PE27 periph C LCDD22 pin */
-                                                         AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD17 pin */
+                                                         AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* LCDD23 pin */
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
index 1b02208ea6ff..026b252f09b3 100644
--- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with
  * 3 MMC ports
  *
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 02848453ca0c..f7fa58fe09f1 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with
  * 2 TC blocks.
  *
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 7a8d4c6115f7..2511d748867b 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
  * UART support
  *
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 782587df5f3f..6b1bb58f9c0b 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -64,9 +64,13 @@
                 gpio2 = &pioC;
                 gpio3 = &pioD;
                 gpio4 = &pioE;
+                pwm0 = &pwm0;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
                 tcb0 = &tcb0;
                 tcb1 = &tcb1;
                 i2c0 = &i2c0;
+                i2c1 = &i2c1;
                 i2c2 = &i2c2;
         };
         cpus {
@@ -310,6 +314,34 @@
                         #size-cells = <1>;
                         ranges;
 
+                        hlcdc: hlcdc@f0000000 {
+                                compatible = "atmel,sama5d4-hlcdc";
+                                reg = <0xf0000000 0x4000>;
+                                interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+                                clock-names = "periph_clk","sys_clk", "slow_clk";
+                                status = "disabled";
+
+                                hlcdc-display-controller {
+                                        compatible = "atmel,hlcdc-display-controller";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        port@0 {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                reg = <0>;
+                                        };
+                                };
+
+                                hlcdc_pwm: hlcdc-pwm {
+                                        compatible = "atmel,hlcdc-pwm";
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_lcd_pwm>;
+                                        #pwm-cells = <3>;
+                                };
+                        };
+
                         dma1: dma-controller@f0004000 {
                                 compatible = "atmel,sama5d4-dma";
                                 reg = <0xf0004000 0x200>;
@@ -319,6 +351,21 @@
                                 clock-names = "dma_clk";
                         };
 
+                        isi: isi@f0008000 {
+                                compatible = "atmel,at91sam9g45-isi";
+                                reg = <0xf0008000 0x4000>;
+                                interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_isi_data_0_7>;
+                                clocks = <&isi_clk>;
+                                clock-names = "isi_clk";
+                                status = "disabled";
+                                port {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                        };
+
                         ramc0: ramc@f0010000 {
                                 compatible = "atmel,sama5d3-ddramc";
                                 reg = <0xf0010000 0x200>;
@@ -800,6 +847,33 @@
                                 clock-names = "mci_clk";
                         };
 
+                        ssc0: ssc@f8008000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf8008000 0x4000>;
+                                interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                dmas = <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+                                        | AT91_XDMAC_DT_PERID(26))>,
+                                       <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+                                        | AT91_XDMAC_DT_PERID(27))>;
+                                dma-names = "tx", "rx";
+                                clocks = <&ssc0_clk>;
+                                clock-names = "pclk";
+                                status = "disabled";
+                        };
+
+                        pwm0: pwm@f800c000 {
+                                compatible = "atmel,sama5d3-pwm";
+                                reg = <0xf800c000 0x300>;
+                                interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                clocks = <&pwm_clk>;
+                                status = "disabled";
+                        };
+
                         spi0: spi@f8010000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -839,6 +913,25 @@
                                 status = "disabled";
                         };
 
+                        i2c1: i2c@f8018000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8018000 0x4000>;
+                                interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(4)>,
+                                       <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(5)>;
+                                dma-names = "tx", "rx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&twi1_clk>;
+                                status = "disabled";
+                        };
+
                         tcb0: timer@f801c000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf801c000 0x100>;
@@ -853,6 +946,8 @@
                                 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 clocks = <&macb0_clk>, <&macb0_clk>;
                                 clock-names = "hclk", "pclk";
                                 status = "disabled";
@@ -953,6 +1048,24 @@
                                 status = "disabled";
                         };
 
+                        ssc1: ssc@fc014000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xfc014000 0x4000>;
+                                interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                dmas = <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+                                        | AT91_XDMAC_DT_PERID(28))>,
+                                       <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+                                        | AT91_XDMAC_DT_PERID(29))>;
+                                dma-names = "tx", "rx";
+                                clocks = <&ssc1_clk>;
+                                clock-names = "pclk";
+                                status = "disabled";
+                        };
+
                         tcb1: timer@fc020000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xfc020000 0x100>;
@@ -1008,6 +1121,46 @@
                                 };
                         };
 
+                        aes@fc044000 {
+                                compatible = "atmel,at91sam9g46-aes";
+                                reg = <0xfc044000 0x100>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(41)>,
+                                       <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(40)>;
+                                dma-names = "tx", "rx";
+                                clocks = <&aes_clk>;
+                                clock-names = "aes_clk";
+                                status = "disabled";
+                        };
+
+                        tdes@fc04c000 {
+                                compatible = "atmel,at91sam9g46-tdes";
+                                reg = <0xfc04c000 0x100>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(42)>,
+                                       <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(43)>;
+                                dma-names = "tx", "rx";
+                                clocks = <&tdes_clk>;
+                                clock-names = "tdes_clk";
+                                status = "disabled";
+                        };
+
+                        sha@fc050000 {
+                                compatible = "atmel,at91sam9g46-sha";
+                                reg = <0xfc050000 0x100>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(44)>;
+                                dma-names = "tx";
+                                clocks = <&sha_clk>;
+                                clock-names = "sha_clk";
+                                status = "disabled";
+                        };
+
                         rstc@fc068600 {
                                 compatible = "atmel,at91sam9g45-rstc";
                                 reg = <0xfc068600 0x10>;
@@ -1190,6 +1343,14 @@
                                         };
                                 };
 
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE   /* TWD1, conflicts with UART0 RX and DIBP */
+                                                         AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
+                                        };
+                                };
+
                                 i2c2 {
                                         pinctrl_i2c2: i2c2-0 {
                                                 atmel,pins =
@@ -1198,6 +1359,155 @@
                                         };
                                 };
 
+                                isi {
+                                        pinctrl_isi_data_0_7: isi-0-data-0-7 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D0 */
+                                                         AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D1 */
+                                                         AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D2 */
+                                                         AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D3 */
+                                                         AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D4 */
+                                                         AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D5 */
+                                                         AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D6 */
+                                                         AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D7 */
+                                                         AT91_PIOB  1 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_PCK, conflict with G0_RXCK */
+                                                         AT91_PIOB  3 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_VSYNC */
+                                                         AT91_PIOB  4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
+                                        };
+                                        pinctrl_isi_data_8_9: isi-0-data-8-9 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
+                                                         AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
+                                        };
+                                        pinctrl_isi_data_10_11: isi-0-data-10-11 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
+                                                         AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
+                                        };
+                                };
+
+                                lcd {
+                                        pinctrl_lcd_base: lcd-base-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDVSYNC */
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDHSYNC */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDEN */
+                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
+                                        };
+                                        pinctrl_lcd_pwm: lcd-pwm-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;    /* LCDPWM */
+                                        };
+                                        pinctrl_lcd_rgb444: lcd-rgb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
+                                        };
+                                        pinctrl_lcd_rgb565: lcd-rgb-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
+                                        };
+                                        pinctrl_lcd_rgb666: lcd-rgb-2 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+                                        };
+                                        pinctrl_lcd_rgb777: lcd-rgb-3 {
+                                                atmel,pins =
+                                                         /* LCDDAT0 conflicts with TMS */
+                                                        <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         /* LCDDAT8 conflicts with TCK */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         /* LCDDAT16 conflicts with NTRST */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+                                        };
+                                        pinctrl_lcd_rgb888: lcd-rgb-4 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+                                        };
+                                };
+
                                 macb0 {
                                         pinctrl_macb0_rmii: macb0_rmii-0 {
                                                 atmel,pins =
@@ -1281,6 +1591,38 @@
                                         };
                                 };
 
+                                ssc0 {
+                                        pinctrl_ssc0_tx: ssc0_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK0 */
+                                                         AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF0 */
+                                                         AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
+                                        };
+
+                                        pinctrl_ssc0_rx: ssc0_rx {
+                                                atmel,pins =
+                                                        <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK0 */
+                                                         AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF0 */
+                                                         AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
+                                        };
+                                };
+
+                                ssc1 {
+                                        pinctrl_ssc1_tx: ssc1_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK1 */
+                                                         AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF1 */
+                                                         AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
+                                        };
+
+                                        pinctrl_ssc1_rx: ssc1_rx {
+                                                atmel,pins =
+                                                        <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK1 */
+                                                         AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF1 */
+                                                         AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
+                                        };
+                                };
+
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 6d32c87632d4..bf365f7fef47 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -45,7 +45,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0x41000000 0x1e800000>;
+                reg = <0x40000000 0x20000000>;
         };
 
         reg_1p8v: regulator@0 {
@@ -188,6 +188,33 @@
 
 &i2c0 {
         status = "okay";
+
+        compass@c {
+                compatible = "asahi-kasei,ak8975";
+                reg = <0x0c>;
+                interrupt-parent = <&irqpin3>;
+                interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+        };
+
+        ak4648: codec@12 {
+                compatible = "asahi-kasei,ak4648";
+                reg = <0x12>;
+                #sound-dai-cells = <0>;
+        };
+
+        accelerometer@1d {
+                compatible = "adi,adxl34x";
+                reg = <0x1d>;
+                interrupt-parent = <&irqpin3>;
+                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
+                             <3 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        rtc@32 {
+                compatible = "ricoh,r2025sd";
+                reg = <0x32>;
+        };
+
         as3711@40 {
                 compatible = "ams,as3711";
                 reg = <0x40>;
@@ -258,11 +285,16 @@
                         };
                 };
         };
+};
 
-        ak4648: ak4648@12 {
-                #sound-dai-cells = <0>;
-                compatible = "asahi-kasei,ak4648";
-                reg = <0x12>;
+&i2c1 {
+        status = "okay";
+
+        touchscreen@55 {
+                compatible = "sitronix,st1232";
+                reg = <0x55>;
+                interrupt-parent = <&irqpin1>;
+                interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
         };
 };
 
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 27c5f426d172..e7dae01933a5 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -21,6 +21,6 @@
 
         memory {
                 device_type = "memory";
-                reg = <0x41000000 0x1e800000>;
+                reg = <0x40000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 2dfd5b44255d..ab319b73e282 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -94,6 +94,8 @@
                               0 6 IRQ_TYPE_LEVEL_HIGH
                               0 7 IRQ_TYPE_LEVEL_HIGH
                               0 8 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+                control-parent;
         };
 
         irqpin1: irqpin@e6900004 {
@@ -113,6 +115,7 @@
                               0 14 IRQ_TYPE_LEVEL_HIGH
                               0 15 IRQ_TYPE_LEVEL_HIGH
                               0 16 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
                 control-parent;
         };
 
@@ -133,6 +136,8 @@
                               0 22 IRQ_TYPE_LEVEL_HIGH
                               0 23 IRQ_TYPE_LEVEL_HIGH
                               0 24 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+                control-parent;
         };
 
         irqpin3: irqpin@e690000c {
@@ -152,6 +157,8 @@
                               0 30 IRQ_TYPE_LEVEL_HIGH
                               0 31 IRQ_TYPE_LEVEL_HIGH
                               0 32 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+                control-parent;
         };
 
         i2c0: i2c@e6820000 {
@@ -426,133 +433,159 @@
                 vclk1_clk: vclk1_clk@e6150008 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150008 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+                                 <0>;
                         #clock-cells = <0>;
                         clock-output-names = "vclk1";
                 };
                 vclk2_clk: vclk2_clk@e615000c {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe615000c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+                                 <0>;
                         #clock-cells = <0>;
                         clock-output-names = "vclk2";
                 };
                 vclk3_clk: vclk3_clk@e615001c {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe615001c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+                                 <0>;
                         #clock-cells = <0>;
                         clock-output-names = "vclk3";
                 };
                 zb_clk: zb_clk@e6150010 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150010 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "zb";
                 };
                 flctl_clk: flctl_clk@e6150014 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150014 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "flctlck";
                 };
                 sdhi0_clk: sdhi0_clk@e6150074 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150074 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&pll1_div13_clk>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "sdhi0ck";
                 };
                 sdhi1_clk: sdhi1_clk@e6150078 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150078 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&pll1_div13_clk>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "sdhi1ck";
                 };
                 sdhi2_clk: sdhi2_clk@e615007c {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe615007c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&pll1_div13_clk>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "sdhi2ck";
                 };
                 fsia_clk: fsia_clk@e6150018 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150018 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&fsiack_clk>, <&fsiack_clk>;
                         #clock-cells = <0>;
                         clock-output-names = "fsia";
                 };
                 fsib_clk: fsib_clk@e6150090 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150090 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&fsibck_clk>, <&fsibck_clk>;
                         #clock-cells = <0>;
                         clock-output-names = "fsib";
                 };
                 sub_clk: sub_clk@e6150080 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150080 4>;
-                        clocks = <&extal2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extal2_clk>, <&extal2_clk>;
                         #clock-cells = <0>;
                         clock-output-names = "sub";
                 };
                 spua_clk: spua_clk@e6150084 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150084 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extal2_clk>, <&extal2_clk>;
                         #clock-cells = <0>;
                         clock-output-names = "spua";
                 };
                 spuv_clk: spuv_clk@e6150094 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150094 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extal2_clk>, <&extal2_clk>;
                         #clock-cells = <0>;
                         clock-output-names = "spuv";
                 };
                 msu_clk: msu_clk@e6150088 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150088 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "msu";
                 };
                 hsi_clk: hsi_clk@e615008c {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe615008c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&pll1_div7_clk>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "hsi";
                 };
                 mfg1_clk: mfg1_clk@e6150098 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150098 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "mfg1";
                 };
                 mfg2_clk: mfg2_clk@e615009c {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe615009c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "mfg2";
                 };
                 dsit_clk: dsit_clk@e6150060 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150060 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "dsit";
                 };
                 dsi0p_clk: dsi0p_clk@e6150064 {
                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                         reg = <0xe6150064 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
+                                 <&extcki_clk>, <0>, <0>, <0>;
                         #clock-cells = <0>;
                         clock-output-names = "dsi0pck";
                 };
@@ -695,5 +728,16 @@
                         clock-output-names =
                                 "iic3", "iic4", "keysc";
                 };
+                mstp5_clks: mstp5_clks@e6150144 {
+                        compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150144 4>, <0xe615003c 4>;
+                        clocks = <&cpg_clocks SH73A0_CLK_HP>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                SH73A0_CLK_INTCA0
+                        >;
+                        clock-output-names =
+                                "intca0";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
new file mode 100644
index 000000000000..2c5cede686dc
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
@@ -0,0 +1,2421 @@
+/ {
+        clock@0,60006000 {
+                emc-timings-3 {
+                        nvidia,ram-code = <3>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+                                nvidia,parent-clock-frequency = <528000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+                                nvidia,parent-clock-frequency = <924000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                };
+        };
+
+        emc@0,7001b000 {
+                emc-timings-3 {
+                        nvidia,ram-code = <3>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000060
+                                        0x00000000
+                                        0x00000018
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000005
+                                        0x00000005
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000064
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000007
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x800001c5
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000005
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000026
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000006
+                                        0x00000006
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x000000a0
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000023a
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000001
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000001
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000134
+                                        0x00000000
+                                        0x0000004d
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000008
+                                        0x0000000f
+                                        0x0000000c
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000013f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000015
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000370
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000003
+                                        0x00000011
+                                        0x00000000
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000202
+                                        0x00000000
+                                        0x00000080
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x0000000f
+                                        0x0000000f
+                                        0x00000013
+                                        0x00000013
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000001
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000213
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000022
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000050e
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000004
+                                        0x0000001a
+                                        0x00000000
+                                        0x00000003
+                                        0x00000001
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000304
+                                        0x00000000
+                                        0x000000c1
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000018
+                                        0x0000000f
+                                        0x0000001c
+                                        0x0000001c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000031c
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000033
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000713
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008cd>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000009
+                                        0x00000035
+                                        0x00000000
+                                        0x00000006
+                                        0x00000002
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x00000006
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000011
+                                        0x00000607
+                                        0x00000000
+                                        0x00000181
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000032
+                                        0x0000000f
+                                        0x00000038
+                                        0x00000038
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000006
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000638
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00008000
+                                        0x00000000
+                                        0x00000000
+                                        0x00008000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00090000
+                                        0x00090000
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000707
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000066
+                                        0x00000000
+                                        0x00000100
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000d2b3
+                                        0x80000d22
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x000008d5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000321>;
+                                nvidia,emc-mrs-wait-cnt = <0x0173000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000000d
+                                        0x0000004d
+                                        0x00000000
+                                        0x00000009
+                                        0x00000003
+                                        0x00000004
+                                        0x00000008
+                                        0x00000002
+                                        0x00000009
+                                        0x00000003
+                                        0x00000003
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000007
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x0000000e
+                                        0x00000010
+                                        0x00000012
+                                        0x000008e4
+                                        0x00000000
+                                        0x00000239
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x0000004b
+                                        0x0000000e
+                                        0x00000052
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000008
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000924
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00098000
+                                        0x00098000
+                                        0x00000000
+                                        0x00098000
+                                        0x00098000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00050000
+                                        0x00050000
+                                        0x00050000
+                                        0x00050000
+                                        0x00005000
+                                        0x00005000
+                                        0x00005000
+                                        0x00005000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000096
+                                        0x00000000
+                                        0x00000100
+                                        0x0173000e
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x800012d7
+                                        0x00000009
+                                >;
+                        };
+
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x00000895>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000521>;
+                                nvidia,emc-mrs-wait-cnt = <0x015b000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000011
+                                        0x00000066
+                                        0x00000000
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000004
+                                        0x00000008
+                                        0x00000002
+                                        0x0000000a
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000001
+                                        0x00000008
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000f
+                                        0x00000010
+                                        0x00000012
+                                        0x00000bd1
+                                        0x00000000
+                                        0x000002f4
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x00000063
+                                        0x0000000f
+                                        0x0000006c
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000c11
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00070000
+                                        0x00070000
+                                        0x00000000
+                                        0x00070000
+                                        0x00070000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00038000
+                                        0x00038000
+                                        0x00038000
+                                        0x00038000
+                                        0x00003800
+                                        0x00003800
+                                        0x00003800
+                                        0x00003800
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x000000c6
+                                        0x00000000
+                                        0x00000100
+                                        0x015b000e
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x8000188b
+                                        0x00000009
+                                >;
+                        };
+
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000941>;
+                                nvidia,emc-mrs-wait-cnt = <0x0139000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0123133d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000018
+                                        0x00000088
+                                        0x00000000
+                                        0x00000010
+                                        0x00000006
+                                        0x00000006
+                                        0x00000009
+                                        0x00000002
+                                        0x0000000d
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000001
+                                        0x00000009
+                                        0x00030000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000010
+                                        0x00000012
+                                        0x00000014
+                                        0x00000fd6
+                                        0x00000000
+                                        0x000003f5
+                                        0x00000002
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000000
+                                        0x00000085
+                                        0x00000012
+                                        0x00000090
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000010
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00001017
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe01200b1
+                                        0x00008000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00054000
+                                        0x00054000
+                                        0x00000000
+                                        0x00054000
+                                        0x00054000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x0139000e
+                                        0x00000000
+                                        0x00000003
+                                        0x000042a0
+                                        0x80002062
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200010>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000b61>;
+                                nvidia,emc-mrs-wait-cnt = <0x0127000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000001b
+                                        0x0000009b
+                                        0x00000000
+                                        0x00000013
+                                        0x00000007
+                                        0x00000007
+                                        0x0000000b
+                                        0x00000003
+                                        0x00000010
+                                        0x00000007
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000b
+                                        0x00070000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000002
+                                        0x00000012
+                                        0x00000016
+                                        0x00000018
+                                        0x00001208
+                                        0x00000000
+                                        0x00000482
+                                        0x00000002
+                                        0x0000000d
+                                        0x00000001
+                                        0x00000000
+                                        0x00000097
+                                        0x00000015
+                                        0x000000a3
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000013
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00001248
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00e00b1
+                                        0x00008000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x0127000e
+                                        0x00000000
+                                        0x00000003
+                                        0x000040a0
+                                        0x800024aa
+                                        0x0000000e
+                                >;
+                        };
+
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200018>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000d71>;
+                                nvidia,emc-mrs-wait-cnt = <0x00f7000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000024
+                                        0x000000cd
+                                        0x00000000
+                                        0x00000019
+                                        0x0000000a
+                                        0x00000008
+                                        0x0000000d
+                                        0x00000004
+                                        0x00000013
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000004
+                                        0x00000002
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x0000000d
+                                        0x00080000
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x00000014
+                                        0x00000018
+                                        0x0000001a
+                                        0x000017e2
+                                        0x00000000
+                                        0x000005f8
+                                        0x00000003
+                                        0x00000011
+                                        0x00000001
+                                        0x00000000
+                                        0x000000c7
+                                        0x00000018
+                                        0x000000d7
+                                        0x00000200
+                                        0x00000005
+                                        0x00000006
+                                        0x00000005
+                                        0x00000019
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00001822
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00700b1
+                                        0x00008000
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00034000
+                                        0x00034000
+                                        0x00000000
+                                        0x00034000
+                                        0x00034000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000000
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x61861820
+                                        0x00514514
+                                        0x00514514
+                                        0x61861800
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x00f7000e
+                                        0x00000000
+                                        0x00000004
+                                        0x00004080
+                                        0x80003012
+                                        0x0000000f
+                                >;
+                        };
+
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430303>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200020>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000f15>;
+                                nvidia,emc-mrs-wait-cnt = <0x00cd000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x0000004c>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000002b
+                                        0x000000f0
+                                        0x00000000
+                                        0x0000001e
+                                        0x0000000b
+                                        0x00000009
+                                        0x0000000f
+                                        0x00000005
+                                        0x00000016
+                                        0x0000000b
+                                        0x0000000b
+                                        0x00000004
+                                        0x00000002
+                                        0x00000000
+                                        0x00000007
+                                        0x00000007
+                                        0x0000000d
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x0000000f
+                                        0x000a0000
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x00000016
+                                        0x0000001a
+                                        0x0000001c
+                                        0x00001be7
+                                        0x00000000
+                                        0x000006f9
+                                        0x00000004
+                                        0x00000015
+                                        0x00000001
+                                        0x00000000
+                                        0x000000e7
+                                        0x0000001b
+                                        0x000000fb
+                                        0x00000200
+                                        0x00000006
+                                        0x00000007
+                                        0x00000006
+                                        0x0000001e
+                                        0x00000000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00001c28
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab898
+                                        0xe00400b1
+                                        0x00008000
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0002c000
+                                        0x0002c000
+                                        0x00000000
+                                        0x0002c000
+                                        0x0002c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000000
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x5d75d720
+                                        0x00514514
+                                        0x00514514
+                                        0x5d75d700
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000128
+                                        0x00cd000e
+                                        0x00000000
+                                        0x00000004
+                                        0x00004080
+                                        0x800037ea
+                                        0x00000011
+                                >;
+                        };
+
+                };
+        };
+
+        memory-controller@0,70019000 {
+                emc-timings-3 {
+                        nvidia,ram-code = <3>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+
+                                nvidia,emem-configuration = <
+                                        0x40040001
+                                        0x8000000a
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0502
+                                        0x77e30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+
+                                nvidia,emem-configuration = <
+                                        0x40020001
+                                        0x80000012
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0502
+                                        0x76230303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+
+                                nvidia,emem-configuration = <
+                                        0xa0000001
+                                        0x80000017
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0502
+                                        0x74a30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x00000001
+                                        0x8000001e
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0502
+                                        0x74230403
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x08000001
+                                        0x80000026
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0503
+                                        0x73c30504
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x01000003
+                                        0x80000040
+                                        0x00000001
+                                        0x00000001
+                                        0x00000004
+                                        0x00000002
+                                        0x00000003
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040203
+                                        0x000a0504
+                                        0x73840a05
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x08000004
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000004
+                                        0x00000004
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000b0607
+                                        0x77450e08
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0f000005
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000005
+                                        0x00000006
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000d0709
+                                        0x7586120a
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0f000007
+                                        0x80000040
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000c
+                                        0x00000007
+                                        0x00000008
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000006
+                                        0x06050202
+                                        0x0010090c
+                                        0x7428180d
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x00000009
+                                        0x80000040
+                                        0x00000003
+                                        0x00000004
+                                        0x0000000e
+                                        0x00000009
+                                        0x0000000a
+                                        0x00000001
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000007
+                                        0x07050202
+                                        0x00130b0e
+                                        0x73a91b0f
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0e00000b
+                                        0x80000040
+                                        0x00000004
+                                        0x00000005
+                                        0x00000013
+                                        0x0000000c
+                                        0x0000000d
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000c
+                                        0x00000002
+                                        0x00000002
+                                        0x00000006
+                                        0x00000008
+                                        0x08060202
+                                        0x00170e13
+                                        0x736c2414
+                                        0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0e00000d
+                                        0x80000040
+                                        0x00000005
+                                        0x00000006
+                                        0x00000016
+                                        0x0000000e
+                                        0x0000000f
+                                        0x00000002
+                                        0x00000004
+                                        0x0000000e
+                                        0x00000002
+                                        0x00000002
+                                        0x00000006
+                                        0x00000009
+                                        0x09060202
+                                        0x001a1016
+                                        0x734e2a17
+                                        0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index dbfaba09703a..ed8a8acd3d34 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -3,6 +3,8 @@
 #include <dt-bindings/input/input.h>
 #include "tegra124.dtsi"
 
+#include "tegra124-jetson-tk1-emc.dtsi"
+
 / {
         model = "NVIDIA Tegra124 Jetson TK1";
         compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
@@ -60,35 +62,35 @@
                                 nvidia,pins = "clk_32k_out_pa0";
                                 nvidia,function = "soc";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         uart3_cts_n_pa1 {
                                 nvidia,pins = "uart3_cts_n_pa1";
-                                nvidia,function = "uartc";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap2_fs_pa2 {
                                 nvidia,pins = "dap2_fs_pa2";
                                 nvidia,function = "i2s1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap2_sclk_pa3 {
                                 nvidia,pins = "dap2_sclk_pa3";
                                 nvidia,function = "i2s1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap2_din_pa4 {
                                 nvidia,pins = "dap2_din_pa4";
                                 nvidia,function = "i2s1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap2_dout_pa5 {
@@ -96,14 +98,14 @@
                                 nvidia,function = "i2s1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_clk_pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc3_cmd_pa7 {
                                 nvidia,pins = "sdmmc3_cmd_pa7";
@@ -116,14 +118,14 @@
                                 nvidia,pins = "pb0";
                                 nvidia,function = "uartd";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pb1 {
                                 nvidia,pins = "pb1";
                                 nvidia,function = "uartd";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc3_dat3_pb4 {
@@ -156,9 +158,9 @@
                         };
                         uart3_rts_n_pc0 {
                                 nvidia,pins = "uart3_rts_n_pc0";
-                                nvidia,function = "uartc";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         uart2_txd_pc2 {
@@ -172,7 +174,7 @@
                                 nvidia,pins = "uart2_rxd_pc3";
                                 nvidia,function = "irda";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gen1_i2c_scl_pc4 {
@@ -194,44 +196,39 @@
                         pc7 {
                                 nvidia,pins = "pc7";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pg0 {
                                 nvidia,pins = "pg0";
-                                nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pg1 {
                                 nvidia,pins = "pg1";
-                                nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pg2 {
                                 nvidia,pins = "pg2";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pg3 {
                                 nvidia,pins = "pg3";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pg4 {
                                 nvidia,pins = "pg4";
-                                nvidia,function = "spi4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pg5 {
                                 nvidia,pins = "pg5";
@@ -251,7 +248,7 @@
                                 nvidia,pins = "pg7";
                                 nvidia,function = "spi4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ph0 {
@@ -270,7 +267,6 @@
                         };
                         ph2 {
                                 nvidia,pins = "ph2";
-                                nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -278,57 +274,53 @@
                         ph3 {
                                 nvidia,pins = "ph3";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ph4 {
                                 nvidia,pins = "ph4";
-                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ph5 {
                                 nvidia,pins = "ph5";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ph6 {
                                 nvidia,pins = "ph6";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ph7 {
                                 nvidia,pins = "ph7";
-                                nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pi0 {
                                 nvidia,pins = "pi0";
-                                nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pi1 {
                                 nvidia,pins = "pi1";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pi2 {
                                 nvidia,pins = "pi2";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pi3 {
@@ -341,22 +333,21 @@
                         pi4 {
                                 nvidia,pins = "pi4";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pi5 {
                                 nvidia,pins = "pi5";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pi6 {
                                 nvidia,pins = "pi6";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pi7 {
@@ -368,23 +359,22 @@
                         };
                         pj0 {
                                 nvidia,pins = "pj0";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pj2 {
                                 nvidia,pins = "pj2";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         uart2_cts_n_pj5 {
                                 nvidia,pins = "uart2_cts_n_pj5";
                                 nvidia,function = "uartb";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         uart2_rts_n_pj6 {
@@ -403,35 +393,32 @@
                         };
                         pk0 {
                                 nvidia,pins = "pk0";
-                                nvidia,function = "soc";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pk1 {
                                 nvidia,pins = "pk1";
-                                nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pk2 {
                                 nvidia,pins = "pk2";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pk3 {
                                 nvidia,pins = "pk3";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pk4 {
                                 nvidia,pins = "pk4";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -439,13 +426,12 @@
                         spdif_out_pk5 {
                                 nvidia,pins = "spdif_out_pk5";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         spdif_in_pk6 {
                                 nvidia,pins = "spdif_in_pk6";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -459,17 +445,17 @@
                         };
                         dap1_fs_pn0 {
                                 nvidia,pins = "dap1_fs_pn0";
-                                nvidia,function = "i2s0";
+                                nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap1_din_pn1 {
                                 nvidia,pins = "dap1_din_pn1";
-                                nvidia,function = "i2s0";
+                                nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap1_dout_pn2 {
                                 nvidia,pins = "dap1_dout_pn2";
@@ -480,108 +466,104 @@
                         };
                         dap1_sclk_pn3 {
                                 nvidia,pins = "dap1_sclk_pn3";
-                                nvidia,function = "i2s0";
+                                nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         usb_vbus_en0_pn4 {
                                 nvidia,pins = "usb_vbus_en0_pn4";
                                 nvidia,function = "usb";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         usb_vbus_en1_pn5 {
                                 nvidia,pins = "usb_vbus_en1_pn5";
                                 nvidia,function = "usb";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         hdmi_int_pn7 {
                                 nvidia,pins = "hdmi_int_pn7";
-                                nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_data7_po0 {
                                 nvidia,pins = "ulpi_data7_po0";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_data0_po1 {
                                 nvidia,pins = "ulpi_data0_po1";
-                                nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi_data1_po2 {
                                 nvidia,pins = "ulpi_data1_po2";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_data2_po3 {
                                 nvidia,pins = "ulpi_data2_po3";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_data3_po4 {
                                 nvidia,pins = "ulpi_data3_po4";
-                                nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi_data4_po5 {
                                 nvidia,pins = "ulpi_data4_po5";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_data5_po6 {
                                 nvidia,pins = "ulpi_data5_po6";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_data6_po7 {
                                 nvidia,pins = "ulpi_data6_po7";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap3_fs_pp0 {
                                 nvidia,pins = "dap3_fs_pp0";
                                 nvidia,function = "i2s2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap3_din_pp1 {
                                 nvidia,pins = "dap3_din_pp1";
                                 nvidia,function = "i2s2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap3_dout_pp2 {
                                 nvidia,pins = "dap3_dout_pp2";
-                                nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -595,91 +577,87 @@
                         };
                         dap4_fs_pp4 {
                                 nvidia,pins = "dap4_fs_pp4";
-                                nvidia,function = "i2s3";
+                                nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap4_din_pp5 {
                                 nvidia,pins = "dap4_din_pp5";
-                                nvidia,function = "i2s3";
+                                nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap4_dout_pp6 {
                                 nvidia,pins = "dap4_dout_pp6";
-                                nvidia,function = "i2s3";
+                                nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap4_sclk_pp7 {
                                 nvidia,pins = "dap4_sclk_pp7";
-                                nvidia,function = "i2s3";
+                                nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col0_pq0 {
                                 nvidia,pins = "kb_col0_pq0";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_col1_pq1 {
                                 nvidia,pins = "kb_col1_pq1";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col2_pq2 {
                                 nvidia,pins = "kb_col2_pq2";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col3_pq3 {
                                 nvidia,pins = "kb_col3_pq3";
-                                nvidia,function = "kbc";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_col4_pq4 {
                                 nvidia,pins = "kb_col4_pq4";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_col5_pq5 {
                                 nvidia,pins = "kb_col5_pq5";
-                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_col6_pq6 {
                                 nvidia,pins = "kb_col6_pq6";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col7_pq7 {
                                 nvidia,pins = "kb_col7_pq7";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row0_pr0 {
                                 nvidia,pins = "kb_row0_pr0";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -687,121 +665,115 @@
                         kb_row1_pr1 {
                                 nvidia,pins = "kb_row1_pr1";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row2_pr2 {
                                 nvidia,pins = "kb_row2_pr2";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row3_pr3 {
                                 nvidia,pins = "kb_row3_pr3";
-                                nvidia,function = "sys";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row4_pr4 {
                                 nvidia,pins = "kb_row4_pr4";
-                                nvidia,function = "rsvd3";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row5_pr5 {
                                 nvidia,pins = "kb_row5_pr5";
                                 nvidia,function = "rsvd3";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row6_pr6 {
                                 nvidia,pins = "kb_row6_pr6";
                                 nvidia,function = "displaya_alt";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row7_pr7 {
                                 nvidia,pins = "kb_row7_pr7";
-                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row8_ps0 {
                                 nvidia,pins = "kb_row8_ps0";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row9_ps1 {
                                 nvidia,pins = "kb_row9_ps1";
-                                nvidia,function = "rsvd2";
+                                nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row10_ps2 {
                                 nvidia,pins = "kb_row10_ps2";
-                                nvidia,function = "rsvd2";
+                                nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row11_ps3 {
                                 nvidia,pins = "kb_row11_ps3";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row12_ps4 {
                                 nvidia,pins = "kb_row12_ps4";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row13_ps5 {
                                 nvidia,pins = "kb_row13_ps5";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row14_ps6 {
                                 nvidia,pins = "kb_row14_ps6";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row15_ps7 {
                                 nvidia,pins = "kb_row15_ps7";
-                                nvidia,function = "soc";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row16_pt0 {
                                 nvidia,pins = "kb_row16_pt0";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row17_pt1 {
                                 nvidia,pins = "kb_row17_pt1";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gen2_i2c_scl_pt5 {
                                 nvidia,pins = "gen2_i2c_scl_pt5";
@@ -828,72 +800,63 @@
                         };
                         pu0 {
                                 nvidia,pins = "pu0";
-                                nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pu1 {
                                 nvidia,pins = "pu1";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pu2 {
                                 nvidia,pins = "pu2";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pu3 {
                                 nvidia,pins = "pu3";
-                                nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pu4 {
                                 nvidia,pins = "pu4";
-                                nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pu5 {
                                 nvidia,pins = "pu5";
-                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pu6 {
                                 nvidia,pins = "pu6";
-                                nvidia,function = "rsvd3";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pv0 {
                                 nvidia,pins = "pv0";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pv1 {
                                 nvidia,pins = "pv1";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc3_cd_n_pv2 {
                                 nvidia,pins = "sdmmc3_cd_n_pv2";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc1_wp_n_pv3 {
@@ -922,16 +885,16 @@
                         gpio_w2_aud_pw2 {
                                 nvidia,pins = "gpio_w2_aud_pw2";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_w3_aud_pw3 {
                                 nvidia,pins = "gpio_w3_aud_pw3";
                                 nvidia,function = "spi6";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap_mclk1_pw4 {
                                 nvidia,pins = "dap_mclk1_pw4";
@@ -949,17 +912,17 @@
                         };
                         uart3_txd_pw6 {
                                 nvidia,pins = "uart3_txd_pw6";
-                                nvidia,function = "uartc";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         uart3_rxd_pw7 {
                                 nvidia,pins = "uart3_rxd_pw7";
-                                nvidia,function = "uartc";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dvfs_pwm_px0 {
                                 nvidia,pins = "dvfs_pwm_px0";
@@ -970,10 +933,9 @@
                         };
                         gpio_x1_aud_px1 {
                                 nvidia,pins = "gpio_x1_aud_px1";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dvfs_clk_px2 {
                                 nvidia,pins = "dvfs_clk_px2";
@@ -985,34 +947,32 @@
                         gpio_x3_aud_px3 {
                                 nvidia,pins = "gpio_x3_aud_px3";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_x4_aud_px4 {
                                 nvidia,pins = "gpio_x4_aud_px4";
-                                nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x5_aud_px5 {
                                 nvidia,pins = "gpio_x5_aud_px5";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_x6_aud_px6 {
                                 nvidia,pins = "gpio_x6_aud_px6";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_x7_aud_px7 {
                                 nvidia,pins = "gpio_x7_aud_px7";
-                                nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1027,8 +987,8 @@
                         ulpi_dir_py1 {
                                 nvidia,pins = "ulpi_dir_py1";
                                 nvidia,function = "spi1";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi_nxt_py2 {
@@ -1048,44 +1008,44 @@
                         sdmmc1_dat3_py4 {
                                 nvidia,pins = "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_dat2_py5 {
                                 nvidia,pins = "sdmmc1_dat2_py5";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_dat1_py6 {
                                 nvidia,pins = "sdmmc1_dat1_py6";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_dat0_py7 {
                                 nvidia,pins = "sdmmc1_dat0_py7";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_clk_pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_cmd_pz1 {
                                 nvidia,pins = "sdmmc1_cmd_pz1";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pwr_i2c_scl_pz6 {
                                 nvidia,pins = "pwr_i2c_scl_pz6";
@@ -1184,7 +1144,6 @@
                         };
                         pbb3 {
                                 nvidia,pins = "pbb3";
-                                nvidia,function = "vgp3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1198,21 +1157,18 @@
                         };
                         pbb5 {
                                 nvidia,pins = "pbb5";
-                                nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pbb6 {
                                 nvidia,pins = "pbb6";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pbb7 {
                                 nvidia,pins = "pbb7";
-                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1226,15 +1182,13 @@
                         };
                         pcc1 {
                                 nvidia,pins = "pcc1";
-                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pcc2 {
                                 nvidia,pins = "pcc2";
-                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
@@ -1248,8 +1202,8 @@
                         clk2_req_pcc5 {
                                 nvidia,pins = "clk2_req_pcc5";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pex_l0_rst_n_pdd1 {
@@ -1262,15 +1216,15 @@
                         pex_l0_clkreq_n_pdd2 {
                                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
                                 nvidia,function = "pe0";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pex_wake_n_pdd3 {
                                 nvidia,pins = "pex_wake_n_pdd3";
                                 nvidia,function = "pe";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pex_l1_rst_n_pdd5 {
@@ -1283,8 +1237,8 @@
                         pex_l1_clkreq_n_pdd6 {
                                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
                                 nvidia,function = "pe1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk3_out_pee0 {
@@ -1297,13 +1251,12 @@
                         clk3_req_pee1 {
                                 nvidia,pins = "clk3_req_pee1";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap_mclk1_req_pee2 {
                                 nvidia,pins = "dap_mclk1_req_pee2";
-                                nvidia,function = "sata";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1314,7 +1267,7 @@
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_clk_lb_out_pee4 {
                                 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
@@ -1333,24 +1286,24 @@
                         dp_hpd_pff0 {
                                 nvidia,pins = "dp_hpd_pff0";
                                 nvidia,function = "dp";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         usb_vbus_en2_pff1 {
                                 nvidia,pins = "usb_vbus_en2_pff1";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         pff2 {
                                 nvidia,pins = "pff2";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         core_pwr_req {
@@ -1362,7 +1315,7 @@
                         };
                         cpu_pwr_req {
                                 nvidia,pins = "cpu_pwr_req";
-                                nvidia,function = "rsvd2";
+                                nvidia,function = "cpu";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1371,7 +1324,7 @@
                                 nvidia,pins = "pwr_int_n";
                                 nvidia,function = "pmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         reset_out_n {
@@ -1379,7 +1332,7 @@
                                 nvidia,function = "reset_out_n";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         owr {
                                 nvidia,pins = "owr";
@@ -1391,9 +1344,9 @@
                         };
                         clk_32k_in {
                                 nvidia,pins = "clk_32k_in";
-                                nvidia,function = "rsvd2";
+                                nvidia,function = "clk";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         jtag_rtck {
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
new file mode 100644
index 000000000000..1a5748d05dda
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
@@ -0,0 +1,2023 @@
+/ {
+        clock@0,60006000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+                                clock-names = "emc-parent";
+                        };
+                        /* TODO: Add 528MHz frequency */
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                };
+        };
+
+        emc@0,7001b000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000060
+                                        0x00000000
+                                        0x00000018
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000005
+                                        0x00000005
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000064
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000007
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x800001c5
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000005
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000026
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000006
+                                        0x00000006
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x000000a0
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000023a
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000001
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000001
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000134
+                                        0x00000000
+                                        0x0000004d
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000008
+                                        0x0000000f
+                                        0x0000000c
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000013f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000015
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000370
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000003
+                                        0x00000011
+                                        0x00000000
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000202
+                                        0x00000000
+                                        0x00000080
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x0000000f
+                                        0x0000000f
+                                        0x00000013
+                                        0x00000013
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000001
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000213
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000022
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000050e
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000004
+                                        0x0000001a
+                                        0x00000000
+                                        0x00000003
+                                        0x00000001
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000304
+                                        0x00000000
+                                        0x000000c1
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000018
+                                        0x0000000f
+                                        0x0000001c
+                                        0x0000001c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000031c
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000033
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000713
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x0000088d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000009
+                                        0x00000035
+                                        0x00000000
+                                        0x00000007
+                                        0x00000002
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x00000006
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000011
+                                        0x00000607
+                                        0x00000000
+                                        0x00000181
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000032
+                                        0x0000000f
+                                        0x00000038
+                                        0x00000038
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000007
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000638
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00094000
+                                        0x00094000
+                                        0x00009400
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000066
+                                        0x00000000
+                                        0x00000100
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000d2b3
+                                        0x80000d22
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x000008d5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000321>;
+                                nvidia,emc-mrs-wait-cnt = <0x0174000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000000d
+                                        0x0000004c
+                                        0x00000000
+                                        0x00000009
+                                        0x00000003
+                                        0x00000004
+                                        0x00000008
+                                        0x00000002
+                                        0x00000009
+                                        0x00000003
+                                        0x00000003
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000007
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x0000000e
+                                        0x00000010
+                                        0x00000012
+                                        0x000008e4
+                                        0x00000000
+                                        0x00000239
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x0000004a
+                                        0x0000000e
+                                        0x00000051
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000009
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000924
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00098000
+                                        0x00098000
+                                        0x00000000
+                                        0x00098000
+                                        0x00098000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00060000
+                                        0x00060000
+                                        0x00060000
+                                        0x00060000
+                                        0x00006000
+                                        0x00006000
+                                        0x00006000
+                                        0x00006000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000101
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000096
+                                        0x00000000
+                                        0x00000100
+                                        0x0174000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x800012d7
+                                        0x00000009
+                                >;
+                        };
+
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x00000895>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000521>;
+                                nvidia,emc-mrs-wait-cnt = <0x015b000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000012
+                                        0x00000065
+                                        0x00000000
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000008
+                                        0x00000002
+                                        0x0000000a
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000001
+                                        0x00000008
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000f
+                                        0x00000010
+                                        0x00000012
+                                        0x00000bd1
+                                        0x00000000
+                                        0x000002f4
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x00000063
+                                        0x0000000f
+                                        0x0000006b
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x0000000d
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000c11
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00070000
+                                        0x00070000
+                                        0x00000000
+                                        0x00070000
+                                        0x00070000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00048000
+                                        0x00048000
+                                        0x00004800
+                                        0x00004800
+                                        0x00004800
+                                        0x00004800
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000101
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x000000c6
+                                        0x00000000
+                                        0x00000100
+                                        0x015b000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x8000188b
+                                        0x00000009
+                                >;
+                        };
+
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200010>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000b61>;
+                                nvidia,emc-mrs-wait-cnt = <0x0128000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000001c
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000013
+                                        0x00000007
+                                        0x00000007
+                                        0x0000000b
+                                        0x00000003
+                                        0x00000010
+                                        0x00000007
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000b
+                                        0x00070000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000002
+                                        0x00000012
+                                        0x00000016
+                                        0x00000018
+                                        0x00001208
+                                        0x00000000
+                                        0x00000482
+                                        0x00000002
+                                        0x0000000d
+                                        0x00000001
+                                        0x00000000
+                                        0x00000096
+                                        0x00000015
+                                        0x000000a2
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000015
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00001249
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00e00b1
+                                        0x00008000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000005
+                                        0x00000006
+                                        0x00000003
+                                        0x00000006
+                                        0x00000005
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000005
+                                        0x00000006
+                                        0x00000003
+                                        0x00000006
+                                        0x00000005
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000101
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x0128000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000040a0
+                                        0x800024aa
+                                        0x0000000e
+                                >;
+                        };
+
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0080089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200418>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000d71>;
+                                nvidia,emc-mrs-wait-cnt = <0x00f8000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000025
+                                        0x000000cc
+                                        0x00000000
+                                        0x0000001a
+                                        0x00000009
+                                        0x00000008
+                                        0x0000000d
+                                        0x00000004
+                                        0x00000013
+                                        0x00000009
+                                        0x00000009
+                                        0x00000003
+                                        0x00000002
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x0000000d
+                                        0x00080000
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x00000014
+                                        0x00000018
+                                        0x0000001a
+                                        0x000017e2
+                                        0x00000000
+                                        0x000005f8
+                                        0x00000003
+                                        0x00000011
+                                        0x00000001
+                                        0x00000000
+                                        0x000000c6
+                                        0x00000018
+                                        0x000000d6
+                                        0x00000200
+                                        0x00000005
+                                        0x00000006
+                                        0x00000005
+                                        0x0000001d
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00001822
+                                        0x00000000
+                                        0x80000005
+                                        0x00000000
+                                        0x104ab198
+                                        0xe00700b1
+                                        0x00008000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00034000
+                                        0x00034000
+                                        0x00000000
+                                        0x00034000
+                                        0x00034000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00000005
+                                        0x00000009
+                                        0x00000009
+                                        0x00000007
+                                        0x00000009
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000005
+                                        0x00000009
+                                        0x00000009
+                                        0x00000007
+                                        0x00000009
+                                        0x00000008
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000101
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x61861820
+                                        0x00514514
+                                        0x00514514
+                                        0x61861800
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x00f8000c
+                                        0x00000007
+                                        0x00000004
+                                        0x00004080
+                                        0x80003012
+                                        0x0000000f
+                                >;
+                        };
+
+                };
+        };
+
+        memory-controller@0,70019000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+
+                                nvidia,emem-configuration = <
+                                        0x40040001
+                                        0x8000000a
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x77e30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+
+                                nvidia,emem-configuration = <
+                                        0x40020001
+                                        0x80000012
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x76230303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+
+                                nvidia,emem-configuration = <
+                                        0xa0000001
+                                        0x80000017
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x74a30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x00000001
+                                        0x8000001e
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x74230403
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x08000001
+                                        0x80000026
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0403
+                                        0x73c30504
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x01000003
+                                        0x80000040
+                                        0x00000001
+                                        0x00000001
+                                        0x00000005
+                                        0x00000002
+                                        0x00000004
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040203
+                                        0x000a0405
+                                        0x73840a06
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x08000004
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000004
+                                        0x00000005
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000b0607
+                                        0x77450e08
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0f000005
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000005
+                                        0x00000007
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000d0709
+                                        0x7586120a
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x00000009
+                                        0x80000040
+                                        0x00000003
+                                        0x00000004
+                                        0x0000000e
+                                        0x00000009
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000007
+                                        0x07050202
+                                        0x00130b0e
+                                        0x73a91b0f
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0e00000b
+                                        0x80000040
+                                        0x00000004
+                                        0x00000005
+                                        0x00000013
+                                        0x0000000c
+                                        0x0000000f
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000c
+                                        0x00000002
+                                        0x00000002
+                                        0x00000006
+                                        0x00000008
+                                        0x08060202
+                                        0x00160d13
+                                        0x734c2414
+                                        0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index 004e8e4e1c04..2d21253ea4e3 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -1,46 +1,29 @@
 /dts-v1/;
 
-#include <dt-bindings/input/input.h>
-#include "tegra124.dtsi"
+#include "tegra124-nyan.dtsi"
+
+#include "tegra124-nyan-big-emc.dtsi"
 
 / {
         model = "Acer Chromebook 13 CB5-311";
         compatible = "google,nyan-big", "nvidia,tegra124";
 
-        aliases {
-                rtc0 = "/i2c@0,7000d000/pmic@40";
-                rtc1 = "/rtc@0,7000e000";
-                serial0 = &uarta;
-        };
+        panel: panel {
+                compatible = "auo,b133xtn01";
 
-        memory {
-                reg = <0x0 0x80000000 0x0 0x80000000>;
+                backlight = <&backlight>;
+                ddc-i2c-bus = <&dpaux>;
         };
 
-        host1x@0,50000000 {
-                hdmi@0,54280000 {
-                        status = "okay";
-
-                        vdd-supply = <&vdd_3v3_hdmi>;
-                        pll-supply = <&vdd_hdmi_pll>;
-                        hdmi-supply = <&vdd_5v0_hdmi>;
-
-                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio =
-                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
-                };
-
-                sor@0,54540000 {
-                        status = "okay";
-
-                        nvidia,dpaux = <&dpaux>;
-                        nvidia,panel = <&panel>;
-                };
+        sdhci@0,700b0400 { /* SD Card on this bus */
+                wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+        };
 
-                dpaux@0,545c0000 {
-                        vdd-supply = <&vdd_3v3_panel>;
-                        status = "okay";
-                };
+        sound {
+                compatible = "nvidia,tegra-audio-max98090-nyan-big",
+                             "nvidia,tegra-audio-max98090-nyan",
+                             "nvidia,tegra-audio-max98090";
+                nvidia,model = "GoogleNyanBig";
         };
 
         pinmux@0,70000868 {
@@ -48,1092 +31,1308 @@
                 pinctrl-0 = <&pinmux_default>;
 
                 pinmux_default: common {
-                        dap_mclk1_pw4 {
-                                nvidia,pins = "dap_mclk1_pw4";
-                                nvidia,function = "extperiph1";
+                        clk_32k_out_pa0 {
+                                nvidia,pins = "clk_32k_out_pa0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "i2s1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap2_din_pa4 {
                                 nvidia,pins = "dap2_din_pa4";
                                 nvidia,function = "i2s1";
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap2_dout_pa5 {
-                                nvidia,pins = "dap2_dout_pa5",
-                                              "dap2_fs_pa2",
-                                              "dap2_sclk_pa3";
+                                nvidia,pins = "dap2_dout_pa5";
                                 nvidia,function = "i2s1";
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dvfs_pwm_px0 {
-                                nvidia,pins = "dvfs_pwm_px0",
-                                              "dvfs_clk_px2";
-                                nvidia,function = "cldvfs";
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_clk_py0 {
-                                nvidia,pins = "ulpi_clk_py0",
-                                              "ulpi_nxt_py2",
-                                              "ulpi_stp_py3";
-                                nvidia,function = "spi1";
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pb0 {
+                                nvidia,pins = "pb0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pb1 {
+                                nvidia,pins = "pb1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        ulpi_dir_py1 {
-                                nvidia,pins = "ulpi_dir_py1";
-                                nvidia,function = "spi1";
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pc7 {
+                                nvidia,pins = "pc7";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        cam_i2c_scl_pbb1 {
-                                nvidia,pins = "cam_i2c_scl_pbb1",
-                                              "cam_i2c_sda_pbb2";
-                                nvidia,function = "i2c3";
+                        pg0 {
+                                nvidia,pins = "pg0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg1 {
+                                nvidia,pins = "pg1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        gen2_i2c_scl_pt5 {
-                                nvidia,pins = "gen2_i2c_scl_pt5",
-                                              "gen2_i2c_sda_pt6";
-                                nvidia,function = "i2c2";
+                        pg2 {
+                                nvidia,pins = "pg2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg3 {
+                                nvidia,pins = "pg3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pg4 {
-                                nvidia,pins = "pg4",
-                                              "pg5",
-                                              "pg6",
-                                              "pi3";
+                                nvidia,pins = "pg4";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg5 {
+                                nvidia,pins = "pg5";
                                 nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg6 {
+                                nvidia,pins = "pg6";
+                                nvidia,function = "spi4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pg7 {
                                 nvidia,pins = "pg7";
                                 nvidia,function = "spi4";
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ph1 {
                                 nvidia,pins = "ph1";
                                 nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph2 {
+                                nvidia,pins = "ph2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pk0 {
-                                nvidia,pins = "pk0",
-                                              "kb_row15_ps7",
-                                              "clk_32k_out_pa0";
-                                nvidia,function = "soc";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                        ph3 {
+                                nvidia,pins = "ph3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph4 {
+                                nvidia,pins = "ph4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_clk_pz0 {
-                                nvidia,pins = "sdmmc1_clk_pz0";
-                                nvidia,function = "sdmmc1";
+                        ph5 {
+                                nvidia,pins = "ph5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph6 {
+                                nvidia,pins = "ph6";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_cmd_pz1 {
-                                nvidia,pins = "sdmmc1_cmd_pz1",
-                                              "sdmmc1_dat0_py7",
-                                              "sdmmc1_dat1_py6",
-                                              "sdmmc1_dat2_py5",
-                                              "sdmmc1_dat3_py4";
-                                nvidia,function = "sdmmc1";
+                        ph7 {
+                                nvidia,pins = "ph7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi0 {
+                                nvidia,pins = "pi0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi1 {
+                                nvidia,pins = "pi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi2 {
+                                nvidia,pins = "pi2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi3 {
+                                nvidia,pins = "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi4 {
+                                nvidia,pins = "pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi5 {
+                                nvidia,pins = "pi5";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        sdmmc3_clk_pa6 {
-                                nvidia,pins = "sdmmc3_clk_pa6";
-                                nvidia,function = "sdmmc3";
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        pi6 {
+                                nvidia,pins = "pi6";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_cmd_pa7 {
-                                nvidia,pins = "sdmmc3_cmd_pa7",
-                                              "sdmmc3_dat0_pb7",
-                                              "sdmmc3_dat1_pb6",
-                                              "sdmmc3_dat2_pb5",
-                                              "sdmmc3_dat3_pb4",
-                                              "kb_col4_pq4",
-                                              "sdmmc3_clk_lb_out_pee4",
-                                              "sdmmc3_clk_lb_in_pee5",
-                                              "sdmmc3_cd_n_pv2";
-                                nvidia,function = "sdmmc3";
+                        pi7 {
+                                nvidia,pins = "pi7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj0 {
+                                nvidia,pins = "pj0";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_clk_pcc4 {
-                                nvidia,pins = "sdmmc4_clk_pcc4";
-                                nvidia,function = "sdmmc4";
+                        pj2 {
+                                nvidia,pins = "pj2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pj7 {
+                                nvidia,pins = "pj7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk0 {
+                                nvidia,pins = "pk0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk1 {
+                                nvidia,pins = "pk1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        sdmmc4_cmd_pt7 {
-                                nvidia,pins = "sdmmc4_cmd_pt7",
-                                              "sdmmc4_dat0_paa0",
-                                              "sdmmc4_dat1_paa1",
-                                              "sdmmc4_dat2_paa2",
-                                              "sdmmc4_dat3_paa3",
-                                              "sdmmc4_dat4_paa4",
-                                              "sdmmc4_dat5_paa5",
-                                              "sdmmc4_dat6_paa6",
-                                              "sdmmc4_dat7_paa7";
-                                nvidia,function = "sdmmc4";
+                        pk2 {
+                                nvidia,pins = "pk2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk3 {
+                                nvidia,pins = "pk3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk4 {
+                                nvidia,pins = "pk4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        pwr_i2c_scl_pz6 {
-                                nvidia,pins = "pwr_i2c_scl_pz6",
-                                              "pwr_i2c_sda_pz7";
-                                nvidia,function = "i2cpwr";
+                        spdif_out_pk5 {
+                                nvidia,pins = "spdif_out_pk5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk7 {
+                                nvidia,pins = "pk7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_fs_pn0 {
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_sclk_pn3 {
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "usb";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        jtag_rtck {
-                                nvidia,pins = "jtag_rtck";
-                                nvidia,function = "rtck";
+                        usb_vbus_en1_pn5 {
+                                nvidia,pins = "usb_vbus_en1_pn5";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data7_po0 {
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data0_po1 {
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data1_po2 {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data2_po3 {
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data3_po4 {
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data6_po7 {
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_fs_pp4 {
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_sclk_pp7 {
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col3_pq3 {
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        clk_32k_in {
-                                nvidia,pins = "clk_32k_in";
-                                nvidia,function = "clk";
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        core_pwr_req {
-                                nvidia,pins = "core_pwr_req";
-                                nvidia,function = "pwron";
+                        kb_row0_pr0 {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        cpu_pwr_req {
-                                nvidia,pins = "cpu_pwr_req";
-                                nvidia,function = "cpu";
+                        kb_row2_pr2 {
+                                nvidia,pins = "kb_row2_pr2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row3_pr3 {
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row4_pr4 {
+                                nvidia,pins = "kb_row4_pr4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pwr_int_n {
-                                nvidia,pins = "pwr_int_n";
-                                nvidia,function = "pmi";
+                        kb_row5_pr5 {
+                                nvidia,pins = "kb_row5_pr5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row7_pr7 {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                        };
+                        kb_row8_ps0 {
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        reset_out_n {
-                                nvidia,pins = "reset_out_n";
-                                nvidia,function = "reset_out_n";
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row12_ps4 {
+                                nvidia,pins = "kb_row12_ps4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        clk3_out_pee0 {
-                                nvidia,pins = "clk3_out_pee0";
-                                nvidia,function = "extperiph3";
+                        kb_row13_ps5 {
+                                nvidia,pins = "kb_row13_ps5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row14_ps6 {
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row15_ps7 {
+                                nvidia,pins = "kb_row15_ps7";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        gen1_i2c_sda_pc5 {
-                                nvidia,pins = "gen1_i2c_sda_pc5",
-                                              "gen1_i2c_scl_pc4";
-                                nvidia,function = "i2c1";
+                        kb_row16_pt0 {
+                                nvidia,pins = "kb_row16_pt0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row17_pt1 {
+                                nvidia,pins = "kb_row17_pt1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "i2c2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        hdmi_cec_pee3 {
-                                nvidia,pins = "hdmi_cec_pee3";
-                                nvidia,function = "cec";
+                        gen2_i2c_sda_pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
+                                nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        hdmi_int_pn7 {
-                                nvidia,pins = "hdmi_int_pn7";
+                        pu0 {
+                                nvidia,pins = "pu0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu2 {
+                                nvidia,pins = "pu2";
                                 nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu5 {
+                                nvidia,pins = "pu5";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv1 {
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cd_n_pv2 {
+                                nvidia,pins = "sdmmc3_cd_n_pv2";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_wp_n_pv3 {
+                                nvidia,pins = "sdmmc1_wp_n_pv3";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ddc_scl_pv4 {
-                                nvidia,pins = "ddc_scl_pv4",
-                                              "ddc_sda_pv5";
+                                nvidia,pins = "ddc_scl_pv4";
                                 nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
-                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row10_ps2 {
-                                nvidia,pins = "kb_row10_ps2";
-                                nvidia,function = "uarta";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                        gpio_w2_aud_pw2 {
+                                nvidia,pins = "gpio_w2_aud_pw2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_w3_aud_pw3 {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        kb_row9_ps1 {
-                                nvidia,pins = "kb_row9_ps1";
-                                nvidia,function = "uarta";
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        usb_vbus_en0_pn4 {
-                                nvidia,pins = "usb_vbus_en0_pn4",
-                                              "usb_vbus_en1_pn5";
-                                nvidia,function = "usb";
+                        clk2_out_pw5 {
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x1_aud_px1 {
+                                nvidia,pins = "gpio_x1_aud_px1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dvfs_clk_px2 {
+                                nvidia,pins = "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        drive_sdio1 {
-                                nvidia,pins = "drive_sdio1";
-                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
-                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,pull-down-strength = <36>;
-                                nvidia,pull-up-strength = <20>;
-                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
-                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
-                        };
-                        drive_sdio3 {
-                                nvidia,pins = "drive_sdio3";
-                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
-                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,pull-down-strength = <22>;
-                                nvidia,pull-up-strength = <36>;
-                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                        };
-                        drive_gma {
-                                nvidia,pins = "drive_gma";
-                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
-                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,pull-down-strength = <2>;
-                                nvidia,pull-up-strength = <1>;
-                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                                nvidia,drive-type = <1>;
-                        };
-                        codec_irq_l {
-                                nvidia,pins = "ph4";
-                                nvidia,function = "gmi";
+                        gpio_x3_aud_px3 {
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x4_aud_px4 {
+                                nvidia,pins = "gpio_x4_aud_px4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        lcd_bl_en {
-                                nvidia,pins = "ph2";
+                        gpio_x5_aud_px5 {
+                                nvidia,pins = "gpio_x5_aud_px5";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x6_aud_px6 {
+                                nvidia,pins = "gpio_x6_aud_px6";
                                 nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x7_aud_px7 {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        touch_irq_l {
-                                nvidia,pins = "gpio_w3_aud_pw3";
-                                nvidia,function = "spi6";
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0";
+                                nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        tpm_davint_l {
-                                nvidia,pins = "ph6";
-                                nvidia,function = "gmi";
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        ts_irq_l {
-                                nvidia,pins = "pk2";
-                                nvidia,function = "gmi";
+                        ulpi_nxt_py2 {
+                                nvidia,pins = "ulpi_nxt_py2";
+                                nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ts_reset_l {
-                                nvidia,pins = "pk4";
-                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ts_shdn_l {
-                                nvidia,pins = "pk1";
-                                nvidia,function = "gmi";
+                        sdmmc1_dat3_py4 {
+                                nvidia,pins = "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        ph7 {
-                                nvidia,pins = "ph7";
-                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                        sdmmc1_dat2_py5 {
+                                nvidia,pins = "sdmmc1_dat2_py5";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        kb_col0_ap {
-                                nvidia,pins = "kb_col0_pq0";
-                                nvidia,function = "rsvd4";
+                        sdmmc1_dat1_py6 {
+                                nvidia,pins = "sdmmc1_dat1_py6";
+                                nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        lid_open {
-                                nvidia,pins = "kb_row4_pr4";
-                                nvidia,function = "rsvd3";
+                        sdmmc1_dat0_py7 {
+                                nvidia,pins = "sdmmc1_dat0_py7";
+                                nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        en_vdd_sd {
-                                nvidia,pins = "kb_row0_pr0";
-                                nvidia,function = "rsvd4";
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        ac_ok {
-                                nvidia,pins = "pj0";
-                                nvidia,function = "gmi";
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1";
+                                nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sensor_irq_l {
-                                nvidia,pins = "pi6";
-                                nvidia,function = "gmi";
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6";
+                                nvidia,function = "i2cpwr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        wifi_en {
-                                nvidia,pins = "gpio_x7_aud_px7";
-                                nvidia,function = "rsvd4";
+                        pwr_i2c_sda_pz7 {
+                                nvidia,pins = "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat1_paa1 {
+                                nvidia,pins = "sdmmc4_dat1_paa1";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "vgp6";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        en_vdd_bl {
-                                nvidia,pins = "dap3_dout_pp2";
-                                nvidia,function = "i2s2";
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3";
+                                nvidia,function = "vgp3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb7 {
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc1 {
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc2 {
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        en_vdd_hdmi {
-                                nvidia,pins = "spdif_in_pk6";
-                                nvidia,function = "spdif";
+                        pex_l0_rst_n_pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 {
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_req_pee2 {
+                                nvidia,pins = "dap_mclk1_req_pee2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_lb_out_pee4 {
+                                nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        soc_warm_reset_l {
-                                nvidia,pins = "pi5";
-                                nvidia,function = "gmi";
+                        sdmmc3_clk_lb_in_pee5 {
+                                nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        hp_det_l {
-                                nvidia,pins = "pi7";
-                                nvidia,function = "rsvd1";
+                        dp_hpd_pff0 {
+                                nvidia,pins = "dp_hpd_pff0";
+                                nvidia,function = "dp";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        mic_det_l {
-                                nvidia,pins = "kb_row7_pr7";
+                        usb_vbus_en2_pff1 {
+                                nvidia,pins = "usb_vbus_en2_pff1";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pff2 {
+                                nvidia,pins = "pff2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                };
-        };
-
-        serial@0,70006000 {
-                /* Debug connector on the bottom of the board near SD card. */
-                status = "okay";
-        };
-
-        pwm@0,7000a000 {
-                status = "okay";
-        };
-
-        i2c@0,7000c000 {
-                status = "okay";
-                clock-frequency = <100000>;
-
-                acodec: audio-codec@10 {
-                        compatible = "maxim,max98090";
-                        reg = <0x10>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
-                };
-
-                temperature-sensor@4c {
-                        compatible = "ti,tmp451";
-                        reg = <0x4c>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
-
-                        #thermal-sensor-cells = <1>;
-                };
-        };
-
-        i2c@0,7000c400 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-
-        i2c@0,7000c500 {
-                status = "okay";
-                clock-frequency = <400000>;
-
-                tpm@20 {
-                        compatible = "infineon,slb9645tt";
-                        reg = <0x20>;
-                };
-        };
-
-        hdmi_ddc: i2c@0,7000c700 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-
-        i2c@0,7000d000 {
-                status = "okay";
-                clock-frequency = <400000>;
-
-                pmic: pmic@40 {
-                        compatible = "ams,as3722";
-                        reg = <0x40>;
-                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-
-                        ams,system-power-controller;
-
-                        #interrupt-cells = <2>;
-                        interrupt-controller;
-
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&as3722_default>;
-
-                        as3722_default: pinmux {
-                                gpio0 {
-                                        pins = "gpio0";
-                                        function = "gpio";
-                                        bias-pull-down;
-                                };
-
-                                gpio1 {
-                                        pins = "gpio1";
-                                        function = "gpio";
-                                        bias-pull-up;
-                                };
-
-                                gpio2_4_7 {
-                                        pins = "gpio2", "gpio4", "gpio7";
-                                        function = "gpio";
-                                        bias-pull-up;
-                                };
-
-                                gpio3_6 {
-                                        pins = "gpio3", "gpio6";
-                                        bias-high-impedance;
-                                };
-
-                                gpio5 {
-                                        pins = "gpio5";
-                                        function = "clk32k-out";
-                                        bias-pull-down;
-                                };
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-
-                        regulators {
-                                vsup-sd2-supply = <&vdd_5v0_sys>;
-                                vsup-sd3-supply = <&vdd_5v0_sys>;
-                                vsup-sd4-supply = <&vdd_5v0_sys>;
-                                vsup-sd5-supply = <&vdd_5v0_sys>;
-                                vin-ldo0-supply = <&vdd_1v35_lp0>;
-                                vin-ldo1-6-supply = <&vdd_3v3_run>;
-                                vin-ldo2-5-7-supply = <&vddio_1v8>;
-                                vin-ldo3-4-supply = <&vdd_3v3_sys>;
-                                vin-ldo9-10-supply = <&vdd_5v0_sys>;
-                                vin-ldo11-supply = <&vdd_3v3_run>;
-
-                                sd0 {
-                                        regulator-name = "+VDD_CPU_AP";
-                                        regulator-min-microvolt = <700000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-min-microamp = <3500000>;
-                                        regulator-max-microamp = <3500000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        ams,ext-control = <2>;
-                                };
-
-                                sd1 {
-                                        regulator-name = "+VDD_CORE";
-                                        regulator-min-microvolt = <700000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-min-microamp = <2500000>;
-                                        regulator-max-microamp = <4000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        ams,ext-control = <1>;
-                                };
-
-                                vdd_1v35_lp0: sd2 {
-                                        regulator-name = "+1.35V_LP0(sd2)";
-                                        regulator-min-microvolt = <1350000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-
-                                sd3 {
-                                        regulator-name = "+1.35V_LP0(sd3)";
-                                        regulator-min-microvolt = <1350000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-
-                                vdd_1v05_run: sd4 {
-                                        regulator-name = "+1.05V_RUN";
-                                        regulator-min-microvolt = <1050000>;
-                                        regulator-max-microvolt = <1050000>;
-                                };
-
-                                vddio_1v8: sd5 {
-                                        regulator-name = "+1.8V_VDDIO";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                };
-
-                                sd6 {
-                                        regulator-name = "+VDD_GPU_AP";
-                                        regulator-min-microvolt = <650000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-min-microamp = <3500000>;
-                                        regulator-max-microamp = <3500000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                };
-
-                                ldo0 {
-                                        regulator-name = "+1.05V_RUN_AVDD";
-                                        regulator-min-microvolt = <1050000>;
-                                        regulator-max-microvolt = <1050000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                        ams,ext-control = <1>;
-                                };
-
-                                ldo1 {
-                                        regulator-name = "+1.8V_RUN_CAM";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-
-                                ldo2 {
-                                        regulator-name = "+1.2V_GEN_AVDD";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                };
-
-                                ldo3 {
-                                        regulator-name = "+1.00V_LP0_VDD_RTC";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                        ams,enable-tracking;
-                                };
-
-                                vdd_run_cam: ldo4 {
-                                        regulator-name = "+3.3V_RUN_CAM";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                };
-
-                                ldo5 {
-                                        regulator-name = "+1.2V_RUN_CAM_FRONT";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                };
-
-                                vddio_sdmmc3: ldo6 {
-                                        regulator-name = "+VDDIO_SDMMC3";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <3300000>;
-                                };
-
-                                ldo7 {
-                                        regulator-name = "+1.05V_RUN_CAM_REAR";
-                                        regulator-min-microvolt = <1050000>;
-                                        regulator-max-microvolt = <1050000>;
-                                };
-
-                                ldo9 {
-                                        regulator-name = "+2.8V_RUN_TOUCH";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                };
-
-                                ldo10 {
-                                        regulator-name = "+2.8V_RUN_CAM_AF";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                };
-
-                                ldo11 {
-                                        regulator-name = "+1.8V_RUN_VPP_FUSE";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
                         };
-                };
-        };
-
-        spi@0,7000d400 {
-                status = "okay";
-
-                cros_ec: cros-ec@0 {
-                        compatible = "google,cros-ec-spi";
-                        spi-max-frequency = <3000000>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
-                        reg = <0>;
-
-                        google,cros-ec-spi-msg-delay = <2000>;
-
-                        i2c-tunnel {
-                                compatible = "google,cros-ec-i2c-tunnel";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                google,remote-bus = <0>;
-
-                                charger: bq24735@9 {
-                                        compatible = "ti,bq24735";
-                                        reg = <0x9>;
-                                        interrupt-parent = <&gpio>;
-                                        interrupts = <TEGRA_GPIO(J, 0)
-                                                        GPIO_ACTIVE_HIGH>;
-                                        ti,ac-detect-gpios = <&gpio
-                                                        TEGRA_GPIO(J, 0)
-                                                        GPIO_ACTIVE_HIGH>;
-                                };
-
-                                battery: sbs-battery@b {
-                                        compatible = "sbs,sbs-battery";
-                                        reg = <0xb>;
-                                        sbs,i2c-retry-count = <2>;
-                                        sbs,poll-retry-count = <10>;
-                                        power-supplies = <&charger>;
-                                };
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                 };
         };
-
-        spi@0,7000da00 {
-                status = "okay";
-                spi-max-frequency = <25000000>;
-
-                flash@0 {
-                        compatible = "winbond,w25q32dw";
-                        reg = <0>;
-                };
-        };
-
-        pmc@0,7000e400 {
-                nvidia,invert-interrupt;
-                nvidia,suspend-mode = <0>;
-                nvidia,cpu-pwr-good-time = <500>;
-                nvidia,cpu-pwr-off-time = <300>;
-                nvidia,core-pwr-good-time = <641 3845>;
-                nvidia,core-pwr-off-time = <61036>;
-                nvidia,core-power-req-active-high;
-                nvidia,sys-clock-req-active-high;
-        };
-
-        hda@0,70030000 {
-                status = "okay";
-        };
-
-        sdhci@0,700b0000 { /* WiFi/BT on this bus */
-                status = "okay";
-                power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
-                bus-width = <4>;
-                no-1-8-v;
-                non-removable;
-        };
-
-        sdhci@0,700b0400 { /* SD Card on this bus */
-                status = "okay";
-                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
-                wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
-                bus-width = <4>;
-                no-1-8-v;
-                vqmmc-supply = <&vddio_sdmmc3>;
-        };
-
-        sdhci@0,700b0600 { /* eMMC on this bus */
-                status = "okay";
-                bus-width = <8>;
-                no-1-8-v;
-                non-removable;
-        };
-
-        ahub@0,70300000 {
-                i2s@0,70301100 {
-                        status = "okay";
-                };
-        };
-
-        usb@0,7d000000 { /* Rear external USB port. */
-                status = "okay";
-        };
-
-        usb-phy@0,7d000000 {
-                status = "okay";
-                vbus-supply = <&vdd_usb1_vbus>;
-        };
-
-        usb@0,7d004000 { /* Internal webcam. */
-                status = "okay";
-        };
-
-        usb-phy@0,7d004000 {
-                status = "okay";
-                vbus-supply = <&vdd_run_cam>;
-        };
-
-        usb@0,7d008000 { /* Left external USB port. */
-                status = "okay";
-        };
-
-        usb-phy@0,7d008000 {
-                status = "okay";
-                vbus-supply = <&vdd_usb3_vbus>;
-        };
-
-        backlight: backlight {
-                compatible = "pwm-backlight";
-
-                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
-                power-supply = <&vdd_led>;
-                pwms = <&pwm 1 1000000>;
-
-                default-brightness-level = <224>;
-                brightness-levels =
-                        <  0   1   2   3   4   5   6   7
-                           8   9  10  11  12  13  14  15
-                          16  17  18  19  20  21  22  23
-                          24  25  26  27  28  29  30  31
-                          32  33  34  35  36  37  38  39
-                          40  41  42  43  44  45  46  47
-                          48  49  50  51  52  53  54  55
-                          56  57  58  59  60  61  62  63
-                          64  65  66  67  68  69  70  71
-                          72  73  74  75  76  77  78  79
-                          80  81  82  83  84  85  86  87
-                          88  89  90  91  92  93  94  95
-                          96  97  98  99 100 101 102 103
-                         104 105 106 107 108 109 110 111
-                         112 113 114 115 116 117 118 119
-                         120 121 122 123 124 125 126 127
-                         128 129 130 131 132 133 134 135
-                         136 137 138 139 140 141 142 143
-                         144 145 146 147 148 149 150 151
-                         152 153 154 155 156 157 158 159
-                         160 161 162 163 164 165 166 167
-                         168 169 170 171 172 173 174 175
-                         176 177 178 179 180 181 182 183
-                         184 185 186 187 188 189 190 191
-                         192 193 194 195 196 197 198 199
-                         200 201 202 203 204 205 206 207
-                         208 209 210 211 212 213 214 215
-                         216 217 218 219 220 221 222 223
-                         224 225 226 227 228 229 230 231
-                         232 233 234 235 236 237 238 239
-                         240 241 242 243 244 245 246 247
-                         248 249 250 251 252 253 254 255
-                         256>;
-        };
-
-        clocks {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                clk32k_in: clock@0 {
-                        compatible = "fixed-clock";
-                        reg = <0>;
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
-        };
-
-        gpio-keys {
-                compatible = "gpio-keys";
-
-                lid {
-                        label = "Lid";
-                        gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
-                        linux,input-type = <5>;
-                        linux,code = <KEY_RESERVED>;
-                        debounce-interval = <1>;
-                        gpio-key,wakeup;
-                };
-
-                power {
-                        label = "Power";
-                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_POWER>;
-                        debounce-interval = <30>;
-                        gpio-key,wakeup;
-                };
-        };
-
-        panel: panel {
-                compatible = "auo,b133xtn01";
-
-                backlight = <&backlight>;
-                ddc-i2c-bus = <&dpaux>;
-        };
-
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                vdd_mux: regulator@0 {
-                        compatible = "regulator-fixed";
-                        reg = <0>;
-                        regulator-name = "+VDD_MUX";
-                        regulator-min-microvolt = <12000000>;
-                        regulator-max-microvolt = <12000000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                };
-
-                vdd_5v0_sys: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "+5V_SYS";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        vin-supply = <&vdd_mux>;
-                };
-
-                vdd_3v3_sys: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        regulator-name = "+3.3V_SYS";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        vin-supply = <&vdd_mux>;
-                };
-
-                vdd_3v3_run: regulator@3 {
-                        compatible = "regulator-fixed";
-                        reg = <3>;
-                        regulator-name = "+3.3V_RUN";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_3v3_sys>;
-                };
-
-                vdd_3v3_hdmi: regulator@4 {
-                        compatible = "regulator-fixed";
-                        reg = <4>;
-                        regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        vin-supply = <&vdd_3v3_run>;
-                };
-
-                vdd_led: regulator@5 {
-                        compatible = "regulator-fixed";
-                        reg = <5>;
-                        regulator-name = "+VDD_LED";
-                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_mux>;
-                };
-
-                vdd_5v0_ts: regulator@6 {
-                        compatible = "regulator-fixed";
-                        reg = <6>;
-                        regulator-name = "+5V_VDD_TS_SW";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-boot-on;
-                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_5v0_sys>;
-                };
-
-                vdd_usb1_vbus: regulator@7 {
-                        compatible = "regulator-fixed";
-                        reg = <7>;
-                        regulator-name = "+5V_USB_HS";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        gpio-open-drain;
-                        vin-supply = <&vdd_5v0_sys>;
-                };
-
-                vdd_usb3_vbus: regulator@8 {
-                        compatible = "regulator-fixed";
-                        reg = <8>;
-                        regulator-name = "+5V_USB_SS";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        gpio-open-drain;
-                        vin-supply = <&vdd_5v0_sys>;
-                };
-
-                vdd_3v3_panel: regulator@9 {
-                        compatible = "regulator-fixed";
-                        reg = <9>;
-                        regulator-name = "+3.3V_PANEL";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_3v3_run>;
-                };
-
-                vdd_3v3_lp0: regulator@10 {
-                        compatible = "regulator-fixed";
-                        reg = <10>;
-                        regulator-name = "+3.3V_LP0";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        /*
-                         * TODO: find a way to wire this up with the USB EHCI
-                         * controllers so that it can be enabled on demand.
-                         */
-                        regulator-always-on;
-                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_3v3_sys>;
-                };
-
-                vdd_hdmi_pll: regulator@11 {
-                        compatible = "regulator-fixed";
-                        reg = <11>;
-                        regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
-                        regulator-min-microvolt = <1050000>;
-                        regulator-max-microvolt = <1050000>;
-                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
-                        vin-supply = <&vdd_1v05_run>;
-                };
-
-                vdd_5v0_hdmi: regulator@12 {
-                        compatible = "regulator-fixed";
-                        reg = <12>;
-                        regulator-name = "+5V_HDMI_CON";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_5v0_sys>;
-                };
-        };
-
-        sound {
-                compatible = "nvidia,tegra-audio-max98090-nyan-big",
-                             "nvidia,tegra-audio-max98090";
-                nvidia,model = "Acer Chromebook 13";
-
-                nvidia,audio-routing =
-                        "Headphones", "HPR",
-                        "Headphones", "HPL",
-                        "Speakers", "SPKR",
-                        "Speakers", "SPKL",
-                        "Mic Jack", "MICBIAS",
-                        "DMICL", "Int Mic",
-                        "DMICR", "Int Mic",
-                        "IN34", "Mic Jack";
-
-                nvidia,i2s-controller = <&tegra_i2s1>;
-                nvidia,audio-codec = <&acodec>;
-
-                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
-                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-                         <&tegra_car TEGRA124_CLK_EXTERN1>;
-                clock-names = "pll_a", "pll_a_out0", "mclk";
-
-                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
-                nvidia,mic-det-gpios =
-                                <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
-        };
 };
-
-#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
new file mode 100644
index 000000000000..9ecd108f56cf
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
@@ -0,0 +1,2049 @@
+/ {
+        clock@0,60006000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+                                clock-names = "emc-parent";
+                        };
+                        /* TODO: Add 528MHz frequency */
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                };
+        };
+
+        emc@0,7001b000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000060
+                                        0x00000000
+                                        0x00000018
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000005
+                                        0x00000005
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000064
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000007
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x800001c5
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000005
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
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+                                        0x00000003
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+                                        0x0000000d
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+                                        0x0000009a
+                                        0x00000000
+                                        0x00000026
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000006
+                                        0x00000006
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
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+                                        0x00000005
+                                        0x00000005
+                                        0x000000a0
+                                        0x00000000
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+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
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+                                        0x00064000
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+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
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+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
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+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000023a
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000001
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000001
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000134
+                                        0x00000000
+                                        0x0000004d
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000008
+                                        0x0000000f
+                                        0x0000000c
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000013f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
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+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
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+                                        0x00064000
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+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000015
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000370
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000003
+                                        0x00000011
+                                        0x00000000
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000202
+                                        0x00000000
+                                        0x00000080
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x0000000f
+                                        0x0000000f
+                                        0x00000013
+                                        0x00000013
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000001
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000213
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
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+                                        0x00064000
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+                                        0x00000000
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+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000022
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000050e
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000004
+                                        0x0000001a
+                                        0x00000000
+                                        0x00000003
+                                        0x00000001
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000304
+                                        0x00000000
+                                        0x000000c1
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000018
+                                        0x0000000f
+                                        0x0000001c
+                                        0x0000001c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000031c
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
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+                                        0x00064000
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+                                        0x00000000
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+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000033
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000713
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x0000088d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000009
+                                        0x00000035
+                                        0x00000000
+                                        0x00000007
+                                        0x00000002
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
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+                                        0x00000002
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+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
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+                                        0x00000003
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000011
+                                        0x00000607
+                                        0x00000000
+                                        0x00000181
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000032
+                                        0x0000000f
+                                        0x00000038
+                                        0x00000038
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000007
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000638
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
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+                                        0x00064000
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+                                        0x00000000
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+                                        0x00000000
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+                                        0x0000c000
+                                        0x00000000
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+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00090000
+                                        0x00090000
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000066
+                                        0x00000000
+                                        0x00000100
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000d2b3
+                                        0x80000d22
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x000008d5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000321>;
+                                nvidia,emc-mrs-wait-cnt = <0x0174000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000000d
+                                        0x0000004c
+                                        0x00000000
+                                        0x00000009
+                                        0x00000003
+                                        0x00000004
+                                        0x00000008
+                                        0x00000002
+                                        0x00000009
+                                        0x00000003
+                                        0x00000003
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000007
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x0000000e
+                                        0x00000010
+                                        0x00000012
+                                        0x000008e4
+                                        0x00000000
+                                        0x00000239
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x0000004a
+                                        0x0000000e
+                                        0x00000051
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000009
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000924
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00060000
+                                        0x00060000
+                                        0x00060000
+                                        0x00060000
+                                        0x00006000
+                                        0x00006000
+                                        0x00006000
+                                        0x00006000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000202
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000096
+                                        0x00000000
+                                        0x00000100
+                                        0x0174000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x800012d7
+                                        0x00000009
+                                >;
+                        };
+
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x00000895>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000521>;
+                                nvidia,emc-mrs-wait-cnt = <0x015b000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000012
+                                        0x00000065
+                                        0x00000000
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000008
+                                        0x00000002
+                                        0x0000000a
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000001
+                                        0x00000008
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000f
+                                        0x00000010
+                                        0x00000012
+                                        0x00000bd1
+                                        0x00000000
+                                        0x000002f4
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x00000063
+                                        0x0000000f
+                                        0x0000006b
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x0000000d
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000c11
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00068000
+                                        0x00068000
+                                        0x00000000
+                                        0x00068000
+                                        0x00068000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00058000
+                                        0x00058000
+                                        0x00058000
+                                        0x00058000
+                                        0x00005800
+                                        0x00005800
+                                        0x00005800
+                                        0x00005800
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000202
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x000000c6
+                                        0x00000000
+                                        0x00000100
+                                        0x015b000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x8000188b
+                                        0x00000009
+                                >;
+                        };
+
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200010>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000b61>;
+                                nvidia,emc-mrs-wait-cnt = <0x0128000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000001c
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000013
+                                        0x00000007
+                                        0x00000007
+                                        0x0000000b
+                                        0x00000003
+                                        0x00000010
+                                        0x00000007
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000b
+                                        0x00070000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000002
+                                        0x00000012
+                                        0x00000016
+                                        0x00000018
+                                        0x00001208
+                                        0x00000000
+                                        0x00000482
+                                        0x00000002
+                                        0x0000000d
+                                        0x00000001
+                                        0x00000000
+                                        0x00000096
+                                        0x00000015
+                                        0x000000a2
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000015
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00001248
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00e00b1
+                                        0x00008000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00040000
+                                        0x00040000
+                                        0x00000000
+                                        0x00040000
+                                        0x00040000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x00000004
+                                        0x00000001
+                                        0x00000005
+                                        0x00000007
+                                        0x00000004
+                                        0x00000006
+                                        0x00000007
+                                        0x00000004
+                                        0x00000004
+                                        0x00000001
+                                        0x00000005
+                                        0x00000007
+                                        0x00000004
+                                        0x00000006
+                                        0x00000007
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000202
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x0128000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000040a0
+                                        0x800024a9
+                                        0x0000000e
+                                >;
+                        };
+
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200018>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000d71>;
+                                nvidia,emc-mrs-wait-cnt = <0x00f8000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000025
+                                        0x000000cc
+                                        0x00000000
+                                        0x0000001a
+                                        0x00000009
+                                        0x00000008
+                                        0x0000000d
+                                        0x00000004
+                                        0x00000013
+                                        0x00000009
+                                        0x00000009
+                                        0x00000003
+                                        0x00000002
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x0000000d
+                                        0x00080000
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x00000014
+                                        0x00000018
+                                        0x0000001a
+                                        0x000017e2
+                                        0x00000000
+                                        0x000005f8
+                                        0x00000003
+                                        0x00000011
+                                        0x00000001
+                                        0x00000000
+                                        0x000000c6
+                                        0x00000018
+                                        0x000000d6
+                                        0x00000200
+                                        0x00000005
+                                        0x00000006
+                                        0x00000005
+                                        0x0000001d
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00001822
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00700b1
+                                        0x00008000
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0002c000
+                                        0x0002c000
+                                        0x00000000
+                                        0x0002c000
+                                        0x0002c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00000005
+                                        0x00000008
+                                        0x0000000a
+                                        0x00000008
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000008
+                                        0x00000008
+                                        0x00000005
+                                        0x00000008
+                                        0x0000000a
+                                        0x00000008
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000202
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x61861820
+                                        0x00492492
+                                        0x00492492
+                                        0x61861800
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x00f8000c
+                                        0x00000000
+                                        0x00000004
+                                        0x00004080
+                                        0x80003012
+                                        0x0000000f
+                                >;
+                        };
+
+                };
+        };
+
+        memory-controller@0,70019000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+
+                                nvidia,emem-configuration = <
+                                        0x40040001
+                                        0x8000000a
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x77e30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+
+                                nvidia,emem-configuration = <
+                                        0x40020001
+                                        0x80000012
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x76230303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+
+                                nvidia,emem-configuration = <
+                                        0xa0000001
+                                        0x80000017
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x74a30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x00000001
+                                        0x8000001e
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x74230403
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x08000001
+                                        0x80000026
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0403
+                                        0x73c30504
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x01000003
+                                        0x80000040
+                                        0x00000001
+                                        0x00000001
+                                        0x00000005
+                                        0x00000002
+                                        0x00000004
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040203
+                                        0x000a0405
+                                        0x73840a06
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x08000004
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000004
+                                        0x00000005
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000b0607
+                                        0x77450e08
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0f000005
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000005
+                                        0x00000007
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000d0709
+                                        0x7586120a
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0f000007
+                                        0x80000040
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000d
+                                        0x00000008
+                                        0x0000000a
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000006
+                                        0x06050202
+                                        0x0010090d
+                                        0x7428180e
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x00000009
+                                        0x80000040
+                                        0x00000003
+                                        0x00000004
+                                        0x0000000e
+                                        0x00000009
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000007
+                                        0x07050202
+                                        0x00130b0e
+                                        0x73a91b0f
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0e00000b
+                                        0x80000040
+                                        0x00000004
+                                        0x00000005
+                                        0x00000013
+                                        0x0000000c
+                                        0x0000000f
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000c
+                                        0x00000002
+                                        0x00000002
+                                        0x00000006
+                                        0x00000008
+                                        0x08060202
+                                        0x00160d13
+                                        0x734c2414
+                                        0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
new file mode 100644
index 000000000000..0d30c514ffad
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
@@ -0,0 +1,1334 @@
+/dts-v1/;
+
+#include "tegra124-nyan.dtsi"
+
+#include "tegra124-nyan-blaze-emc.dtsi"
+
+/ {
+        model = "HP Chromebook 14";
+        compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124";
+
+        panel: panel {
+                compatible = "samsung,ltn140at29-301";
+
+                backlight = <&backlight>;
+                ddc-i2c-bus = <&dpaux>;
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-max98090-nyan-blaze",
+                             "nvidia,tegra-audio-max98090-nyan",
+                             "nvidia,tegra-audio-max98090";
+                nvidia,model = "GoogleNyanBlaze";
+        };
+
+        pinmux@0,70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinmux_default>;
+
+                pinmux_default: common {
+                        clk_32k_out_pa0 {
+                                nvidia,pins = "clk_32k_out_pa0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pb0 {
+                                nvidia,pins = "pb0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pb1 {
+                                nvidia,pins = "pb1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pc7 {
+                                nvidia,pins = "pc7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg0 {
+                                nvidia,pins = "pg0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg1 {
+                                nvidia,pins = "pg1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg2 {
+                                nvidia,pins = "pg2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg3 {
+                                nvidia,pins = "pg3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg4 {
+                                nvidia,pins = "pg4";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg5 {
+                                nvidia,pins = "pg5";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg6 {
+                                nvidia,pins = "pg6";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg7 {
+                                nvidia,pins = "pg7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph1 {
+                                nvidia,pins = "ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph2 {
+                                nvidia,pins = "ph2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph3 {
+                                nvidia,pins = "ph3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph4 {
+                                nvidia,pins = "ph4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph5 {
+                                nvidia,pins = "ph5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph6 {
+                                nvidia,pins = "ph6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph7 {
+                                nvidia,pins = "ph7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi0 {
+                                nvidia,pins = "pi0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi1 {
+                                nvidia,pins = "pi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi2 {
+                                nvidia,pins = "pi2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi3 {
+                                nvidia,pins = "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi4 {
+                                nvidia,pins = "pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi5 {
+                                nvidia,pins = "pi5";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi6 {
+                                nvidia,pins = "pi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi7 {
+                                nvidia,pins = "pi7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj0 {
+                                nvidia,pins = "pj0";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj2 {
+                                nvidia,pins = "pj2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pj7 {
+                                nvidia,pins = "pj7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk0 {
+                                nvidia,pins = "pk0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk1 {
+                                nvidia,pins = "pk1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk2 {
+                                nvidia,pins = "pk2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk3 {
+                                nvidia,pins = "pk3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk4 {
+                                nvidia,pins = "pk4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_out_pk5 {
+                                nvidia,pins = "spdif_out_pk5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk7 {
+                                nvidia,pins = "pk7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_fs_pn0 {
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_sclk_pn3 {
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en1_pn5 {
+                                nvidia,pins = "usb_vbus_en1_pn5";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data7_po0 {
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data0_po1 {
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data1_po2 {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data2_po3 {
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data3_po4 {
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data6_po7 {
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_fs_pp4 {
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_sclk_pp7 {
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col3_pq3 {
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row0_pr0 {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row2_pr2 {
+                                nvidia,pins = "kb_row2_pr2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row3_pr3 {
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row4_pr4 {
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row5_pr5 {
+                                nvidia,pins = "kb_row5_pr5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row7_pr7 {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row8_ps0 {
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row12_ps4 {
+                                nvidia,pins = "kb_row12_ps4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row13_ps5 {
+                                nvidia,pins = "kb_row13_ps5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row14_ps6 {
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row15_ps7 {
+                                nvidia,pins = "kb_row15_ps7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row16_pt0 {
+                                nvidia,pins = "kb_row16_pt0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row17_pt1 {
+                                nvidia,pins = "kb_row17_pt1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_sda_pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu0 {
+                                nvidia,pins = "pu0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu2 {
+                                nvidia,pins = "pu2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu5 {
+                                nvidia,pins = "pu5";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv1 {
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cd_n_pv2 {
+                                nvidia,pins = "sdmmc3_cd_n_pv2";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_wp_n_pv3 {
+                                nvidia,pins = "sdmmc1_wp_n_pv3";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_w2_aud_pw2 {
+                                nvidia,pins = "gpio_w2_aud_pw2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_w3_aud_pw3 {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk2_out_pw5 {
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x1_aud_px1 {
+                                nvidia,pins = "gpio_x1_aud_px1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dvfs_clk_px2 {
+                                nvidia,pins = "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x3_aud_px3 {
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x4_aud_px4 {
+                                nvidia,pins = "gpio_x4_aud_px4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x5_aud_px5 {
+                                nvidia,pins = "gpio_x5_aud_px5";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x6_aud_px6 {
+                                nvidia,pins = "gpio_x6_aud_px6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x7_aud_px7 {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_nxt_py2 {
+                                nvidia,pins = "ulpi_nxt_py2";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_dat3_py4 {
+                                nvidia,pins = "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat2_py5 {
+                                nvidia,pins = "sdmmc1_dat2_py5";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat1_py6 {
+                                nvidia,pins = "sdmmc1_dat1_py6";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat0_py7 {
+                                nvidia,pins = "sdmmc1_dat0_py7";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_sda_pz7 {
+                                nvidia,pins = "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat1_paa1 {
+                                nvidia,pins = "sdmmc4_dat1_paa1";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "vgp6";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3";
+                                nvidia,function = "vgp3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb7 {
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc1 {
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc2 {
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_rst_n_pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 {
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_req_pee2 {
+                                nvidia,pins = "dap_mclk1_req_pee2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_lb_out_pee4 {
+                                nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_clk_lb_in_pee5 {
+                                nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dp_hpd_pff0 {
+                                nvidia,pins = "dp_hpd_pff0";
+                                nvidia,function = "dp";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en2_pff1 {
+                                nvidia,pins = "usb_vbus_en2_pff1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pff2 {
+                                nvidia,pins = "pff2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
new file mode 100644
index 000000000000..a9aec23e06f2
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -0,0 +1,695 @@
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+
+/ {
+        aliases {
+                rtc0 = "/i2c@0,7000d000/pmic@40";
+                rtc1 = "/rtc@0,7000e000";
+                serial0 = &uarta;
+        };
+
+        memory {
+                reg = <0x0 0x80000000 0x0 0x80000000>;
+        };
+
+        host1x@0,50000000 {
+                hdmi@0,54280000 {
+                        status = "okay";
+
+                        vdd-supply = <&vdd_3v3_hdmi>;
+                        pll-supply = <&vdd_hdmi_pll>;
+                        hdmi-supply = <&vdd_5v0_hdmi>;
+
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
+
+                sor@0,54540000 {
+                        status = "okay";
+
+                        nvidia,dpaux = <&dpaux>;
+                        nvidia,panel = <&panel>;
+                };
+
+                dpaux@0,545c0000 {
+                        vdd-supply = <&vdd_3v3_panel>;
+                        status = "okay";
+                };
+        };
+
+        serial@0,70006000 {
+                /* Debug connector on the bottom of the board near SD card. */
+                status = "okay";
+        };
+
+        pwm@0,7000a000 {
+                status = "okay";
+        };
+
+        i2c@0,7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                acodec: audio-codec@10 {
+                        compatible = "maxim,max98090";
+                        reg = <0x10>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+                };
+
+                temperature-sensor@4c {
+                        compatible = "ti,tmp451";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+
+                        #thermal-sensor-cells = <1>;
+                };
+        };
+
+        i2c@0,7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                trackpad@15 {
+                        compatible = "elan,ekth3000";
+                        reg = <0x15>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
+                        wakeup-source;
+                };
+        };
+
+        i2c@0,7000c500 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                tpm@20 {
+                        compatible = "infineon,slb9645tt";
+                        reg = <0x20>;
+                };
+        };
+
+        hdmi_ddc: i2c@0,7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@0,7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                pmic: pmic@40 {
+                        compatible = "ams,as3722";
+                        reg = <0x40>;
+                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+                        ams,system-power-controller;
+
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&as3722_default>;
+
+                        as3722_default: pinmux {
+                                gpio0 {
+                                        pins = "gpio0";
+                                        function = "gpio";
+                                        bias-pull-down;
+                                };
+
+                                gpio1 {
+                                        pins = "gpio1";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+
+                                gpio2_4_7 {
+                                        pins = "gpio2", "gpio4", "gpio7";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+
+                                gpio3_6 {
+                                        pins = "gpio3", "gpio6";
+                                        bias-high-impedance;
+                                };
+
+                                gpio5 {
+                                        pins = "gpio5";
+                                        function = "clk32k-out";
+                                        bias-pull-down;
+                                };
+                        };
+
+                        regulators {
+                                vsup-sd2-supply = <&vdd_5v0_sys>;
+                                vsup-sd3-supply = <&vdd_5v0_sys>;
+                                vsup-sd4-supply = <&vdd_5v0_sys>;
+                                vsup-sd5-supply = <&vdd_5v0_sys>;
+                                vin-ldo0-supply = <&vdd_1v35_lp0>;
+                                vin-ldo1-6-supply = <&vdd_3v3_run>;
+                                vin-ldo2-5-7-supply = <&vddio_1v8>;
+                                vin-ldo3-4-supply = <&vdd_3v3_sys>;
+                                vin-ldo9-10-supply = <&vdd_5v0_sys>;
+                                vin-ldo11-supply = <&vdd_3v3_run>;
+
+                                sd0 {
+                                        regulator-name = "+VDD_CPU_AP";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <2>;
+                                };
+
+                                sd1 {
+                                        regulator-name = "+VDD_CORE";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <2500000>;
+                                        regulator-max-microamp = <4000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <1>;
+                                };
+
+                                vdd_1v35_lp0: sd2 {
+                                        regulator-name = "+1.35V_LP0(sd2)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                sd3 {
+                                        regulator-name = "+1.35V_LP0(sd3)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                vdd_1v05_run: sd4 {
+                                        regulator-name = "+1.05V_RUN";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                vddio_1v8: sd5 {
+                                        regulator-name = "+1.8V_VDDIO";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                sd6 {
+                                        regulator-name = "+VDD_GPU_AP";
+                                        regulator-min-microvolt = <650000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo0 {
+                                        regulator-name = "+1.05V_RUN_AVDD";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,ext-control = <1>;
+                                };
+
+                                ldo1 {
+                                        regulator-name = "+1.8V_RUN_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                ldo2 {
+                                        regulator-name = "+1.2V_GEN_AVDD";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo3 {
+                                        regulator-name = "+1.00V_LP0_VDD_RTC";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,enable-tracking;
+                                };
+
+                                vdd_run_cam: ldo4 {
+                                        regulator-name = "+3.3V_RUN_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo5 {
+                                        regulator-name = "+1.2V_RUN_CAM_FRONT";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                vddio_sdmmc3: ldo6 {
+                                        regulator-name = "+VDDIO_SDMMC3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo7 {
+                                        regulator-name = "+1.05V_RUN_CAM_REAR";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                ldo9 {
+                                        regulator-name = "+2.8V_RUN_TOUCH";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo10 {
+                                        regulator-name = "+2.8V_RUN_CAM_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo11 {
+                                        regulator-name = "+1.8V_RUN_VPP_FUSE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                        };
+                };
+        };
+
+        spi@0,7000d400 {
+                status = "okay";
+
+                cros_ec: cros-ec@0 {
+                        compatible = "google,cros-ec-spi";
+                        spi-max-frequency = <3000000>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+                        reg = <0>;
+
+                        google,cros-ec-spi-msg-delay = <2000>;
+
+                        i2c-tunnel {
+                                compatible = "google,cros-ec-i2c-tunnel";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                google,remote-bus = <0>;
+
+                                charger: bq24735@9 {
+                                        compatible = "ti,bq24735";
+                                        reg = <0x9>;
+                                        interrupt-parent = <&gpio>;
+                                        interrupts = <TEGRA_GPIO(J, 0)
+                                                        GPIO_ACTIVE_HIGH>;
+                                        ti,ac-detect-gpios = <&gpio
+                                                        TEGRA_GPIO(J, 0)
+                                                        GPIO_ACTIVE_HIGH>;
+                                };
+
+                                battery: sbs-battery@b {
+                                        compatible = "sbs,sbs-battery";
+                                        reg = <0xb>;
+                                        sbs,i2c-retry-count = <2>;
+                                        sbs,poll-retry-count = <10>;
+                                        power-supplies = <&charger>;
+                                };
+                        };
+                };
+        };
+
+        spi@0,7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+
+                flash@0 {
+                        compatible = "winbond,w25q32dw";
+                        spi-max-frequency = <25000000>;
+                        reg = <0>;
+                };
+        };
+
+        pmc@0,7000e400 {
+                nvidia,invert-interrupt;
+                nvidia,suspend-mode = <0>;
+                nvidia,cpu-pwr-good-time = <500>;
+                nvidia,cpu-pwr-off-time = <300>;
+                nvidia,core-pwr-good-time = <641 3845>;
+                nvidia,core-pwr-off-time = <61036>;
+                nvidia,core-power-req-active-high;
+                nvidia,sys-clock-req-active-high;
+        };
+
+        hda@0,70030000 {
+                status = "okay";
+        };
+
+        sdhci0_pwrseq: sdhci0_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+
+                reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
+        };
+
+        sdhci@0,700b0000 { /* WiFi/BT on this bus */
+                status = "okay";
+                bus-width = <4>;
+                no-1-8-v;
+                non-removable;
+                mmc-pwrseq = <&sdhci0_pwrseq>;
+                vmmc-supply = <&vdd_3v3_lp0>;
+                vqmmc-supply = <&vddio_1v8>;
+                keep-power-in-suspend;
+        };
+
+        sdhci@0,700b0400 { /* SD Card on this bus */
+                status = "okay";
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+                bus-width = <4>;
+                no-1-8-v;
+                vqmmc-supply = <&vddio_sdmmc3>;
+        };
+
+        sdhci@0,700b0600 { /* eMMC on this bus */
+                status = "okay";
+                bus-width = <8>;
+                no-1-8-v;
+                non-removable;
+        };
+
+        ahub@0,70300000 {
+                i2s@0,70301100 {
+                        status = "okay";
+                };
+        };
+
+        usb@0,7d000000 { /* Rear external USB port. */
+                status = "okay";
+        };
+
+        usb-phy@0,7d000000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb1_vbus>;
+        };
+
+        usb@0,7d004000 { /* Internal webcam. */
+                status = "okay";
+        };
+
+        usb-phy@0,7d004000 {
+                status = "okay";
+                vbus-supply = <&vdd_run_cam>;
+        };
+
+        usb@0,7d008000 { /* Left external USB port. */
+                status = "okay";
+        };
+
+        usb-phy@0,7d008000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb3_vbus>;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_led>;
+                pwms = <&pwm 1 1000000>;
+
+                default-brightness-level = <224>;
+                brightness-levels =
+                        <  0   1   2   3   4   5   6   7
+                           8   9  10  11  12  13  14  15
+                          16  17  18  19  20  21  22  23
+                          24  25  26  27  28  29  30  31
+                          32  33  34  35  36  37  38  39
+                          40  41  42  43  44  45  46  47
+                          48  49  50  51  52  53  54  55
+                          56  57  58  59  60  61  62  63
+                          64  65  66  67  68  69  70  71
+                          72  73  74  75  76  77  78  79
+                          80  81  82  83  84  85  86  87
+                          88  89  90  91  92  93  94  95
+                          96  97  98  99 100 101 102 103
+                         104 105 106 107 108 109 110 111
+                         112 113 114 115 116 117 118 119
+                         120 121 122 123 124 125 126 127
+                         128 129 130 131 132 133 134 135
+                         136 137 138 139 140 141 142 143
+                         144 145 146 147 148 149 150 151
+                         152 153 154 155 156 157 158 159
+                         160 161 162 163 164 165 166 167
+                         168 169 170 171 172 173 174 175
+                         176 177 178 179 180 181 182 183
+                         184 185 186 187 188 189 190 191
+                         192 193 194 195 196 197 198 199
+                         200 201 202 203 204 205 206 207
+                         208 209 210 211 212 213 214 215
+                         216 217 218 219 220 221 222 223
+                         224 225 226 227 228 229 230 231
+                         232 233 234 235 236 237 238 239
+                         240 241 242 243 244 245 246 247
+                         248 249 250 251 252 253 254 255
+                         256>;
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                lid {
+                        label = "Lid";
+                        gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+                        linux,input-type = <5>;
+                        linux,code = <KEY_RESERVED>;
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        debounce-interval = <30>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_mux: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "+VDD_MUX";
+                        regulator-min-microvolt = <12000000>;
+                        regulator-max-microvolt = <12000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                vdd_5v0_sys: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "+5V_SYS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
+                };
+
+                vdd_3v3_sys: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "+3.3V_SYS";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
+                };
+
+                vdd_3v3_run: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "+3.3V_RUN";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_sys>;
+                };
+
+                vdd_3v3_hdmi: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        vin-supply = <&vdd_3v3_run>;
+                };
+
+                vdd_led: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "+VDD_LED";
+                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_mux>;
+                };
+
+                vdd_5v0_ts: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "+5V_VDD_TS_SW";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+
+                vdd_usb1_vbus: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "+5V_USB_HS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+
+                vdd_usb3_vbus: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "+5V_USB_SS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+
+                vdd_3v3_panel: regulator@9 {
+                        compatible = "regulator-fixed";
+                        reg = <9>;
+                        regulator-name = "+3.3V_PANEL";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_run>;
+                };
+
+                vdd_3v3_lp0: regulator@10 {
+                        compatible = "regulator-fixed";
+                        reg = <10>;
+                        regulator-name = "+3.3V_LP0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        /*
+                         * TODO: find a way to wire this up with the USB EHCI
+                         * controllers so that it can be enabled on demand.
+                         */
+                        regulator-always-on;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_sys>;
+                };
+
+                vdd_hdmi_pll: regulator@11 {
+                        compatible = "regulator-fixed";
+                        reg = <11>;
+                        regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+                        regulator-min-microvolt = <1050000>;
+                        regulator-max-microvolt = <1050000>;
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+                        vin-supply = <&vdd_1v05_run>;
+                };
+
+                vdd_5v0_hdmi: regulator@12 {
+                        compatible = "regulator-fixed";
+                        reg = <12>;
+                        regulator-name = "+5V_HDMI_CON";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+        };
+
+        sound {
+                nvidia,audio-routing =
+                        "Headphones", "HPR",
+                        "Headphones", "HPL",
+                        "Speakers", "SPKR",
+                        "Speakers", "SPKL",
+                        "Mic Jack", "MICBIAS",
+                        "DMICL", "Int Mic",
+                        "DMICR", "Int Mic",
+                        "IN34", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&acodec>;
+
+                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA124_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
+                nvidia,mic-det-gpios =
+                                <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
+        };
+
+        gpio-restart {
+                compatible = "gpio-restart";
+                gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                priority = <200>;
+        };
+};
+
+#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index db85695aa7aa..cf01c818b8ea 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -220,6 +220,7 @@
                 reg = <0x0 0x60006000 0x0 0x1000>;
                 #clock-cells = <1>;
                 #reset-cells = <1>;
+                nvidia,external-memory-controller = <&emc>;
         };
 
         flow-controller@0,60007000 {
@@ -227,6 +228,17 @@
                 reg = <0x0 0x60007000 0x0 0x1000>;
         };
 
+        actmon@0,6000c800 {
+                compatible = "nvidia,tegra124-actmon";
+                reg = <0x0 0x6000c800 0x0 0x400>;
+                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
+                         <&tegra_car TEGRA124_CLK_EMC>;
+                clock-names = "actmon", "emc";
+                resets = <&tegra_car 119>;
+                reset-names = "actmon";
+        };
+
         gpio: gpio@0,6000d000 {
                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
                 reg = <0x0 0x6000d000 0x0 0x1000>;
@@ -582,6 +594,13 @@
                 #iommu-cells = <1>;
         };
 
+        emc: emc@0,7001b000 {
+                compatible = "nvidia,tegra124-emc";
+                reg = <0x0 0x7001b000 0x0 0x1000>;
+
+                nvidia,memory-controller = <&mc>;
+        };
+
         sata@0,70020000 {
                 compatible = "nvidia,tegra124-ahci";
 
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 6b157eeabcc5..3dede3934446 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -62,71 +62,1652 @@
                 pinctrl-0 = <&state_default>;
 
                 state_default: pinmux {
-                        sdmmc1_clk_pz0 {
-                                nvidia,pins = "sdmmc1_clk_pz0";
-                                nvidia,function = "sdmmc1";
+                        clk_32k_out_pa0 {
+                                nvidia,pins = "clk_32k_out_pa0";
+                                nvidia,function = "blink";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        sdmmc1_cmd_pz1 {
-                                nvidia,pins =   "sdmmc1_cmd_pz1",
-                                                "sdmmc1_dat0_py7",
-                                                "sdmmc1_dat1_py6",
-                                                "sdmmc1_dat2_py5",
-                                                "sdmmc1_dat3_py4";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc3_clk_pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc3_cmd_pa7 {
-                                nvidia,pins =   "sdmmc3_cmd_pa7",
-                                                "sdmmc3_dat0_pb7",
-                                                "sdmmc3_dat1_pb6",
-                                                "sdmmc3_dat2_pb5",
-                                                "sdmmc3_dat3_pb4";
+                                nvidia,pins = "sdmmc3_cmd_pa7";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_clk_pcc4 {
-                                nvidia,pins =   "sdmmc4_clk_pcc4",
-                                                "sdmmc4_rst_n_pcc3";
+                        gmi_a17_pb0 {
+                                nvidia,pins = "gmi_a17_pb0";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_a18_pb1 {
+                                nvidia,pins = "gmi_a18_pb1";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_pwr0_pb2 {
+                                nvidia,pins = "lcd_pwr0_pb2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_pclk_pb3 {
+                                nvidia,pins = "lcd_pclk_pb3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd_pwr1_pc1 {
+                                nvidia,pins = "lcd_pwr1_pc1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_pwr2_pc6 {
+                                nvidia,pins = "lcd_pwr2_pc6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_wp_n_pc7 {
+                                nvidia,pins = "gmi_wp_n_pc7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat5_pd0 {
+                                nvidia,pins = "sdmmc3_dat5_pd0";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat4_pd1 {
+                                nvidia,pins = "sdmmc3_dat4_pd1";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_dc1_pd2 {
+                                nvidia,pins = "lcd_dc1_pd2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat6_pd3 {
+                                nvidia,pins = "sdmmc3_dat6_pd3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat7_pd4 {
+                                nvidia,pins = "sdmmc3_dat7_pd4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d1_pd5 {
+                                nvidia,pins = "vi_d1_pd5";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_vsync_pd6 {
+                                nvidia,pins = "vi_vsync_pd6";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_hsync_pd7 {
+                                nvidia,pins = "vi_hsync_pd7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d0_pe0 {
+                                nvidia,pins = "lcd_d0_pe0";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d1_pe1 {
+                                nvidia,pins = "lcd_d1_pe1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d2_pe2 {
+                                nvidia,pins = "lcd_d2_pe2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d3_pe3 {
+                                nvidia,pins = "lcd_d3_pe3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d4_pe4 {
+                                nvidia,pins = "lcd_d4_pe4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d5_pe5 {
+                                nvidia,pins = "lcd_d5_pe5";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d6_pe6 {
+                                nvidia,pins = "lcd_d6_pe6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d7_pe7 {
+                                nvidia,pins = "lcd_d7_pe7";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d8_pf0 {
+                                nvidia,pins = "lcd_d8_pf0";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d9_pf1 {
+                                nvidia,pins = "lcd_d9_pf1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d10_pf2 {
+                                nvidia,pins = "lcd_d10_pf2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d11_pf3 {
+                                nvidia,pins = "lcd_d11_pf3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d12_pf4 {
+                                nvidia,pins = "lcd_d12_pf4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d13_pf5 {
+                                nvidia,pins = "lcd_d13_pf5";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d14_pf6 {
+                                nvidia,pins = "lcd_d14_pf6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d15_pf7 {
+                                nvidia,pins = "lcd_d15_pf7";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad0_pg0 {
+                                nvidia,pins = "gmi_ad0_pg0";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad1_pg1 {
+                                nvidia,pins = "gmi_ad1_pg1";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad2_pg2 {
+                                nvidia,pins = "gmi_ad2_pg2";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad3_pg3 {
+                                nvidia,pins = "gmi_ad3_pg3";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad4_pg4 {
+                                nvidia,pins = "gmi_ad4_pg4";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad5_pg5 {
+                                nvidia,pins = "gmi_ad5_pg5";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad6_pg6 {
+                                nvidia,pins = "gmi_ad6_pg6";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad7_pg7 {
+                                nvidia,pins = "gmi_ad7_pg7";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad8_ph0 {
+                                nvidia,pins = "gmi_ad8_ph0";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad9_ph1 {
+                                nvidia,pins = "gmi_ad9_ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad10_ph2 {
+                                nvidia,pins = "gmi_ad10_ph2";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad11_ph3 {
+                                nvidia,pins = "gmi_ad11_ph3";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad12_ph4 {
+                                nvidia,pins = "gmi_ad12_ph4";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad13_ph5 {
+                                nvidia,pins = "gmi_ad13_ph5";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad14_ph6 {
+                                nvidia,pins = "gmi_ad14_ph6";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_wr_n_pi0 {
+                                nvidia,pins = "gmi_wr_n_pi0";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_oe_n_pi1 {
+                                nvidia,pins = "gmi_oe_n_pi1";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_dqs_pi2 {
+                                nvidia,pins = "gmi_dqs_pi2";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_iordy_pi5 {
+                                nvidia,pins = "gmi_iordy_pi5";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_cs7_n_pi6 {
+                                nvidia,pins = "gmi_cs7_n_pi6";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_wait_pi7 {
+                                nvidia,pins = "gmi_wait_pi7";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd_de_pj1 {
+                                nvidia,pins = "lcd_de_pj1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_hsync_pj3 {
+                                nvidia,pins = "lcd_hsync_pj3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_vsync_pj4 {
+                                nvidia,pins = "lcd_vsync_pj4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_a16_pj7 {
+                                nvidia,pins = "gmi_a16_pj7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_adv_n_pk0 {
+                                nvidia,pins = "gmi_adv_n_pk0";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_clk_pk1 {
+                                nvidia,pins = "gmi_clk_pk1";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_cs2_n_pk3 {
+                                nvidia,pins = "gmi_cs2_n_pk3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_cs3_n_pk4 {
+                                nvidia,pins = "gmi_cs3_n_pk4";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_out_pk5 {
+                                nvidia,pins = "spdif_out_pk5";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_a19_pk7 {
+                                nvidia,pins = "gmi_a19_pk7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d2_pl0 {
+                                nvidia,pins = "vi_d2_pl0";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d3_pl1 {
+                                nvidia,pins = "vi_d3_pl1";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d4_pl2 {
+                                nvidia,pins = "vi_d4_pl2";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        vi_d5_pl3 {
+                                nvidia,pins = "vi_d5_pl3";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d6_pl4 {
+                                nvidia,pins = "vi_d6_pl4";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        vi_d7_pl5 {
+                                nvidia,pins = "vi_d7_pl5";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d8_pl6 {
+                                nvidia,pins = "vi_d8_pl6";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d9_pl7 {
+                                nvidia,pins = "vi_d9_pl7";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d16_pm0 {
+                                nvidia,pins = "lcd_d16_pm0";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d17_pm1 {
+                                nvidia,pins = "lcd_d17_pm1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d18_pm2 {
+                                nvidia,pins = "lcd_d18_pm2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d19_pm3 {
+                                nvidia,pins = "lcd_d19_pm3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d20_pm4 {
+                                nvidia,pins = "lcd_d20_pm4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d21_pm5 {
+                                nvidia,pins = "lcd_d21_pm5";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d22_pm6 {
+                                nvidia,pins = "lcd_d22_pm6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d23_pm7 {
+                                nvidia,pins = "lcd_d23_pm7";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_fs_pn0 {
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_sclk_pn3 {
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_cs0_n_pn4 {
+                                nvidia,pins = "lcd_cs0_n_pn4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_sdout_pn5 {
+                                nvidia,pins = "lcd_sdout_pn5";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_dc0_pn6 {
+                                nvidia,pins = "lcd_dc0_pn6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data7_po0 {
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data0_po1 {
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data1_po2 {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data2_po3 {
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data3_po4 {
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data6_po7 {
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_fs_pp4 {
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_sclk_pp7 {
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col3_pq3 {
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row0_pr0 {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row2_pr2 {
+                                nvidia,pins = "kb_row2_pr2";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row3_pr3 {
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row4_pr4 {
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row5_pr5 {
+                                nvidia,pins = "kb_row5_pr5";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row7_pr7 {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row8_ps0 {
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row12_ps4 {
+                                nvidia,pins = "kb_row12_ps4";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row13_ps5 {
+                                nvidia,pins = "kb_row13_ps5";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row14_ps6 {
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row15_ps7 {
+                                nvidia,pins = "kb_row15_ps7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_pclk_pt0 {
+                                nvidia,pins = "vi_pclk_pt0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_mclk_pt1 {
+                                nvidia,pins = "vi_mclk_pt1";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d10_pt2 {
+                                nvidia,pins = "vi_d10_pt2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d11_pt3 {
+                                nvidia,pins = "vi_d11_pt3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d0_pt4 {
+                                nvidia,pins = "vi_d0_pt4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_sda_pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
                                 nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu0 {
+                                nvidia,pins = "pu0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu2 {
+                                nvidia,pins = "pu2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu5 {
+                                nvidia,pins = "pu5";
+                                nvidia,function = "pwm2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck_pu7 {
+                                nvidia,pins = "jtag_rtck_pu7";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv2 {
+                                nvidia,pins = "pv2";
+                                nvidia,function = "owr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pv3 {
+                                nvidia,pins = "pv3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        crt_hsync_pv6 {
+                                nvidia,pins = "crt_hsync_pv6";
+                                nvidia,function = "crt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        crt_vsync_pv7 {
+                                nvidia,pins = "crt_vsync_pv7";
+                                nvidia,function = "crt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd_cs1_n_pw0 {
+                                nvidia,pins = "lcd_cs1_n_pw0";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_m1_pw1 {
+                                nvidia,pins = "lcd_m1_pw1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi2_cs1_n_pw2 {
+                                nvidia,pins = "spi2_cs1_n_pw2";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk1_out_pw4 {
+                                nvidia,pins = "clk1_out_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_out_pw5 {
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "extperiph2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi2_sck_px2 {
+                                nvidia,pins = "spi2_sck_px2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi1_mosi_px4 {
+                                nvidia,pins = "spi1_mosi_px4";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi1_sck_px5 {
+                                nvidia,pins = "spi1_sck_px5";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi1_cs0_n_px6 {
+                                nvidia,pins = "spi1_cs0_n_px6";
+                                nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi1_miso_px7 {
+                                nvidia,pins = "spi1_miso_px7";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_nxt_py2 {
+                                nvidia,pins = "ulpi_nxt_py2";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_dat3_py4 {
+                                nvidia,pins = "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat2_py5 {
+                                nvidia,pins = "sdmmc1_dat2_py5";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat1_py6 {
+                                nvidia,pins = "sdmmc1_dat1_py6";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat0_py7 {
+                                nvidia,pins = "sdmmc1_dat0_py7";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_sdin_pz2 {
+                                nvidia,pins = "lcd_sdin_pz2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_wr_n_pz3 {
+                                nvidia,pins = "lcd_wr_n_pz3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_sck_pz4 {
+                                nvidia,pins = "lcd_sck_pz4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sys_clk_req_pz5 {
+                                nvidia,pins = "sys_clk_req_pz5";
+                                nvidia,function = "sysclk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_sda_pz7 {
+                                nvidia,pins = "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc4_dat0_paa0 {
-                                nvidia,pins =   "sdmmc4_dat0_paa0",
-                                                "sdmmc4_dat1_paa1",
-                                                "sdmmc4_dat2_paa2",
-                                                "sdmmc4_dat3_paa3",
-                                                "sdmmc4_dat4_paa4",
-                                                "sdmmc4_dat5_paa5",
-                                                "sdmmc4_dat6_paa6",
-                                                "sdmmc4_dat7_paa7";
+                                nvidia,pins = "sdmmc4_dat0_paa0";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap2_fs_pa2 {
-                                nvidia,pins =   "dap2_fs_pa2",
-                                                "dap2_sclk_pa3",
-                                                "dap2_din_pa4",
-                                                "dap2_dout_pa5";
-                                nvidia,function = "i2s1";
+                        sdmmc4_dat1_paa1 {
+                                nvidia,pins = "sdmmc4_dat1_paa1";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3";
+                                nvidia,function = "vgp3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "vgp5";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "vgp6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb7 {
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "i2s4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pcc1 {
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pcc2 {
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "i2s4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_rst_n_pcc3 {
+                                nvidia,pins = "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "dap";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l2_rst_n_pcc6 {
+                                nvidia,pins = "pex_l2_rst_n_pcc6";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l2_clkreq_n_pcc7 {
+                                nvidia,pins = "pex_l2_clkreq_n_pcc7";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l0_prsnt_n_pdd0 {
+                                nvidia,pins = "pex_l0_prsnt_n_pdd0";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l0_rst_n_pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pex_l1_prsnt_n_pdd4 {
-                                nvidia,pins =   "pex_l1_prsnt_n_pdd4",
-                                                "pex_l1_clkreq_n_pdd6";
+                                nvidia,pins = "pex_l1_prsnt_n_pdd4";
+                                nvidia,function = "pcie";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l2_prsnt_n_pdd7 {
+                                nvidia,pins = "pex_l2_prsnt_n_pdd7";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 {
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "dev3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk1_req_pee2 {
+                                nvidia,pins = "clk1_req_pee2";
+                                nvidia,function = "dap";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "owr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdio3 {
                                 nvidia,pins = "drive_sdio3";
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index cd30f6f5f2ff..dd8f5312b2c0 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -200,17 +200,6 @@ config DA850_UI_SD_VIDEO_PORT
 
 endchoice
 
-config DA850_WL12XX
-        bool "AM18x wl1271 daughter board"
-        depends on MACH_DAVINCI_DA850_EVM
-        help
-          The wl1271 daughter card for AM18x EVMs is a combo wireless
-          connectivity add-on card, based on the LS Research TiWi module with
-          Texas Instruments' wl1271 solution.
-          Say Y if you want to use a wl1271 expansion card connected to the
-          AM18x EVM.
-
-
 config MACH_MITYOMAPL138
         bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
         depends on ARCH_DAVINCI_DA850
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6b5a97da9fe3..1ed545cc2b83 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -38,7 +38,6 @@
 #include <linux/regulator/fixed.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#include <linux/wl12xx.h>
 
 #include <mach/common.h>
 #include <mach/cp_intc.h>
@@ -60,9 +59,6 @@
 #define DA850_MMCSD_CD_PIN              GPIO_TO_PIN(4, 0)
 #define DA850_MMCSD_WP_PIN              GPIO_TO_PIN(4, 1)
 
-#define DA850_WLAN_EN                   GPIO_TO_PIN(6, 9)
-#define DA850_WLAN_IRQ                  GPIO_TO_PIN(6, 10)
-
 #define DA850_MII_MDIO_CLKEN_PIN        GPIO_TO_PIN(2, 6)
 
 static struct mtd_partition da850evm_spiflash_part[] = {
@@ -1343,109 +1339,6 @@ static __init void da850_vpif_init(void)
 static __init void da850_vpif_init(void) {}
 #endif
 
-#ifdef CONFIG_DA850_WL12XX
-
-static void wl12xx_set_power(int index, bool power_on)
-{
-        static bool power_state;
-
-        pr_debug("Powering %s wl12xx", power_on ? "on" : "off");
-
-        if (power_on == power_state)
-                return;
-        power_state = power_on;
-
-        if (power_on) {
-                /* Power up sequence required for wl127x devices */
-                gpio_set_value(DA850_WLAN_EN, 1);
-                usleep_range(15000, 15000);
-                gpio_set_value(DA850_WLAN_EN, 0);
-                usleep_range(1000, 1000);
-                gpio_set_value(DA850_WLAN_EN, 1);
-                msleep(70);
-        } else {
-                gpio_set_value(DA850_WLAN_EN, 0);
-        }
-}
-
-static struct davinci_mmc_config da850_wl12xx_mmc_config = {
-        .set_power      = wl12xx_set_power,
-        .wires          = 4,
-        .max_freq       = 25000000,
-        .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE |
-                          MMC_CAP_POWER_OFF_CARD,
-};
-
-static const short da850_wl12xx_pins[] __initconst = {
-        DA850_MMCSD1_DAT_0, DA850_MMCSD1_DAT_1, DA850_MMCSD1_DAT_2,
-        DA850_MMCSD1_DAT_3, DA850_MMCSD1_CLK, DA850_MMCSD1_CMD,
-        DA850_GPIO6_9, DA850_GPIO6_10,
-        -1
-};
-
-static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = {
-        .irq                    = -1,
-        .board_ref_clock        = WL12XX_REFCLOCK_38,
-        .platform_quirks        = WL12XX_PLATFORM_QUIRK_EDGE_IRQ,
-};
-
-static __init int da850_wl12xx_init(void)
-{
-        int ret;
-
-        ret = davinci_cfg_reg_list(da850_wl12xx_pins);
-        if (ret) {
-                pr_err("wl12xx/mmc mux setup failed: %d\n", ret);
-                goto exit;
-        }
-
-        ret = da850_register_mmcsd1(&da850_wl12xx_mmc_config);
-        if (ret) {
-                pr_err("wl12xx/mmc registration failed: %d\n", ret);
-                goto exit;
-        }
-
-        ret = gpio_request_one(DA850_WLAN_EN, GPIOF_OUT_INIT_LOW, "wl12xx_en");
-        if (ret) {
-                pr_err("Could not request wl12xx enable gpio: %d\n", ret);
-                goto exit;
-        }
-
-        ret = gpio_request_one(DA850_WLAN_IRQ, GPIOF_IN, "wl12xx_irq");
-        if (ret) {
-                pr_err("Could not request wl12xx irq gpio: %d\n", ret);
-                goto free_wlan_en;
-        }
-
-        da850_wl12xx_wlan_data.irq = gpio_to_irq(DA850_WLAN_IRQ);
-
-        ret = wl12xx_set_platform_data(&da850_wl12xx_wlan_data);
-        if (ret) {
-                pr_err("Could not set wl12xx data: %d\n", ret);
-                goto free_wlan_irq;
-        }
-
-        return 0;
-
-free_wlan_irq:
-        gpio_free(DA850_WLAN_IRQ);
-
-free_wlan_en:
-        gpio_free(DA850_WLAN_EN);
-
-exit:
-        return ret;
-}
-
-#else /* CONFIG_DA850_WL12XX */
-
-static __init int da850_wl12xx_init(void)
-{
-        return 0;
-}
-
-#endif /* CONFIG_DA850_WL12XX */
-
 #define DA850EVM_SATA_REFCLKPN_RATE     (100 * 1000 * 1000)
 
 static __init void da850_evm_init(void)
@@ -1502,11 +1395,6 @@ static __init void da850_evm_init(void)
                 if (ret)
                         pr_warn("%s: MMCSD0 registration failed: %d\n",
                                 __func__, ret);
-
-                ret = da850_wl12xx_init();
-                if (ret)
-                        pr_warn("%s: WL12xx initialization failed: %d\n",
-                                __func__, ret);
         }
 
         davinci_serial_init(da8xx_serial_device);
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index e642b079e9f3..af11511dda50 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/ti_wilink_st.h>
-#include <linux/wl12xx.h>
 
 #include <linux/platform_data/pinctrl-single.h>
 #include <linux/platform_data/iommu-omap.h>
@@ -35,34 +34,6 @@ struct pdata_init {
 struct of_dev_auxdata omap_auxdata_lookup[];
 static struct twl4030_gpio_platform_data twl_gpio_auxdata;
 
-#if IS_ENABLED(CONFIG_WL12XX)
-
-static struct wl12xx_platform_data wl12xx __initdata;
-
-static void __init __used legacy_init_wl12xx(unsigned ref_clock,
-                                             unsigned tcxo_clock,
-                                             int gpio)
-{
-        int res;
-
-        wl12xx.board_ref_clock = ref_clock;
-        wl12xx.board_tcxo_clock = tcxo_clock;
-        wl12xx.irq = gpio_to_irq(gpio);
-
-        res = wl12xx_set_platform_data(&wl12xx);
-        if (res) {
-                pr_err("error setting wl12xx data: %d\n", res);
-                return;
-        }
-}
-#else
-static inline void legacy_init_wl12xx(unsigned ref_clock,
-                                      unsigned tcxo_clock,
-                                      int gpio)
-{
-}
-#endif
-
 #ifdef CONFIG_MACH_NOKIA_N8X0
 static void __init omap2420_n8x0_legacy_init(void)
 {
@@ -129,7 +100,6 @@ static void __init omap3_sbc_t3730_twl_init(void)
 static void __init omap3_sbc_t3730_legacy_init(void)
 {
         omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136);
 }
 
 static void __init omap3_sbc_t3530_legacy_init(void)
@@ -159,14 +129,12 @@ static struct platform_device btwilink_device = {
 
 static void __init omap3_igep0020_rev_f_legacy_init(void)
 {
-        legacy_init_wl12xx(0, 0, 177);
         platform_device_register(&wl18xx_device);
         platform_device_register(&btwilink_device);
 }
 
 static void __init omap3_igep0030_rev_g_legacy_init(void)
 {
-        legacy_init_wl12xx(0, 0, 136);
         platform_device_register(&wl18xx_device);
         platform_device_register(&btwilink_device);
 }
@@ -174,12 +142,6 @@ static void __init omap3_igep0030_rev_g_legacy_init(void)
 static void __init omap3_evm_legacy_init(void)
 {
         hsmmc2_internal_input_clk();
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149);
-}
-
-static void __init omap3_zoom_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162);
 }
 
 static void am35xx_enable_emac_int(void)
@@ -246,7 +208,6 @@ static void __init omap3_sbc_t3517_legacy_init(void)
         am35xx_emac_reset();
         hsmmc2_internal_input_clk();
         omap3_sbc_t3517_wifi_init();
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145);
 }
 
 static void __init am3517_evm_legacy_init(void)
@@ -288,24 +249,6 @@ static void __init omap3_tao3530_legacy_init(void)
 }
 #endif /* CONFIG_ARCH_OMAP3 */
 
-#ifdef CONFIG_ARCH_OMAP4
-static void __init omap4_sdp_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_26,
-                           WL12XX_TCXOCLOCK_26, 53);
-}
-
-static void __init omap4_panda_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53);
-}
-
-static void __init var_som_om44_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 41);
-}
-#endif
-
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
 static struct iommu_platform_data omap4_iommu_pdata = {
         .reset_name = "mmu_cache",
@@ -314,13 +257,6 @@ static struct iommu_platform_data omap4_iommu_pdata = {
 };
 #endif
 
-#ifdef CONFIG_SOC_AM33XX
-static void __init am335x_evmsk_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 31);
-}
-#endif
-
 #ifdef CONFIG_SOC_OMAP5
 static void __init omap5_uevm_legacy_init(void)
 {
@@ -421,19 +357,9 @@ static struct pdata_init pdata_quirks[] __initdata = {
         { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
         { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
         { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
-        { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
         { "ti,am3517-evm", am3517_evm_legacy_init, },
         { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, },
 #endif
-#ifdef CONFIG_ARCH_OMAP4
-        { "ti,omap4-sdp", omap4_sdp_legacy_init, },
-        { "ti,omap4-panda", omap4_panda_legacy_init, },
-        { "variscite,var-dvk-om44", var_som_om44_legacy_init, },
-        { "variscite,var-stk-om44", var_som_om44_legacy_init, },
-#endif
-#ifdef CONFIG_SOC_AM33XX
-        { "ti,am335x-evmsk", am335x_evmsk_legacy_init, },
-#endif
 #ifdef CONFIG_SOC_OMAP5
         { "ti,omap5-uevm", omap5_uevm_legacy_init, },
 #endif
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index f8be41575d7c..930f45cbc08a 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -38,11 +38,11 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = {
 
 static struct rcar_apmu_config r8a7790_apmu_config[] = {
         {
-                .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+                .iomem = DEFINE_RES_MEM(0xe6152000, 0x188),
                 .cpus = { 0, 1, 2, 3 },
         },
         {
-                .iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
+                .iomem = DEFINE_RES_MEM(0xe6151000, 0x188),
                 .cpus = { 0x100, 0x0101, 0x102, 0x103 },
         }
 };
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index 6658682d5c9e..5e2d1db79afa 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -27,7 +27,7 @@
 
 static struct rcar_apmu_config r8a7791_apmu_config[] = {
         {
-                .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+                .iomem = DEFINE_RES_MEM(0xe6152000, 0x188),
                 .cpus = { 0, 1 },
         }
 };
diff --git a/drivers/net/wireless/ti/wilink_platform_data.c b/drivers/net/wireless/ti/wilink_platform_data.c
index a92bd3e89796..ea0e359bdb43 100644
--- a/drivers/net/wireless/ti/wilink_platform_data.c
+++ b/drivers/net/wireless/ti/wilink_platform_data.c
@@ -23,31 +23,6 @@
 #include <linux/err.h>
 #include <linux/wl12xx.h>
 
-static struct wl12xx_platform_data *wl12xx_platform_data;
-
-int __init wl12xx_set_platform_data(const struct wl12xx_platform_data *data)
-{
-        if (wl12xx_platform_data)
-                return -EBUSY;
-        if (!data)
-                return -EINVAL;
-
-        wl12xx_platform_data = kmemdup(data, sizeof(*data), GFP_KERNEL);
-        if (!wl12xx_platform_data)
-                return -ENOMEM;
-
-        return 0;
-}
-
-struct wl12xx_platform_data *wl12xx_get_platform_data(void)
-{
-        if (!wl12xx_platform_data)
-                return ERR_PTR(-ENODEV);
-
-        return wl12xx_platform_data;
-}
-EXPORT_SYMBOL(wl12xx_get_platform_data);
-
 static struct wl1251_platform_data *wl1251_platform_data;
 
 int __init wl1251_set_platform_data(const struct wl1251_platform_data *data)
diff --git a/drivers/net/wireless/ti/wl12xx/main.c b/drivers/net/wireless/ti/wl12xx/main.c
index 144d1f8ba473..af0fe2e17151 100644
--- a/drivers/net/wireless/ti/wl12xx/main.c
+++ b/drivers/net/wireless/ti/wl12xx/main.c
@@ -24,8 +24,6 @@
 
 #include <linux/err.h>
 
-#include <linux/wl12xx.h>
-
 #include "../wlcore/wlcore.h"
 #include "../wlcore/debug.h"
 #include "../wlcore/io.h"
@@ -1770,11 +1768,44 @@ wl12xx_iface_combinations[] = {
         },
 };
 
+static const struct wl12xx_clock wl12xx_refclock_table[] = {
+        { 19200000,     false,  WL12XX_REFCLOCK_19      },
+        { 26000000,     false,  WL12XX_REFCLOCK_26      },
+        { 26000000,     true,   WL12XX_REFCLOCK_26_XTAL },
+        { 38400000,     false,  WL12XX_REFCLOCK_38      },
+        { 38400000,     true,   WL12XX_REFCLOCK_38_XTAL },
+        { 52000000,     false,  WL12XX_REFCLOCK_52      },
+        { 0,            false,  0 }
+};
+
+static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
+        { 16368000,     true,   WL12XX_TCXOCLOCK_16_368 },
+        { 16800000,     true,   WL12XX_TCXOCLOCK_16_8   },
+        { 19200000,     true,   WL12XX_TCXOCLOCK_19_2   },
+        { 26000000,     true,   WL12XX_TCXOCLOCK_26     },
+        { 32736000,     true,   WL12XX_TCXOCLOCK_32_736 },
+        { 33600000,     true,   WL12XX_TCXOCLOCK_33_6   },
+        { 38400000,     true,   WL12XX_TCXOCLOCK_38_4   },
+        { 52000000,     true,   WL12XX_TCXOCLOCK_52     },
+        { 0,            false,  0 }
+};
+
+static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
+                                u32 freq, bool xtal)
+{
+        int i;
+
+        for (i = 0; table[i].freq != 0; i++)
+                if ((table[i].freq == freq) && (table[i].xtal == xtal))
+                        return table[i].hw_idx;
+
+        return -EINVAL;
+}
+
 static int wl12xx_setup(struct wl1271 *wl)
 {
         struct wl12xx_priv *priv = wl->priv;
         struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev);
-        struct wl12xx_platform_data *pdata = pdev_data->pdata;
 
         BUILD_BUG_ON(WL12XX_MAX_LINKS > WLCORE_MAX_LINKS);
         BUILD_BUG_ON(WL12XX_MAX_AP_STATIONS > WL12XX_MAX_LINKS);
@@ -1799,7 +1830,17 @@ static int wl12xx_setup(struct wl1271 *wl)
         wl12xx_conf_init(wl);
 
         if (!fref_param) {
-                priv->ref_clock = pdata->board_ref_clock;
+                priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
+                                                pdev_data->ref_clock_freq,
+                                                pdev_data->ref_clock_xtal);
+                if (priv->ref_clock < 0) {
+                        wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
+                                     pdev_data->ref_clock_freq,
+                                     pdev_data->ref_clock_xtal ?
+                                     "XTAL" : "not XTAL");
+
+                        return priv->ref_clock;
+                }
         } else {
                 if (!strcmp(fref_param, "19.2"))
                         priv->ref_clock = WL12XX_REFCLOCK_19;
@@ -1817,9 +1858,17 @@ static int wl12xx_setup(struct wl1271 *wl)
                         wl1271_error("Invalid fref parameter %s", fref_param);
         }
 
-        if (!tcxo_param) {
-                priv->tcxo_clock = pdata->board_tcxo_clock;
-        } else {
+        if (!tcxo_param && pdev_data->tcxo_clock_freq) {
+                priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
+                                                pdev_data->tcxo_clock_freq,
+                                                true);
+                if (priv->tcxo_clock < 0) {
+                        wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
+                                     pdev_data->tcxo_clock_freq);
+
+                        return priv->tcxo_clock;
+                }
+        } else if (tcxo_param) {
                 if (!strcmp(tcxo_param, "19.2"))
                         priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
                 else if (!strcmp(tcxo_param, "26"))
diff --git a/drivers/net/wireless/ti/wl12xx/wl12xx.h b/drivers/net/wireless/ti/wl12xx/wl12xx.h
index 75c92658bfea..5952e99ace1b 100644
--- a/drivers/net/wireless/ti/wl12xx/wl12xx.h
+++ b/drivers/net/wireless/ti/wl12xx/wl12xx.h
@@ -82,6 +82,34 @@ struct wl12xx_priv {
         struct wl127x_rx_mem_pool_addr *rx_mem_addr;
 };
 
+/* Reference clock values */
+enum {
+        WL12XX_REFCLOCK_19      = 0, /* 19.2 MHz */
+        WL12XX_REFCLOCK_26      = 1, /* 26 MHz */
+        WL12XX_REFCLOCK_38      = 2, /* 38.4 MHz */
+        WL12XX_REFCLOCK_52      = 3, /* 52 MHz */
+        WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
+        WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
+};
+
+/* TCXO clock values */
+enum {
+        WL12XX_TCXOCLOCK_19_2   = 0, /* 19.2MHz */
+        WL12XX_TCXOCLOCK_26     = 1, /* 26 MHz */
+        WL12XX_TCXOCLOCK_38_4   = 2, /* 38.4MHz */
+        WL12XX_TCXOCLOCK_52     = 3, /* 52 MHz */
+        WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */
+        WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */
+        WL12XX_TCXOCLOCK_16_8   = 6, /* 16.8 MHz */
+        WL12XX_TCXOCLOCK_33_6   = 7, /* 33.6 MHz */
+};
+
+struct wl12xx_clock {
+        u32     freq;
+        bool    xtal;
+        u8      hw_idx;
+};
+
 struct wl12xx_fw_packet_counters {
         /* Cumulative counter of released packets per AC */
         u8 tx_released_pkts[NUM_TX_QUEUES];
diff --git a/drivers/net/wireless/ti/wlcore/boot.c b/drivers/net/wireless/ti/wlcore/boot.c
index 77752b03f189..19b7ec7b69c2 100644
--- a/drivers/net/wireless/ti/wlcore/boot.c
+++ b/drivers/net/wireless/ti/wlcore/boot.c
@@ -22,7 +22,6 @@
  */
 
 #include <linux/slab.h>
-#include <linux/wl12xx.h>
 #include <linux/export.h>
 
 #include "debug.h"
diff --git a/drivers/net/wireless/ti/wlcore/debugfs.c b/drivers/net/wireless/ti/wlcore/debugfs.c
index 68f3bf229b5a..eb43f94a1597 100644
--- a/drivers/net/wireless/ti/wlcore/debugfs.c
+++ b/drivers/net/wireless/ti/wlcore/debugfs.c
@@ -502,7 +502,7 @@ static ssize_t driver_state_read(struct file *file, char __user *user_buf,
         DRIVER_STATE_PRINT_HEX(irq);
         /* TODO: ref_clock and tcxo_clock were moved to wl12xx priv */
         DRIVER_STATE_PRINT_HEX(hw_pg_ver);
-        DRIVER_STATE_PRINT_HEX(platform_quirks);
+        DRIVER_STATE_PRINT_HEX(irq_flags);
         DRIVER_STATE_PRINT_HEX(chip.id);
         DRIVER_STATE_PRINT_STR(chip.fw_ver_str);
         DRIVER_STATE_PRINT_STR(chip.phy_fw_ver_str);
diff --git a/drivers/net/wireless/ti/wlcore/main.c b/drivers/net/wireless/ti/wlcore/main.c
index 1e136993580f..0be807951afe 100644
--- a/drivers/net/wireless/ti/wlcore/main.c
+++ b/drivers/net/wireless/ti/wlcore/main.c
@@ -25,8 +25,8 @@
 #include <linux/firmware.h>
 #include <linux/etherdevice.h>
 #include <linux/vmalloc.h>
-#include <linux/wl12xx.h>
 #include <linux/interrupt.h>
+#include <linux/irq.h>
 
 #include "wlcore.h"
 #include "debug.h"
@@ -538,7 +538,7 @@ static int wlcore_irq_locked(struct wl1271 *wl)
          * In case edge triggered interrupt must be used, we cannot iterate
          * more than once without introducing race conditions with the hardirq.
          */
-        if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ)
+        if (wl->irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
                 loopcount = 1;
 
         wl1271_debug(DEBUG_IRQ, "IRQ work");
@@ -6249,7 +6249,6 @@ struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
         wl->ap_ps_map = 0;
         wl->ap_fw_ps_map = 0;
         wl->quirks = 0;
-        wl->platform_quirks = 0;
         wl->system_hlid = WL12XX_SYSTEM_HLID;
         wl->active_sta_count = 0;
         wl->active_link_count = 0;
@@ -6390,8 +6389,8 @@ static void wlcore_nvs_cb(const struct firmware *fw, void *context)
         struct wl1271 *wl = context;
         struct platform_device *pdev = wl->pdev;
         struct wlcore_platdev_data *pdev_data = dev_get_platdata(&pdev->dev);
-        struct wl12xx_platform_data *pdata = pdev_data->pdata;
-        unsigned long irqflags;
+        struct resource *res;
+
         int ret;
         irq_handler_t hardirq_fn = NULL;
 
@@ -6418,19 +6417,23 @@ static void wlcore_nvs_cb(const struct firmware *fw, void *context)
         /* adjust some runtime configuration parameters */
         wlcore_adjust_conf(wl);
 
-        wl->irq = platform_get_irq(pdev, 0);
-        wl->platform_quirks = pdata->platform_quirks;
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (!res) {
+                wl1271_error("Could not get IRQ resource");
+                goto out_free_nvs;
+        }
+
+        wl->irq = res->start;
+        wl->irq_flags = res->flags & IRQF_TRIGGER_MASK;
         wl->if_ops = pdev_data->if_ops;
 
-        if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ) {
-                irqflags = IRQF_TRIGGER_RISING;
+        if (wl->irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
                 hardirq_fn = wlcore_hardirq;
-        } else {
-                irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
-        }
+        else
+                wl->irq_flags |= IRQF_ONESHOT;
 
         ret = request_threaded_irq(wl->irq, hardirq_fn, wlcore_irq,
-                                   irqflags, pdev->name, wl);
+                                   wl->irq_flags, pdev->name, wl);
         if (ret < 0) {
                 wl1271_error("request_irq() failed: %d", ret);
                 goto out_free_nvs;
@@ -6441,7 +6444,7 @@ static void wlcore_nvs_cb(const struct firmware *fw, void *context)
         if (!ret) {
                 wl->irq_wake_enabled = true;
                 device_init_wakeup(wl->dev, 1);
-                if (pdata->pwr_in_suspend)
+                if (pdev_data->pwr_in_suspend)
                         wl->hw->wiphy->wowlan = &wlcore_wowlan_support;
         }
 #endif
diff --git a/drivers/net/wireless/ti/wlcore/sdio.c b/drivers/net/wireless/ti/wlcore/sdio.c
index d3dd7bfdf3f1..ea7e07abca4e 100644
--- a/drivers/net/wireless/ti/wlcore/sdio.c
+++ b/drivers/net/wireless/ti/wlcore/sdio.c
@@ -31,9 +31,10 @@
 #include <linux/mmc/card.h>
 #include <linux/mmc/host.h>
 #include <linux/gpio.h>
-#include <linux/wl12xx.h>
 #include <linux/pm_runtime.h>
 #include <linux/printk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include "wlcore.h"
 #include "wl12xx_80211.h"
@@ -214,6 +215,52 @@ static struct wl1271_if_operations sdio_ops = {
         .set_block_size = wl1271_sdio_set_block_size,
 };
 
+#ifdef CONFIG_OF
+static const struct of_device_id wlcore_sdio_of_match_table[] = {
+        { .compatible = "ti,wl1271" },
+        { .compatible = "ti,wl1273" },
+        { .compatible = "ti,wl1281" },
+        { .compatible = "ti,wl1283" },
+        { .compatible = "ti,wl1801" },
+        { .compatible = "ti,wl1805" },
+        { .compatible = "ti,wl1807" },
+        { .compatible = "ti,wl1831" },
+        { .compatible = "ti,wl1835" },
+        { .compatible = "ti,wl1837" },
+        { }
+};
+
+static int wlcore_probe_of(struct device *dev, int *irq,
+                           struct wlcore_platdev_data *pdev_data)
+{
+        struct device_node *np = dev->of_node;
+
+        if (!np || !of_match_node(wlcore_sdio_of_match_table, np))
+                return -ENODATA;
+
+        *irq = irq_of_parse_and_map(np, 0);
+        if (!*irq) {
+                dev_err(dev, "No irq in platform data\n");
+                kfree(pdev_data);
+                return -EINVAL;
+        }
+
+        /* optional clock frequency params */
+        of_property_read_u32(np, "ref-clock-frequency",
+                             &pdev_data->ref_clock_freq);
+        of_property_read_u32(np, "tcxo-clock-frequency",
+                             &pdev_data->tcxo_clock_freq);
+
+        return 0;
+}
+#else
+static int wlcore_probe_of(struct device *dev, int *irq,
+                           struct wlcore_platdev_data *pdev_data)
+{
+        return -ENODATA;
+}
+#endif
+
 static int wl1271_probe(struct sdio_func *func,
                                   const struct sdio_device_id *id)
 {
@@ -222,6 +269,7 @@ static int wl1271_probe(struct sdio_func *func,
         struct resource res[1];
         mmc_pm_flag_t mmcflags;
         int ret = -ENOMEM;
+        int irq;
         const char *chip_family;
 
         /* We are only able to handle the wlan function */
@@ -245,19 +293,15 @@ static int wl1271_probe(struct sdio_func *func,
         /* Use block mode for transferring over one block size of data */
         func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
 
-        pdev_data.pdata = wl12xx_get_platform_data();
-        if (IS_ERR(pdev_data.pdata)) {
-                ret = PTR_ERR(pdev_data.pdata);
-                dev_err(glue->dev, "missing wlan platform data: %d\n", ret);
+        if (wlcore_probe_of(&func->dev, &irq, &pdev_data))
                 goto out_free_glue;
-        }
 
         /* if sdio can keep power while host is suspended, enable wow */
         mmcflags = sdio_get_host_pm_caps(func);
         dev_dbg(glue->dev, "sdio PM caps = 0x%x\n", mmcflags);
 
         if (mmcflags & MMC_PM_KEEP_POWER)
-                pdev_data.pdata->pwr_in_suspend = true;
+                pdev_data.pwr_in_suspend = true;
 
         sdio_set_drvdata(func, glue);
 
@@ -286,8 +330,9 @@ static int wl1271_probe(struct sdio_func *func,
 
         memset(res, 0x00, sizeof(res));
 
-        res[0].start = pdev_data.pdata->irq;
-        res[0].flags = IORESOURCE_IRQ;
+        res[0].start = irq;
+        res[0].flags = IORESOURCE_IRQ |
+                       irqd_get_trigger_type(irq_get_irq_data(irq));
         res[0].name = "irq";
 
         ret = platform_device_add_resources(glue->core, res, ARRAY_SIZE(res));
diff --git a/drivers/net/wireless/ti/wlcore/spi.c b/drivers/net/wireless/ti/wlcore/spi.c
index 69601f6741d9..f1ac2839d97c 100644
--- a/drivers/net/wireless/ti/wlcore/spi.c
+++ b/drivers/net/wireless/ti/wlcore/spi.c
@@ -331,11 +331,7 @@ static int wl1271_probe(struct spi_device *spi)
 
         memset(&pdev_data, 0x00, sizeof(pdev_data));
 
-        pdev_data.pdata = dev_get_platdata(&spi->dev);
-        if (!pdev_data.pdata) {
-                dev_err(&spi->dev, "no platform data\n");
-                return -ENODEV;
-        }
+        /* TODO: add DT parsing when needed */
 
         pdev_data.if_ops = &spi_ops;
 
diff --git a/drivers/net/wireless/ti/wlcore/wlcore.h b/drivers/net/wireless/ti/wlcore/wlcore.h
index d599c869e6e8..7f363fa566a3 100644
--- a/drivers/net/wireless/ti/wlcore/wlcore.h
+++ b/drivers/net/wireless/ti/wlcore/wlcore.h
@@ -197,6 +197,8 @@ struct wl1271 {
 
         int irq;
 
+        int irq_flags;
+
         spinlock_t wl_lock;
 
         enum wlcore_state state;
@@ -404,9 +406,6 @@ struct wl1271 {
         /* Quirks of specific hardware revisions */
         unsigned int quirks;
 
-        /* Platform limitations */
-        unsigned int platform_quirks;
-
         /* number of currently active RX BA sessions */
         int ba_rx_session_count;
 
diff --git a/drivers/net/wireless/ti/wlcore/wlcore_i.h b/drivers/net/wireless/ti/wlcore/wlcore_i.h
index 3396ce5a934d..39efc6d78b10 100644
--- a/drivers/net/wireless/ti/wlcore/wlcore_i.h
+++ b/drivers/net/wireless/ti/wlcore/wlcore_i.h
@@ -201,8 +201,12 @@ struct wl1271_if_operations {
 };
 
 struct wlcore_platdev_data {
-        struct wl12xx_platform_data *pdata;
         struct wl1271_if_operations *if_ops;
+
+        bool ref_clock_xtal;    /* specify whether the clock is XTAL or not */
+        u32 ref_clock_freq;     /* in Hertz */
+        u32 tcxo_clock_freq;    /* in Hertz, tcxo is always XTAL */
+        bool pwr_in_suspend;
 };
 
 #define MAX_NUM_KEYS 14
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 91940271cf83..3f2c6b198d4a 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -21,6 +21,8 @@
 #define R8A7790_CLK_SD0                 7
 #define R8A7790_CLK_SD1                 8
 #define R8A7790_CLK_Z                   9
+#define R8A7790_CLK_RCAN                10
+#define R8A7790_CLK_ADSP                11
 
 /* MSTP0 */
 #define R8A7790_CLK_MSIOF0              0
@@ -80,6 +82,7 @@
 /* MSTP5 */
 #define R8A7790_CLK_AUDIO_DMAC1         1
 #define R8A7790_CLK_AUDIO_DMAC0         2
+#define R8A7790_CLK_ADSP_MOD            6
 #define R8A7790_CLK_THERMAL             22
 #define R8A7790_CLK_PWM                 23
 
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index f096f3f6c16a..8fc5dc8faeea 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -20,6 +20,8 @@
 #define R8A7791_CLK_SDH                 6
 #define R8A7791_CLK_SD0                 7
 #define R8A7791_CLK_Z                   8
+#define R8A7791_CLK_RCAN                9
+#define R8A7791_CLK_ADSP                10
 
 /* MSTP0 */
 #define R8A7791_CLK_MSIOF0              0
@@ -71,6 +73,7 @@
 /* MSTP5 */
 #define R8A7791_CLK_AUDIO_DMAC1         1
 #define R8A7791_CLK_AUDIO_DMAC0         2
+#define R8A7791_CLK_ADSP_MOD            6
 #define R8A7791_CLK_THERMAL             22
 #define R8A7791_CLK_PWM                 23
 
diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h
index 1dd3eb2b7d90..53369568c24c 100644
--- a/include/dt-bindings/clock/sh73a0-clock.h
+++ b/include/dt-bindings/clock/sh73a0-clock.h
@@ -76,4 +76,7 @@
 #define SH73A0_CLK_IIC4         10
 #define SH73A0_CLK_KEYSC        3
 
+/* MSTP5 */
+#define SH73A0_CLK_INTCA0       8
+
 #endif
diff --git a/include/dt-bindings/media/omap3-isp.h b/include/dt-bindings/media/omap3-isp.h
new file mode 100644
index 000000000000..b18c60e468c7
--- /dev/null
+++ b/include/dt-bindings/media/omap3-isp.h
@@ -0,0 +1,22 @@
+/*
+ * include/dt-bindings/media/omap3-isp.h
+ *
+ * Copyright (C) 2015 Sakari Ailus
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_OMAP3_ISP_H__
+#define __DT_BINDINGS_OMAP3_ISP_H__
+
+#define OMAP3ISP_PHY_TYPE_COMPLEX_IO    0
+#define OMAP3ISP_PHY_TYPE_CSIPHY        1
+
+#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */
diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h
index a9c723be1acf..95704cd4cfab 100644
--- a/include/linux/wl12xx.h
+++ b/include/linux/wl12xx.h
@@ -26,28 +26,6 @@
 
 #include <linux/err.h>
 
-/* Reference clock values */
-enum {
-        WL12XX_REFCLOCK_19      = 0, /* 19.2 MHz */
-        WL12XX_REFCLOCK_26      = 1, /* 26 MHz */
-        WL12XX_REFCLOCK_38      = 2, /* 38.4 MHz */
-        WL12XX_REFCLOCK_52      = 3, /* 52 MHz */
-        WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
-        WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
-};
-
-/* TCXO clock values */
-enum {
-        WL12XX_TCXOCLOCK_19_2   = 0, /* 19.2MHz */
-        WL12XX_TCXOCLOCK_26     = 1, /* 26 MHz */
-        WL12XX_TCXOCLOCK_38_4   = 2, /* 38.4MHz */
-        WL12XX_TCXOCLOCK_52     = 3, /* 52 MHz */
-        WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */
-        WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */
-        WL12XX_TCXOCLOCK_16_8   = 6, /* 16.8 MHz */
-        WL12XX_TCXOCLOCK_33_6   = 7, /* 33.6 MHz */
-};
-
 struct wl1251_platform_data {
         int power_gpio;
         /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */
@@ -55,23 +33,8 @@ struct wl1251_platform_data {
         bool use_eeprom;
 };
 
-struct wl12xx_platform_data {
-        int irq;
-        int board_ref_clock;
-        int board_tcxo_clock;
-        unsigned long platform_quirks;
-        bool pwr_in_suspend;
-};
-
-/* Platform does not support level trigger interrupts */
-#define WL12XX_PLATFORM_QUIRK_EDGE_IRQ  BIT(0)
-
 #ifdef CONFIG_WILINK_PLATFORM_DATA
 
-int wl12xx_set_platform_data(const struct wl12xx_platform_data *data);
-
-struct wl12xx_platform_data *wl12xx_get_platform_data(void);
-
 int wl1251_set_platform_data(const struct wl1251_platform_data *data);
 
 struct wl1251_platform_data *wl1251_get_platform_data(void);
@@ -79,18 +42,6 @@ struct wl1251_platform_data *wl1251_get_platform_data(void);
 #else
 
 static inline
-int wl12xx_set_platform_data(const struct wl12xx_platform_data *data)
-{
-        return -ENOSYS;
-}
-
-static inline
-struct wl12xx_platform_data *wl12xx_get_platform_data(void)
-{
-        return ERR_PTR(-ENODATA);
-}
-
-static inline
 int wl1251_set_platform_data(const struct wl1251_platform_data *data)
 {
         return -ENOSYS;